diff options
author | polwex <polwex@sortug.com> | 2025-10-05 21:56:51 +0700 |
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committer | polwex <polwex@sortug.com> | 2025-10-05 21:56:51 +0700 |
commit | fcedfddf00b3f994e4f4e40332ac7fc192c63244 (patch) | |
tree | 51d38e62c7bdfcc5f9a5e9435fe820c93cfc9a3d /vere/ext/nasm/x86/regs.dat |
claude is gud
Diffstat (limited to 'vere/ext/nasm/x86/regs.dat')
-rw-r--r-- | vere/ext/nasm/x86/regs.dat | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/vere/ext/nasm/x86/regs.dat b/vere/ext/nasm/x86/regs.dat new file mode 100644 index 0000000..cec8420 --- /dev/null +++ b/vere/ext/nasm/x86/regs.dat @@ -0,0 +1,141 @@ +## -------------------------------------------------------------------------- +## +## Copyright 1996-2009 The NASM Authors - All Rights Reserved +## See the file AUTHORS included with the NASM distribution for +## the specific copyright holders. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following +## conditions are met: +## +## * Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## * Redistributions in binary form must reproduce the above +## copyright notice, this list of conditions and the following +## disclaimer in the documentation and/or other materials provided +## with the distribution. +## +## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND +## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR +## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +## +## -------------------------------------------------------------------------- + +# +# List of registers and their classes; classes are defined in nasm.h +# +# The columns are: +# +# register name, assembler class, disassembler class(es), x86 register number[, token flag] +# +# If the register name ends in two numbers separated by a dash, then it is +# repeated as many times as indicated, and the register number is +# updated with it. +# +# If 'token flag' is present, this value will be assigned to tokflag field in +# 'struct tokendata tokendata[]' table. Token flag can be used for specifying +# special usage of corresponding register. E.g. opmask registers can be either +# enclosed by curly braces or standalone operand depending on the usage. +# + +# General-purpose registers +al REG_AL reg8,reg8_rex 0 +ah REG_HIGH reg8 4 +ax REG_AX reg16 0 +eax REG_EAX reg32 0 +rax REG_RAX reg64 0 +bl REG8NA reg8,reg8_rex 3 +bh REG_HIGH reg8 7 +bx REG16NA reg16 3 +ebx REG32NA reg32 3 +rbx REG64NA reg64 3 +cl REG_CL reg8,reg8_rex 1 +ch REG_HIGH reg8 5 +cx REG_CX reg16 1 +ecx REG_ECX reg32 1 +rcx REG_RCX reg64 1 +dl REG_DL reg8,reg8_rex 2 +dh REG_HIGH reg8 6 +dx REG_DX reg16 2 +edx REG_EDX reg32 2 +rdx REG_RDX reg64 2 +spl REG8NA reg8_rex 4 +sp REG16NA reg16 4 +esp REG32NA reg32 4 +rsp REG64NA reg64 4 +bpl REG8NA reg8_rex 5 +bp REG16NA reg16 5 +ebp REG32NA reg32 5 +rbp REG64NA reg64 5 +sil REG8NA reg8_rex 6 +si REG16NA reg16 6 +esi REG32NA reg32 6 +rsi REG64NA reg64 6 +dil REG8NA reg8_rex 7 +di REG16NA reg16 7 +edi REG32NA reg32 7 +rdi REG64NA reg64 7 +r8-15b REG8NA reg8_rex 8 +r8-15w REG16NA reg16 8 +r8-15d REG32NA reg32 8 +r8-15 REG64NA reg64 8 + +# Segment registers +es REG_ES sreg 0 +cs REG_CS sreg 1 +ss REG_SS sreg 2 +ds REG_DS sreg 3 +fs REG_FS sreg 4 +gs REG_GS sreg 5 +segr6-7 REG_SEG67 sreg 6 + +# Control registers +cr0-15 REG_CREG creg 0 + +# Debug registers +dr0-15 REG_DREG dreg 0 + +# Test registers +tr0-7 REG_TREG treg 0 + +# Floating-point registers +st0 FPU0 fpureg 0 +st1-7 FPUREG fpureg 1 + +# MMX registers +mm0-7 MMXREG mmxreg 0 + +# SSE registers +xmm0 XMM0 xmmreg 0 +xmm1-15 XMM_L16 xmmreg 1 +xmm16-31 XMMREG xmmreg 16 + +# AVX registers +ymm0 YMM0 ymmreg 0 +ymm1-15 YMM_L16 ymmreg 1 +ymm16-31 YMMREG ymmreg 16 + +# AVX512 registers +zmm0 ZMM0 zmmreg 0 +zmm1-15 ZMM_L16 zmmreg 1 +zmm16-31 ZMMREG zmmreg 16 + +# AMX tile registers +tmm0-7 TMMREG tmmreg 0 + +# Opmask registers +k0 OPMASK0 opmaskreg 0 +k1-7 OPMASKREG opmaskreg 1 TFLAG_BRC_OPT + +# Bounds registers +bnd0-3 BNDREG bndreg 0 |