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authorpolwex <polwex@sortug.com>2025-10-05 21:56:51 +0700
committerpolwex <polwex@sortug.com>2025-10-05 21:56:51 +0700
commitfcedfddf00b3f994e4f4e40332ac7fc192c63244 (patch)
tree51d38e62c7bdfcc5f9a5e9435fe820c93cfc9a3d /vere/ext/nasm/x86
claude is gud
Diffstat (limited to 'vere/ext/nasm/x86')
-rw-r--r--vere/ext/nasm/x86/disp8.c131
-rw-r--r--vere/ext/nasm/x86/iflag.c315
-rw-r--r--vere/ext/nasm/x86/iflaggen.h287
-rw-r--r--vere/ext/nasm/x86/iflags.ph153
-rw-r--r--vere/ext/nasm/x86/insns-iflags.ph251
-rw-r--r--vere/ext/nasm/x86/insns.dat6570
-rwxr-xr-xvere/ext/nasm/x86/insns.pl1167
-rw-r--r--vere/ext/nasm/x86/insnsa.c19532
-rw-r--r--vere/ext/nasm/x86/insnsb.c6748
-rw-r--r--vere/ext/nasm/x86/insnsd.c29941
-rw-r--r--vere/ext/nasm/x86/insnsi.h2265
-rw-r--r--vere/ext/nasm/x86/insnsn.c2254
-rw-r--r--vere/ext/nasm/x86/regdis.c21
-rw-r--r--vere/ext/nasm/x86/regflags.c256
-rw-r--r--vere/ext/nasm/x86/regs.c254
-rw-r--r--vere/ext/nasm/x86/regs.dat141
-rw-r--r--vere/ext/nasm/x86/regs.h514
-rwxr-xr-xvere/ext/nasm/x86/regs.pl205
-rw-r--r--vere/ext/nasm/x86/regvals.c255
19 files changed, 71260 insertions, 0 deletions
diff --git a/vere/ext/nasm/x86/disp8.c b/vere/ext/nasm/x86/disp8.c
new file mode 100644
index 0000000..64c921b
--- /dev/null
+++ b/vere/ext/nasm/x86/disp8.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------- *
+ *
+ * Copyright 1996-2013 The NASM Authors - All Rights Reserved
+ * See the file AUTHORS included with the NASM distribution for
+ * the specific copyright holders.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials provided
+ * with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * disp8.c : Contains a common logic for EVEX compressed displacement
+ */
+
+#include "disp8.h"
+
+/*
+ * Find N value for compressed displacement (disp8 * N)
+ */
+uint8_t get_disp8N(insn *ins)
+{
+ static const uint8_t fv_n[2][2][VLMAX] = {{{16, 32, 64}, {4, 4, 4}},
+ {{16, 32, 64}, {8, 8, 8}}};
+ static const uint8_t hv_n[2][VLMAX] = {{8, 16, 32}, {4, 4, 4}};
+ static const uint8_t dup_n[VLMAX] = {8, 32, 64};
+
+ bool evex_b = (ins->evex_p[2] & EVEX_P2B) >> 4;
+ enum ttypes tuple = ins->evex_tuple;
+ enum vectlens vectlen = (ins->evex_p[2] & EVEX_P2LL) >> 5;
+ bool evex_w = (ins->evex_p[1] & EVEX_P1W) >> 7;
+ uint8_t n = 0;
+
+ switch(tuple) {
+ case FV:
+ n = fv_n[evex_w][evex_b][vectlen];
+ break;
+ case HV:
+ n = hv_n[evex_b][vectlen];
+ break;
+
+ case FVM:
+ /* 16, 32, 64 for VL 128, 256, 512 respectively*/
+ n = 1 << (vectlen + 4);
+ break;
+ case T1S8: /* N = 1 */
+ case T1S16: /* N = 2 */
+ n = tuple - T1S8 + 1;
+ break;
+ case T1S:
+ /* N = 4 for 32bit, 8 for 64bit */
+ n = evex_w ? 8 : 4;
+ break;
+ case T1F32:
+ case T1F64:
+ /* N = 4 for 32bit, 8 for 64bit */
+ n = (tuple == T1F32 ? 4 : 8);
+ break;
+ case T2:
+ case T4:
+ case T8:
+ if (vectlen + 7 <= (evex_w + 5) + (tuple - T2 + 1))
+ n = 0;
+ else
+ n = 1 << (tuple - T2 + evex_w + 3);
+ break;
+ case HVM:
+ case QVM:
+ case OVM:
+ n = 1 << (OVM - tuple + vectlen + 1);
+ break;
+ case M128:
+ n = 16;
+ break;
+ case DUP:
+ n = dup_n[vectlen];
+ break;
+
+ default:
+ break;
+ }
+
+ return n;
+}
+
+/*
+ * Check if offset is a multiple of N with corresponding tuple type
+ * if Disp8*N is available, compressed displacement is stored in compdisp
+ */
+bool is_disp8n(operand *input, insn *ins, int8_t *compdisp)
+{
+ int32_t off = input->offset;
+ uint8_t n;
+ int32_t disp8;
+
+ n = get_disp8N(ins);
+
+ if (n && !(off & (n - 1))) {
+ disp8 = off / n;
+ /* if it fits in Disp8 */
+ if (disp8 >= -128 && disp8 <= 127) {
+ *compdisp = disp8;
+ return true;
+ }
+ }
+
+ *compdisp = 0;
+ return false;
+}
diff --git a/vere/ext/nasm/x86/iflag.c b/vere/ext/nasm/x86/iflag.c
new file mode 100644
index 0000000..d47ce89
--- /dev/null
+++ b/vere/ext/nasm/x86/iflag.c
@@ -0,0 +1,315 @@
+/* This file is auto-generated. Don't edit. */
+#include "iflag.h"
+
+/* All combinations of instruction flags used in instruction patterns */
+const iflag_t insns_flags[309] = {
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 0 : 8086 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 1 : 8086,NOLONG */
+ {{UINT32_C(0x00000004),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 2 : 8086,NOLONG,SB */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 3 : 8086,LOCK,SM */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 4 : 386,LOCK,SM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 5 : 386 */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000028),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 6 : LOCK,LONG,SM,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 7 : LONG,X86_64 */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 8 : 8086,SM */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 9 : 386,SM */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 10 : LONG,SM,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 11 : 8086,LOCK */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 12 : 386,LOCK */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000028),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 13 : LOCK,LONG,X86_64 */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000018),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 14 : 8086,LOCK,NOLONG,SM */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000014),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 15 : 286,NOLONG,PROT,SM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000014),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 16 : 286,NOLONG,PROT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00040020)}}, /* 17 : CYRIX,OBSOLETE,PENT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000002)}}, /* 18 : 186,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 19 : 386,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000010)}}, /* 20 : 486 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000200),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 21 : 8086,BND */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000210),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 22 : 8086,BND,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000210),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 23 : 386,BND,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000220),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 24 : BND,LONG,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 25 : 286,PRIV */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 26 : 8086,NOLONG,SM */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 27 : LOCK,PENT,SM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 28 : PENT */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000408),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000010)}}, /* 29 : 486,LOCK,OBSOLETE,SM,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000010)}}, /* 30 : 486,OBSOLETE,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 31 : LOCK,PENT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040020)}}, /* 32 : CYRIX,PENT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040040)}}, /* 33 : CYRIX,P6 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 34 : MMX,PENT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000002)}}, /* 35 : 186 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00001000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 36 : 8086,FPU */
+ {{UINT32_C(0x00000000),UINT32_C(0x00001000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000040)}}, /* 37 : FPU,P6 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00001000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 38 : 386,FPU */
+ {{UINT32_C(0x00000000),UINT32_C(0x00004000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 39 : 3DNOW,PENT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00001400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 40 : 286,FPU,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00001000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000200)}}, /* 41 : FPU,PRESCOTT */
+ {{UINT32_C(0x00000008),UINT32_C(0x00001000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 42 : 8086,FPU,SW */
+ {{UINT32_C(0x00000000),UINT32_C(0x00001000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 43 : 286,FPU */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 44 : 8086,PRIV */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000008)}}, /* 45 : 386,OBSOLETE,SW,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000008)}}, /* 46 : 386,OBSOLETE,UNDOC */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000008)}}, /* 47 : 386,OBSOLETE,SD,UNDOC */
+ {{UINT32_C(0x00000002),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000002)}}, /* 48 : 186,SM2 */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000002)}}, /* 49 : 186,SM */
+ {{UINT32_C(0x00000002),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 50 : 386,SM2 */
+ {{UINT32_C(0x00000002),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 51 : LONG,SM2,X86_64 */
+ {{UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 52 : 8086,SB */
+ {{UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 53 : 386,SB */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000010)}}, /* 54 : 486,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x80000011),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 55 : FUTURE,INVPCID,NOLONG,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x80000021),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 56 : FUTURE,INVPCID,LONG,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080400)}}, /* 57 : AMD,NOLONG,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080400)}}, /* 58 : AMD,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080400)}}, /* 59 : AMD,LONG,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00008000)}}, /* 60 : IA64 */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 61 : 286,PROT,SW */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 62 : 286,PROT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 63 : 386,PROT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000024),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 64 : LONG,PROT,X86_64 */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 65 : 386,PROT,SW */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000024),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 66 : LONG,PROT,SW,X86_64 */
+ {{UINT32_C(0x00000800),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 67 : 8086,ANYSIZE */
+ {{UINT32_C(0x00000800),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 68 : 386,ANYSIZE */
+ {{UINT32_C(0x00000800),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 69 : ANYSIZE,LONG,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000005),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 70 : 286,PRIV,PROT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000004)}}, /* 71 : 286,OBSOLETE,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000200)}}, /* 72 : PRESCOTT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000200)}}, /* 73 : NOLONG,PRESCOTT */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080000)}}, /* 74 : AMD */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 75 : 8086,SW */
+ {{UINT32_C(0x00020000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 76 : LONG,OPT,X86_64 */
+ {{UINT32_C(0x00020000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 77 : 8086,OPT */
+ {{UINT32_C(0x00020000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 78 : 386,OPT */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000040),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 79 : 8086,NOHLE,SM */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000040),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 80 : 386,NOHLE,SM */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000060),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 81 : LONG,NOHLE,SM,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000011),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 82 : 386,NOLONG,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000021),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 83 : LONG,PRIV,X86_64 */
+ {{UINT32_C(0x00020001),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 84 : LONG,OPT,SM,X86_64 */
+ {{UINT32_C(0x00000010),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 85 : MMX,PENT,SD */
+ {{UINT32_C(0x00000400),UINT32_C(0x00002020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 86 : LONG,MMX,SX,X86_64 */
+ {{UINT32_C(0x00000020),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 87 : MMX,PENT,SQ */
+ {{UINT32_C(0x00000000),UINT32_C(0x00002020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 88 : LONG,MMX,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000040)}}, /* 89 : P6 */
+ {{UINT32_C(0x00000020),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040020)}}, /* 90 : CYRIX,MMX,PENT,SQ */
+ {{UINT32_C(0x00000020),UINT32_C(0x00004000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 91 : 3DNOW,PENT,SQ */
+ {{UINT32_C(0x00000001),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040020)}}, /* 92 : CYRIX,MMX,PENT,SM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000001)}}, /* 93 : 8086,OBSOLETE,UNDOC */
+ {{UINT32_C(0x00001200),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000002)}}, /* 94 : 186,AR0,SIZE */
+ {{UINT32_C(0x00001200),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 95 : 386,AR0,NOLONG,SIZE */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 96 : 386,NOLONG,SD */
+ {{UINT32_C(0x00001200),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 97 : AR0,LONG,SIZE,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000002),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040040)}}, /* 98 : CYRIX,P6,SMM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 99 : PENT,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 100 : X86_64 */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000200),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 101 : 8086,BND,SW */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000210),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 102 : 8086,BND,NOLONG,SW */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000220),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 103 : BND,LONG,SW,X86_64 */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 104 : LONG,SW,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000002),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040010)}}, /* 105 : 486,CYRIX,SMM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000002),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020)}}, /* 106 : PENT,SMM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001)}}, /* 107 : 8086,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004)}}, /* 108 : 286 */
+ {{UINT32_C(0x00004006),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 109 : 386,AR2,SB,SM2 */
+ {{UINT32_C(0x00004006),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 110 : AR2,LONG,SB,SM2,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 111 : 386,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00040010)}}, /* 112 : 486,CYRIX,OBSOLETE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080040)}}, /* 113 : AMD,P6 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000040)}}, /* 114 : P6,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080040)}}, /* 115 : AMD,P6,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000002)}}, /* 116 : 186,OBSOLETE */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 117 : 386,SM,UNDOC */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000010)}}, /* 118 : 486,LOCK,SM */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 119 : 386,SW,UNDOC */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 120 : 386,SD,UNDOC */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000040)}}, /* 121 : P6,SM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000200),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008)}}, /* 122 : 386,BND */
+ {{UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 123 : KATMAI,SSE */
+ {{UINT32_C(0x00000000),UINT32_C(0x0000a000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 124 : KATMAI,MMX,SSE */
+ {{UINT32_C(0x00002010),UINT32_C(0x00008000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 125 : AR1,KATMAI,SD,SSE */
+ {{UINT32_C(0x00002020),UINT32_C(0x00008020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 126 : AR1,LONG,SQ,SSE,X86_64 */
+ {{UINT32_C(0x00002010),UINT32_C(0x00008020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 127 : AR1,LONG,SD,SSE,X86_64 */
+ {{UINT32_C(0x00000020),UINT32_C(0x0000a000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 128 : KATMAI,MMX,SQ,SSE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00008020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 129 : LONG,SSE,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00009000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000040)}}, /* 130 : FPU,P6,SSE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00009020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 131 : FPU,LONG,SSE,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800)}}, /* 132 : NEHALEM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800)}}, /* 133 : NEHALEM,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800)}}, /* 134 : LONG,NEHALEM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 135 : FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 136 : FUTURE,LONG */
+ {{UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 137 : KATMAI,SB */
+ {{UINT32_C(0x00000004),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100),UINT32_C(0x00004000)}}, /* 138 : FUTURE,PREFETCHI,SB */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 139 : KATMAI */
+ {{UINT32_C(0x00000000),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 140 : KATMAI,MMX */
+ {{UINT32_C(0x00000020),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 141 : KATMAI,MMX,SQ */
+ {{UINT32_C(0x00004004),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 142 : AR2,KATMAI,MMX,SB */
+ {{UINT32_C(0x00004006),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000080)}}, /* 143 : AR2,KATMAI,MMX,SB,SM2 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 144 : SSE2,WILLAMETTE */
+ {{UINT32_C(0x00000040),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 145 : SO,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 146 : SD,WILLAMETTE */
+ {{UINT32_C(0x00000020),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 147 : LONG,SQ,X86_64 */
+ {{UINT32_C(0x00000010),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 148 : SD,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00000020),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 149 : SQ,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00010020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 150 : LONG,SSE2,X86_64 */
+ {{UINT32_C(0x00000020),UINT32_C(0x00002000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 151 : MMX,SQ,WILLAMETTE */
+ {{UINT32_C(0x00004004),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 152 : AR2,SB,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00004004),UINT32_C(0x00010020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 153 : AR2,LONG,SB,SSE2,X86_64 */
+ {{UINT32_C(0x00004006),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 154 : AR2,SB,SM2,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00002004),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 155 : AR1,SB,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00002020),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 156 : AR1,SQ,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00002020),UINT32_C(0x00010020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 157 : AR1,LONG,SQ,SSE2,X86_64 */
+ {{UINT32_C(0x00002010),UINT32_C(0x00010000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100)}}, /* 158 : AR1,SD,SSE2,WILLAMETTE */
+ {{UINT32_C(0x00000040),UINT32_C(0x00020000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000200)}}, /* 159 : PRESCOTT,SO,SSE3 */
+ {{UINT32_C(0x00000020),UINT32_C(0x00020000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000200)}}, /* 160 : PRESCOTT,SQ,SSE3 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00020000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000200)}}, /* 161 : PRESCOTT,SSE3 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080000)}}, /* 162 : AMD,VMX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 163 : VMX */
+ {{UINT32_C(0x00000010),UINT32_C(0x00040010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 164 : NOLONG,SD,VMX */
+ {{UINT32_C(0x00000020),UINT32_C(0x00040020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 165 : LONG,SQ,VMX,X86_64 */
+ {{UINT32_C(0x00000040),UINT32_C(0x00040010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 166 : NOLONG,SO,VMX */
+ {{UINT32_C(0x00000040),UINT32_C(0x00040020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 167 : LONG,SO,VMX */
+ {{UINT32_C(0x00000020),UINT32_C(0x00082000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 168 : MMX,SQ,SSSE3 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00080000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 169 : SSSE3 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00100000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080000)}}, /* 170 : AMD,SSE4A */
+ {{UINT32_C(0x00000020),UINT32_C(0x00100000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080000)}}, /* 171 : AMD,SQ,SSE4A */
+ {{UINT32_C(0x00000010),UINT32_C(0x00100000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080000)}}, /* 172 : AMD,SD,SSE4A */
+ {{UINT32_C(0x00000000),UINT32_C(0x00200000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 173 : SSE41 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00200020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 174 : LONG,SSE41,X86_64 */
+ {{UINT32_C(0x00004004),UINT32_C(0x00200000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 175 : AR2,SB,SSE41 */
+ {{UINT32_C(0x00004004),UINT32_C(0x00200020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 176 : AR2,LONG,SB,SSE41,X86_64 */
+ {{UINT32_C(0x00000020),UINT32_C(0x00200000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 177 : SQ,SSE41 */
+ {{UINT32_C(0x00000010),UINT32_C(0x00200000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 178 : SD,SSE41 */
+ {{UINT32_C(0x00000008),UINT32_C(0x00200000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 179 : SSE41,SW */
+ {{UINT32_C(0x00000000),UINT32_C(0x00400000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000)}}, /* 180 : SSE42 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00400020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 181 : LONG,SSE42,X86_64 */
+ {{UINT32_C(0x00000008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800)}}, /* 182 : NEHALEM,SW */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800)}}, /* 183 : NEHALEM,SD */
+ {{UINT32_C(0x00000020),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800)}}, /* 184 : LONG,NEHALEM,SQ */
+ {{UINT32_C(0x00000020),UINT32_C(0x00004000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040020)}}, /* 185 : 3DNOW,CYRIX,PENT,SQ */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800)}}, /* 186 : NEHALEM,SM */
+ {{UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00001000)}}, /* 187 : SSE,WESTMERE */
+ {{UINT32_C(0x00000000),UINT32_C(0x01000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00002000)}}, /* 188 : AVX,SANDYBRIDGE,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00002000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 189 : FUTURE,VAES,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00002081),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 190 : AVX512,AVX512VL,EVEX,FUTURE,VAES */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00002001),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 191 : AVX512,EVEX,FUTURE,VAES */
+ {{UINT32_C(0x00000040),UINT32_C(0x01000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00002000)}}, /* 192 : AVX,SANDYBRIDGE,SO,VEX */
+ {{UINT32_C(0x00000080),UINT32_C(0x01000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00002000)}}, /* 193 : AVX,SANDYBRIDGE,SY,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x01000020),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00002000)}}, /* 194 : AVX,LONG,SANDYBRIDGE,VEX */
+ {{UINT32_C(0x00000010),UINT32_C(0x01000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00002000)}}, /* 195 : AVX,SANDYBRIDGE,SD,VEX */
+ {{UINT32_C(0x00000020),UINT32_C(0x01000020),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00002000)}}, /* 196 : AVX,LONG,SANDYBRIDGE,SQ,VEX */
+ {{UINT32_C(0x00000020),UINT32_C(0x01000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00002000)}}, /* 197 : AVX,SANDYBRIDGE,SQ,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 198 : FUTURE,VEX,VPCLMULQDQ */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004080),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 199 : AVX512VL,EVEX,FUTURE,VPCLMULQDQ */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004001),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 200 : AVX512,EVEX,FUTURE,VPCLMULQDQ */
+ {{UINT32_C(0x00000000),UINT32_C(0x04000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 201 : FMA,FUTURE,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x01000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 202 : AVX,FUTURE,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 203 : FUTURE,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00080008)}}, /* 204 : 386,AMD,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00080400)}}, /* 205 : AMD,LONG,VEX,X86_64 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00800000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00080000)}}, /* 206 : AMD,SSE5,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x02000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 207 : AVX2,FUTURE,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x40000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 208 : FUTURE,RTM */
+ {{UINT32_C(0x00000000),UINT32_C(0x40000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 209 : FUTURE,NOLONG,RTM */
+ {{UINT32_C(0x00000000),UINT32_C(0x40000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 210 : FUTURE,LONG,RTM */
+ {{UINT32_C(0x00000000),UINT32_C(0x40000800),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 211 : FUTURE,HLE,RTM */
+ {{UINT32_C(0x00000000),UINT32_C(0x08000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 212 : BMI1,FUTURE,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x08000020),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 213 : BMI1,FUTURE,LONG,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x20000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 214 : FUTURE,TBM,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x20000020),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 215 : FUTURE,LONG,TBM,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x10000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 216 : BMI2,FUTURE,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x10000020),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 217 : BMI2,FUTURE,LONG,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x08000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 218 : BMI1,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x08000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 219 : BMI1,FUTURE,LONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000040),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 220 : FUTURE,PREFETCHWT1 */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000080),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 221 : FUTURE,MIB,MPX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 222 : FUTURE,MPX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 223 : FUTURE,MPX,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 224 : FUTURE,LONG,MPX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000090),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 225 : FUTURE,MIB,MPX,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x000000a0),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 226 : FUTURE,LONG,MIB,MPX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 227 : FUTURE,SHA */
+ {{UINT32_C(0x00040008),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040800),UINT32_C(0x00004000)}}, /* 228 : AVXNECONVERT,FUTURE,LATEVEX,SW,VEX */
+ {{UINT32_C(0x00040400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040800),UINT32_C(0x00004000)}}, /* 229 : AVXNECONVERT,FUTURE,LATEVEX,SX,VEX */
+ {{UINT32_C(0x00040080),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040800),UINT32_C(0x00004000)}}, /* 230 : AVXNECONVERT,FUTURE,LATEVEX,SY,VEX */
+ {{UINT32_C(0x00040400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00041000),UINT32_C(0x00004000)}}, /* 231 : AVXVNNIINT8,FUTURE,LATEVEX,SX,VEX */
+ {{UINT32_C(0x00040080),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00041000),UINT32_C(0x00004000)}}, /* 232 : AVXVNNIINT8,FUTURE,LATEVEX,SY,VEX */
+ {{UINT32_C(0x00040400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00042000),UINT32_C(0x00004000)}}, /* 233 : AVXIFMA,FUTURE,LATEVEX,SX,VEX */
+ {{UINT32_C(0x00040080),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00042000),UINT32_C(0x00004000)}}, /* 234 : AVXIFMA,FUTURE,LATEVEX,SY,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 235 : FUTURE,VEX */
+ {{UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 236 : FUTURE,SM,VEX */
+ {{UINT32_C(0x00000005),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 237 : FUTURE,SB,SM,VEX */
+ {{UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 238 : FUTURE,SX,VEX */
+ {{UINT32_C(0x00000002),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 239 : FUTURE,SM2,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000081),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 240 : AVX512,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 241 : AVX512,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000180),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 242 : AVX512DQ,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000100),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 243 : AVX512DQ,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000280),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 244 : AVX512BW,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000200),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 245 : AVX512BW,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000004),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 246 : AVX512ER,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000008),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 247 : AVX512PF,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000082),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 248 : AVX512CD,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000002),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 249 : AVX512CD,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000880),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 250 : AVX512VBMI,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000800),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 251 : AVX512VBMI,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000480),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 252 : AVX512IFMA,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 253 : AVX512IFMA,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 254 : FUTURE,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000420),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 255 : FUTURE,LONG,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00038000),UINT32_C(0x00004000)}}, /* 256 : FUTURE,NEVER,NOP,OBSOLETE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00084000)}}, /* 257 : AMD,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00084000)}}, /* 258 : AMD,FUTURE,NOLONG */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00084000)}}, /* 259 : AMD,FUTURE,LONG */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 260 : FUTURE,SD */
+ {{UINT32_C(0x00000020),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 261 : FUTURE,LONG,SQ */
+ {{UINT32_C(0x00000000),UINT32_C(0x00008000),UINT32_C(0x00008000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 262 : FUTURE,GFNI,SSE */
+ {{UINT32_C(0x00000000),UINT32_C(0x01000000),UINT32_C(0x00008000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 263 : AVX,FUTURE,GFNI,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00008080),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 264 : AVX512VL,EVEX,FUTURE,GFNI */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00008001),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 265 : AVX512,EVEX,FUTURE,GFNI */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00010080),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 266 : AVX512VBMI2,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00010000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 267 : AVX512VBMI2,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00020080),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 268 : AVX512VL,AVX512VNNI,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00020000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 269 : AVX512VNNI,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040080),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 270 : AVX512BITALG,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00040000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 271 : AVX512BITALG,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080080),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 272 : AVX512VL,AVX512VPOPCNTDQ,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00080000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 273 : AVX512VPOPCNTDQ,EVEX,FUTURE */
+ {{UINT32_C(0x00000040),UINT32_C(0x00000000),UINT32_C(0x00100000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 274 : AVX5124FMAPS,EVEX,FUTURE,SO */
+ {{UINT32_C(0x00000040),UINT32_C(0x00000000),UINT32_C(0x00200000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 275 : AVX5124VNNIW,EVEX,FUTURE,SO */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x01000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 276 : FUTURE,SGX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x02000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 277 : CET,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x02000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 278 : CET,FUTURE,LONG */
+ {{UINT32_C(0x00000100),UINT32_C(0x00000010),UINT32_C(0x04000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 279 : ENQCMD,FUTURE,NOLONG,SZ */
+ {{UINT32_C(0x00000100),UINT32_C(0x00000000),UINT32_C(0x04000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 280 : ENQCMD,FUTURE,SZ */
+ {{UINT32_C(0x00000100),UINT32_C(0x00000020),UINT32_C(0x04000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 281 : ENQCMD,FUTURE,LONG,SZ */
+ {{UINT32_C(0x00000100),UINT32_C(0x00000011),UINT32_C(0x04000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 282 : ENQCMD,FUTURE,NOLONG,PRIV,SZ */
+ {{UINT32_C(0x00000100),UINT32_C(0x00000001),UINT32_C(0x04000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 283 : ENQCMD,FUTURE,PRIV,SZ */
+ {{UINT32_C(0x00000100),UINT32_C(0x00000021),UINT32_C(0x04000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 284 : ENQCMD,FUTURE,LONG,PRIV,SZ */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x08000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 285 : FUTURE,PCONFIG,PRIV */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x40000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 286 : FUTURE,SERIALIZE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000001),UINT32_C(0x10000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 287 : FUTURE,PRIV,WBNOINVD */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x20000000),UINT32_C(0x00000000),UINT32_C(0x00004000)}}, /* 288 : FUTURE,TSXLDTRK */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x80000000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 289 : AVX512BF16,EVEX,FUTURE */
+ {{UINT32_C(0x00000100),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00040002),UINT32_C(0x00004000)}}, /* 290 : AMXTILE,FUTURE,LONG,SZ,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00040004),UINT32_C(0x00004000)}}, /* 291 : AMXBF16,FUTURE,LONG,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00040008),UINT32_C(0x00004000)}}, /* 292 : AMXINT8,FUTURE,LONG,VEX */
+ {{UINT32_C(0x00000400),UINT32_C(0x000001a0),UINT32_C(0x00000000),UINT32_C(0x00040002),UINT32_C(0x00004000)}}, /* 293 : AMXTILE,FUTURE,LONG,MIB,SIB,SX,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00040002),UINT32_C(0x00004000)}}, /* 294 : AMXTILE,FUTURE,LONG,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00400080),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 295 : AVX512FP16,AVX512VL,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00400000),UINT32_C(0x00080000),UINT32_C(0x00004000)}}, /* 296 : AVX512FP16,EVEX,FUTURE */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00800000),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 297 : AVX512FC16,FUTURE,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00800080),UINT32_C(0x00040000),UINT32_C(0x00004000)}}, /* 298 : AVX512FC16,AVX512VL,FUTURE,VEX */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00004000)}}, /* 299 : FUTURE,RAOINT,SD */
+ {{UINT32_C(0x00000020),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00004000)}}, /* 300 : FUTURE,LONG,RAOINT,SQ */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00000040),UINT32_C(0x00004000)}}, /* 301 : FUTURE,LONG,UINTR */
+ {{UINT32_C(0x00000010),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00040080),UINT32_C(0x00004000)}}, /* 302 : CMPCCXADD,FUTURE,LONG,SD,VEX */
+ {{UINT32_C(0x00000020),UINT32_C(0x00000020),UINT32_C(0x00000000),UINT32_C(0x00040080),UINT32_C(0x00004000)}}, /* 303 : CMPCCXADD,FUTURE,LONG,SQ,VEX */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000021),UINT32_C(0x00000000),UINT32_C(0x00000200),UINT32_C(0x00004000)}}, /* 304 : FUTURE,LONG,PRIV,WRMSRNS */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000021),UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00004000)}}, /* 305 : FUTURE,LONG,MSRLIST,PRIV */
+ {{UINT32_C(0x00000004),UINT32_C(0x00000001),UINT32_C(0x00000000),UINT32_C(0x00004000),UINT32_C(0x00004000)}}, /* 306 : FUTURE,HRESET,PRIV,SB */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000400),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000040)}}, /* 307 : P6,UNDOC */
+ {{UINT32_C(0x00000000),UINT32_C(0x00000420),UINT32_C(0x00000000),UINT32_C(0x00000000),UINT32_C(0x00000400)}}, /* 308 : LONG,UNDOC,X86_64 */
+};
diff --git a/vere/ext/nasm/x86/iflaggen.h b/vere/ext/nasm/x86/iflaggen.h
new file mode 100644
index 0000000..fdaee3b
--- /dev/null
+++ b/vere/ext/nasm/x86/iflaggen.h
@@ -0,0 +1,287 @@
+/* This file is auto-generated. Don't edit. */
+#ifndef NASM_IFLAGGEN_H
+#define NASM_IFLAGGEN_H 1
+
+#define IF_SM 0 /* Size match */
+#define IF_SM2 1 /* Size match first two operands */
+#define IF_SB 2 /* Unsized operands can't be non-byte */
+#define IF_SW 3 /* Unsized operands can't be non-word */
+#define IF_SD 4 /* Unsized operands can't be non-dword */
+#define IF_SQ 5 /* Unsized operands can't be non-qword */
+#define IF_SO 6 /* Unsized operands can't be non-oword */
+#define IF_SY 7 /* Unsized operands can't be non-yword */
+#define IF_SZ 8 /* Unsized operands can't be non-zword */
+#define IF_SIZE 9 /* Unsized operands must match the bitsize */
+#define IF_SX 10 /* Unsized operands not allowed */
+#define IF_ANYSIZE 11 /* Ignore operand size even if explicit */
+#define IF_AR0 12 /* SB, SW, SD applies to argument 0 */
+#define IF_AR1 13 /* SB, SW, SD applies to argument 1 */
+#define IF_AR2 14 /* SB, SW, SD applies to argument 2 */
+#define IF_AR3 15 /* SB, SW, SD applies to argument 3 */
+#define IF_AR4 16 /* SB, SW, SD applies to argument 4 */
+#define IF_OPT 17 /* Optimizing assembly only */
+#define IF_LATEVEX 18 /* Only if EVEX instructions are disabled */
+ /* 18...31 reserved */
+#define IF_PRIV 32 /* Privileged instruction */
+#define IF_SMM 33 /* Only valid in SMM */
+#define IF_PROT 34 /* Protected mode only */
+#define IF_LOCK 35 /* Lockable if operand 0 is memory */
+#define IF_NOLONG 36 /* Not available in long mode */
+#define IF_LONG 37 /* Long mode */
+#define IF_NOHLE 38 /* HLE prefixes forbidden */
+#define IF_MIB 39 /* split base/index EA */
+#define IF_SIB 40 /* SIB encoding required */
+#define IF_BND 41 /* BND (0xF2) prefix available */
+#define IF_UNDOC 42 /* Undocumented */
+#define IF_HLE 43 /* HLE prefixed */
+#define IF_FPU 44 /* FPU */
+#define IF_MMX 45 /* MMX */
+#define IF_3DNOW 46 /* 3DNow! */
+#define IF_SSE 47 /* SSE (KNI, MMX2) */
+#define IF_SSE2 48 /* SSE2 */
+#define IF_SSE3 49 /* SSE3 (PNI) */
+#define IF_VMX 50 /* VMX */
+#define IF_SSSE3 51 /* SSSE3 */
+#define IF_SSE4A 52 /* AMD SSE4a */
+#define IF_SSE41 53 /* SSE4.1 */
+#define IF_SSE42 54 /* SSE4.2 */
+#define IF_SSE5 55 /* SSE5 */
+#define IF_AVX 56 /* AVX (256-bit floating point) */
+#define IF_AVX2 57 /* AVX2 (256-bit integer) */
+#define IF_FMA 58 /* */
+#define IF_BMI1 59 /* */
+#define IF_BMI2 60 /* */
+#define IF_TBM 61 /* */
+#define IF_RTM 62 /* */
+#define IF_INVPCID 63 /* */
+#define IF_AVX512 64 /* AVX-512F (512-bit base architecture) */
+#define IF_AVX512CD 65 /* AVX-512 Conflict Detection */
+#define IF_AVX512ER 66 /* AVX-512 Exponential and Reciprocal */
+#define IF_AVX512PF 67 /* AVX-512 Prefetch */
+#define IF_MPX 68 /* MPX */
+#define IF_SHA 69 /* SHA */
+#define IF_PREFETCHWT1 70 /* PREFETCHWT1 */
+#define IF_AVX512VL 71 /* AVX-512 Vector Length Orthogonality */
+#define IF_AVX512DQ 72 /* AVX-512 Dword and Qword */
+#define IF_AVX512BW 73 /* AVX-512 Byte and Word */
+#define IF_AVX512IFMA 74 /* AVX-512 IFMA instructions */
+#define IF_AVX512VBMI 75 /* AVX-512 VBMI instructions */
+#define IF_AES 76 /* AES instructions */
+#define IF_VAES 77 /* AES AVX instructions */
+#define IF_VPCLMULQDQ 78 /* AVX Carryless Multiplication */
+#define IF_GFNI 79 /* Galois Field instructions */
+#define IF_AVX512VBMI2 80 /* AVX-512 VBMI2 instructions */
+#define IF_AVX512VNNI 81 /* AVX-512 VNNI instructions */
+#define IF_AVX512BITALG 82 /* AVX-512 Bit Algorithm instructions */
+#define IF_AVX512VPOPCNTDQ 83 /* AVX-512 VPOPCNTD/VPOPCNTQ */
+#define IF_AVX5124FMAPS 84 /* AVX-512 4-iteration multiply-add */
+#define IF_AVX5124VNNIW 85 /* AVX-512 4-iteration dot product */
+#define IF_AVX512FP16 86 /* AVX-512 FP16 instructions */
+#define IF_AVX512FC16 87 /* AVX-512 FC16 instructions */
+#define IF_SGX 88 /* Intel Software Guard Extensions (SGX) */
+#define IF_CET 89 /* Intel Control-Flow Enforcement Technology (CET) */
+#define IF_ENQCMD 90 /* Enqueue command instructions */
+#define IF_PCONFIG 91 /* Platform configuration instruction */
+#define IF_WBNOINVD 92 /* Writeback and do not invalidate instruction */
+#define IF_TSXLDTRK 93 /* TSX suspend load address tracking */
+#define IF_SERIALIZE 94 /* SERIALIZE instruction */
+#define IF_AVX512BF16 95 /* AVX-512 bfloat16 */
+#define IF_AVX512VP2INTERSECT 96 /* AVX-512 VP2INTERSECT instructions */
+#define IF_AMXTILE 97 /* AMX tile configuration instructions */
+#define IF_AMXBF16 98 /* AMX bfloat16 multiplication */
+#define IF_AMXINT8 99 /* AMX 8-bit integer multiplication */
+#define IF_FRED 100 /* Flexible Return and Exception Delivery (FRED) */
+#define IF_RAOINT 101 /* Remote atomic operations (RAO-INT) */
+#define IF_UINTR 102 /* User interrupts */
+#define IF_CMPCCXADD 103 /* CMPccXADD instructions */
+#define IF_PREFETCHI 104 /* PREFETCHI0 and PREFETCHI1 */
+#define IF_WRMSRNS 105 /* WRMSRNS */
+#define IF_MSRLIST 106 /* RDMSRLIST and WRMSRLIST */
+#define IF_AVXNECONVERT 107 /* AVX exceptionless floating-point conversions */
+#define IF_AVXVNNIINT8 108 /* AVX Vector Neural Network 8-bit integer instructions */
+#define IF_AVXIFMA 109 /* AVX integer multiply and add */
+#define IF_HRESET 110 /* History reset */
+#define IF_OBSOLETE 111 /* Instruction removed from architecture */
+#define IF_NEVER 112 /* Instruction never implemented */
+#define IF_NOP 113 /* Instruction is always a (nonintentional) NOP */
+#define IF_VEX 114 /* VEX or XOP encoded instruction */
+#define IF_EVEX 115 /* EVEX encoded instruction */
+ /* 115...127 reserved */
+#define IF_8086 128 /* 8086 */
+#define IF_186 129 /* 186+ */
+#define IF_286 130 /* 286+ */
+#define IF_386 131 /* 386+ */
+#define IF_486 132 /* 486+ */
+#define IF_PENT 133 /* Pentium */
+#define IF_P6 134 /* P6 */
+#define IF_KATMAI 135 /* Katmai */
+#define IF_WILLAMETTE 136 /* Willamette */
+#define IF_PRESCOTT 137 /* Prescott */
+#define IF_X86_64 138 /* x86-64 (long or legacy mode) */
+#define IF_NEHALEM 139 /* Nehalem */
+#define IF_WESTMERE 140 /* Westmere */
+#define IF_SANDYBRIDGE 141 /* Sandy Bridge */
+#define IF_FUTURE 142 /* Ivy Bridge or newer */
+#define IF_IA64 143 /* IA64 (in x86 mode) */
+#define IF_DEFAULT 144 /* Default CPU level */
+#define IF_ANY 145 /* Allow any known instruction */
+#define IF_CYRIX 146 /* Cyrix-specific */
+#define IF_AMD 147 /* AMD-specific */
+ /* 147...159 reserved */
+
+/* Mask bits for field 0 : 0...31 */
+#define IFM_SM UINT32_C(0x00000001) /* 0 */
+#define IFM_SM2 UINT32_C(0x00000002) /* 1 */
+#define IFM_SB UINT32_C(0x00000004) /* 2 */
+#define IFM_SW UINT32_C(0x00000008) /* 3 */
+#define IFM_SD UINT32_C(0x00000010) /* 4 */
+#define IFM_SQ UINT32_C(0x00000020) /* 5 */
+#define IFM_SO UINT32_C(0x00000040) /* 6 */
+#define IFM_SY UINT32_C(0x00000080) /* 7 */
+#define IFM_SZ UINT32_C(0x00000100) /* 8 */
+#define IFM_SIZE UINT32_C(0x00000200) /* 9 */
+#define IFM_SX UINT32_C(0x00000400) /* 10 */
+#define IFM_ANYSIZE UINT32_C(0x00000800) /* 11 */
+#define IFM_AR0 UINT32_C(0x00001000) /* 12 */
+#define IFM_AR1 UINT32_C(0x00002000) /* 13 */
+#define IFM_AR2 UINT32_C(0x00004000) /* 14 */
+#define IFM_AR3 UINT32_C(0x00008000) /* 15 */
+#define IFM_AR4 UINT32_C(0x00010000) /* 16 */
+#define IFM_OPT UINT32_C(0x00020000) /* 17 */
+#define IFM_LATEVEX UINT32_C(0x00040000) /* 18 */
+/* Mask bits for field 1 : 32...63 */
+#define IFM_PRIV UINT32_C(0x00000001) /* 32 */
+#define IFM_SMM UINT32_C(0x00000002) /* 33 */
+#define IFM_PROT UINT32_C(0x00000004) /* 34 */
+#define IFM_LOCK UINT32_C(0x00000008) /* 35 */
+#define IFM_NOLONG UINT32_C(0x00000010) /* 36 */
+#define IFM_LONG UINT32_C(0x00000020) /* 37 */
+#define IFM_NOHLE UINT32_C(0x00000040) /* 38 */
+#define IFM_MIB UINT32_C(0x00000080) /* 39 */
+#define IFM_SIB UINT32_C(0x00000100) /* 40 */
+#define IFM_BND UINT32_C(0x00000200) /* 41 */
+#define IFM_UNDOC UINT32_C(0x00000400) /* 42 */
+#define IFM_HLE UINT32_C(0x00000800) /* 43 */
+#define IFM_FPU UINT32_C(0x00001000) /* 44 */
+#define IFM_MMX UINT32_C(0x00002000) /* 45 */
+#define IFM_3DNOW UINT32_C(0x00004000) /* 46 */
+#define IFM_SSE UINT32_C(0x00008000) /* 47 */
+#define IFM_SSE2 UINT32_C(0x00010000) /* 48 */
+#define IFM_SSE3 UINT32_C(0x00020000) /* 49 */
+#define IFM_VMX UINT32_C(0x00040000) /* 50 */
+#define IFM_SSSE3 UINT32_C(0x00080000) /* 51 */
+#define IFM_SSE4A UINT32_C(0x00100000) /* 52 */
+#define IFM_SSE41 UINT32_C(0x00200000) /* 53 */
+#define IFM_SSE42 UINT32_C(0x00400000) /* 54 */
+#define IFM_SSE5 UINT32_C(0x00800000) /* 55 */
+#define IFM_AVX UINT32_C(0x01000000) /* 56 */
+#define IFM_AVX2 UINT32_C(0x02000000) /* 57 */
+#define IFM_FMA UINT32_C(0x04000000) /* 58 */
+#define IFM_BMI1 UINT32_C(0x08000000) /* 59 */
+#define IFM_BMI2 UINT32_C(0x10000000) /* 60 */
+#define IFM_TBM UINT32_C(0x20000000) /* 61 */
+#define IFM_RTM UINT32_C(0x40000000) /* 62 */
+#define IFM_INVPCID UINT32_C(0x80000000) /* 63 */
+/* Mask bits for field 2 : 64...95 */
+#define IFM_AVX512 UINT32_C(0x00000001) /* 64 */
+#define IFM_AVX512CD UINT32_C(0x00000002) /* 65 */
+#define IFM_AVX512ER UINT32_C(0x00000004) /* 66 */
+#define IFM_AVX512PF UINT32_C(0x00000008) /* 67 */
+#define IFM_MPX UINT32_C(0x00000010) /* 68 */
+#define IFM_SHA UINT32_C(0x00000020) /* 69 */
+#define IFM_PREFETCHWT1 UINT32_C(0x00000040) /* 70 */
+#define IFM_AVX512VL UINT32_C(0x00000080) /* 71 */
+#define IFM_AVX512DQ UINT32_C(0x00000100) /* 72 */
+#define IFM_AVX512BW UINT32_C(0x00000200) /* 73 */
+#define IFM_AVX512IFMA UINT32_C(0x00000400) /* 74 */
+#define IFM_AVX512VBMI UINT32_C(0x00000800) /* 75 */
+#define IFM_AES UINT32_C(0x00001000) /* 76 */
+#define IFM_VAES UINT32_C(0x00002000) /* 77 */
+#define IFM_VPCLMULQDQ UINT32_C(0x00004000) /* 78 */
+#define IFM_GFNI UINT32_C(0x00008000) /* 79 */
+#define IFM_AVX512VBMI2 UINT32_C(0x00010000) /* 80 */
+#define IFM_AVX512VNNI UINT32_C(0x00020000) /* 81 */
+#define IFM_AVX512BITALG UINT32_C(0x00040000) /* 82 */
+#define IFM_AVX512VPOPCNTDQ UINT32_C(0x00080000) /* 83 */
+#define IFM_AVX5124FMAPS UINT32_C(0x00100000) /* 84 */
+#define IFM_AVX5124VNNIW UINT32_C(0x00200000) /* 85 */
+#define IFM_AVX512FP16 UINT32_C(0x00400000) /* 86 */
+#define IFM_AVX512FC16 UINT32_C(0x00800000) /* 87 */
+#define IFM_SGX UINT32_C(0x01000000) /* 88 */
+#define IFM_CET UINT32_C(0x02000000) /* 89 */
+#define IFM_ENQCMD UINT32_C(0x04000000) /* 90 */
+#define IFM_PCONFIG UINT32_C(0x08000000) /* 91 */
+#define IFM_WBNOINVD UINT32_C(0x10000000) /* 92 */
+#define IFM_TSXLDTRK UINT32_C(0x20000000) /* 93 */
+#define IFM_SERIALIZE UINT32_C(0x40000000) /* 94 */
+#define IFM_AVX512BF16 UINT32_C(0x80000000) /* 95 */
+/* Mask bits for field 3 : 96...127 */
+#define IFM_AVX512VP2INTERSECT UINT32_C(0x00000001) /* 96 */
+#define IFM_AMXTILE UINT32_C(0x00000002) /* 97 */
+#define IFM_AMXBF16 UINT32_C(0x00000004) /* 98 */
+#define IFM_AMXINT8 UINT32_C(0x00000008) /* 99 */
+#define IFM_FRED UINT32_C(0x00000010) /* 100 */
+#define IFM_RAOINT UINT32_C(0x00000020) /* 101 */
+#define IFM_UINTR UINT32_C(0x00000040) /* 102 */
+#define IFM_CMPCCXADD UINT32_C(0x00000080) /* 103 */
+#define IFM_PREFETCHI UINT32_C(0x00000100) /* 104 */
+#define IFM_WRMSRNS UINT32_C(0x00000200) /* 105 */
+#define IFM_MSRLIST UINT32_C(0x00000400) /* 106 */
+#define IFM_AVXNECONVERT UINT32_C(0x00000800) /* 107 */
+#define IFM_AVXVNNIINT8 UINT32_C(0x00001000) /* 108 */
+#define IFM_AVXIFMA UINT32_C(0x00002000) /* 109 */
+#define IFM_HRESET UINT32_C(0x00004000) /* 110 */
+#define IFM_OBSOLETE UINT32_C(0x00008000) /* 111 */
+#define IFM_NEVER UINT32_C(0x00010000) /* 112 */
+#define IFM_NOP UINT32_C(0x00020000) /* 113 */
+#define IFM_VEX UINT32_C(0x00040000) /* 114 */
+#define IFM_EVEX UINT32_C(0x00080000) /* 115 */
+/* Mask bits for field 4 : 128...159 */
+#define IFM_8086 UINT32_C(0x00000001) /* 128 */
+#define IFM_186 UINT32_C(0x00000002) /* 129 */
+#define IFM_286 UINT32_C(0x00000004) /* 130 */
+#define IFM_386 UINT32_C(0x00000008) /* 131 */
+#define IFM_486 UINT32_C(0x00000010) /* 132 */
+#define IFM_PENT UINT32_C(0x00000020) /* 133 */
+#define IFM_P6 UINT32_C(0x00000040) /* 134 */
+#define IFM_KATMAI UINT32_C(0x00000080) /* 135 */
+#define IFM_WILLAMETTE UINT32_C(0x00000100) /* 136 */
+#define IFM_PRESCOTT UINT32_C(0x00000200) /* 137 */
+#define IFM_X86_64 UINT32_C(0x00000400) /* 138 */
+#define IFM_NEHALEM UINT32_C(0x00000800) /* 139 */
+#define IFM_WESTMERE UINT32_C(0x00001000) /* 140 */
+#define IFM_SANDYBRIDGE UINT32_C(0x00002000) /* 141 */
+#define IFM_FUTURE UINT32_C(0x00004000) /* 142 */
+#define IFM_IA64 UINT32_C(0x00008000) /* 143 */
+#define IFM_DEFAULT UINT32_C(0x00010000) /* 144 */
+#define IFM_ANY UINT32_C(0x00020000) /* 145 */
+#define IFM_CYRIX UINT32_C(0x00040000) /* 146 */
+#define IFM_AMD UINT32_C(0x00080000) /* 147 */
+
+/* IF_SM (0) ... IF_LATEVEX (18) */
+#define IF_IGEN_FIRST 0
+#define IF_IGEN_COUNT 19
+#define IF_IGEN_FIELD 0
+#define IF_IGEN_NFIELDS 1
+
+/* IF_PRIV (32) ... IF_EVEX (115) */
+#define IF_FEATURE_FIRST 32
+#define IF_FEATURE_COUNT 84
+#define IF_FEATURE_FIELD 1
+#define IF_FEATURE_NFIELDS 3
+
+/* IF_8086 (128) ... IF_AMD (147) */
+#define IF_CPU_FIRST 128
+#define IF_CPU_COUNT 20
+#define IF_CPU_FIELD 4
+#define IF_CPU_NFIELDS 1
+
+#define IF_FIELD_COUNT 5
+typedef struct {
+ uint32_t field[IF_FIELD_COUNT];
+} iflag_t;
+
+/* All combinations of instruction flags used in instruction patterns */
+extern const iflag_t insns_flags[309];
+
+#endif /* NASM_IFLAGGEN_H */
diff --git a/vere/ext/nasm/x86/iflags.ph b/vere/ext/nasm/x86/iflags.ph
new file mode 100644
index 0000000..ffeb8e5
--- /dev/null
+++ b/vere/ext/nasm/x86/iflags.ph
@@ -0,0 +1,153 @@
+# -*- perl -*-
+
+#
+# dword bound, index 0 - specific flags
+#
+if_align('IGEN');
+
+if_("SM", "Size match");
+if_("SM2", "Size match first two operands");
+if_("SB", "Unsized operands can't be non-byte");
+if_("SW", "Unsized operands can't be non-word");
+if_("SD", "Unsized operands can't be non-dword");
+if_("SQ", "Unsized operands can't be non-qword");
+if_("SO", "Unsized operands can't be non-oword");
+if_("SY", "Unsized operands can't be non-yword");
+if_("SZ", "Unsized operands can't be non-zword");
+if_("SIZE", "Unsized operands must match the bitsize");
+if_("SX", "Unsized operands not allowed");
+if_("ANYSIZE", "Ignore operand size even if explicit");
+if_("AR0", "SB, SW, SD applies to argument 0");
+if_("AR1", "SB, SW, SD applies to argument 1");
+if_("AR2", "SB, SW, SD applies to argument 2");
+if_("AR3", "SB, SW, SD applies to argument 3");
+if_("AR4", "SB, SW, SD applies to argument 4");
+if_("OPT", "Optimizing assembly only");
+if_("LATEVEX", "Only if EVEX instructions are disabled");
+
+#
+# dword bound - instruction feature filtering flags
+#
+if_align('FEATURE');
+
+if_("PRIV", "Privileged instruction");
+if_("SMM", "Only valid in SMM");
+if_("PROT", "Protected mode only");
+if_("LOCK", "Lockable if operand 0 is memory");
+if_("NOLONG", "Not available in long mode");
+if_("LONG", "Long mode");
+if_("NOHLE", "HLE prefixes forbidden");
+if_("MIB", "split base/index EA");
+if_("SIB", "SIB encoding required");
+if_("BND", "BND (0xF2) prefix available");
+if_("UNDOC", "Undocumented");
+if_("HLE", "HLE prefixed");
+if_("FPU", "FPU");
+if_("MMX", "MMX");
+if_("3DNOW", "3DNow!");
+if_("SSE", "SSE (KNI, MMX2)");
+if_("SSE2", "SSE2");
+if_("SSE3", "SSE3 (PNI)");
+if_("VMX", "VMX");
+if_("SSSE3", "SSSE3");
+if_("SSE4A", "AMD SSE4a");
+if_("SSE41", "SSE4.1");
+if_("SSE42", "SSE4.2");
+if_("SSE5", "SSE5");
+if_("AVX", "AVX (256-bit floating point)");
+if_("AVX2", "AVX2 (256-bit integer)");
+if_("FMA", "");
+if_("BMI1", "");
+if_("BMI2", "");
+if_("TBM", "");
+if_("RTM", "");
+if_("INVPCID", "");
+if_("AVX512", "AVX-512F (512-bit base architecture)");
+if_("AVX512CD", "AVX-512 Conflict Detection");
+if_("AVX512ER", "AVX-512 Exponential and Reciprocal");
+if_("AVX512PF", "AVX-512 Prefetch");
+if_("MPX", "MPX");
+if_("SHA", "SHA");
+if_("PREFETCHWT1", "PREFETCHWT1");
+if_("AVX512VL", "AVX-512 Vector Length Orthogonality");
+if_("AVX512DQ", "AVX-512 Dword and Qword");
+if_("AVX512BW", "AVX-512 Byte and Word");
+if_("AVX512IFMA", "AVX-512 IFMA instructions");
+if_("AVX512VBMI", "AVX-512 VBMI instructions");
+if_("AES", "AES instructions");
+if_("VAES", "AES AVX instructions");
+if_("VPCLMULQDQ", "AVX Carryless Multiplication");
+if_("GFNI", "Galois Field instructions");
+if_("AVX512VBMI2", "AVX-512 VBMI2 instructions");
+if_("AVX512VNNI", "AVX-512 VNNI instructions");
+if_("AVX512BITALG", "AVX-512 Bit Algorithm instructions");
+if_("AVX512VPOPCNTDQ", "AVX-512 VPOPCNTD/VPOPCNTQ");
+if_("AVX5124FMAPS", "AVX-512 4-iteration multiply-add");
+if_("AVX5124VNNIW", "AVX-512 4-iteration dot product");
+if_("AVX512FP16", "AVX-512 FP16 instructions");
+if_("AVX512FC16", "AVX-512 FC16 instructions");
+if_("SGX", "Intel Software Guard Extensions (SGX)");
+if_("CET", "Intel Control-Flow Enforcement Technology (CET)");
+if_("ENQCMD", "Enqueue command instructions");
+if_("PCONFIG", "Platform configuration instruction");
+if_("WBNOINVD", "Writeback and do not invalidate instruction");
+if_("TSXLDTRK", "TSX suspend load address tracking");
+if_("SERIALIZE", "SERIALIZE instruction");
+if_("AVX512BF16", "AVX-512 bfloat16");
+if_("AVX512VP2INTERSECT", "AVX-512 VP2INTERSECT instructions");
+if_("AMXTILE", "AMX tile configuration instructions");
+if_("AMXBF16", "AMX bfloat16 multiplication");
+if_("AMXINT8", "AMX 8-bit integer multiplication");
+if_("FRED", "Flexible Return and Exception Delivery (FRED)");
+if_("RAOINT", "Remote atomic operations (RAO-INT)");
+if_("UINTR", "User interrupts");
+if_("CMPCCXADD", "CMPccXADD instructions");
+if_("PREFETCHI", "PREFETCHI0 and PREFETCHI1");
+if_("WRMSRNS", "WRMSRNS");
+if_("MSRLIST", "RDMSRLIST and WRMSRLIST");
+if_("AVXNECONVERT", "AVX exceptionless floating-point conversions");
+if_("AVXVNNIINT8", "AVX Vector Neural Network 8-bit integer instructions");
+if_("AVXIFMA", "AVX integer multiply and add");
+if_("HRESET", "History reset");
+
+# Put these last to minimize their relevance
+if_("OBSOLETE", "Instruction removed from architecture");
+if_("NEVER", "Instruction never implemented");
+if_("NOP", "Instruction is always a (nonintentional) NOP");
+if_("VEX", "VEX or XOP encoded instruction");
+if_("EVEX", "EVEX encoded instruction");
+
+#
+# dword bound - cpu type flags
+#
+# The CYRIX and AMD flags should have the highest bit values; the
+# disassembler selection algorithm depends on it.
+#
+if_align('CPU');
+
+if_("8086", "8086");
+if_("186", "186+");
+if_("286", "286+");
+if_("386", "386+");
+if_("486", "486+");
+if_("PENT", "Pentium");
+if_("P6", "P6");
+if_("KATMAI", "Katmai");
+if_("WILLAMETTE", "Willamette");
+if_("PRESCOTT", "Prescott");
+if_("X86_64", "x86-64 (long or legacy mode)");
+if_("NEHALEM", "Nehalem");
+if_("WESTMERE", "Westmere");
+if_("SANDYBRIDGE", "Sandy Bridge");
+if_("FUTURE", "Ivy Bridge or newer");
+if_("IA64", "IA64 (in x86 mode)");
+
+# Default CPU level
+if_("DEFAULT", "Default CPU level");
+
+# Must be the last CPU definition
+if_("ANY", "Allow any known instruction");
+
+# These must come after the CPU definitions proper
+if_("CYRIX", "Cyrix-specific");
+if_("AMD", "AMD-specific");
diff --git a/vere/ext/nasm/x86/insns-iflags.ph b/vere/ext/nasm/x86/insns-iflags.ph
new file mode 100644
index 0000000..3c73be9
--- /dev/null
+++ b/vere/ext/nasm/x86/insns-iflags.ph
@@ -0,0 +1,251 @@
+#!/usr/bin/perl
+## --------------------------------------------------------------------------
+##
+## Copyright 1996-2018 The NASM Authors - All Rights Reserved
+## See the file AUTHORS included with the NASM distribution for
+## the specific copyright holders.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following
+## conditions are met:
+##
+## * Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## * Redistributions in binary form must reproduce the above
+## copyright notice, this list of conditions and the following
+## disclaimer in the documentation and/or other materials provided
+## with the distribution.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##
+## --------------------------------------------------------------------------
+
+#
+# Instruction template flags. These specify which processor
+# targets the instruction is eligible for, whether it is
+# privileged or undocumented, and also specify extra error
+# checking on the matching of the instruction.
+#
+# IF_SM stands for Size Match: any operand whose size is not
+# explicitly specified by the template is `really' intended to be
+# the same size as the first size-specified operand.
+# Non-specification is tolerated in the input instruction, but
+# _wrong_ specification is not.
+#
+# IF_SM2 invokes Size Match on only the first _two_ operands, for
+# three-operand instructions such as SHLD: it implies that the
+# first two operands must match in size, but that the third is
+# required to be _unspecified_.
+#
+# IF_SB invokes Size Byte: operands with unspecified size in the
+# template are really bytes, and so no non-byte specification in
+# the input instruction will be tolerated. IF_SW similarly invokes
+# Size Word, and IF_SD invokes Size Doubleword.
+#
+# (The default state if neither IF_SM nor IF_SM2 is specified is
+# that any operand with unspecified size in the template is
+# required to have unspecified size in the instruction too...)
+#
+# iflag_t is defined to store these flags.
+#
+# The order does matter here. We use some predefined masks to quick test
+# for a set of flags, so be careful moving bits (and
+# don't forget to update C code generation then).
+#
+sub dword_align($) {
+ my($n) = @_;
+
+ $$n = ($$n + 31) & ~31;
+ return $n;
+}
+
+
+my $n_iflags = 0;
+my %flag_byname;
+my @flag_bynum;
+my @flag_fields;
+my $iflag_words;
+
+sub if_($$) {
+ my($name, $def) = @_;
+ my $num = $n_iflags++;
+ my $v = [$num, $name, $def];
+
+ $flag_byname{$name} = $v;
+ $flag_bynum[$num] = $v;
+
+ return 1;
+}
+sub if_align($) {
+ my($name) = @_;
+
+ if ($#flag_fields >= 0) {
+ $flag_fields[$#flag_fields]->[2] = $n_iflags-1;
+ }
+ $n_iflags = ($n_iflags + 31) & ~31;
+
+ if (defined($name)) {
+ push(@flag_fields, [$name, $n_iflags, undef]);
+ }
+
+ return 1;
+}
+
+sub if_end() {
+ if_align(undef);
+ $iflag_words = $n_iflags >> 5;
+}
+
+# The actual flags definitions
+require 'x86/iflags.ph';
+if_end();
+
+# Compute the combinations of instruction flags actually used in templates
+
+my %insns_flag_hash = ();
+my @insns_flag_values = ();
+my @insns_flag_lists = ();
+
+sub insns_flag_index(@) {
+ return undef if $_[0] eq "ignore";
+
+ my @prekey = sort(@_);
+ my $key = join(',', @prekey);
+ my $flag_index = $insns_flag_hash{$key};
+
+ unless (defined($flag_index)) {
+ my @newkey = (0) x $iflag_words;
+
+ foreach my $i (@prekey) {
+ my $flag = $flag_byname{$i};
+ die "No key for $i (in $key)\n" if not defined($flag);
+ $newkey[$flag->[0] >> 5] |= (1 << ($flag->[0] & 31));
+ }
+
+ my $str = join(',', map { sprintf("UINT32_C(0x%08x)",$_) } @newkey);
+
+ push @insns_flag_values, $str;
+ push @insns_flag_lists, $key;
+ $insns_flag_hash{$key} = $flag_index = $#insns_flag_values;
+ }
+
+ return $flag_index;
+}
+
+sub write_iflaggen_h() {
+ print STDERR "Writing $oname...\n";
+
+ open(N, '>', $oname) or die "$0: $!\n";
+
+ print N "/* This file is auto-generated. Don't edit. */\n";
+ print N "#ifndef NASM_IFLAGGEN_H\n";
+ print N "#define NASM_IFLAGGEN_H 1\n\n";
+
+ # The flag numbers; the <= in the loop is intentional
+
+ my $next = 0;
+ for ($i = 0; $i <= $n_iflags; $i++) {
+ if ((defined($flag_bynum[$i]) || $i >= $n_iflags) &&
+ $next != $i) {
+ printf N "%-31s /* %-64s */\n", '',
+ ($next < $i-1) ?
+ sprintf("%d...%d reserved", $next-1, $i-1) :
+ sprintf("%d reserved", $i-1);
+ }
+
+ if (defined($flag_bynum[$i])) {
+ printf N "#define IF_%-16s %3d /* %-64s */\n",
+ $flag_bynum[$i]->[1], $i, $flag_bynum[$i]->[2];
+ $next = $i+1;
+ }
+ }
+ print N "\n";
+
+ # The flag masks for individual bits
+
+ $next = 0;
+ for ($i = 0; $i < $n_iflags; $i++) {
+ if (($i & 31) == 0) {
+ printf N "/* Mask bits for field %d : %d...%d */\n",
+ $i >> 5, $i, $i+31;
+ }
+ if (defined(my $v = $flag_bynum[$i])) {
+ printf N "#define IFM_%-15s UINT32_C(0x%08x) /* %3d */\n",
+ $v->[1], 1 << ($i & 31), $i;
+ $next = $i+1;
+ }
+ }
+ print N "\n";
+
+ # The names of flag groups
+
+ for ($i = 0; $i <= $#flag_fields; $i++) {
+ printf N "/* IF_%s (%d) ... IF_%s (%d) */\n",
+ $flag_bynum[$flag_fields[$i]->[1]]->[1],
+ $flag_bynum[$flag_fields[$i]->[1]]->[0],
+ $flag_bynum[$flag_fields[$i]->[2]]->[1],
+ $flag_bynum[$flag_fields[$i]->[2]]->[0];
+
+ # Bit definitions
+ printf N "#define %-19s %3d\n",
+ 'IF_'.$flag_fields[$i]->[0].'_FIRST',
+ $flag_fields[$i]->[1];
+ printf N "#define %-19s %3d\n",
+ 'IF_'.$flag_fields[$i]->[0].'_COUNT',
+ ($flag_fields[$i]->[2] - $flag_fields[$i]->[1] + 1);
+
+ # Field (uint32) definitions
+ printf N "#define %-19s %3d\n",
+ 'IF_'.$flag_fields[$i]->[0].'_FIELD',
+ $flag_fields[$i]->[1] >> 5;
+ printf N "#define %-19s %3d\n",
+ 'IF_'.$flag_fields[$i]->[0].'_NFIELDS',
+ ($flag_fields[$i]->[2] - $flag_fields[$i]->[1] + 31) >> 5;
+ print N "\n";
+ }
+
+ printf N "#define IF_FIELD_COUNT %d\n", $iflag_words;
+ print N "typedef struct {\n";
+ print N " uint32_t field[IF_FIELD_COUNT];\n";
+ print N "} iflag_t;\n";
+
+ print N "\n";
+ print N "/* All combinations of instruction flags used in instruction patterns */\n";
+ printf N "extern const iflag_t insns_flags[%d];\n\n",
+ $#insns_flag_values + 1;
+
+ print N "#endif /* NASM_IFLAGGEN_H */\n";
+ close N;
+}
+
+sub write_iflag_c() {
+ print STDERR "Writing $oname...\n";
+
+ open(N, '>', $oname) or die "$0: $!\n";
+
+ print N "/* This file is auto-generated. Don't edit. */\n";
+ print N "#include \"iflag.h\"\n\n";
+ print N "/* All combinations of instruction flags used in instruction patterns */\n";
+ printf N "const iflag_t insns_flags[%d] = {\n",
+ $#insns_flag_values + 1;
+ foreach my $i (0 .. $#insns_flag_values) {
+ printf N " {{%s}}, /* %3d : %s */\n",
+ $insns_flag_values[$i], $i, $insns_flag_lists[$i];
+ }
+ print N "};\n";
+ close N;
+}
+
+1;
diff --git a/vere/ext/nasm/x86/insns.dat b/vere/ext/nasm/x86/insns.dat
new file mode 100644
index 0000000..17a3f10
--- /dev/null
+++ b/vere/ext/nasm/x86/insns.dat
@@ -0,0 +1,6570 @@
+;; --------------------------------------------------------------------------
+;;
+;; Copyright 1996-2022 The NASM Authors - All Rights Reserved
+;; See the file AUTHORS included with the NASM distribution for
+;; the specific copyright holders.
+;;
+;; Redistribution and use in source and binary forms, with or without
+;; modification, are permitted provided that the following
+;; conditions are met:
+;;
+;; * Redistributions of source code must retain the above copyright
+;; notice, this list of conditions and the following disclaimer.
+;; * Redistributions in binary form must reproduce the above
+;; copyright notice, this list of conditions and the following
+;; disclaimer in the documentation and/or other materials provided
+;; with the distribution.
+;;
+;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+;; CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+;; INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+;; MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+;; CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+;; SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+;; NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+;; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+;; HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+;; OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+;; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+;;
+;; --------------------------------------------------------------------------
+
+;
+; insns.dat table of instructions for the Netwide Assembler
+;
+; Format of file: All four fields must be present on every functional
+; line. Hence `void' for no-operand instructions, and `\0' for such
+; as EQU. If the last three fields are all `ignore', no action is
+; taken except to register the opcode as being present.
+;
+; For a detailed description of the code string (third field), please
+; see insns.pl and the comment at the top of assemble.c. For a detailed
+; description of the flags (fourth field), please see insns-iflags.ph.
+;
+; Comments with a pound sign after the semicolon generate section
+; subheaders in the NASM documentation.
+;
+
+;# Special instructions (pseudo-ops)
+; These MUST be first in this file and must maintain the pattern of
+; Dx by size, RESx by size, and INCBIN in that order.
+DB ignore ignore ignore
+DW ignore ignore ignore
+DD ignore ignore ignore
+DQ ignore ignore ignore
+DT ignore ignore ignore
+DO ignore ignore ignore
+DY ignore ignore ignore
+DZ ignore ignore ignore
+RESB imm [ resb] 8086
+RESW imm [ resb] 8086
+RESD imm [ resb] 8086
+RESQ imm [ resb] 8086
+REST imm [ resb] 8086
+RESO imm [ resb] 8086
+RESY imm [ resb] 8086
+RESZ imm [ resb] 8086
+INCBIN ignore ignore ignore
+
+;# Conventional instructions
+AAA void [ 37] 8086,NOLONG
+AAD void [ d5 0a] 8086,NOLONG
+AAD imm [i: d5 ib,u] 8086,SB,NOLONG
+AAM void [ d4 0a] 8086,NOLONG
+AAM imm [i: d4 ib,u] 8086,SB,NOLONG
+AAS void [ 3f] 8086,NOLONG
+ADC mem,reg8 [mr: hle 10 /r] 8086,SM,LOCK
+ADC reg8,reg8 [mr: 10 /r] 8086
+ADC mem,reg16 [mr: hle o16 11 /r] 8086,SM,LOCK
+ADC reg16,reg16 [mr: o16 11 /r] 8086
+ADC mem,reg32 [mr: hle o32 11 /r] 386,SM,LOCK
+ADC reg32,reg32 [mr: o32 11 /r] 386
+ADC mem,reg64 [mr: hle o64 11 /r] X86_64,LONG,SM,LOCK
+ADC reg64,reg64 [mr: o64 11 /r] X86_64,LONG
+ADC reg8,mem [rm: 12 /r] 8086,SM
+ADC reg8,reg8 [rm: 12 /r] 8086
+ADC reg16,mem [rm: o16 13 /r] 8086,SM
+ADC reg16,reg16 [rm: o16 13 /r] 8086
+ADC reg32,mem [rm: o32 13 /r] 386,SM
+ADC reg32,reg32 [rm: o32 13 /r] 386
+ADC reg64,mem [rm: o64 13 /r] X86_64,LONG,SM
+ADC reg64,reg64 [rm: o64 13 /r] X86_64,LONG
+ADC rm16,imm8 [mi: hle o16 83 /2 ib,s] 8086,LOCK
+ADC rm32,imm8 [mi: hle o32 83 /2 ib,s] 386,LOCK
+ADC rm64,imm8 [mi: hle o64 83 /2 ib,s] X86_64,LONG,LOCK
+ADC reg_al,imm [-i: 14 ib] 8086,SM
+ADC reg_ax,sbyteword [mi: o16 83 /2 ib,s] 8086,SM,ND
+ADC reg_ax,imm [-i: o16 15 iw] 8086,SM
+ADC reg_eax,sbytedword [mi: o32 83 /2 ib,s] 386,SM,ND
+ADC reg_eax,imm [-i: o32 15 id] 386,SM
+ADC reg_rax,sbytedword [mi: o64 83 /2 ib,s] X86_64,LONG,SM,ND
+ADC reg_rax,imm [-i: o64 15 id,s] X86_64,LONG,SM
+ADC rm8,imm [mi: hle 80 /2 ib] 8086,SM,LOCK
+ADC rm16,sbyteword [mi: hle o16 83 /2 ib,s] 8086,SM,LOCK,ND
+ADC rm16,imm [mi: hle o16 81 /2 iw] 8086,SM,LOCK
+ADC rm32,sbytedword [mi: hle o32 83 /2 ib,s] 386,SM,LOCK,ND
+ADC rm32,imm [mi: hle o32 81 /2 id] 386,SM,LOCK
+ADC rm64,sbytedword [mi: hle o64 83 /2 ib,s] X86_64,LONG,SM,LOCK,ND
+ADC rm64,imm [mi: hle o64 81 /2 id,s] X86_64,LONG,SM,LOCK
+ADC mem,imm8 [mi: hle 80 /2 ib] 8086,SM,LOCK,ND
+ADC mem,sbyteword16 [mi: hle o16 83 /2 ib,s] 8086,SM,LOCK,ND
+ADC mem,imm16 [mi: hle o16 81 /2 iw] 8086,SM,LOCK
+ADC mem,sbytedword32 [mi: hle o32 83 /2 ib,s] 386,SM,LOCK,ND
+ADC mem,imm32 [mi: hle o32 81 /2 id] 386,SM,LOCK
+ADC rm8,imm [mi: hle 82 /2 ib] 8086,SM,LOCK,ND,NOLONG
+ADD mem,reg8 [mr: hle 00 /r] 8086,SM,LOCK
+ADD reg8,reg8 [mr: 00 /r] 8086
+ADD mem,reg16 [mr: hle o16 01 /r] 8086,SM,LOCK
+ADD reg16,reg16 [mr: o16 01 /r] 8086
+ADD mem,reg32 [mr: hle o32 01 /r] 386,SM,LOCK
+ADD reg32,reg32 [mr: o32 01 /r] 386
+ADD mem,reg64 [mr: hle o64 01 /r] X86_64,LONG,SM,LOCK
+ADD reg64,reg64 [mr: o64 01 /r] X86_64,LONG
+ADD reg8,mem [rm: 02 /r] 8086,SM
+ADD reg8,reg8 [rm: 02 /r] 8086
+ADD reg16,mem [rm: o16 03 /r] 8086,SM
+ADD reg16,reg16 [rm: o16 03 /r] 8086
+ADD reg32,mem [rm: o32 03 /r] 386,SM
+ADD reg32,reg32 [rm: o32 03 /r] 386
+ADD reg64,mem [rm: o64 03 /r] X86_64,LONG,SM
+ADD reg64,reg64 [rm: o64 03 /r] X86_64,LONG
+ADD rm16,imm8 [mi: hle o16 83 /0 ib,s] 8086,LOCK
+ADD rm32,imm8 [mi: hle o32 83 /0 ib,s] 386,LOCK
+ADD rm64,imm8 [mi: hle o64 83 /0 ib,s] X86_64,LONG,LOCK
+ADD reg_al,imm [-i: 04 ib] 8086,SM
+ADD reg_ax,sbyteword [mi: o16 83 /0 ib,s] 8086,SM,ND
+ADD reg_ax,imm [-i: o16 05 iw] 8086,SM
+ADD reg_eax,sbytedword [mi: o32 83 /0 ib,s] 386,SM,ND
+ADD reg_eax,imm [-i: o32 05 id] 386,SM
+ADD reg_rax,sbytedword [mi: o64 83 /0 ib,s] X86_64,LONG,SM,ND
+ADD reg_rax,imm [-i: o64 05 id,s] X86_64,LONG,SM
+ADD rm8,imm [mi: hle 80 /0 ib] 8086,SM,LOCK
+ADD rm16,sbyteword [mi: hle o16 83 /0 ib,s] 8086,SM,LOCK,ND
+ADD rm16,imm [mi: hle o16 81 /0 iw] 8086,SM,LOCK
+ADD rm32,sbytedword [mi: hle o32 83 /0 ib,s] 386,SM,LOCK,ND
+ADD rm32,imm [mi: hle o32 81 /0 id] 386,SM,LOCK
+ADD rm64,sbytedword [mi: hle o64 83 /0 ib,s] X86_64,LONG,SM,LOCK,ND
+ADD rm64,imm [mi: hle o64 81 /0 id,s] X86_64,LONG,SM,LOCK
+ADD mem,imm8 [mi: hle 80 /0 ib] 8086,SM,LOCK
+ADD mem,sbyteword16 [mi: hle o16 83 /0 ib,s] 8086,SM,LOCK,ND
+ADD mem,imm16 [mi: hle o16 81 /0 iw] 8086,SM,LOCK
+ADD mem,sbytedword32 [mi: hle o32 83 /0 ib,s] 386,SM,LOCK,ND
+ADD mem,imm32 [mi: hle o32 81 /0 id] 386,SM,LOCK
+ADD rm8,imm [mi: hle 82 /0 ib] 8086,SM,LOCK,ND,NOLONG
+AND mem,reg8 [mr: hle 20 /r] 8086,SM,LOCK
+AND reg8,reg8 [mr: 20 /r] 8086
+AND mem,reg16 [mr: hle o16 21 /r] 8086,SM,LOCK
+AND reg16,reg16 [mr: o16 21 /r] 8086
+AND mem,reg32 [mr: hle o32 21 /r] 386,SM,LOCK
+AND reg32,reg32 [mr: o32 21 /r] 386
+AND mem,reg64 [mr: hle o64 21 /r] X86_64,LONG,SM,LOCK
+AND reg64,reg64 [mr: o64 21 /r] X86_64,LONG
+AND reg8,mem [rm: 22 /r] 8086,SM
+AND reg8,reg8 [rm: 22 /r] 8086
+AND reg16,mem [rm: o16 23 /r] 8086,SM
+AND reg16,reg16 [rm: o16 23 /r] 8086
+AND reg32,mem [rm: o32 23 /r] 386,SM
+AND reg32,reg32 [rm: o32 23 /r] 386
+AND reg64,mem [rm: o64 23 /r] X86_64,LONG,SM
+AND reg64,reg64 [rm: o64 23 /r] X86_64,LONG
+AND rm16,imm8 [mi: hle o16 83 /4 ib,s] 8086,LOCK
+AND rm32,imm8 [mi: hle o32 83 /4 ib,s] 386,LOCK
+AND rm64,imm8 [mi: hle o64 83 /4 ib,s] X86_64,LONG,LOCK
+AND reg_al,imm [-i: 24 ib] 8086,SM
+AND reg_ax,sbyteword [mi: o16 83 /4 ib,s] 8086,SM,ND
+AND reg_ax,imm [-i: o16 25 iw] 8086,SM
+AND reg_eax,sbytedword [mi: o32 83 /4 ib,s] 386,SM,ND
+AND reg_eax,imm [-i: o32 25 id] 386,SM
+AND reg_rax,sbytedword [mi: o64 83 /4 ib,s] X86_64,LONG,SM,ND
+AND reg_rax,imm [-i: o64 25 id,s] X86_64,LONG,SM
+AND rm8,imm [mi: hle 80 /4 ib] 8086,SM,LOCK
+AND rm16,sbyteword [mi: hle o16 83 /4 ib,s] 8086,SM,LOCK,ND
+AND rm16,imm [mi: hle o16 81 /4 iw] 8086,SM,LOCK
+AND rm32,sbytedword [mi: hle o32 83 /4 ib,s] 386,SM,LOCK,ND
+AND rm32,imm [mi: hle o32 81 /4 id] 386,SM,LOCK
+AND rm64,sbytedword [mi: hle o64 83 /4 ib,s] X86_64,LONG,SM,LOCK,ND
+AND rm64,imm [mi: hle o64 81 /4 id,s] X86_64,LONG,SM,LOCK
+AND mem,imm8 [mi: hle 80 /4 ib] 8086,SM,LOCK
+AND mem,sbyteword16 [mi: hle o16 83 /4 ib,s] 8086,SM,LOCK,ND
+AND mem,imm16 [mi: hle o16 81 /4 iw] 8086,SM,LOCK
+AND mem,sbytedword32 [mi: hle o32 83 /4 ib,s] 386,SM,LOCK,ND
+AND mem,imm32 [mi: hle o32 81 /4 id] 386,SM,LOCK
+AND rm8,imm [mi: hle 82 /4 ib] 8086,SM,LOCK,ND,NOLONG
+ARPL mem,reg16 [mr: 63 /r] 286,PROT,SM,NOLONG
+ARPL reg16,reg16 [mr: 63 /r] 286,PROT,NOLONG
+BB0_RESET void [ 0f 3a] PENT,CYRIX,ND,OBSOLETE
+BB1_RESET void [ 0f 3b] PENT,CYRIX,ND,OBSOLETE
+BOUND reg16,mem [rm: o16 62 /r] 186,NOLONG
+BOUND reg32,mem [rm: o32 62 /r] 386,NOLONG
+BSF reg16,mem [rm: o16 nof3 0f bc /r] 386,SM
+BSF reg16,reg16 [rm: o16 nof3 0f bc /r] 386
+BSF reg32,mem [rm: o32 nof3 0f bc /r] 386,SM
+BSF reg32,reg32 [rm: o32 nof3 0f bc /r] 386
+BSF reg64,mem [rm: o64 nof3 0f bc /r] X86_64,LONG,SM
+BSF reg64,reg64 [rm: o64 nof3 0f bc /r] X86_64,LONG
+BSR reg16,mem [rm: o16 nof3 0f bd /r] 386,SM
+BSR reg16,reg16 [rm: o16 nof3 0f bd /r] 386
+BSR reg32,mem [rm: o32 nof3 0f bd /r] 386,SM
+BSR reg32,reg32 [rm: o32 nof3 0f bd /r] 386
+BSR reg64,mem [rm: o64 nof3 0f bd /r] X86_64,LONG,SM
+BSR reg64,reg64 [rm: o64 nof3 0f bd /r] X86_64,LONG
+BSWAP reg32 [r: o32 0f c8+r] 486
+BSWAP reg64 [r: o64 0f c8+r] X86_64,LONG
+BT mem,reg16 [mr: o16 0f a3 /r] 386,SM
+BT reg16,reg16 [mr: o16 0f a3 /r] 386
+BT mem,reg32 [mr: o32 0f a3 /r] 386,SM
+BT reg32,reg32 [mr: o32 0f a3 /r] 386
+BT mem,reg64 [mr: o64 0f a3 /r] X86_64,LONG,SM
+BT reg64,reg64 [mr: o64 0f a3 /r] X86_64,LONG
+BT rm16,imm8 [mi: o16 0f ba /4 ib,u] 386
+BT rm32,imm8 [mi: o32 0f ba /4 ib,u] 386
+BT rm64,imm8 [mi: o64 0f ba /4 ib,u] X86_64,LONG
+BTC mem,reg16 [mr: hle o16 0f bb /r] 386,SM,LOCK
+BTC reg16,reg16 [mr: o16 0f bb /r] 386
+BTC mem,reg32 [mr: hle o32 0f bb /r] 386,SM,LOCK
+BTC reg32,reg32 [mr: o32 0f bb /r] 386
+BTC mem,reg64 [mr: hle o64 0f bb /r] X86_64,LONG,SM,LOCK
+BTC reg64,reg64 [mr: o64 0f bb /r] X86_64,LONG
+BTC rm16,imm8 [mi: hle o16 0f ba /7 ib,u] 386,LOCK
+BTC rm32,imm8 [mi: hle o32 0f ba /7 ib,u] 386,LOCK
+BTC rm64,imm8 [mi: hle o64 0f ba /7 ib,u] X86_64,LONG,LOCK
+BTR mem,reg16 [mr: hle o16 0f b3 /r] 386,SM,LOCK
+BTR reg16,reg16 [mr: o16 0f b3 /r] 386
+BTR mem,reg32 [mr: hle o32 0f b3 /r] 386,SM,LOCK
+BTR reg32,reg32 [mr: o32 0f b3 /r] 386
+BTR mem,reg64 [mr: hle o64 0f b3 /r] X86_64,LONG,SM,LOCK
+BTR reg64,reg64 [mr: o64 0f b3 /r] X86_64,LONG
+BTR rm16,imm8 [mi: hle o16 0f ba /6 ib,u] 386,LOCK
+BTR rm32,imm8 [mi: hle o32 0f ba /6 ib,u] 386,LOCK
+BTR rm64,imm8 [mi: hle o64 0f ba /6 ib,u] X86_64,LONG,LOCK
+BTS mem,reg16 [mr: hle o16 0f ab /r] 386,SM,LOCK
+BTS reg16,reg16 [mr: o16 0f ab /r] 386
+BTS mem,reg32 [mr: hle o32 0f ab /r] 386,SM,LOCK
+BTS reg32,reg32 [mr: o32 0f ab /r] 386
+BTS mem,reg64 [mr: hle o64 0f ab /r] X86_64,LONG,SM,LOCK
+BTS reg64,reg64 [mr: o64 0f ab /r] X86_64,LONG
+BTS rm16,imm8 [mi: hle o16 0f ba /5 ib,u] 386,LOCK
+BTS rm32,imm8 [mi: hle o32 0f ba /5 ib,u] 386,LOCK
+BTS rm64,imm8 [mi: hle o64 0f ba /5 ib,u] X86_64,LONG,LOCK
+CALL imm [i: odf e8 rel] 8086,BND
+CALL imm|near [i: odf e8 rel] 8086,ND,BND
+CALL imm|far [i: odf 9a iwd seg] 8086,ND,NOLONG
+; Call/jmp near imm/reg/mem is always 64-bit in long mode.
+CALL imm16 [i: o16 e8 rel] 8086,NOLONG,BND
+CALL imm16|near [i: o16 e8 rel] 8086,ND,NOLONG,BND
+CALL imm16|far [i: o16 9a iwd seg] 8086,ND,NOLONG
+CALL imm32 [i: o32 e8 rel] 386,NOLONG,BND
+CALL imm32|near [i: o32 e8 rel] 386,ND,NOLONG,BND
+CALL imm32|far [i: o32 9a iwd seg] 386,ND,NOLONG
+CALL imm64 [i: o64nw e8 rel] X86_64,LONG,BND
+CALL imm64|near [i: o64nw e8 rel] X86_64,LONG,ND,BND
+CALL imm:imm [ji: odf 9a iwd iw] 8086,NOLONG
+CALL imm16:imm [ji: o16 9a iw iw] 8086,NOLONG
+CALL imm:imm16 [ji: o16 9a iw iw] 8086,NOLONG
+CALL imm32:imm [ji: o32 9a id iw] 386,NOLONG
+CALL imm:imm32 [ji: o32 9a id iw] 386,NOLONG
+CALL mem|far [m: odf ff /3] 8086,NOLONG
+CALL mem|far [m: o64 ff /3] X86_64,LONG
+CALL mem16|far [m: o16 ff /3] 8086
+CALL mem32|far [m: o32 ff /3] 386
+CALL mem64|far [m: o64 ff /3] X86_64,LONG
+CALL mem|near [m: odf ff /2] 8086,ND,BND
+CALL rm16|near [m: o16 ff /2] 8086,NOLONG,ND,BND
+CALL rm32|near [m: o32 ff /2] 386,NOLONG,ND,BND
+CALL rm64|near [m: o64nw ff /2] X86_64,LONG,ND,BND
+CALL mem [m: odf ff /2] 8086,BND
+CALL rm16 [m: o16 ff /2] 8086,NOLONG,BND
+CALL rm32 [m: o32 ff /2] 386,NOLONG,BND
+CALL rm64 [m: o64nw ff /2] X86_64,LONG,BND
+
+CBW void [ o16 98] 8086
+CDQ void [ o32 99] 386
+CDQE void [ o64 98] X86_64,LONG
+CLC void [ f8] 8086
+CLD void [ fc] 8086
+CLI void [ fa] 8086
+CLTS void [ 0f 06] 286,PRIV
+CMC void [ f5] 8086
+CMP mem,reg8 [mr: 38 /r] 8086,SM
+CMP reg8,reg8 [mr: 38 /r] 8086
+CMP mem,reg16 [mr: o16 39 /r] 8086,SM
+CMP reg16,reg16 [mr: o16 39 /r] 8086
+CMP mem,reg32 [mr: o32 39 /r] 386,SM
+CMP reg32,reg32 [mr: o32 39 /r] 386
+CMP mem,reg64 [mr: o64 39 /r] X86_64,LONG,SM
+CMP reg64,reg64 [mr: o64 39 /r] X86_64,LONG
+CMP reg8,mem [rm: 3a /r] 8086,SM
+CMP reg8,reg8 [rm: 3a /r] 8086
+CMP reg16,mem [rm: o16 3b /r] 8086,SM
+CMP reg16,reg16 [rm: o16 3b /r] 8086
+CMP reg32,mem [rm: o32 3b /r] 386,SM
+CMP reg32,reg32 [rm: o32 3b /r] 386
+CMP reg64,mem [rm: o64 3b /r] X86_64,LONG,SM
+CMP reg64,reg64 [rm: o64 3b /r] X86_64,LONG
+CMP rm16,imm8 [mi: o16 83 /7 ib,s] 8086
+CMP rm32,imm8 [mi: o32 83 /7 ib,s] 386
+CMP rm64,imm8 [mi: o64 83 /7 ib,s] X86_64,LONG
+CMP reg_al,imm [-i: 3c ib] 8086,SM
+CMP reg_ax,sbyteword [mi: o16 83 /7 ib,s] 8086,SM,ND
+CMP reg_ax,imm [-i: o16 3d iw] 8086,SM
+CMP reg_eax,sbytedword [mi: o32 83 /7 ib,s] 386,SM,ND
+CMP reg_eax,imm [-i: o32 3d id] 386,SM
+CMP reg_rax,sbytedword [mi: o64 83 /7 ib,s] X86_64,LONG,SM,ND
+CMP reg_rax,imm [-i: o64 3d id,s] X86_64,LONG,SM
+CMP rm8,imm [mi: 80 /7 ib] 8086,SM
+CMP rm16,sbyteword [mi: o16 83 /7 ib,s] 8086,SM,ND
+CMP rm16,imm [mi: o16 81 /7 iw] 8086,SM
+CMP rm32,sbytedword [mi: o32 83 /7 ib,s] 386,SM,ND
+CMP rm32,imm [mi: o32 81 /7 id] 386,SM
+CMP rm64,sbytedword [mi: o64 83 /7 ib,s] X86_64,LONG,SM,ND
+CMP rm64,imm [mi: o64 81 /7 id,s] X86_64,LONG,SM
+CMP mem,imm8 [mi: 80 /7 ib] 8086,SM
+CMP mem,sbyteword16 [mi: o16 83 /7 ib,s] 8086,SM,ND
+CMP mem,imm16 [mi: o16 81 /7 iw] 8086,SM
+CMP mem,sbytedword32 [mi: o32 83 /7 ib,s] 386,SM,ND
+CMP mem,imm32 [mi: o32 81 /7 id] 386,SM
+CMP rm8,imm [mi: 82 /7 ib] 8086,SM,ND,NOLONG
+CMPSB void [ repe a6] 8086
+CMPSD void [ repe o32 a7] 386
+CMPSQ void [ repe o64 a7] X86_64,LONG
+CMPSW void [ repe o16 a7] 8086
+CMPXCHG mem,reg8 [mr: hle 0f b0 /r] PENT,SM,LOCK
+CMPXCHG reg8,reg8 [mr: 0f b0 /r] PENT
+CMPXCHG mem,reg16 [mr: hle o16 0f b1 /r] PENT,SM,LOCK
+CMPXCHG reg16,reg16 [mr: o16 0f b1 /r] PENT
+CMPXCHG mem,reg32 [mr: hle o32 0f b1 /r] PENT,SM,LOCK
+CMPXCHG reg32,reg32 [mr: o32 0f b1 /r] PENT
+CMPXCHG mem,reg64 [mr: hle o64 0f b1 /r] X86_64,LONG,SM,LOCK
+CMPXCHG reg64,reg64 [mr: o64 0f b1 /r] X86_64,LONG
+CMPXCHG486 mem,reg8 [mr: 0f a6 /r] 486,SM,UNDOC,ND,LOCK,OBSOLETE
+CMPXCHG486 reg8,reg8 [mr: 0f a6 /r] 486,UNDOC,ND,OBSOLETE
+CMPXCHG486 mem,reg16 [mr: o16 0f a7 /r] 486,SM,UNDOC,ND,LOCK,OBSOLETE
+CMPXCHG486 reg16,reg16 [mr: o16 0f a7 /r] 486,UNDOC,ND,OBSOLETE
+CMPXCHG486 mem,reg32 [mr: o32 0f a7 /r] 486,SM,UNDOC,ND,LOCK,OBSOLETE
+CMPXCHG486 reg32,reg32 [mr: o32 0f a7 /r] 486,UNDOC,ND,OBSOLETE
+CMPXCHG8B mem64 [m: hle norexw 0f c7 /1] PENT,LOCK
+CMPXCHG16B mem128 [m: o64 0f c7 /1] X86_64,LONG,LOCK
+CPUID void [ 0f a2] PENT
+CPU_READ void [ 0f 3d] PENT,CYRIX
+CPU_WRITE void [ 0f 3c] PENT,CYRIX
+CQO void [ o64 99] X86_64,LONG
+CWD void [ o16 99] 8086
+CWDE void [ o32 98] 386
+DAA void [ 27] 8086,NOLONG
+DAS void [ 2f] 8086,NOLONG
+DEC reg16 [r: o16 48+r] 8086,NOLONG
+DEC reg32 [r: o32 48+r] 386,NOLONG
+DEC rm8 [m: hle fe /1] 8086,LOCK
+DEC rm16 [m: hle o16 ff /1] 8086,LOCK
+DEC rm32 [m: hle o32 ff /1] 386,LOCK
+DEC rm64 [m: hle o64 ff /1] X86_64,LONG,LOCK
+DIV rm8 [m: f6 /6] 8086
+DIV rm16 [m: o16 f7 /6] 8086
+DIV rm32 [m: o32 f7 /6] 386
+DIV rm64 [m: o64 f7 /6] X86_64,LONG
+DMINT void [ 0f 39] P6,CYRIX
+EMMS void [ 0f 77] PENT,MMX
+ENTER imm,imm [ij: c8 iw ib,u] 186
+EQU imm ignore 8086
+EQU imm:imm ignore 8086
+F2XM1 void [ d9 f0] 8086,FPU
+FABS void [ d9 e1] 8086,FPU
+FADD mem32 [m: d8 /0] 8086,FPU
+FADD mem64 [m: dc /0] 8086,FPU
+FADD fpureg|to [r: dc c0+r] 8086,FPU
+FADD fpureg [r: d8 c0+r] 8086,FPU
+FADD fpureg,fpu0 [r-: dc c0+r] 8086,FPU
+FADD fpu0,fpureg [-r: d8 c0+r] 8086,FPU
+FADD void [ de c1] 8086,FPU,ND
+FADDP fpureg [r: de c0+r] 8086,FPU
+FADDP fpureg,fpu0 [r-: de c0+r] 8086,FPU
+FADDP void [ de c1] 8086,FPU,ND
+FBLD mem80 [m: df /4] 8086,FPU
+FBLD mem [m: df /4] 8086,FPU
+FBSTP mem80 [m: df /6] 8086,FPU
+FBSTP mem [m: df /6] 8086,FPU
+FCHS void [ d9 e0] 8086,FPU
+FCLEX void [ wait db e2] 8086,FPU
+FCMOVB fpureg [r: da c0+r] P6,FPU
+FCMOVB fpu0,fpureg [-r: da c0+r] P6,FPU
+FCMOVB void [ da c1] P6,FPU,ND
+FCMOVBE fpureg [r: da d0+r] P6,FPU
+FCMOVBE fpu0,fpureg [-r: da d0+r] P6,FPU
+FCMOVBE void [ da d1] P6,FPU,ND
+FCMOVE fpureg [r: da c8+r] P6,FPU
+FCMOVE fpu0,fpureg [-r: da c8+r] P6,FPU
+FCMOVE void [ da c9] P6,FPU,ND
+FCMOVNB fpureg [r: db c0+r] P6,FPU
+FCMOVNB fpu0,fpureg [-r: db c0+r] P6,FPU
+FCMOVNB void [ db c1] P6,FPU,ND
+FCMOVNBE fpureg [r: db d0+r] P6,FPU
+FCMOVNBE fpu0,fpureg [-r: db d0+r] P6,FPU
+FCMOVNBE void [ db d1] P6,FPU,ND
+FCMOVNE fpureg [r: db c8+r] P6,FPU
+FCMOVNE fpu0,fpureg [-r: db c8+r] P6,FPU
+FCMOVNE void [ db c9] P6,FPU,ND
+FCMOVNU fpureg [r: db d8+r] P6,FPU
+FCMOVNU fpu0,fpureg [-r: db d8+r] P6,FPU
+FCMOVNU void [ db d9] P6,FPU,ND
+FCMOVU fpureg [r: da d8+r] P6,FPU
+FCMOVU fpu0,fpureg [-r: da d8+r] P6,FPU
+FCMOVU void [ da d9] P6,FPU,ND
+FCOM mem32 [m: d8 /2] 8086,FPU
+FCOM mem64 [m: dc /2] 8086,FPU
+FCOM fpureg [r: d8 d0+r] 8086,FPU
+FCOM fpu0,fpureg [-r: d8 d0+r] 8086,FPU
+FCOM void [ d8 d1] 8086,FPU,ND
+FCOMI fpureg [r: db f0+r] P6,FPU
+FCOMI fpu0,fpureg [-r: db f0+r] P6,FPU
+FCOMI void [ db f1] P6,FPU,ND
+FCOMIP fpureg [r: df f0+r] P6,FPU
+FCOMIP fpu0,fpureg [-r: df f0+r] P6,FPU
+FCOMIP void [ df f1] P6,FPU,ND
+FCOMP mem32 [m: d8 /3] 8086,FPU
+FCOMP mem64 [m: dc /3] 8086,FPU
+FCOMP fpureg [r: d8 d8+r] 8086,FPU
+FCOMP fpu0,fpureg [-r: d8 d8+r] 8086,FPU
+FCOMP void [ d8 d9] 8086,FPU,ND
+FCOMPP void [ de d9] 8086,FPU
+FCOS void [ d9 ff] 386,FPU
+FDECSTP void [ d9 f6] 8086,FPU
+FDISI void [ wait db e1] 8086,FPU
+FDIV mem32 [m: d8 /6] 8086,FPU
+FDIV mem64 [m: dc /6] 8086,FPU
+FDIV fpureg|to [r: dc f8+r] 8086,FPU
+FDIV fpureg [r: d8 f0+r] 8086,FPU
+FDIV fpureg,fpu0 [r-: dc f8+r] 8086,FPU
+FDIV fpu0,fpureg [-r: d8 f0+r] 8086,FPU
+FDIV void [ de f9] 8086,FPU,ND
+FDIVP fpureg [r: de f8+r] 8086,FPU
+FDIVP fpureg,fpu0 [r-: de f8+r] 8086,FPU
+FDIVP void [ de f9] 8086,FPU,ND
+FDIVR mem32 [m: d8 /7] 8086,FPU
+FDIVR mem64 [m: dc /7] 8086,FPU
+FDIVR fpureg|to [r: dc f0+r] 8086,FPU
+FDIVR fpureg,fpu0 [r-: dc f0+r] 8086,FPU
+FDIVR fpureg [r: d8 f8+r] 8086,FPU
+FDIVR fpu0,fpureg [-r: d8 f8+r] 8086,FPU
+FDIVR void [ de f1] 8086,FPU,ND
+FDIVRP fpureg [r: de f0+r] 8086,FPU
+FDIVRP fpureg,fpu0 [r-: de f0+r] 8086,FPU
+FDIVRP void [ de f1] 8086,FPU,ND
+FEMMS void [ 0f 0e] PENT,3DNOW
+FENI void [ wait db e0] 8086,FPU
+FFREE fpureg [r: dd c0+r] 8086,FPU
+FFREE void [ dd c1] 8086,FPU
+FFREEP fpureg [r: df c0+r] 286,FPU,UNDOC
+FFREEP void [ df c1] 286,FPU,UNDOC
+FIADD mem32 [m: da /0] 8086,FPU
+FIADD mem16 [m: de /0] 8086,FPU
+FICOM mem32 [m: da /2] 8086,FPU
+FICOM mem16 [m: de /2] 8086,FPU
+FICOMP mem32 [m: da /3] 8086,FPU
+FICOMP mem16 [m: de /3] 8086,FPU
+FIDIV mem32 [m: da /6] 8086,FPU
+FIDIV mem16 [m: de /6] 8086,FPU
+FIDIVR mem32 [m: da /7] 8086,FPU
+FIDIVR mem16 [m: de /7] 8086,FPU
+FILD mem32 [m: db /0] 8086,FPU
+FILD mem16 [m: df /0] 8086,FPU
+FILD mem64 [m: df /5] 8086,FPU
+FIMUL mem32 [m: da /1] 8086,FPU
+FIMUL mem16 [m: de /1] 8086,FPU
+FINCSTP void [ d9 f7] 8086,FPU
+FINIT void [ wait db e3] 8086,FPU
+FIST mem32 [m: db /2] 8086,FPU
+FIST mem16 [m: df /2] 8086,FPU
+FISTP mem32 [m: db /3] 8086,FPU
+FISTP mem16 [m: df /3] 8086,FPU
+FISTP mem64 [m: df /7] 8086,FPU
+FISTTP mem16 [m: df /1] PRESCOTT,FPU
+FISTTP mem32 [m: db /1] PRESCOTT,FPU
+FISTTP mem64 [m: dd /1] PRESCOTT,FPU
+FISUB mem32 [m: da /4] 8086,FPU
+FISUB mem16 [m: de /4] 8086,FPU
+FISUBR mem32 [m: da /5] 8086,FPU
+FISUBR mem16 [m: de /5] 8086,FPU
+FLD mem32 [m: d9 /0] 8086,FPU
+FLD mem64 [m: dd /0] 8086,FPU
+FLD mem80 [m: db /5] 8086,FPU
+FLD fpureg [r: d9 c0+r] 8086,FPU
+FLD void [ d9 c1] 8086,FPU,ND
+FLD1 void [ d9 e8] 8086,FPU
+FLDCW mem [m: d9 /5] 8086,FPU,SW
+FLDENV mem [m: d9 /4] 8086,FPU
+FLDL2E void [ d9 ea] 8086,FPU
+FLDL2T void [ d9 e9] 8086,FPU
+FLDLG2 void [ d9 ec] 8086,FPU
+FLDLN2 void [ d9 ed] 8086,FPU
+FLDPI void [ d9 eb] 8086,FPU
+FLDZ void [ d9 ee] 8086,FPU
+FMUL mem32 [m: d8 /1] 8086,FPU
+FMUL mem64 [m: dc /1] 8086,FPU
+FMUL fpureg|to [r: dc c8+r] 8086,FPU
+FMUL fpureg,fpu0 [r-: dc c8+r] 8086,FPU
+FMUL fpureg [r: d8 c8+r] 8086,FPU
+FMUL fpu0,fpureg [-r: d8 c8+r] 8086,FPU
+FMUL void [ de c9] 8086,FPU,ND
+FMULP fpureg [r: de c8+r] 8086,FPU
+FMULP fpureg,fpu0 [r-: de c8+r] 8086,FPU
+FMULP void [ de c9] 8086,FPU,ND
+FNCLEX void [ db e2] 8086,FPU
+FNDISI void [ db e1] 8086,FPU
+FNENI void [ db e0] 8086,FPU
+FNINIT void [ db e3] 8086,FPU
+FNOP void [ d9 d0] 8086,FPU
+FNSAVE mem [m: dd /6] 8086,FPU
+FNSTCW mem [m: d9 /7] 8086,FPU,SW
+FNSTENV mem [m: d9 /6] 8086,FPU
+FNSTSW mem [m: dd /7] 8086,FPU,SW
+FNSTSW reg_ax [-: df e0] 286,FPU
+FPATAN void [ d9 f3] 8086,FPU
+FPREM void [ d9 f8] 8086,FPU
+FPREM1 void [ d9 f5] 386,FPU
+FPTAN void [ d9 f2] 8086,FPU
+FRNDINT void [ d9 fc] 8086,FPU
+FRSTOR mem [m: dd /4] 8086,FPU
+FSAVE mem [m: wait dd /6] 8086,FPU
+FSCALE void [ d9 fd] 8086,FPU
+FSETPM void [ db e4] 286,FPU
+FSIN void [ d9 fe] 386,FPU
+FSINCOS void [ d9 fb] 386,FPU
+FSQRT void [ d9 fa] 8086,FPU
+FST mem32 [m: d9 /2] 8086,FPU
+FST mem64 [m: dd /2] 8086,FPU
+FST fpureg [r: dd d0+r] 8086,FPU
+FST void [ dd d1] 8086,FPU,ND
+FSTCW mem [m: wait d9 /7] 8086,FPU,SW
+FSTENV mem [m: wait d9 /6] 8086,FPU
+FSTP mem32 [m: d9 /3] 8086,FPU
+FSTP mem64 [m: dd /3] 8086,FPU
+FSTP mem80 [m: db /7] 8086,FPU
+FSTP fpureg [r: dd d8+r] 8086,FPU
+FSTP void [ dd d9] 8086,FPU,ND
+FSTSW mem [m: wait dd /7] 8086,FPU,SW
+FSTSW reg_ax [-: wait df e0] 286,FPU
+FSUB mem32 [m: d8 /4] 8086,FPU
+FSUB mem64 [m: dc /4] 8086,FPU
+FSUB fpureg|to [r: dc e8+r] 8086,FPU
+FSUB fpureg,fpu0 [r-: dc e8+r] 8086,FPU
+FSUB fpureg [r: d8 e0+r] 8086,FPU
+FSUB fpu0,fpureg [-r: d8 e0+r] 8086,FPU
+FSUB void [ de e9] 8086,FPU,ND
+FSUBP fpureg [r: de e8+r] 8086,FPU
+FSUBP fpureg,fpu0 [r-: de e8+r] 8086,FPU
+FSUBP void [ de e9] 8086,FPU,ND
+FSUBR mem32 [m: d8 /5] 8086,FPU
+FSUBR mem64 [m: dc /5] 8086,FPU
+FSUBR fpureg|to [r: dc e0+r] 8086,FPU
+FSUBR fpureg,fpu0 [r-: dc e0+r] 8086,FPU
+FSUBR fpureg [r: d8 e8+r] 8086,FPU
+FSUBR fpu0,fpureg [-r: d8 e8+r] 8086,FPU
+FSUBR void [ de e1] 8086,FPU,ND
+FSUBRP fpureg [r: de e0+r] 8086,FPU
+FSUBRP fpureg,fpu0 [r-: de e0+r] 8086,FPU
+FSUBRP void [ de e1] 8086,FPU,ND
+FTST void [ d9 e4] 8086,FPU
+FUCOM fpureg [r: dd e0+r] 386,FPU
+FUCOM fpu0,fpureg [-r: dd e0+r] 386,FPU
+FUCOM void [ dd e1] 386,FPU,ND
+FUCOMI fpureg [r: db e8+r] P6,FPU
+FUCOMI fpu0,fpureg [-r: db e8+r] P6,FPU
+FUCOMI void [ db e9] P6,FPU,ND
+FUCOMIP fpureg [r: df e8+r] P6,FPU
+FUCOMIP fpu0,fpureg [-r: df e8+r] P6,FPU
+FUCOMIP void [ df e9] P6,FPU,ND
+FUCOMP fpureg [r: dd e8+r] 386,FPU
+FUCOMP fpu0,fpureg [-r: dd e8+r] 386,FPU
+FUCOMP void [ dd e9] 386,FPU,ND
+FUCOMPP void [ da e9] 386,FPU
+FXAM void [ d9 e5] 8086,FPU
+FXCH fpureg [r: d9 c8+r] 8086,FPU
+FXCH fpureg,fpu0 [r-: d9 c8+r] 8086,FPU
+FXCH fpu0,fpureg [-r: d9 c8+r] 8086,FPU
+FXCH void [ d9 c9] 8086,FPU,ND
+FXTRACT void [ d9 f4] 8086,FPU
+FYL2X void [ d9 f1] 8086,FPU
+FYL2XP1 void [ d9 f9] 8086,FPU
+HLT void [ f4] 8086,PRIV
+IBTS mem,reg16 [mr: o16 0f a7 /r] 386,SW,UNDOC,ND,OBSOLETE
+IBTS reg16,reg16 [mr: o16 0f a7 /r] 386,UNDOC,ND,OBSOLETE
+IBTS mem,reg32 [mr: o32 0f a7 /r] 386,SD,UNDOC,ND,OBSOLETE
+IBTS reg32,reg32 [mr: o32 0f a7 /r] 386,UNDOC,ND,OBSOLETE
+ICEBP void [ f1] 386,ND
+IDIV rm8 [m: f6 /7] 8086
+IDIV rm16 [m: o16 f7 /7] 8086
+IDIV rm32 [m: o32 f7 /7] 386
+IDIV rm64 [m: o64 f7 /7] X86_64,LONG
+IMUL rm8 [m: f6 /5] 8086
+IMUL rm16 [m: o16 f7 /5] 8086
+IMUL rm32 [m: o32 f7 /5] 386
+IMUL rm64 [m: o64 f7 /5] X86_64,LONG
+IMUL reg16,mem [rm: o16 0f af /r] 386,SM
+IMUL reg16,reg16 [rm: o16 0f af /r] 386
+IMUL reg32,mem [rm: o32 0f af /r] 386,SM
+IMUL reg32,reg32 [rm: o32 0f af /r] 386
+IMUL reg64,mem [rm: o64 0f af /r] X86_64,LONG,SM
+IMUL reg64,reg64 [rm: o64 0f af /r] X86_64,LONG
+IMUL reg16,mem,imm8 [rmi: o16 6b /r ib,s] 186,SM2
+IMUL reg16,mem,sbyteword [rmi: o16 6b /r ib,s] 186,SM,ND
+IMUL reg16,mem,imm16 [rmi: o16 69 /r iw] 186,SM
+IMUL reg16,mem,imm [rmi: o16 69 /r iw] 186,SM,ND
+IMUL reg16,reg16,imm8 [rmi: o16 6b /r ib,s] 186
+IMUL reg16,reg16,sbyteword [rmi: o16 6b /r ib,s] 186,SM,ND
+IMUL reg16,reg16,imm16 [rmi: o16 69 /r iw] 186
+IMUL reg16,reg16,imm [rmi: o16 69 /r iw] 186,SM,ND
+IMUL reg32,mem,imm8 [rmi: o32 6b /r ib,s] 386,SM2
+IMUL reg32,mem,sbytedword [rmi: o32 6b /r ib,s] 386,SM,ND
+IMUL reg32,mem,imm32 [rmi: o32 69 /r id] 386,SM
+IMUL reg32,mem,imm [rmi: o32 69 /r id] 386,SM,ND
+IMUL reg32,reg32,imm8 [rmi: o32 6b /r ib,s] 386
+IMUL reg32,reg32,sbytedword [rmi: o32 6b /r ib,s] 386,SM,ND
+IMUL reg32,reg32,imm32 [rmi: o32 69 /r id] 386
+IMUL reg32,reg32,imm [rmi: o32 69 /r id] 386,SM,ND
+IMUL reg64,mem,imm8 [rmi: o64 6b /r ib,s] X86_64,LONG,SM2
+IMUL reg64,mem,sbytedword [rmi: o64 6b /r ib,s] X86_64,LONG,SM,ND
+IMUL reg64,mem,imm32 [rmi: o64 69 /r id] X86_64,LONG,SM2
+IMUL reg64,mem,imm [rmi: o64 69 /r id,s] X86_64,LONG,SM,ND
+IMUL reg64,reg64,imm8 [rmi: o64 6b /r ib,s] X86_64,LONG
+IMUL reg64,reg64,sbytedword [rmi: o64 6b /r ib,s] X86_64,LONG,SM,ND
+IMUL reg64,reg64,imm32 [rmi: o64 69 /r id] X86_64,LONG
+IMUL reg64,reg64,imm [rmi: o64 69 /r id,s] X86_64,LONG,SM,ND
+IMUL reg16,imm8 [r+mi: o16 6b /r ib,s] 186
+IMUL reg16,sbyteword [r+mi: o16 6b /r ib,s] 186,SM,ND
+IMUL reg16,imm16 [r+mi: o16 69 /r iw] 186
+IMUL reg16,imm [r+mi: o16 69 /r iw] 186,SM,ND
+IMUL reg32,imm8 [r+mi: o32 6b /r ib,s] 386
+IMUL reg32,sbytedword [r+mi: o32 6b /r ib,s] 386,SM,ND
+IMUL reg32,imm32 [r+mi: o32 69 /r id] 386
+IMUL reg32,imm [r+mi: o32 69 /r id] 386,SM,ND
+IMUL reg64,imm8 [r+mi: o64 6b /r ib,s] X86_64,LONG
+IMUL reg64,sbytedword [r+mi: o64 6b /r ib,s] X86_64,LONG,SM,ND
+IMUL reg64,imm32 [r+mi: o64 69 /r id,s] X86_64,LONG
+IMUL reg64,imm [r+mi: o64 69 /r id,s] X86_64,LONG,SM,ND
+IN reg_al,imm [-i: e4 ib,u] 8086,SB
+IN reg_ax,imm [-i: o16 e5 ib,u] 8086,SB
+IN reg_eax,imm [-i: o32 e5 ib,u] 386,SB
+IN reg_al,reg_dx [--: ec] 8086
+IN reg_ax,reg_dx [--: o16 ed] 8086
+IN reg_eax,reg_dx [--: o32 ed] 386
+INC reg16 [r: o16 40+r] 8086,NOLONG
+INC reg32 [r: o32 40+r] 386,NOLONG
+INC rm8 [m: hle fe /0] 8086,LOCK
+INC rm16 [m: hle o16 ff /0] 8086,LOCK
+INC rm32 [m: hle o32 ff /0] 386,LOCK
+INC rm64 [m: hle o64 ff /0] X86_64,LONG,LOCK
+INSB void [ 6c] 186
+INSD void [ o32 6d] 386
+INSW void [ o16 6d] 186
+INT imm [i: cd ib,u] 8086,SB
+INT01 void [ f1] 386,ND
+INT1 void [ f1] 386
+INT03 void [ cc] 8086,ND
+INT3 void [ cc] 8086
+INTO void [ ce] 8086,NOLONG
+INVD void [ 0f 08] 486,PRIV
+INVPCID reg32,mem128 [rm: 66 0f 38 82 /r] FUTURE,INVPCID,PRIV,NOLONG
+INVPCID reg64,mem128 [rm: 66 0f 38 82 /r] FUTURE,INVPCID,PRIV,LONG
+INVLPG mem [m: 0f 01 /7] 486,PRIV
+INVLPGA reg_ax,reg_ecx [--: a16 0f 01 df] X86_64,AMD,NOLONG
+INVLPGA reg_eax,reg_ecx [--: a32 0f 01 df] X86_64,AMD
+INVLPGA reg_rax,reg_ecx [--: o64nw a64 0f 01 df] X86_64,LONG,AMD
+INVLPGA void [ 0f 01 df] X86_64,AMD
+IRET void [ odf cf] 8086
+IRETD void [ o32 cf] 386
+IRETQ void [ o64 cf] X86_64,LONG
+IRETW void [ o16 cf] 8086
+JCXZ imm [i: a16 e3 rel8] 8086,NOLONG
+JECXZ imm [i: a32 e3 rel8] 386
+JRCXZ imm [i: o64nw a64 e3 rel8] X86_64,LONG
+JMP imm|short [i: eb rel8] 8086
+JMP imm [i: jmp8 eb rel8] 8086,ND
+JMP imm [i: odf e9 rel] 8086,BND
+JMP imm|near [i: odf e9 rel] 8086,ND,BND
+JMP imm|far [i: odf ea iwd seg] 8086,ND,NOLONG
+; Call/jmp near imm/reg/mem is always 64-bit in long mode.
+JMP imm16 [i: o16 e9 rel] 8086,NOLONG,BND
+JMP imm16|near [i: o16 e9 rel] 8086,ND,NOLONG,BND
+JMP imm16|far [i: o16 ea iwd seg] 8086,ND,NOLONG
+JMP imm32 [i: o32 e9 rel] 386,NOLONG,BND
+JMP imm32|near [i: o32 e9 rel] 386,ND,NOLONG,BND
+JMP imm32|far [i: o32 ea iwd seg] 386,ND,NOLONG
+JMP imm64 [i: o64nw e9 rel] X86_64,LONG,BND
+JMP imm64|near [i: o64nw e9 rel] X86_64,LONG,ND,BND
+JMP imm:imm [ji: odf ea iwd iw] 8086,NOLONG
+JMP imm16:imm [ji: o16 ea iw iw] 8086,NOLONG
+JMP imm:imm16 [ji: o16 ea iw iw] 8086,NOLONG
+JMP imm32:imm [ji: o32 ea id iw] 386,NOLONG
+JMP imm:imm32 [ji: o32 ea id iw] 386,NOLONG
+JMP mem|far [m: odf ff /5] 8086,NOLONG
+JMP mem|far [m: o64 ff /5] X86_64,LONG
+JMP mem16|far [m: o16 ff /5] 8086
+JMP mem32|far [m: o32 ff /5] 386
+JMP mem64|far [m: o64 ff /5] X86_64,LONG
+JMP mem|near [m: odf ff /4] 8086,ND,BND
+JMP rm16|near [m: o16 ff /4] 8086,NOLONG,ND,BND
+JMP rm32|near [m: o32 ff /4] 386,NOLONG,ND,BND
+JMP rm64|near [m: o64nw ff /4] X86_64,LONG,ND,BND
+JMP mem [m: odf ff /4] 8086,BND
+JMP rm16 [m: o16 ff /4] 8086,NOLONG,BND
+JMP rm32 [m: o32 ff /4] 386,NOLONG,BND
+JMP rm64 [m: o64nw ff /4] X86_64,LONG,BND
+
+JMPE imm [i: odf 0f b8 rel] IA64
+JMPE imm16 [i: o16 0f b8 rel] IA64
+JMPE imm32 [i: o32 0f b8 rel] IA64
+JMPE rm16 [m: o16 0f 00 /6] IA64
+JMPE rm32 [m: o32 0f 00 /6] IA64
+LAHF void [ 9f] 8086
+LAR reg16,mem [rm: o16 0f 02 /r] 286,PROT,SW
+LAR reg16,reg16 [rm: o16 0f 02 /r] 286,PROT
+LAR reg16,reg32 [rm: o16 0f 02 /r] 386,PROT
+LAR reg16,reg64 [rm: o16 o64nw 0f 02 /r] X86_64,LONG,PROT,ND
+LAR reg32,mem [rm: o32 0f 02 /r] 386,PROT,SW
+LAR reg32,reg16 [rm: o32 0f 02 /r] 386,PROT
+LAR reg32,reg32 [rm: o32 0f 02 /r] 386,PROT
+LAR reg32,reg64 [rm: o32 o64nw 0f 02 /r] X86_64,LONG,PROT,ND
+LAR reg64,mem [rm: o64 0f 02 /r] X86_64,LONG,PROT,SW
+LAR reg64,reg16 [rm: o64 0f 02 /r] X86_64,LONG,PROT
+LAR reg64,reg32 [rm: o64 0f 02 /r] X86_64,LONG,PROT
+LAR reg64,reg64 [rm: o64 0f 02 /r] X86_64,LONG,PROT
+LDS reg16,mem [rm: o16 c5 /r] 8086,NOLONG
+LDS reg32,mem [rm: o32 c5 /r] 386,NOLONG
+LEA reg16,mem [rm: o16 8d /r] 8086,ANYSIZE
+LEA reg32,mem [rm: o32 8d /r] 386,ANYSIZE
+LEA reg64,mem [rm: o64 8d /r] X86_64,LONG,ANYSIZE
+LEA reg16,imm [rm: o16 8d /r] 8086,ND,ANYSIZE
+LEA reg32,imm [rm: o32 8d /r] 386,ND,ANYSIZE
+LEA reg64,imm [rm: o64 8d /r] X86_64,LONG,ND,ANYSIZE
+LEAVE void [ c9] 186
+LES reg16,mem [rm: o16 c4 /r] 8086,NOLONG
+LES reg32,mem [rm: o32 c4 /r] 386,NOLONG
+LFENCE void [ np 0f ae e8] X86_64,LONG,AMD
+LFS reg16,mem [rm: o16 0f b4 /r] 386
+LFS reg32,mem [rm: o32 0f b4 /r] 386
+LFS reg64,mem [rm: o64 0f b4 /r] X86_64,LONG
+LGDT mem [m: 0f 01 /2] 286,PRIV
+LGS reg16,mem [rm: o16 0f b5 /r] 386
+LGS reg32,mem [rm: o32 0f b5 /r] 386
+LGS reg64,mem [rm: o64 0f b5 /r] X86_64,LONG
+LIDT mem [m: 0f 01 /3] 286,PRIV
+LLDT mem [m: 0f 00 /2] 286,PROT,PRIV
+LLDT mem16 [m: 0f 00 /2] 286,PROT,PRIV
+LLDT reg16 [m: 0f 00 /2] 286,PROT,PRIV
+LMSW mem [m: 0f 01 /6] 286,PRIV
+LMSW mem16 [m: 0f 01 /6] 286,PRIV
+LMSW reg16 [m: 0f 01 /6] 286,PRIV
+LOADALL void [ 0f 07] 386,UNDOC,ND,OBSOLETE
+LOADALL286 void [ 0f 05] 286,UNDOC,ND,OBSOLETE
+LODSB void [ ac] 8086
+LODSD void [ o32 ad] 386
+LODSQ void [ o64 ad] X86_64,LONG
+LODSW void [ o16 ad] 8086
+LOOP imm [i: adf e2 rel8] 8086
+LOOP imm,reg_cx [i-: a16 e2 rel8] 8086,NOLONG
+LOOP imm,reg_ecx [i-: a32 e2 rel8] 386
+LOOP imm,reg_rcx [i-: a64 e2 rel8] X86_64,LONG
+LOOPE imm [i: adf e1 rel8] 8086
+LOOPE imm,reg_cx [i-: a16 e1 rel8] 8086,NOLONG
+LOOPE imm,reg_ecx [i-: a32 e1 rel8] 386
+LOOPE imm,reg_rcx [i-: a64 e1 rel8] X86_64,LONG
+LOOPNE imm [i: adf e0 rel8] 8086
+LOOPNE imm,reg_cx [i-: a16 e0 rel8] 8086,NOLONG
+LOOPNE imm,reg_ecx [i-: a32 e0 rel8] 386
+LOOPNE imm,reg_rcx [i-: a64 e0 rel8] X86_64,LONG
+LOOPNZ imm [i: adf e0 rel8] 8086
+LOOPNZ imm,reg_cx [i-: a16 e0 rel8] 8086,NOLONG
+LOOPNZ imm,reg_ecx [i-: a32 e0 rel8] 386
+LOOPNZ imm,reg_rcx [i-: a64 e0 rel8] X86_64,LONG
+LOOPZ imm [i: adf e1 rel8] 8086
+LOOPZ imm,reg_cx [i-: a16 e1 rel8] 8086,NOLONG
+LOOPZ imm,reg_ecx [i-: a32 e1 rel8] 386
+LOOPZ imm,reg_rcx [i-: a64 e1 rel8] X86_64,LONG
+LSL reg16,mem [rm: o16 0f 03 /r] 286,PROT,SW
+LSL reg16,reg16 [rm: o16 0f 03 /r] 286,PROT
+LSL reg16,reg32 [rm: o16 0f 03 /r] 386,PROT
+LSL reg16,reg64 [rm: o16 o64nw 0f 03 /r] X86_64,LONG,PROT,ND
+LSL reg32,mem [rm: o32 0f 03 /r] 386,PROT,SW
+LSL reg32,reg16 [rm: o32 0f 03 /r] 386,PROT
+LSL reg32,reg32 [rm: o32 0f 03 /r] 386,PROT
+LSL reg32,reg64 [rm: o32 o64nw 0f 03 /r] X86_64,LONG,PROT,ND
+LSL reg64,mem [rm: o64 0f 03 /r] X86_64,LONG,PROT,SW
+LSL reg64,reg16 [rm: o64 0f 03 /r] X86_64,LONG,PROT
+LSL reg64,reg32 [rm: o64 0f 03 /r] X86_64,LONG,PROT
+LSL reg64,reg64 [rm: o64 0f 03 /r] X86_64,LONG,PROT
+LSS reg16,mem [rm: o16 0f b2 /r] 386
+LSS reg32,mem [rm: o32 0f b2 /r] 386
+LSS reg64,mem [rm: o64 0f b2 /r] X86_64,LONG
+LTR mem [m: 0f 00 /3] 286,PROT,PRIV
+LTR mem16 [m: 0f 00 /3] 286,PROT,PRIV
+LTR reg16 [m: 0f 00 /3] 286,PROT,PRIV
+MFENCE void [ np 0f ae f0] X86_64,LONG,AMD
+MONITOR void [ 0f 01 c8] PRESCOTT
+MONITOR reg_eax,reg_ecx,reg_edx [---: 0f 01 c8] PRESCOTT,NOLONG,ND
+MONITOR reg_rax,reg_ecx,reg_edx [---: 0f 01 c8] X86_64,LONG,ND
+MONITORX void [ 0f 01 fa] AMD
+MONITORX reg_rax,reg_ecx,reg_edx [---: 0f 01 fa] X86_64,LONG,AMD,ND
+MONITORX reg_eax,reg_ecx,reg_edx [---: 0f 01 fa] AMD,ND
+MONITORX reg_ax,reg_ecx,reg_edx [---: 0f 01 fa] AMD,ND
+MOV mem,reg_sreg [mr: 8c /r] 8086,SW
+MOV reg16,reg_sreg [mr: o16 8c /r] 8086
+MOV reg32,reg_sreg [mr: o32 8c /r] 386
+MOV reg64,reg_sreg [mr: o64nw 8c /r] X86_64,LONG,OPT,ND
+MOV rm64,reg_sreg [mr: o64 8c /r] X86_64,LONG
+MOV reg_sreg,mem [rm: 8e /r] 8086,SW
+MOV reg_sreg,reg16 [rm: 8e /r] 8086,OPT,ND
+MOV reg_sreg,reg32 [rm: 8e /r] 386,OPT,ND
+MOV reg_sreg,reg64 [rm: o64nw 8e /r] X86_64,LONG,OPT,ND
+MOV reg_sreg,reg16 [rm: o16 8e /r] 8086
+MOV reg_sreg,reg32 [rm: o32 8e /r] 386
+MOV reg_sreg,rm64 [rm: o64 8e /r] X86_64,LONG
+MOV reg_al,mem_offs [-i: a0 iwdq] 8086,SM
+MOV reg_ax,mem_offs [-i: o16 a1 iwdq] 8086,SM
+MOV reg_eax,mem_offs [-i: o32 a1 iwdq] 386,SM
+MOV reg_rax,mem_offs [-i: o64 a1 iwdq] X86_64,LONG,SM
+MOV mem_offs,reg_al [i-: a2 iwdq] 8086,SM,NOHLE
+MOV mem_offs,reg_ax [i-: o16 a3 iwdq] 8086,SM,NOHLE
+MOV mem_offs,reg_eax [i-: o32 a3 iwdq] 386,SM,NOHLE
+MOV mem_offs,reg_rax [i-: o64 a3 iwdq] X86_64,LONG,SM,NOHLE
+MOV reg32,reg_creg [mr: rex.l 0f 20 /r] 386,PRIV,NOLONG
+MOV reg64,reg_creg [mr: o64nw 0f 20 /r] X86_64,LONG,PRIV
+MOV reg_creg,reg32 [rm: rex.l 0f 22 /r] 386,PRIV,NOLONG
+MOV reg_creg,reg64 [rm: o64nw 0f 22 /r] X86_64,LONG,PRIV
+MOV reg32,reg_dreg [mr: 0f 21 /r] 386,PRIV,NOLONG
+MOV reg64,reg_dreg [mr: o64nw 0f 21 /r] X86_64,LONG,PRIV
+MOV reg_dreg,reg32 [rm: 0f 23 /r] 386,PRIV,NOLONG
+MOV reg_dreg,reg64 [rm: o64nw 0f 23 /r] X86_64,LONG,PRIV
+MOV reg32,reg_treg [mr: 0f 24 /r] 386,NOLONG,ND
+MOV reg_treg,reg32 [rm: 0f 26 /r] 386,NOLONG,ND
+MOV mem,reg8 [mr: hlexr 88 /r] 8086,SM
+MOV reg8,reg8 [mr: 88 /r] 8086
+MOV mem,reg16 [mr: hlexr o16 89 /r] 8086,SM
+MOV reg16,reg16 [mr: o16 89 /r] 8086
+MOV mem,reg32 [mr: hlexr o32 89 /r] 386,SM
+MOV reg32,reg32 [mr: o32 89 /r] 386
+MOV mem,reg64 [mr: hlexr o64 89 /r] X86_64,LONG,SM
+MOV reg64,reg64 [mr: o64 89 /r] X86_64,LONG
+MOV reg8,mem [rm: 8a /r] 8086,SM
+MOV reg8,reg8 [rm: 8a /r] 8086
+MOV reg16,mem [rm: o16 8b /r] 8086,SM
+MOV reg16,reg16 [rm: o16 8b /r] 8086
+MOV reg32,mem [rm: o32 8b /r] 386,SM
+MOV reg32,reg32 [rm: o32 8b /r] 386
+MOV reg64,mem [rm: o64 8b /r] X86_64,LONG,SM
+MOV reg64,reg64 [rm: o64 8b /r] X86_64,LONG
+MOV reg8,imm [ri: b0+r ib] 8086,SM
+MOV reg16,imm [ri: o16 b8+r iw] 8086,SM
+MOV reg32,imm [ri: o32 b8+r id] 386,SM
+MOV reg64,udword [ri: o64nw b8+r id] X86_64,LONG,SM,OPT,ND
+MOV reg64,sdword [mi: o64 c7 /0 id,s] X86_64,LONG,SM,OPT,ND
+MOV reg64,imm [ri: o64 b8+r iq] X86_64,LONG,SM
+MOV rm8,imm [mi: hlexr c6 /0 ib] 8086,SM
+MOV rm16,imm [mi: hlexr o16 c7 /0 iw] 8086,SM
+MOV rm32,imm [mi: hlexr o32 c7 /0 id] 386,SM
+MOV rm64,imm [mi: hlexr o64 c7 /0 id,s] X86_64,LONG,SM
+MOV rm64,imm32 [mi: hlexr o64 c7 /0 id,s] X86_64,LONG
+MOV mem,imm8 [mi: hlexr c6 /0 ib] 8086,SM
+MOV mem,imm16 [mi: hlexr o16 c7 /0 iw] 8086,SM
+MOV mem,imm32 [mi: hlexr o32 c7 /0 id] 386,SM
+MOVD mmxreg,rm32 [rm: np 0f 6e /r] PENT,MMX,SD
+MOVD rm32,mmxreg [mr: np 0f 7e /r] PENT,MMX,SD
+MOVD mmxreg,rm64 [rm: np o64 0f 6e /r] X86_64,LONG,MMX,SX,ND
+MOVD rm64,mmxreg [mr: np o64 0f 7e /r] X86_64,LONG,MMX,SX,ND
+MOVQ mmxreg,mmxrm [rm: np 0f 6f /r] PENT,MMX,SQ
+MOVQ mmxrm,mmxreg [mr: np 0f 7f /r] PENT,MMX,SQ
+MOVQ mmxreg,rm64 [rm: np o64 0f 6e /r] X86_64,LONG,MMX
+MOVQ rm64,mmxreg [mr: np o64 0f 7e /r] X86_64,LONG,MMX
+MOVSB void [ a4] 8086
+MOVSD void [ o32 a5] 386
+MOVSQ void [ o64 a5] X86_64,LONG
+MOVSW void [ o16 a5] 8086
+MOVSX reg16,mem [rm: o16 0f be /r] 386,SB
+MOVSX reg16,reg8 [rm: o16 0f be /r] 386
+MOVSX reg32,rm8 [rm: o32 0f be /r] 386
+MOVSX reg32,rm16 [rm: o32 0f bf /r] 386
+MOVSX reg64,rm8 [rm: o64 0f be /r] X86_64,LONG
+MOVSX reg64,rm16 [rm: o64 0f bf /r] X86_64,LONG
+MOVSXD reg64,rm32 [rm: o64 63 /r] X86_64,LONG
+MOVSX reg64,rm32 [rm: o64 63 /r] X86_64,LONG,ND
+MOVZX reg16,mem [rm: o16 0f b6 /r] 386,SB
+MOVZX reg16,reg8 [rm: o16 0f b6 /r] 386
+MOVZX reg32,rm8 [rm: o32 0f b6 /r] 386
+MOVZX reg32,rm16 [rm: o32 0f b7 /r] 386
+MOVZX reg64,rm8 [rm: o64 0f b6 /r] X86_64,LONG
+MOVZX reg64,rm16 [rm: o64 0f b7 /r] X86_64,LONG
+MUL rm8 [m: f6 /4] 8086
+MUL rm16 [m: o16 f7 /4] 8086
+MUL rm32 [m: o32 f7 /4] 386
+MUL rm64 [m: o64 f7 /4] X86_64,LONG
+MWAIT void [ 0f 01 c9] PRESCOTT
+MWAIT reg_eax,reg_ecx [--: 0f 01 c9] PRESCOTT,ND
+MWAITX void [ 0f 01 fb] AMD
+MWAITX reg_eax,reg_ecx [--: 0f 01 fb] AMD,ND
+NEG rm8 [m: hle f6 /3] 8086,LOCK
+NEG rm16 [m: hle o16 f7 /3] 8086,LOCK
+NEG rm32 [m: hle o32 f7 /3] 386,LOCK
+NEG rm64 [m: hle o64 f7 /3] X86_64,LONG,LOCK
+NOP void [ norexb nof3 90] 8086
+NOP rm16 [m: o16 0f 1f /0] P6
+NOP rm32 [m: o32 0f 1f /0] P6
+NOP rm64 [m: o64 0f 1f /0] X86_64,LONG
+NOT rm8 [m: hle f6 /2] 8086,LOCK
+NOT rm16 [m: hle o16 f7 /2] 8086,LOCK
+NOT rm32 [m: hle o32 f7 /2] 386,LOCK
+NOT rm64 [m: hle o64 f7 /2] X86_64,LONG,LOCK
+OR mem,reg8 [mr: hle 08 /r] 8086,SM,LOCK
+OR reg8,reg8 [mr: 08 /r] 8086
+OR mem,reg16 [mr: hle o16 09 /r] 8086,SM,LOCK
+OR reg16,reg16 [mr: o16 09 /r] 8086
+OR mem,reg32 [mr: hle o32 09 /r] 386,SM,LOCK
+OR reg32,reg32 [mr: o32 09 /r] 386
+OR mem,reg64 [mr: hle o64 09 /r] X86_64,LONG,SM,LOCK
+OR reg64,reg64 [mr: o64 09 /r] X86_64,LONG
+OR reg8,mem [rm: 0a /r] 8086,SM
+OR reg8,reg8 [rm: 0a /r] 8086
+OR reg16,mem [rm: o16 0b /r] 8086,SM
+OR reg16,reg16 [rm: o16 0b /r] 8086
+OR reg32,mem [rm: o32 0b /r] 386,SM
+OR reg32,reg32 [rm: o32 0b /r] 386
+OR reg64,mem [rm: o64 0b /r] X86_64,LONG,SM
+OR reg64,reg64 [rm: o64 0b /r] X86_64,LONG
+OR rm16,imm8 [mi: hle o16 83 /1 ib,s] 8086,LOCK
+OR rm32,imm8 [mi: hle o32 83 /1 ib,s] 386,LOCK
+OR rm64,imm8 [mi: hle o64 83 /1 ib,s] X86_64,LONG,LOCK
+OR reg_al,imm [-i: 0c ib] 8086,SM
+OR reg_ax,sbyteword [mi: o16 83 /1 ib,s] 8086,SM,ND
+OR reg_ax,imm [-i: o16 0d iw] 8086,SM
+OR reg_eax,sbytedword [mi: o32 83 /1 ib,s] 386,SM,ND
+OR reg_eax,imm [-i: o32 0d id] 386,SM
+OR reg_rax,sbytedword [mi: o64 83 /1 ib,s] X86_64,LONG,SM,ND
+OR reg_rax,imm [-i: o64 0d id,s] X86_64,LONG,SM
+OR rm8,imm [mi: hle 80 /1 ib] 8086,SM,LOCK
+OR rm16,sbyteword [mi: hle o16 83 /1 ib,s] 8086,SM,LOCK,ND
+OR rm16,imm [mi: hle o16 81 /1 iw] 8086,SM,LOCK
+OR rm32,sbytedword [mi: hle o32 83 /1 ib,s] 386,SM,LOCK,ND
+OR rm32,imm [mi: hle o32 81 /1 id] 386,SM,LOCK
+OR rm64,sbytedword [mi: hle o64 83 /1 ib,s] X86_64,LONG,SM,LOCK,ND
+OR rm64,imm [mi: hle o64 81 /1 id,s] X86_64,LONG,SM,LOCK
+OR mem,imm8 [mi: hle 80 /1 ib] 8086,SM,LOCK
+OR mem,sbyteword16 [mi: hle o16 83 /1 ib,s] 8086,SM,LOCK,ND
+OR mem,imm16 [mi: hle o16 81 /1 iw] 8086,SM,LOCK
+OR mem,sbytedword32 [mi: hle o32 83 /1 ib,s] 386,SM,LOCK,ND
+OR mem,imm32 [mi: hle o32 81 /1 id] 386,SM,LOCK
+OR rm8,imm [mi: hle 82 /1 ib] 8086,SM,LOCK,ND,NOLONG
+OUT imm,reg_al [i-: e6 ib,u] 8086,SB
+OUT imm,reg_ax [i-: o16 e7 ib,u] 8086,SB
+OUT imm,reg_eax [i-: o32 e7 ib,u] 386,SB
+OUT reg_dx,reg_al [--: ee] 8086
+OUT reg_dx,reg_ax [--: o16 ef] 8086
+OUT reg_dx,reg_eax [--: o32 ef] 386
+OUTSB void [ 6e] 186
+OUTSD void [ o32 6f] 386
+OUTSW void [ o16 6f] 186
+PACKSSDW mmxreg,mmxrm [rm: np o64nw 0f 6b /r] PENT,MMX,SQ
+PACKSSWB mmxreg,mmxrm [rm: np o64nw 0f 63 /r] PENT,MMX,SQ
+PACKUSWB mmxreg,mmxrm [rm: np o64nw 0f 67 /r] PENT,MMX,SQ
+PADDB mmxreg,mmxrm [rm: np o64nw 0f fc /r] PENT,MMX,SQ
+PADDD mmxreg,mmxrm [rm: np o64nw 0f fe /r] PENT,MMX,SQ
+PADDSB mmxreg,mmxrm [rm: np o64nw 0f ec /r] PENT,MMX,SQ
+PADDSIW mmxreg,mmxrm [rm: o64nw 0f 51 /r] PENT,MMX,SQ,CYRIX
+PADDSW mmxreg,mmxrm [rm: np o64nw 0f ed /r] PENT,MMX,SQ
+PADDUSB mmxreg,mmxrm [rm: np o64nw 0f dc /r] PENT,MMX,SQ
+PADDUSW mmxreg,mmxrm [rm: np o64nw 0f dd /r] PENT,MMX,SQ
+PADDW mmxreg,mmxrm [rm: np o64nw 0f fd /r] PENT,MMX,SQ
+PAND mmxreg,mmxrm [rm: np o64nw 0f db /r] PENT,MMX,SQ
+PANDN mmxreg,mmxrm [rm: np o64nw 0f df /r] PENT,MMX,SQ
+PAUSE void [ f3i 90] 8086
+PAVEB mmxreg,mmxrm [rm: o64nw 0f 50 /r] PENT,MMX,SQ,CYRIX
+PAVGUSB mmxreg,mmxrm [rm: o64nw 0f 0f /r bf] PENT,3DNOW,SQ
+PCMPEQB mmxreg,mmxrm [rm: np o64nw 0f 74 /r] PENT,MMX,SQ
+PCMPEQD mmxreg,mmxrm [rm: np o64nw 0f 76 /r] PENT,MMX,SQ
+PCMPEQW mmxreg,mmxrm [rm: np o64nw 0f 75 /r] PENT,MMX,SQ
+PCMPGTB mmxreg,mmxrm [rm: np o64nw 0f 64 /r] PENT,MMX,SQ
+PCMPGTD mmxreg,mmxrm [rm: np o64nw 0f 66 /r] PENT,MMX,SQ
+PCMPGTW mmxreg,mmxrm [rm: np o64nw 0f 65 /r] PENT,MMX,SQ
+PDISTIB mmxreg,mem [rm: 0f 54 /r] PENT,MMX,SM,CYRIX
+PF2ID mmxreg,mmxrm [rm: o64nw 0f 0f /r 1d] PENT,3DNOW,SQ
+PFACC mmxreg,mmxrm [rm: o64nw 0f 0f /r ae] PENT,3DNOW,SQ
+PFADD mmxreg,mmxrm [rm: o64nw 0f 0f /r 9e] PENT,3DNOW,SQ
+PFCMPEQ mmxreg,mmxrm [rm: o64nw 0f 0f /r b0] PENT,3DNOW,SQ
+PFCMPGE mmxreg,mmxrm [rm: o64nw 0f 0f /r 90] PENT,3DNOW,SQ
+PFCMPGT mmxreg,mmxrm [rm: o64nw 0f 0f /r a0] PENT,3DNOW,SQ
+PFMAX mmxreg,mmxrm [rm: o64nw 0f 0f /r a4] PENT,3DNOW,SQ
+PFMIN mmxreg,mmxrm [rm: o64nw 0f 0f /r 94] PENT,3DNOW,SQ
+PFMUL mmxreg,mmxrm [rm: o64nw 0f 0f /r b4] PENT,3DNOW,SQ
+PFRCP mmxreg,mmxrm [rm: o64nw 0f 0f /r 96] PENT,3DNOW,SQ
+PFRCPIT1 mmxreg,mmxrm [rm: o64nw 0f 0f /r a6] PENT,3DNOW,SQ
+PFRCPIT2 mmxreg,mmxrm [rm: o64nw 0f 0f /r b6] PENT,3DNOW,SQ
+PFRSQIT1 mmxreg,mmxrm [rm: o64nw 0f 0f /r a7] PENT,3DNOW,SQ
+PFRSQRT mmxreg,mmxrm [rm: o64nw 0f 0f /r 97] PENT,3DNOW,SQ
+PFSUB mmxreg,mmxrm [rm: o64nw 0f 0f /r 9a] PENT,3DNOW,SQ
+PFSUBR mmxreg,mmxrm [rm: o64nw 0f 0f /r aa] PENT,3DNOW,SQ
+PI2FD mmxreg,mmxrm [rm: o64nw 0f 0f /r 0d] PENT,3DNOW,SQ
+PMACHRIW mmxreg,mem [rm: 0f 5e /r] PENT,MMX,SM,CYRIX
+PMADDWD mmxreg,mmxrm [rm: np o64nw 0f f5 /r] PENT,MMX,SQ
+PMAGW mmxreg,mmxrm [rm: o64nw 0f 52 /r] PENT,MMX,SQ,CYRIX
+PMULHRIW mmxreg,mmxrm [rm: o64nw 0f 5d /r] PENT,MMX,SQ,CYRIX
+PMULHRWA mmxreg,mmxrm [rm: o64nw 0f 0f /r b7] PENT,3DNOW,SQ
+PMULHRWC mmxreg,mmxrm [rm: o64nw 0f 59 /r] PENT,MMX,SQ,CYRIX
+PMULHW mmxreg,mmxrm [rm: np o64nw 0f e5 /r] PENT,MMX,SQ
+PMULLW mmxreg,mmxrm [rm: np o64nw 0f d5 /r] PENT,MMX,SQ
+PMVGEZB mmxreg,mem [rm: 0f 5c /r] PENT,MMX,SQ,CYRIX
+PMVLZB mmxreg,mem [rm: 0f 5b /r] PENT,MMX,SQ,CYRIX
+PMVNZB mmxreg,mem [rm: 0f 5a /r] PENT,MMX,SQ,CYRIX
+PMVZB mmxreg,mem [rm: 0f 58 /r] PENT,MMX,SQ,CYRIX
+POP reg16 [r: o16 58+r] 8086
+POP reg32 [r: o32 58+r] 386,NOLONG
+POP reg64 [r: o64nw 58+r] X86_64,LONG
+POP rm16 [m: o16 8f /0] 8086
+POP rm32 [m: o32 8f /0] 386,NOLONG
+POP rm64 [m: o64nw 8f /0] X86_64,LONG
+POP reg_es [-: 07] 8086,NOLONG
+POP reg_cs [-: 0f] 8086,UNDOC,ND,OBSOLETE
+POP reg_ss [-: 17] 8086,NOLONG
+POP reg_ds [-: 1f] 8086,NOLONG
+POP reg_fs [-: 0f a1] 386
+POP reg_gs [-: 0f a9] 386
+POPA void [ odf 61] 186,NOLONG
+POPAD void [ o32 61] 386,NOLONG
+POPAW void [ o16 61] 186,NOLONG
+POPF void [ odf 9d] 8086
+POPFD void [ o32 9d] 386,NOLONG
+POPFQ void [ o32 9d] X86_64,LONG
+POPFW void [ o16 9d] 8086
+POR mmxreg,mmxrm [rm: np o64nw 0f eb /r] PENT,MMX,SQ
+PREFETCH mem [m: 0f 0d /0] PENT,3DNOW,SQ
+PREFETCHW mem [m: 0f 0d /1] PENT,3DNOW,SQ
+PSLLD mmxreg,mmxrm [rm: np o64nw 0f f2 /r] PENT,MMX,SQ
+PSLLD mmxreg,imm [mi: np 0f 72 /6 ib,u] PENT,MMX
+PSLLQ mmxreg,mmxrm [rm: np o64nw 0f f3 /r] PENT,MMX,SQ
+PSLLQ mmxreg,imm [mi: np 0f 73 /6 ib,u] PENT,MMX
+PSLLW mmxreg,mmxrm [rm: np o64nw 0f f1 /r] PENT,MMX,SQ
+PSLLW mmxreg,imm [mi: np 0f 71 /6 ib,u] PENT,MMX
+PSRAD mmxreg,mmxrm [rm: np o64nw 0f e2 /r] PENT,MMX,SQ
+PSRAD mmxreg,imm [mi: np 0f 72 /4 ib,u] PENT,MMX
+PSRAW mmxreg,mmxrm [rm: np o64nw 0f e1 /r] PENT,MMX,SQ
+PSRAW mmxreg,imm [mi: np 0f 71 /4 ib,u] PENT,MMX
+PSRLD mmxreg,mmxrm [rm: np o64nw 0f d2 /r] PENT,MMX,SQ
+PSRLD mmxreg,imm [mi: np 0f 72 /2 ib,u] PENT,MMX
+PSRLQ mmxreg,mmxrm [rm: np o64nw 0f d3 /r] PENT,MMX,SQ
+PSRLQ mmxreg,imm [mi: np 0f 73 /2 ib,u] PENT,MMX
+PSRLW mmxreg,mmxrm [rm: np o64nw 0f d1 /r] PENT,MMX,SQ
+PSRLW mmxreg,imm [mi: np 0f 71 /2 ib,u] PENT,MMX
+PSUBB mmxreg,mmxrm [rm: np o64nw 0f f8 /r] PENT,MMX,SQ
+PSUBD mmxreg,mmxrm [rm: np o64nw 0f fa /r] PENT,MMX,SQ
+PSUBSB mmxreg,mmxrm [rm: np o64nw 0f e8 /r] PENT,MMX,SQ
+PSUBSIW mmxreg,mmxrm [rm: o64nw 0f 55 /r] PENT,MMX,SQ,CYRIX
+PSUBSW mmxreg,mmxrm [rm: np o64nw 0f e9 /r] PENT,MMX,SQ
+PSUBUSB mmxreg,mmxrm [rm: np o64nw 0f d8 /r] PENT,MMX,SQ
+PSUBUSW mmxreg,mmxrm [rm: np o64nw 0f d9 /r] PENT,MMX,SQ
+PSUBW mmxreg,mmxrm [rm: np o64nw 0f f9 /r] PENT,MMX,SQ
+PUNPCKHBW mmxreg,mmxrm [rm: np o64nw 0f 68 /r] PENT,MMX,SQ
+PUNPCKHDQ mmxreg,mmxrm [rm: np o64nw 0f 6a /r] PENT,MMX,SQ
+PUNPCKHWD mmxreg,mmxrm [rm: np o64nw 0f 69 /r] PENT,MMX,SQ
+PUNPCKLBW mmxreg,mmxrm [rm: np o64nw 0f 60 /r] PENT,MMX,SQ
+PUNPCKLDQ mmxreg,mmxrm [rm: np o64nw 0f 62 /r] PENT,MMX,SQ
+PUNPCKLWD mmxreg,mmxrm [rm: np o64nw 0f 61 /r] PENT,MMX,SQ
+PUSH reg16 [r: o16 50+r] 8086
+PUSH reg32 [r: o32 50+r] 386,NOLONG
+PUSH reg64 [r: o64nw 50+r] X86_64,LONG
+PUSH rm16 [m: o16 ff /6] 8086
+PUSH rm32 [m: o32 ff /6] 386,NOLONG
+PUSH rm64 [m: o64nw ff /6] X86_64,LONG
+PUSH reg_es [-: 06] 8086,NOLONG
+PUSH reg_cs [-: 0e] 8086,NOLONG
+PUSH reg_ss [-: 16] 8086,NOLONG
+PUSH reg_ds [-: 1e] 8086,NOLONG
+PUSH reg_fs [-: 0f a0] 386
+PUSH reg_gs [-: 0f a8] 386
+PUSH imm8 [i: 6a ib,s] 186
+PUSH sbyteword16 [i: o16 6a ib,s] 186,AR0,SIZE,ND
+PUSH imm16 [i: o16 68 iw] 186,AR0,SIZE
+PUSH sbytedword32 [i: o32 6a ib,s] 386,NOLONG,AR0,SIZE,ND
+PUSH imm32 [i: o32 68 id] 386,NOLONG,AR0,SIZE
+PUSH sbytedword32 [i: o32 6a ib,s] 386,NOLONG,SD,ND
+PUSH imm32 [i: o32 68 id] 386,NOLONG,SD
+PUSH sbytedword64 [i: o64nw 6a ib,s] X86_64,LONG,AR0,SIZE,ND
+PUSH imm64 [i: o64nw 68 id,s] X86_64,LONG,AR0,SIZE
+PUSH sbytedword32 [i: o64nw 6a ib,s] X86_64,LONG,AR0,SIZE,ND
+PUSH imm32 [i: o64nw 68 id,s] X86_64,LONG,AR0,SIZE
+PUSHA void [ odf 60] 186,NOLONG
+PUSHAD void [ o32 60] 386,NOLONG
+PUSHAW void [ o16 60] 186,NOLONG
+PUSHF void [ odf 9c] 8086
+PUSHFD void [ o32 9c] 386,NOLONG
+PUSHFQ void [ o32 9c] X86_64,LONG
+PUSHFW void [ o16 9c] 8086
+PXOR mmxreg,mmxrm [rm: np o64nw 0f ef /r] PENT,MMX,SQ
+RCL rm8,unity [m-: d0 /2] 8086
+RCL rm8,reg_cl [m-: d2 /2] 8086
+RCL rm8,imm8 [mi: c0 /2 ib,u] 186
+RCL rm16,unity [m-: o16 d1 /2] 8086
+RCL rm16,reg_cl [m-: o16 d3 /2] 8086
+RCL rm16,imm8 [mi: o16 c1 /2 ib,u] 186
+RCL rm32,unity [m-: o32 d1 /2] 386
+RCL rm32,reg_cl [m-: o32 d3 /2] 386
+RCL rm32,imm8 [mi: o32 c1 /2 ib,u] 386
+RCL rm64,unity [m-: o64 d1 /2] X86_64,LONG
+RCL rm64,reg_cl [m-: o64 d3 /2] X86_64,LONG
+RCL rm64,imm8 [mi: o64 c1 /2 ib,u] X86_64,LONG
+RCR rm8,unity [m-: d0 /3] 8086
+RCR rm8,reg_cl [m-: d2 /3] 8086
+RCR rm8,imm8 [mi: c0 /3 ib,u] 186
+RCR rm16,unity [m-: o16 d1 /3] 8086
+RCR rm16,reg_cl [m-: o16 d3 /3] 8086
+RCR rm16,imm8 [mi: o16 c1 /3 ib,u] 186
+RCR rm32,unity [m-: o32 d1 /3] 386
+RCR rm32,reg_cl [m-: o32 d3 /3] 386
+RCR rm32,imm8 [mi: o32 c1 /3 ib,u] 386
+RCR rm64,unity [m-: o64 d1 /3] X86_64,LONG
+RCR rm64,reg_cl [m-: o64 d3 /3] X86_64,LONG
+RCR rm64,imm8 [mi: o64 c1 /3 ib,u] X86_64,LONG
+RDSHR rm32 [m: o32 0f 36 /0] P6,CYRIX,SMM
+RDMSR void [ 0f 32] PENT,PRIV
+RDPMC void [ 0f 33] P6
+RDTSC void [ 0f 31] PENT
+RDTSCP void [ 0f 01 f9] X86_64
+RET void [ c3] 8086,BND
+RET imm [i: c2 iw] 8086,SW,BND
+RETF void [ cb] 8086
+RETF imm [i: ca iw] 8086,SW
+RETN void [ c3] 8086,BND
+RETN imm [i: c2 iw] 8086,SW,BND
+RETW void [ o16 c3] 8086,BND
+RETW imm [i: c2 iw] 8086,SW,BND
+RETFW void [ o16 cb] 8086
+RETFW imm [i: o16 ca iw] 8086,SW
+RETNW void [ o16 c3] 8086,BND
+RETNW imm [i: o16 c2 iw] 8086,SW,BND
+RETD void [ o32 c3] 8086,BND,NOLONG
+RETD imm [i: o32 c2 iw] 8086,SW,BND,NOLONG
+RETFD void [ o32 cb] 8086
+RETFD imm [i: o32 ca iw] 8086,SW
+RETND void [ o32 c3] 8086,BND,NOLONG
+RETND imm [i: o32 c2 iw] 8086,SW,BND,NOLONG
+RETQ void [ o64nw c3] X86_64,LONG,BND
+RETQ imm [i: o64nw c2 iw] X86_64,LONG,SW,BND
+RETFQ void [ o64 cb] X86_64,LONG
+RETFQ imm [i: o64 ca iw] X86_64,LONG,SW
+RETNQ void [ o64nw c3] X86_64,LONG,BND
+RETNQ imm [i: o64nw c2 iw] X86_64,LONG,SW,BND
+
+ROL rm8,unity [m-: d0 /0] 8086
+ROL rm8,reg_cl [m-: d2 /0] 8086
+ROL rm8,imm8 [mi: c0 /0 ib,u] 186
+ROL rm16,unity [m-: o16 d1 /0] 8086
+ROL rm16,reg_cl [m-: o16 d3 /0] 8086
+ROL rm16,imm8 [mi: o16 c1 /0 ib,u] 186
+ROL rm32,unity [m-: o32 d1 /0] 386
+ROL rm32,reg_cl [m-: o32 d3 /0] 386
+ROL rm32,imm8 [mi: o32 c1 /0 ib,u] 386
+ROL rm64,unity [m-: o64 d1 /0] X86_64,LONG
+ROL rm64,reg_cl [m-: o64 d3 /0] X86_64,LONG
+ROL rm64,imm8 [mi: o64 c1 /0 ib,u] X86_64,LONG
+ROR rm8,unity [m-: d0 /1] 8086
+ROR rm8,reg_cl [m-: d2 /1] 8086
+ROR rm8,imm8 [mi: c0 /1 ib,u] 186
+ROR rm16,unity [m-: o16 d1 /1] 8086
+ROR rm16,reg_cl [m-: o16 d3 /1] 8086
+ROR rm16,imm8 [mi: o16 c1 /1 ib,u] 186
+ROR rm32,unity [m-: o32 d1 /1] 386
+ROR rm32,reg_cl [m-: o32 d3 /1] 386
+ROR rm32,imm8 [mi: o32 c1 /1 ib,u] 386
+ROR rm64,unity [m-: o64 d1 /1] X86_64,LONG
+ROR rm64,reg_cl [m-: o64 d3 /1] X86_64,LONG
+ROR rm64,imm8 [mi: o64 c1 /1 ib,u] X86_64,LONG
+RDM void [ 0f 3a] P6,CYRIX,ND
+RSDC reg_sreg,mem80 [rm: 0f 79 /r] 486,CYRIX,SMM
+RSLDT mem80 [m: 0f 7b /0] 486,CYRIX,SMM
+RSM void [ 0f aa] PENT,SMM
+RSTS mem80 [m: 0f 7d /0] 486,CYRIX,SMM
+SAHF void [ 9e] 8086
+SAL rm8,unity [m-: d0 /4] 8086,ND
+SAL rm8,reg_cl [m-: d2 /4] 8086,ND
+SAL rm8,imm8 [mi: c0 /4 ib,u] 186,ND
+SAL rm16,unity [m-: o16 d1 /4] 8086,ND
+SAL rm16,reg_cl [m-: o16 d3 /4] 8086,ND
+SAL rm16,imm8 [mi: o16 c1 /4 ib,u] 186,ND
+SAL rm32,unity [m-: o32 d1 /4] 386,ND
+SAL rm32,reg_cl [m-: o32 d3 /4] 386,ND
+SAL rm32,imm8 [mi: o32 c1 /4 ib,u] 386,ND
+SAL rm64,unity [m-: o64 d1 /4] X86_64,LONG,ND
+SAL rm64,reg_cl [m-: o64 d3 /4] X86_64,LONG,ND
+SAL rm64,imm8 [mi: o64 c1 /4 ib,u] X86_64,LONG,ND
+SALC void [ d6] 8086,UNDOC
+SAR rm8,unity [m-: d0 /7] 8086
+SAR rm8,reg_cl [m-: d2 /7] 8086
+SAR rm8,imm8 [mi: c0 /7 ib,u] 186
+SAR rm16,unity [m-: o16 d1 /7] 8086
+SAR rm16,reg_cl [m-: o16 d3 /7] 8086
+SAR rm16,imm8 [mi: o16 c1 /7 ib,u] 186
+SAR rm32,unity [m-: o32 d1 /7] 386
+SAR rm32,reg_cl [m-: o32 d3 /7] 386
+SAR rm32,imm8 [mi: o32 c1 /7 ib,u] 386
+SAR rm64,unity [m-: o64 d1 /7] X86_64,LONG
+SAR rm64,reg_cl [m-: o64 d3 /7] X86_64,LONG
+SAR rm64,imm8 [mi: o64 c1 /7 ib,u] X86_64,LONG
+SBB mem,reg8 [mr: hle 18 /r] 8086,SM,LOCK
+SBB reg8,reg8 [mr: 18 /r] 8086
+SBB mem,reg16 [mr: hle o16 19 /r] 8086,SM,LOCK
+SBB reg16,reg16 [mr: o16 19 /r] 8086
+SBB mem,reg32 [mr: hle o32 19 /r] 386,SM,LOCK
+SBB reg32,reg32 [mr: o32 19 /r] 386
+SBB mem,reg64 [mr: hle o64 19 /r] X86_64,LONG,SM,LOCK
+SBB reg64,reg64 [mr: o64 19 /r] X86_64,LONG
+SBB reg8,mem [rm: 1a /r] 8086,SM
+SBB reg8,reg8 [rm: 1a /r] 8086
+SBB reg16,mem [rm: o16 1b /r] 8086,SM
+SBB reg16,reg16 [rm: o16 1b /r] 8086
+SBB reg32,mem [rm: o32 1b /r] 386,SM
+SBB reg32,reg32 [rm: o32 1b /r] 386
+SBB reg64,mem [rm: o64 1b /r] X86_64,LONG,SM
+SBB reg64,reg64 [rm: o64 1b /r] X86_64,LONG
+SBB rm16,imm8 [mi: hle o16 83 /3 ib,s] 8086,LOCK
+SBB rm32,imm8 [mi: hle o32 83 /3 ib,s] 386,LOCK
+SBB rm64,imm8 [mi: hle o64 83 /3 ib,s] X86_64,LONG,LOCK
+SBB reg_al,imm [-i: 1c ib] 8086,SM
+SBB reg_ax,sbyteword [mi: o16 83 /3 ib,s] 8086,SM,ND
+SBB reg_ax,imm [-i: o16 1d iw] 8086,SM
+SBB reg_eax,sbytedword [mi: o32 83 /3 ib,s] 386,SM,ND
+SBB reg_eax,imm [-i: o32 1d id] 386,SM
+SBB reg_rax,sbytedword [mi: o64 83 /3 ib,s] X86_64,LONG,SM,ND
+SBB reg_rax,imm [-i: o64 1d id,s] X86_64,LONG,SM
+SBB rm8,imm [mi: hle 80 /3 ib] 8086,SM,LOCK
+SBB rm16,sbyteword [mi: hle o16 83 /3 ib,s] 8086,SM,LOCK,ND
+SBB rm16,imm [mi: hle o16 81 /3 iw] 8086,SM,LOCK
+SBB rm32,sbytedword [mi: hle o32 83 /3 ib,s] 386,SM,LOCK,ND
+SBB rm32,imm [mi: hle o32 81 /3 id] 386,SM,LOCK
+SBB rm64,sbytedword [mi: hle o64 83 /3 ib,s] X86_64,LONG,SM,LOCK,ND
+SBB rm64,imm [mi: hle o64 81 /3 id,s] X86_64,LONG,SM,LOCK
+SBB mem,imm8 [mi: hle 80 /3 ib] 8086,SM,LOCK
+SBB mem,sbyteword16 [mi: hle o16 83 /3 ib,s] 8086,SM,LOCK,ND
+SBB mem,imm16 [mi: hle o16 81 /3 iw] 8086,SM,LOCK
+SBB mem,sbytedword32 [mi: hle o32 83 /3 ib,s] 386,SM,LOCK,ND
+SBB mem,imm32 [mi: hle o32 81 /3 id] 386,SM,LOCK
+SBB rm8,imm [mi: hle 82 /3 ib] 8086,SM,LOCK,ND,NOLONG
+SCASB void [ repe ae] 8086
+SCASD void [ repe o32 af] 386
+SCASQ void [ repe o64 af] X86_64,LONG
+SCASW void [ repe o16 af] 8086
+SFENCE void [ np 0f ae f8] X86_64,LONG,AMD
+SGDT mem [m: 0f 01 /0] 286
+SHL rm8,unity [m-: d0 /4] 8086
+SHL rm8,reg_cl [m-: d2 /4] 8086
+SHL rm8,imm8 [mi: c0 /4 ib,u] 186
+SHL rm16,unity [m-: o16 d1 /4] 8086
+SHL rm16,reg_cl [m-: o16 d3 /4] 8086
+SHL rm16,imm8 [mi: o16 c1 /4 ib,u] 186
+SHL rm32,unity [m-: o32 d1 /4] 386
+SHL rm32,reg_cl [m-: o32 d3 /4] 386
+SHL rm32,imm8 [mi: o32 c1 /4 ib,u] 386
+SHL rm64,unity [m-: o64 d1 /4] X86_64,LONG
+SHL rm64,reg_cl [m-: o64 d3 /4] X86_64,LONG
+SHL rm64,imm8 [mi: o64 c1 /4 ib,u] X86_64,LONG
+SHLD mem,reg16,imm [mri: o16 0f a4 /r ib,u] 386,SM2,SB,AR2
+SHLD reg16,reg16,imm [mri: o16 0f a4 /r ib,u] 386,SM2,SB,AR2
+SHLD mem,reg32,imm [mri: o32 0f a4 /r ib,u] 386,SM2,SB,AR2
+SHLD reg32,reg32,imm [mri: o32 0f a4 /r ib,u] 386,SM2,SB,AR2
+SHLD mem,reg64,imm [mri: o64 0f a4 /r ib,u] X86_64,LONG,SM2,SB,AR2
+SHLD reg64,reg64,imm [mri: o64 0f a4 /r ib,u] X86_64,LONG,SM2,SB,AR2
+SHLD mem,reg16,reg_cl [mr-: o16 0f a5 /r] 386,SM
+SHLD reg16,reg16,reg_cl [mr-: o16 0f a5 /r] 386
+SHLD mem,reg32,reg_cl [mr-: o32 0f a5 /r] 386,SM
+SHLD reg32,reg32,reg_cl [mr-: o32 0f a5 /r] 386
+SHLD mem,reg64,reg_cl [mr-: o64 0f a5 /r] X86_64,LONG,SM
+SHLD reg64,reg64,reg_cl [mr-: o64 0f a5 /r] X86_64,LONG
+SHR rm8,unity [m-: d0 /5] 8086
+SHR rm8,reg_cl [m-: d2 /5] 8086
+SHR rm8,imm8 [mi: c0 /5 ib,u] 186
+SHR rm16,unity [m-: o16 d1 /5] 8086
+SHR rm16,reg_cl [m-: o16 d3 /5] 8086
+SHR rm16,imm8 [mi: o16 c1 /5 ib,u] 186
+SHR rm32,unity [m-: o32 d1 /5] 386
+SHR rm32,reg_cl [m-: o32 d3 /5] 386
+SHR rm32,imm8 [mi: o32 c1 /5 ib,u] 386
+SHR rm64,unity [m-: o64 d1 /5] X86_64,LONG
+SHR rm64,reg_cl [m-: o64 d3 /5] X86_64,LONG
+SHR rm64,imm8 [mi: o64 c1 /5 ib,u] X86_64,LONG
+SHRD mem,reg16,imm [mri: o16 0f ac /r ib,u] 386,SM2,SB,AR2
+SHRD reg16,reg16,imm [mri: o16 0f ac /r ib,u] 386,SM2,SB,AR2
+SHRD mem,reg32,imm [mri: o32 0f ac /r ib,u] 386,SM2,SB,AR2
+SHRD reg32,reg32,imm [mri: o32 0f ac /r ib,u] 386,SM2,SB,AR2
+SHRD mem,reg64,imm [mri: o64 0f ac /r ib,u] X86_64,LONG,SM2,SB,AR2
+SHRD reg64,reg64,imm [mri: o64 0f ac /r ib,u] X86_64,LONG,SM2,SB,AR2
+SHRD mem,reg16,reg_cl [mr-: o16 0f ad /r] 386,SM
+SHRD reg16,reg16,reg_cl [mr-: o16 0f ad /r] 386
+SHRD mem,reg32,reg_cl [mr-: o32 0f ad /r] 386,SM
+SHRD reg32,reg32,reg_cl [mr-: o32 0f ad /r] 386
+SHRD mem,reg64,reg_cl [mr-: o64 0f ad /r] X86_64,LONG,SM
+SHRD reg64,reg64,reg_cl [mr-: o64 0f ad /r] X86_64,LONG
+SIDT mem [m: 0f 01 /1] 286
+SLDT mem [m: 0f 00 /0] 286
+SLDT mem16 [m: 0f 00 /0] 286
+SLDT reg16 [m: o16 0f 00 /0] 286
+SLDT reg32 [m: o32 0f 00 /0] 386
+SLDT reg64 [m: o64nw 0f 00 /0] X86_64,LONG,ND
+SLDT reg64 [m: o64 0f 00 /0] X86_64,LONG
+SKINIT void [ 0f 01 de] X86_64,LONG
+SMI void [ f1] 386,UNDOC
+SMINT void [ 0f 38] P6,CYRIX,ND
+; Older Cyrix chips had this; they had to move due to conflict with MMX
+SMINTOLD void [ 0f 7e] 486,CYRIX,ND,OBSOLETE
+SMSW mem [m: 0f 01 /4] 286
+SMSW mem16 [m: 0f 01 /4] 286
+SMSW reg16 [m: o16 0f 01 /4] 286
+SMSW reg32 [m: o32 0f 01 /4] 386
+SMSW reg64 [m: o64 0f 01 /4] X86_64,LONG
+STC void [ f9] 8086
+STD void [ fd] 8086
+STI void [ fb] 8086
+STOSB void [ aa] 8086
+STOSD void [ o32 ab] 386
+STOSQ void [ o64 ab] X86_64,LONG
+STOSW void [ o16 ab] 8086
+STR mem [m: 0f 00 /1] 286,PROT
+STR mem16 [m: 0f 00 /1] 286,PROT
+STR reg16 [m: o16 0f 00 /1] 286,PROT
+STR reg32 [m: o32 0f 00 /1] 386,PROT
+STR reg64 [m: o64 0f 00 /1] X86_64,LONG
+SUB mem,reg8 [mr: hle 28 /r] 8086,SM,LOCK
+SUB reg8,reg8 [mr: 28 /r] 8086
+SUB mem,reg16 [mr: hle o16 29 /r] 8086,SM,LOCK
+SUB reg16,reg16 [mr: o16 29 /r] 8086
+SUB mem,reg32 [mr: hle o32 29 /r] 386,SM,LOCK
+SUB reg32,reg32 [mr: o32 29 /r] 386
+SUB mem,reg64 [mr: hle o64 29 /r] X86_64,LONG,SM,LOCK
+SUB reg64,reg64 [mr: o64 29 /r] X86_64,LONG
+SUB reg8,mem [rm: 2a /r] 8086,SM
+SUB reg8,reg8 [rm: 2a /r] 8086
+SUB reg16,mem [rm: o16 2b /r] 8086,SM
+SUB reg16,reg16 [rm: o16 2b /r] 8086
+SUB reg32,mem [rm: o32 2b /r] 386,SM
+SUB reg32,reg32 [rm: o32 2b /r] 386
+SUB reg64,mem [rm: o64 2b /r] X86_64,LONG,SM
+SUB reg64,reg64 [rm: o64 2b /r] X86_64,LONG
+SUB rm16,imm8 [mi: hle o16 83 /5 ib,s] 8086,LOCK
+SUB rm32,imm8 [mi: hle o32 83 /5 ib,s] 386,LOCK
+SUB rm64,imm8 [mi: hle o64 83 /5 ib,s] X86_64,LONG,LOCK
+SUB reg_al,imm [-i: 2c ib] 8086,SM
+SUB reg_ax,sbyteword [mi: o16 83 /5 ib,s] 8086,SM,ND
+SUB reg_ax,imm [-i: o16 2d iw] 8086,SM
+SUB reg_eax,sbytedword [mi: o32 83 /5 ib,s] 386,SM,ND
+SUB reg_eax,imm [-i: o32 2d id] 386,SM
+SUB reg_rax,sbytedword [mi: o64 83 /5 ib,s] X86_64,LONG,SM,ND
+SUB reg_rax,imm [-i: o64 2d id,s] X86_64,LONG,SM
+SUB rm8,imm [mi: hle 80 /5 ib] 8086,SM,LOCK
+SUB rm16,sbyteword [mi: hle o16 83 /5 ib,s] 8086,SM,LOCK,ND
+SUB rm16,imm [mi: hle o16 81 /5 iw] 8086,SM,LOCK
+SUB rm32,sbytedword [mi: hle o32 83 /5 ib,s] 386,SM,LOCK,ND
+SUB rm32,imm [mi: hle o32 81 /5 id] 386,SM,LOCK
+SUB rm64,sbytedword [mi: hle o64 83 /5 ib,s] X86_64,LONG,SM,LOCK,ND
+SUB rm64,imm [mi: hle o64 81 /5 id,s] X86_64,LONG,SM,LOCK
+SUB mem,imm8 [mi: hle 80 /5 ib] 8086,SM,LOCK
+SUB mem,sbyteword16 [mi: hle o16 83 /5 ib,s] 8086,SM,LOCK,ND
+SUB mem,imm16 [mi: hle o16 81 /5 iw] 8086,SM,LOCK
+SUB mem,sbytedword32 [mi: hle o32 83 /5 ib,s] 386,SM,LOCK,ND
+SUB mem,imm32 [mi: hle o32 81 /5 id] 386,SM,LOCK
+SUB rm8,imm [mi: hle 82 /5 ib] 8086,SM,LOCK,ND,NOLONG
+SVDC mem80,reg_sreg [mr: 0f 78 /r] 486,CYRIX,SMM
+SVLDT mem80 [m: 0f 7a /0] 486,CYRIX,SMM,ND
+SVTS mem80 [m: 0f 7c /0] 486,CYRIX,SMM
+SWAPGS void [ 0f 01 f8] X86_64,LONG
+SYSCALL void [ 0f 05] P6,AMD
+SYSENTER void [ 0f 34] P6
+SYSEXIT void [ 0f 35] P6,PRIV
+SYSRET void [ 0f 07] P6,PRIV,AMD
+TEST mem,reg8 [mr: 84 /r] 8086,SM
+TEST reg8,reg8 [mr: 84 /r] 8086
+TEST mem,reg16 [mr: o16 85 /r] 8086,SM
+TEST reg16,reg16 [mr: o16 85 /r] 8086
+TEST mem,reg32 [mr: o32 85 /r] 386,SM
+TEST reg32,reg32 [mr: o32 85 /r] 386
+TEST mem,reg64 [mr: o64 85 /r] X86_64,LONG,SM
+TEST reg64,reg64 [mr: o64 85 /r] X86_64,LONG
+TEST reg8,mem [rm: 84 /r] 8086,SM
+TEST reg16,mem [rm: o16 85 /r] 8086,SM
+TEST reg32,mem [rm: o32 85 /r] 386,SM
+TEST reg64,mem [rm: o64 85 /r] X86_64,LONG,SM
+TEST reg_al,imm [-i: a8 ib] 8086,SM
+TEST reg_ax,imm [-i: o16 a9 iw] 8086,SM
+TEST reg_eax,imm [-i: o32 a9 id] 386,SM
+TEST reg_rax,imm [-i: o64 a9 id,s] X86_64,LONG,SM
+TEST rm8,imm [mi: f6 /0 ib] 8086,SM
+TEST rm16,imm [mi: o16 f7 /0 iw] 8086,SM
+TEST rm32,imm [mi: o32 f7 /0 id] 386,SM
+TEST rm64,imm [mi: o64 f7 /0 id,s] X86_64,LONG,SM
+TEST mem,imm8 [mi: f6 /0 ib] 8086,SM
+TEST mem,imm16 [mi: o16 f7 /0 iw] 8086,SM
+TEST mem,imm32 [mi: o32 f7 /0 id] 386,SM
+UD0 void [ 0f ff] 186,OBSOLETE
+UD0 reg16,rm16 [rm: o16 0f ff /r] 186
+UD0 reg32,rm32 [rm: o32 0f ff /r] 186
+UD0 reg64,rm64 [rm: o64 0f ff /r] 186
+UD1 reg16,rm16 [rm: o16 0f b9 /r] 186
+UD1 reg32,rm32 [rm: o32 0f b9 /r] 186
+UD1 reg64,rm64 [rm: o64 0f b9 /r] 186
+UD1 void [ 0f b9] 186,ND
+UD2B void [ 0f b9] 186,ND
+UD2B reg16,rm16 [rm: o16 0f b9 /r] 186,ND
+UD2B reg32,rm32 [rm: o32 0f b9 /r] 186,ND
+UD2B reg64,rm64 [rm: o64 0f b9 /r] 186,ND
+UD2 void [ 0f 0b] 186
+UD2A void [ 0f 0b] 186,ND
+UMOV mem,reg8 [mr: np 0f 10 /r] 386,UNDOC,SM,ND
+UMOV reg8,reg8 [mr: np 0f 10 /r] 386,UNDOC,ND
+UMOV mem,reg16 [mr: np o16 0f 11 /r] 386,UNDOC,SM,ND
+UMOV reg16,reg16 [mr: np o16 0f 11 /r] 386,UNDOC,ND
+UMOV mem,reg32 [mr: np o32 0f 11 /r] 386,UNDOC,SM,ND
+UMOV reg32,reg32 [mr: np o32 0f 11 /r] 386,UNDOC,ND
+UMOV reg8,mem [rm: np 0f 12 /r] 386,UNDOC,SM,ND
+UMOV reg8,reg8 [rm: np 0f 12 /r] 386,UNDOC,ND
+UMOV reg16,mem [rm: np o16 0f 13 /r] 386,UNDOC,SM,ND
+UMOV reg16,reg16 [rm: np o16 0f 13 /r] 386,UNDOC,ND
+UMOV reg32,mem [rm: np o32 0f 13 /r] 386,UNDOC,SM,ND
+UMOV reg32,reg32 [rm: np o32 0f 13 /r] 386,UNDOC,ND
+VERR mem [m: 0f 00 /4] 286,PROT
+VERR mem16 [m: 0f 00 /4] 286,PROT
+VERR reg16 [m: 0f 00 /4] 286,PROT
+VERW mem [m: 0f 00 /5] 286,PROT
+VERW mem16 [m: 0f 00 /5] 286,PROT
+VERW reg16 [m: 0f 00 /5] 286,PROT
+FWAIT void [ wait] 8086
+WBINVD void [ 0f 09] 486,PRIV
+WRSHR rm32 [m: o32 0f 37 /0] P6,CYRIX,SMM
+WRMSR void [ 0f 30] PENT,PRIV
+XADD mem,reg8 [mr: hle 0f c0 /r] 486,SM,LOCK
+XADD reg8,reg8 [mr: 0f c0 /r] 486
+XADD mem,reg16 [mr: hle o16 0f c1 /r] 486,SM,LOCK
+XADD reg16,reg16 [mr: o16 0f c1 /r] 486
+XADD mem,reg32 [mr: hle o32 0f c1 /r] 486,SM,LOCK
+XADD reg32,reg32 [mr: o32 0f c1 /r] 486
+XADD mem,reg64 [mr: hle o64 0f c1 /r] X86_64,LONG,SM,LOCK
+XADD reg64,reg64 [mr: o64 0f c1 /r] X86_64,LONG
+XBTS reg16,mem [rm: o16 0f a6 /r] 386,SW,UNDOC,ND
+XBTS reg16,reg16 [rm: o16 0f a6 /r] 386,UNDOC,ND
+XBTS reg32,mem [rm: o32 0f a6 /r] 386,SD,UNDOC,ND
+XBTS reg32,reg32 [rm: o32 0f a6 /r] 386,UNDOC,ND
+XCHG reg_ax,reg16 [-r: o16 90+r] 8086
+XCHG reg_eax,reg32na [-r: o32 90+r] 386
+XCHG reg_rax,reg64 [-r: o64 90+r] X86_64,LONG
+XCHG reg16,reg_ax [r-: o16 90+r] 8086
+XCHG reg32na,reg_eax [r-: o32 90+r] 386
+XCHG reg64,reg_rax [r-: o64 90+r] X86_64,LONG
+; This must be NOLONG since opcode 90 is NOP, and in 64-bit mode
+; "xchg eax,eax" is *not* a NOP.
+XCHG reg_eax,reg_eax [--: o32 90] 386,NOLONG
+XCHG reg8,mem [rm: hlenl 86 /r] 8086,SM,LOCK
+XCHG reg8,reg8 [rm: 86 /r] 8086
+XCHG reg16,mem [rm: hlenl o16 87 /r] 8086,SM,LOCK
+XCHG reg16,reg16 [rm: o16 87 /r] 8086
+XCHG reg32,mem [rm: hlenl o32 87 /r] 386,SM,LOCK
+XCHG reg32,reg32 [rm: o32 87 /r] 386
+XCHG reg64,mem [rm: hlenl o64 87 /r] X86_64,LONG,SM,LOCK
+XCHG reg64,reg64 [rm: o64 87 /r] X86_64,LONG
+XCHG mem,reg8 [mr: hlenl 86 /r] 8086,SM,LOCK
+XCHG reg8,reg8 [mr: 86 /r] 8086
+XCHG mem,reg16 [mr: hlenl o16 87 /r] 8086,SM,LOCK
+XCHG reg16,reg16 [mr: o16 87 /r] 8086
+XCHG mem,reg32 [mr: hlenl o32 87 /r] 386,SM,LOCK
+XCHG reg32,reg32 [mr: o32 87 /r] 386
+XCHG mem,reg64 [mr: hlenl o64 87 /r] X86_64,LONG,SM,LOCK
+XCHG reg64,reg64 [mr: o64 87 /r] X86_64,LONG
+XLATB void [ d7] 8086
+XLAT void [ d7] 8086
+XOR mem,reg8 [mr: hle 30 /r] 8086,SM,LOCK
+XOR reg8,reg8 [mr: 30 /r] 8086
+XOR mem,reg16 [mr: hle o16 31 /r] 8086,SM,LOCK
+XOR reg16,reg16 [mr: o16 31 /r] 8086
+XOR mem,reg32 [mr: hle o32 31 /r] 386,SM,LOCK
+XOR reg32,reg32 [mr: o32 31 /r] 386
+XOR mem,reg64 [mr: hle o64 31 /r] X86_64,LONG,SM,LOCK
+XOR reg64,reg64 [mr: o64 31 /r] X86_64,LONG
+XOR reg8,mem [rm: 32 /r] 8086,SM
+XOR reg8,reg8 [rm: 32 /r] 8086
+XOR reg16,mem [rm: o16 33 /r] 8086,SM
+XOR reg16,reg16 [rm: o16 33 /r] 8086
+XOR reg32,mem [rm: o32 33 /r] 386,SM
+XOR reg32,reg32 [rm: o32 33 /r] 386
+XOR reg64,mem [rm: o64 33 /r] X86_64,LONG,SM
+XOR reg64,reg64 [rm: o64 33 /r] X86_64,LONG
+XOR rm16,imm8 [mi: hle o16 83 /6 ib,s] 8086,LOCK
+XOR rm32,imm8 [mi: hle o32 83 /6 ib,s] 386,LOCK
+XOR rm64,imm8 [mi: hle o64 83 /6 ib,s] X86_64,LONG,LOCK
+XOR reg_al,imm [-i: 34 ib] 8086,SM
+XOR reg_ax,sbyteword [mi: o16 83 /6 ib,s] 8086,SM,ND
+XOR reg_ax,imm [-i: o16 35 iw] 8086,SM
+XOR reg_eax,sbytedword [mi: o32 83 /6 ib,s] 386,SM,ND
+XOR reg_eax,imm [-i: o32 35 id] 386,SM
+XOR reg_rax,sbytedword [mi: o64 83 /6 ib,s] X86_64,LONG,SM,ND
+XOR reg_rax,imm [-i: o64 35 id,s] X86_64,LONG,SM
+XOR rm8,imm [mi: hle 80 /6 ib] 8086,SM,LOCK
+XOR rm16,sbyteword [mi: hle o16 83 /6 ib,s] 8086,SM,LOCK,ND
+XOR rm16,imm [mi: hle o16 81 /6 iw] 8086,SM,LOCK
+XOR rm32,sbytedword [mi: hle o32 83 /6 ib,s] 386,SM,LOCK,ND
+XOR rm32,imm [mi: hle o32 81 /6 id] 386,SM,LOCK
+XOR rm64,sbytedword [mi: hle o64 83 /6 ib,s] X86_64,LONG,SM,LOCK,ND
+XOR rm64,imm [mi: hle o64 81 /6 id,s] X86_64,LONG,SM,LOCK
+XOR mem,imm8 [mi: hle 80 /6 ib] 8086,SM,LOCK
+XOR mem,sbyteword16 [mi: hle o16 83 /6 ib,s] 8086,SM,LOCK,ND
+XOR mem,imm16 [mi: hle o16 81 /6 iw] 8086,SM,LOCK
+XOR mem,sbytedword32 [mi: hle o32 83 /6 ib,s] 386,SM,LOCK,ND
+XOR mem,imm32 [mi: hle o32 81 /6 id] 386,SM,LOCK
+XOR rm8,imm [mi: hle 82 /6 ib] 8086,SM,LOCK,ND,NOLONG
+CMOVcc reg16,mem [rm: o16 0f 40+c /r] P6,SM
+CMOVcc reg16,reg16 [rm: o16 0f 40+c /r] P6
+CMOVcc reg32,mem [rm: o32 0f 40+c /r] P6,SM
+CMOVcc reg32,reg32 [rm: o32 0f 40+c /r] P6
+CMOVcc reg64,mem [rm: o64 0f 40+c /r] X86_64,LONG,SM
+CMOVcc reg64,reg64 [rm: o64 0f 40+c /r] X86_64,LONG
+Jcc imm|near [i: odf 0f 80+c rel] 386,BND
+Jcc imm16|near [i: o16 0f 80+c rel] 386,NOLONG,BND
+Jcc imm32|near [i: o32 0f 80+c rel] 386,NOLONG,BND
+Jcc imm64|near [i: o64nw 0f 80+c rel] X86_64,LONG,BND
+Jcc imm|short [i: 70+c rel8] 8086,ND,BND
+Jcc imm [i: jcc8 70+c rel8] 8086,ND,BND
+Jcc imm [i: 0f 80+c rel] 386,ND,BND
+Jcc imm [i: 71+c jlen e9 rel] 8086,ND,BND
+Jcc imm [i: 70+c rel8] 8086,BND
+
+SETcc mem [m: 0f 90+c /0] 386,SB
+SETcc reg8 [m: 0f 90+c /0] 386
+
+;# Katmai Streaming SIMD instructions (SSE -- a.k.a. KNI, XMM, MMX2)
+ADDPS xmmreg,xmmrm128 [rm: np 0f 58 /r] KATMAI,SSE
+ADDSS xmmreg,xmmrm32 [rm: f3 0f 58 /r] KATMAI,SSE
+ANDNPS xmmreg,xmmrm128 [rm: np 0f 55 /r] KATMAI,SSE
+ANDPS xmmreg,xmmrm128 [rm: np 0f 54 /r] KATMAI,SSE
+CMPEQPS xmmreg,xmmrm128 [rm: np 0f c2 /r 00] KATMAI,SSE
+CMPEQSS xmmreg,xmmrm32 [rm: f3 0f c2 /r 00] KATMAI,SSE
+CMPLEPS xmmreg,xmmrm128 [rm: np 0f c2 /r 02] KATMAI,SSE
+CMPLESS xmmreg,xmmrm32 [rm: f3 0f c2 /r 02] KATMAI,SSE
+CMPLTPS xmmreg,xmmrm128 [rm: np 0f c2 /r 01] KATMAI,SSE
+CMPLTSS xmmreg,xmmrm32 [rm: f3 0f c2 /r 01] KATMAI,SSE
+CMPNEQPS xmmreg,xmmrm128 [rm: np 0f c2 /r 04] KATMAI,SSE
+CMPNEQSS xmmreg,xmmrm32 [rm: f3 0f c2 /r 04] KATMAI,SSE
+CMPNLEPS xmmreg,xmmrm128 [rm: np 0f c2 /r 06] KATMAI,SSE
+CMPNLESS xmmreg,xmmrm32 [rm: f3 0f c2 /r 06] KATMAI,SSE
+CMPNLTPS xmmreg,xmmrm128 [rm: np 0f c2 /r 05] KATMAI,SSE
+CMPNLTSS xmmreg,xmmrm32 [rm: f3 0f c2 /r 05] KATMAI,SSE
+CMPORDPS xmmreg,xmmrm128 [rm: np 0f c2 /r 07] KATMAI,SSE
+CMPORDSS xmmreg,xmmrm32 [rm: f3 0f c2 /r 07] KATMAI,SSE
+CMPUNORDPS xmmreg,xmmrm128 [rm: np 0f c2 /r 03] KATMAI,SSE
+CMPUNORDSS xmmreg,xmmrm32 [rm: f3 0f c2 /r 03] KATMAI,SSE
+; CMPPS/CMPSS must come after the specific ops; that way the disassembler will find the
+; specific ops first and only disassemble illegal ones as cmpps/cmpss.
+CMPPS xmmreg,xmmrm128,imm8 [rmi: np 0f c2 /r ib,u] KATMAI,SSE
+CMPSS xmmreg,xmmrm32,imm8 [rmi: f3 0f c2 /r ib,u] KATMAI,SSE
+COMISS xmmreg,xmmrm32 [rm: np 0f 2f /r] KATMAI,SSE
+CVTPI2PS xmmreg,mmxrm64 [rm: np 0f 2a /r] KATMAI,SSE,MMX
+CVTPS2PI mmxreg,xmmrm64 [rm: np 0f 2d /r] KATMAI,SSE,MMX
+CVTSI2SS xmmreg,mem [rm: f3 0f 2a /r] KATMAI,SSE,SD,AR1,ND
+CVTSI2SS xmmreg,rm32 [rm: f3 0f 2a /r] KATMAI,SSE,SD,AR1
+CVTSI2SS xmmreg,rm64 [rm: o64 f3 0f 2a /r] X86_64,LONG,SSE,SQ,AR1
+CVTSS2SI reg32,xmmreg [rm: f3 0f 2d /r] KATMAI,SSE,SD,AR1
+CVTSS2SI reg32,mem [rm: f3 0f 2d /r] KATMAI,SSE,SD,AR1
+CVTSS2SI reg64,xmmreg [rm: o64 f3 0f 2d /r] X86_64,LONG,SSE,SD,AR1
+CVTSS2SI reg64,mem [rm: o64 f3 0f 2d /r] X86_64,LONG,SSE,SD,AR1
+CVTTPS2PI mmxreg,xmmrm [rm: np 0f 2c /r] KATMAI,SSE,MMX,SQ
+CVTTSS2SI reg32,xmmrm [rm: f3 0f 2c /r] KATMAI,SSE,SD,AR1
+CVTTSS2SI reg64,xmmrm [rm: o64 f3 0f 2c /r] X86_64,LONG,SSE,SD,AR1
+DIVPS xmmreg,xmmrm128 [rm: np 0f 5e /r] KATMAI,SSE
+DIVSS xmmreg,xmmrm32 [rm: f3 0f 5e /r] KATMAI,SSE
+LDMXCSR mem32 [m: np 0f ae /2] KATMAI,SSE
+MAXPS xmmreg,xmmrm128 [rm: np 0f 5f /r] KATMAI,SSE
+MAXSS xmmreg,xmmrm32 [rm: f3 0f 5f /r] KATMAI,SSE
+MINPS xmmreg,xmmrm128 [rm: np 0f 5d /r] KATMAI,SSE
+MINSS xmmreg,xmmrm32 [rm: f3 0f 5d /r] KATMAI,SSE
+MOVAPS xmmreg,xmmrm128 [rm: np 0f 28 /r] KATMAI,SSE
+MOVAPS xmmrm128,xmmreg [mr: np 0f 29 /r] KATMAI,SSE
+MOVHPS xmmreg,mem64 [rm: np 0f 16 /r] KATMAI,SSE
+MOVHPS mem64,xmmreg [mr: np 0f 17 /r] KATMAI,SSE
+MOVLHPS xmmreg,xmmreg [rm: np 0f 16 /r] KATMAI,SSE
+MOVLPS xmmreg,mem64 [rm: np 0f 12 /r] KATMAI,SSE
+MOVLPS mem64,xmmreg [mr: np 0f 13 /r] KATMAI,SSE
+MOVHLPS xmmreg,xmmreg [rm: np 0f 12 /r] KATMAI,SSE
+MOVMSKPS reg32,xmmreg [rm: np 0f 50 /r] KATMAI,SSE
+MOVMSKPS reg64,xmmreg [rm: np o64 0f 50 /r] X86_64,LONG,SSE
+MOVNTPS mem128,xmmreg [mr: np 0f 2b /r] KATMAI,SSE
+MOVSS xmmreg,xmmrm32 [rm: f3 0f 10 /r] KATMAI,SSE
+MOVSS xmmrm32,xmmreg [mr: f3 0f 11 /r] KATMAI,SSE
+MOVUPS xmmreg,xmmrm128 [rm: np 0f 10 /r] KATMAI,SSE
+MOVUPS xmmrm128,xmmreg [mr: np 0f 11 /r] KATMAI,SSE
+MULPS xmmreg,xmmrm128 [rm: np 0f 59 /r] KATMAI,SSE
+MULSS xmmreg,xmmrm32 [rm: f3 0f 59 /r] KATMAI,SSE
+ORPS xmmreg,xmmrm128 [rm: np 0f 56 /r] KATMAI,SSE
+RCPPS xmmreg,xmmrm128 [rm: np 0f 53 /r] KATMAI,SSE
+RCPSS xmmreg,xmmrm32 [rm: f3 0f 53 /r] KATMAI,SSE
+RSQRTPS xmmreg,xmmrm128 [rm: np 0f 52 /r] KATMAI,SSE
+RSQRTSS xmmreg,xmmrm32 [rm: f3 0f 52 /r] KATMAI,SSE
+SHUFPS xmmreg,xmmrm128,imm8 [rmi: np 0f c6 /r ib,u] KATMAI,SSE
+SQRTPS xmmreg,xmmrm128 [rm: np 0f 51 /r] KATMAI,SSE
+SQRTSS xmmreg,xmmrm32 [rm: f3 0f 51 /r] KATMAI,SSE
+STMXCSR mem32 [m: np 0f ae /3] KATMAI,SSE
+SUBPS xmmreg,xmmrm128 [rm: np 0f 5c /r] KATMAI,SSE
+SUBSS xmmreg,xmmrm32 [rm: f3 0f 5c /r] KATMAI,SSE
+UCOMISS xmmreg,xmmrm32 [rm: np 0f 2e /r] KATMAI,SSE
+UNPCKHPS xmmreg,xmmrm128 [rm: np 0f 15 /r] KATMAI,SSE
+UNPCKLPS xmmreg,xmmrm128 [rm: np 0f 14 /r] KATMAI,SSE
+XORPS xmmreg,xmmrm128 [rm: np 0f 57 /r] KATMAI,SSE
+
+;# Introduced in Deschutes but necessary for SSE support
+FXRSTOR mem [m: np 0f ae /1] P6,SSE,FPU
+FXRSTOR64 mem [m: o64 np 0f ae /1] X86_64,LONG,SSE,FPU
+FXSAVE mem [m: np 0f ae /0] P6,SSE,FPU
+FXSAVE64 mem [m: o64 np 0f ae /0] X86_64,LONG,SSE,FPU
+
+;# XSAVE group (AVX and extended state)
+; Introduced in late Penryn ... we really need to clean up the handling
+; of CPU feature bits.
+XGETBV void [ 0f 01 d0] NEHALEM
+XSETBV void [ 0f 01 d1] NEHALEM,PRIV
+XSAVE mem [m: np 0f ae /4] NEHALEM
+XSAVE64 mem [m: o64 np 0f ae /4] LONG,NEHALEM
+XSAVEC mem [m: np 0f c7 /4] FUTURE
+XSAVEC64 mem [m: o64 np 0f c7 /4] LONG,FUTURE
+XSAVEOPT mem [m: np 0f ae /6] FUTURE
+XSAVEOPT64 mem [m: o64 np 0f ae /6] LONG,FUTURE
+XSAVES mem [m: np 0f c7 /5] FUTURE
+XSAVES64 mem [m: o64 np 0f c7 /5] LONG,FUTURE
+XRSTOR mem [m: np 0f ae /5] NEHALEM
+XRSTOR64 mem [m: o64 np 0f ae /5] LONG,NEHALEM
+XRSTORS mem [m: np 0f c7 /3] FUTURE
+XRSTORS64 mem [m: o64 np 0f c7 /3] LONG,FUTURE
+
+; These instructions are not SSE-specific; they are
+;# Generic memory operations
+; and work even if CR4.OSFXFR == 0
+PREFETCHNTA mem8 [m: 0f 18 /0] KATMAI,SB
+PREFETCHT0 mem8 [m: 0f 18 /1] KATMAI,SB
+PREFETCHT1 mem8 [m: 0f 18 /2] KATMAI,SB
+PREFETCHT2 mem8 [m: 0f 18 /3] KATMAI,SB
+PREFETCHIT0 mem8 [m: 0f 18 /7] FUTURE,PREFETCHI,SB
+PREFETCHIT1 mem8 [m: 0f 18 /6] FUTURE,PREFETCHI,SB
+SFENCE void [ np 0f ae f8] KATMAI
+
+;# New MMX instructions introduced in Katmai
+MASKMOVQ mmxreg,mmxreg [rm: np 0f f7 /r] KATMAI,MMX
+MOVNTQ mem,mmxreg [mr: np 0f e7 /r] KATMAI,MMX,SQ
+PAVGB mmxreg,mmxrm [rm: np o64nw 0f e0 /r] KATMAI,MMX,SQ
+PAVGW mmxreg,mmxrm [rm: np o64nw 0f e3 /r] KATMAI,MMX,SQ
+PEXTRW reg32,mmxreg,imm [rmi: np 0f c5 /r ib,u] KATMAI,MMX,SB,AR2
+; PINSRW is documented as using a reg32, but it's really using only 16 bit
+; -- accept either, but be truthful in disassembly
+PINSRW mmxreg,mem,imm [rmi: np 0f c4 /r ib,u] KATMAI,MMX,SB,AR2
+PINSRW mmxreg,rm16,imm [rmi: np 0f c4 /r ib,u] KATMAI,MMX,SB,AR2
+PINSRW mmxreg,reg32,imm [rmi: np 0f c4 /r ib,u] KATMAI,MMX,SB,AR2
+PMAXSW mmxreg,mmxrm [rm: np o64nw 0f ee /r] KATMAI,MMX,SQ
+PMAXUB mmxreg,mmxrm [rm: np o64nw 0f de /r] KATMAI,MMX,SQ
+PMINSW mmxreg,mmxrm [rm: np o64nw 0f ea /r] KATMAI,MMX,SQ
+PMINUB mmxreg,mmxrm [rm: np o64nw 0f da /r] KATMAI,MMX,SQ
+PMOVMSKB reg32,mmxreg [rm: np 0f d7 /r] KATMAI,MMX
+PMULHUW mmxreg,mmxrm [rm: np o64nw 0f e4 /r] KATMAI,MMX,SQ
+PSADBW mmxreg,mmxrm [rm: np o64nw 0f f6 /r] KATMAI,MMX,SQ
+PSHUFW mmxreg,mmxrm,imm [rmi: np o64nw 0f 70 /r ib] KATMAI,MMX,SM2,SB,AR2
+
+;# AMD Enhanced 3DNow! (Athlon) instructions
+PF2IW mmxreg,mmxrm [rm: o64nw 0f 0f /r 1c] PENT,3DNOW,SQ
+PFNACC mmxreg,mmxrm [rm: o64nw 0f 0f /r 8a] PENT,3DNOW,SQ
+PFPNACC mmxreg,mmxrm [rm: o64nw 0f 0f /r 8e] PENT,3DNOW,SQ
+PI2FW mmxreg,mmxrm [rm: o64nw 0f 0f /r 0c] PENT,3DNOW,SQ
+PSWAPD mmxreg,mmxrm [rm: o64nw 0f 0f /r bb] PENT,3DNOW,SQ
+
+;# Willamette SSE2 Cacheability Instructions
+MASKMOVDQU xmmreg,xmmreg [rm: 66 0f f7 /r] WILLAMETTE,SSE2
+; CLFLUSH needs its own feature flag implemented one day
+CLFLUSH mem [m: np 0f ae /7] WILLAMETTE,SSE2
+MOVNTDQ mem,xmmreg [mr: 66 0f e7 /r] WILLAMETTE,SSE2,SO
+MOVNTI mem,reg32 [mr: np 0f c3 /r] WILLAMETTE,SD
+MOVNTI mem,reg64 [mr: o64 np 0f c3 /r] X86_64,LONG,SQ
+MOVNTPD mem,xmmreg [mr: 66 0f 2b /r] WILLAMETTE,SSE2,SO
+LFENCE void [ np 0f ae e8] WILLAMETTE,SSE2
+MFENCE void [ np 0f ae f0] WILLAMETTE,SSE2
+
+;# Willamette MMX instructions (SSE2 SIMD Integer Instructions)
+MOVD mem,xmmreg [mr: 66 norexw 0f 7e /r] WILLAMETTE,SSE2,SD
+MOVD xmmreg,mem [rm: 66 norexw 0f 6e /r] WILLAMETTE,SSE2,SD
+MOVD xmmreg,rm32 [rm: 66 norexw 0f 6e /r] WILLAMETTE,SSE2
+MOVD rm32,xmmreg [mr: 66 norexw 0f 7e /r] WILLAMETTE,SSE2
+MOVDQA xmmreg,xmmrm128 [rm: 66 0f 6f /r] WILLAMETTE,SSE2,SO
+MOVDQA xmmrm128,xmmreg [mr: 66 0f 7f /r] WILLAMETTE,SSE2,SO
+MOVDQU xmmreg,xmmrm128 [rm: f3 0f 6f /r] WILLAMETTE,SSE2,SO
+MOVDQU xmmrm128,xmmreg [mr: f3 0f 7f /r] WILLAMETTE,SSE2,SO
+MOVDQ2Q mmxreg,xmmreg [rm: f2 0f d6 /r] WILLAMETTE,SSE2
+MOVQ xmmreg,xmmreg [rm: f3 0f 7e /r] WILLAMETTE,SSE2
+MOVQ xmmreg,xmmreg [mr: 66 0f d6 /r] WILLAMETTE,SSE2
+MOVQ mem,xmmreg [mr: 66 0f d6 /r] WILLAMETTE,SSE2,SQ
+MOVQ xmmreg,mem [rm: f3 0f 7e /r] WILLAMETTE,SSE2,SQ
+MOVQ xmmreg,rm64 [rm: 66 o64 0f 6e /r] X86_64,LONG,SSE2
+MOVQ rm64,xmmreg [mr: 66 o64 0f 7e /r] X86_64,LONG,SSE2
+MOVQ2DQ xmmreg,mmxreg [rm: f3 0f d6 /r] WILLAMETTE,SSE2
+PACKSSWB xmmreg,xmmrm [rm: 66 0f 63 /r] WILLAMETTE,SSE2,SO
+PACKSSDW xmmreg,xmmrm [rm: 66 0f 6b /r] WILLAMETTE,SSE2,SO
+PACKUSWB xmmreg,xmmrm [rm: 66 0f 67 /r] WILLAMETTE,SSE2,SO
+PADDB xmmreg,xmmrm [rm: 66 0f fc /r] WILLAMETTE,SSE2,SO
+PADDW xmmreg,xmmrm [rm: 66 0f fd /r] WILLAMETTE,SSE2,SO
+PADDD xmmreg,xmmrm [rm: 66 0f fe /r] WILLAMETTE,SSE2,SO
+PADDQ mmxreg,mmxrm [rm: np 0f d4 /r] WILLAMETTE,MMX,SQ
+PADDQ xmmreg,xmmrm [rm: 66 0f d4 /r] WILLAMETTE,SSE2,SO
+PADDSB xmmreg,xmmrm [rm: 66 0f ec /r] WILLAMETTE,SSE2,SO
+PADDSW xmmreg,xmmrm [rm: 66 0f ed /r] WILLAMETTE,SSE2,SO
+PADDUSB xmmreg,xmmrm [rm: 66 0f dc /r] WILLAMETTE,SSE2,SO
+PADDUSW xmmreg,xmmrm [rm: 66 0f dd /r] WILLAMETTE,SSE2,SO
+PAND xmmreg,xmmrm [rm: 66 0f db /r] WILLAMETTE,SSE2,SO
+PANDN xmmreg,xmmrm [rm: 66 0f df /r] WILLAMETTE,SSE2,SO
+PAVGB xmmreg,xmmrm [rm: 66 0f e0 /r] WILLAMETTE,SSE2,SO
+PAVGW xmmreg,xmmrm [rm: 66 0f e3 /r] WILLAMETTE,SSE2,SO
+PCMPEQB xmmreg,xmmrm [rm: 66 0f 74 /r] WILLAMETTE,SSE2,SO
+PCMPEQW xmmreg,xmmrm [rm: 66 0f 75 /r] WILLAMETTE,SSE2,SO
+PCMPEQD xmmreg,xmmrm [rm: 66 0f 76 /r] WILLAMETTE,SSE2,SO
+PCMPGTB xmmreg,xmmrm [rm: 66 0f 64 /r] WILLAMETTE,SSE2,SO
+PCMPGTW xmmreg,xmmrm [rm: 66 0f 65 /r] WILLAMETTE,SSE2,SO
+PCMPGTD xmmreg,xmmrm [rm: 66 0f 66 /r] WILLAMETTE,SSE2,SO
+PEXTRW reg32,xmmreg,imm [rmi: 66 0f c5 /r ib,u] WILLAMETTE,SSE2,SB,AR2
+PEXTRW reg64,xmmreg,imm [rmi: 66 0f c5 /r ib,u] X86_64,LONG,SSE2,SB,AR2,ND
+PINSRW xmmreg,reg16,imm [rmi: 66 0f c4 /r ib,u] WILLAMETTE,SSE2,SB,AR2
+PINSRW xmmreg,reg32,imm [rmi: 66 0f c4 /r ib,u] WILLAMETTE,SSE2,SB,AR2,ND
+PINSRW xmmreg,reg64,imm [rmi: 66 0f c4 /r ib,u] X86_64,LONG,SSE2,SB,AR2,ND
+PINSRW xmmreg,mem,imm [rmi: 66 0f c4 /r ib,u] WILLAMETTE,SSE2,SB,AR2
+PINSRW xmmreg,mem16,imm [rmi: 66 0f c4 /r ib,u] WILLAMETTE,SSE2,SB,AR2
+PMADDWD xmmreg,xmmrm [rm: 66 0f f5 /r] WILLAMETTE,SSE2,SO
+PMAXSW xmmreg,xmmrm [rm: 66 0f ee /r] WILLAMETTE,SSE2,SO
+PMAXUB xmmreg,xmmrm [rm: 66 0f de /r] WILLAMETTE,SSE2,SO
+PMINSW xmmreg,xmmrm [rm: 66 0f ea /r] WILLAMETTE,SSE2,SO
+PMINUB xmmreg,xmmrm [rm: 66 0f da /r] WILLAMETTE,SSE2,SO
+PMOVMSKB reg32,xmmreg [rm: 66 0f d7 /r] WILLAMETTE,SSE2
+PMULHUW xmmreg,xmmrm [rm: 66 0f e4 /r] WILLAMETTE,SSE2,SO
+PMULHW xmmreg,xmmrm [rm: 66 0f e5 /r] WILLAMETTE,SSE2,SO
+PMULLW xmmreg,xmmrm [rm: 66 0f d5 /r] WILLAMETTE,SSE2,SO
+PMULUDQ mmxreg,mmxrm [rm: np o64nw 0f f4 /r] WILLAMETTE,SSE2,SO
+PMULUDQ xmmreg,xmmrm [rm: 66 0f f4 /r] WILLAMETTE,SSE2,SO
+POR xmmreg,xmmrm [rm: 66 0f eb /r] WILLAMETTE,SSE2,SO
+PSADBW xmmreg,xmmrm [rm: 66 0f f6 /r] WILLAMETTE,SSE2,SO
+PSHUFD xmmreg,xmmreg,imm [rmi: 66 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
+PSHUFD xmmreg,mem,imm [rmi: 66 0f 70 /r ib] WILLAMETTE,SSE2,SM2,SB,AR2
+PSHUFHW xmmreg,xmmreg,imm [rmi: f3 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
+PSHUFHW xmmreg,mem,imm [rmi: f3 0f 70 /r ib] WILLAMETTE,SSE2,SM2,SB,AR2
+PSHUFLW xmmreg,xmmreg,imm [rmi: f2 0f 70 /r ib] WILLAMETTE,SSE2,SB,AR2
+PSHUFLW xmmreg,mem,imm [rmi: f2 0f 70 /r ib] WILLAMETTE,SSE2,SM2,SB,AR2
+PSLLDQ xmmreg,imm [mi: 66 0f 73 /7 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSLLW xmmreg,xmmrm [rm: 66 0f f1 /r] WILLAMETTE,SSE2,SO
+PSLLW xmmreg,imm [mi: 66 0f 71 /6 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSLLD xmmreg,xmmrm [rm: 66 0f f2 /r] WILLAMETTE,SSE2,SO
+PSLLD xmmreg,imm [mi: 66 0f 72 /6 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSLLQ xmmreg,xmmrm [rm: 66 0f f3 /r] WILLAMETTE,SSE2,SO
+PSLLQ xmmreg,imm [mi: 66 0f 73 /6 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSRAW xmmreg,xmmrm [rm: 66 0f e1 /r] WILLAMETTE,SSE2,SO
+PSRAW xmmreg,imm [mi: 66 0f 71 /4 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSRAD xmmreg,xmmrm [rm: 66 0f e2 /r] WILLAMETTE,SSE2,SO
+PSRAD xmmreg,imm [mi: 66 0f 72 /4 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSRLDQ xmmreg,imm [mi: 66 0f 73 /3 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSRLW xmmreg,xmmrm [rm: 66 0f d1 /r] WILLAMETTE,SSE2,SO
+PSRLW xmmreg,imm [mi: 66 0f 71 /2 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSRLD xmmreg,xmmrm [rm: 66 0f d2 /r] WILLAMETTE,SSE2,SO
+PSRLD xmmreg,imm [mi: 66 0f 72 /2 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSRLQ xmmreg,xmmrm [rm: 66 0f d3 /r] WILLAMETTE,SSE2,SO
+PSRLQ xmmreg,imm [mi: 66 0f 73 /2 ib,u] WILLAMETTE,SSE2,SB,AR1
+PSUBB xmmreg,xmmrm [rm: 66 0f f8 /r] WILLAMETTE,SSE2,SO
+PSUBW xmmreg,xmmrm [rm: 66 0f f9 /r] WILLAMETTE,SSE2,SO
+PSUBD xmmreg,xmmrm [rm: 66 0f fa /r] WILLAMETTE,SSE2,SO
+PSUBQ mmxreg,mmxrm [rm: np o64nw 0f fb /r] WILLAMETTE,SSE2,SO
+PSUBQ xmmreg,xmmrm [rm: 66 0f fb /r] WILLAMETTE,SSE2,SO
+PSUBSB xmmreg,xmmrm [rm: 66 0f e8 /r] WILLAMETTE,SSE2,SO
+PSUBSW xmmreg,xmmrm [rm: 66 0f e9 /r] WILLAMETTE,SSE2,SO
+PSUBUSB xmmreg,xmmrm [rm: 66 0f d8 /r] WILLAMETTE,SSE2,SO
+PSUBUSW xmmreg,xmmrm [rm: 66 0f d9 /r] WILLAMETTE,SSE2,SO
+PUNPCKHBW xmmreg,xmmrm [rm: 66 0f 68 /r] WILLAMETTE,SSE2,SO
+PUNPCKHWD xmmreg,xmmrm [rm: 66 0f 69 /r] WILLAMETTE,SSE2,SO
+PUNPCKHDQ xmmreg,xmmrm [rm: 66 0f 6a /r] WILLAMETTE,SSE2,SO
+PUNPCKHQDQ xmmreg,xmmrm [rm: 66 0f 6d /r] WILLAMETTE,SSE2,SO
+PUNPCKLBW xmmreg,xmmrm [rm: 66 0f 60 /r] WILLAMETTE,SSE2,SO
+PUNPCKLWD xmmreg,xmmrm [rm: 66 0f 61 /r] WILLAMETTE,SSE2,SO
+PUNPCKLDQ xmmreg,xmmrm [rm: 66 0f 62 /r] WILLAMETTE,SSE2,SO
+PUNPCKLQDQ xmmreg,xmmrm [rm: 66 0f 6c /r] WILLAMETTE,SSE2,SO
+PXOR xmmreg,xmmrm [rm: 66 0f ef /r] WILLAMETTE,SSE2,SO
+
+;# Willamette Streaming SIMD instructions (SSE2)
+ADDPD xmmreg,xmmrm [rm: 66 0f 58 /r] WILLAMETTE,SSE2,SO
+ADDSD xmmreg,xmmrm [rm: f2 0f 58 /r] WILLAMETTE,SSE2,SQ
+ANDNPD xmmreg,xmmrm [rm: 66 0f 55 /r] WILLAMETTE,SSE2,SO
+ANDPD xmmreg,xmmrm [rm: 66 0f 54 /r] WILLAMETTE,SSE2,SO
+CMPEQPD xmmreg,xmmrm [rm: 66 0f c2 /r 00] WILLAMETTE,SSE2,SO
+CMPEQSD xmmreg,xmmrm [rm: f2 0f c2 /r 00] WILLAMETTE,SSE2,SQ
+CMPLEPD xmmreg,xmmrm [rm: 66 0f c2 /r 02] WILLAMETTE,SSE2,SO
+CMPLESD xmmreg,xmmrm [rm: f2 0f c2 /r 02] WILLAMETTE,SSE2,SQ
+CMPLTPD xmmreg,xmmrm [rm: 66 0f c2 /r 01] WILLAMETTE,SSE2,SO
+CMPLTSD xmmreg,xmmrm [rm: f2 0f c2 /r 01] WILLAMETTE,SSE2,SQ
+CMPNEQPD xmmreg,xmmrm [rm: 66 0f c2 /r 04] WILLAMETTE,SSE2,SO
+CMPNEQSD xmmreg,xmmrm [rm: f2 0f c2 /r 04] WILLAMETTE,SSE2,SQ
+CMPNLEPD xmmreg,xmmrm [rm: 66 0f c2 /r 06] WILLAMETTE,SSE2,SO
+CMPNLESD xmmreg,xmmrm [rm: f2 0f c2 /r 06] WILLAMETTE,SSE2,SQ
+CMPNLTPD xmmreg,xmmrm [rm: 66 0f c2 /r 05] WILLAMETTE,SSE2,SO
+CMPNLTSD xmmreg,xmmrm [rm: f2 0f c2 /r 05] WILLAMETTE,SSE2,SQ
+CMPORDPD xmmreg,xmmrm [rm: 66 0f c2 /r 07] WILLAMETTE,SSE2,SO
+CMPORDSD xmmreg,xmmrm [rm: f2 0f c2 /r 07] WILLAMETTE,SSE2,SQ
+CMPUNORDPD xmmreg,xmmrm [rm: 66 0f c2 /r 03] WILLAMETTE,SSE2,SO
+CMPUNORDSD xmmreg,xmmrm [rm: f2 0f c2 /r 03] WILLAMETTE,SSE2,SQ
+; CMPPD/CMPSD must come after the specific ops; that way the disassembler will find the
+; specific ops first and only disassemble illegal ones as cmppd/cmpsd.
+CMPPD xmmreg,xmmrm128,imm8 [rmi: 66 0f c2 /r ib,u] WILLAMETTE,SSE2
+CMPSD xmmreg,xmmrm128,imm8 [rmi: f2 0f c2 /r ib,u] WILLAMETTE,SSE2
+COMISD xmmreg,xmmrm64 [rm: 66 0f 2f /r] WILLAMETTE,SSE2
+CVTDQ2PD xmmreg,xmmrm [rm: f3 0f e6 /r] WILLAMETTE,SSE2,SQ
+CVTDQ2PS xmmreg,xmmrm [rm: np 0f 5b /r] WILLAMETTE,SSE2,SO
+CVTPD2DQ xmmreg,xmmrm [rm: f2 0f e6 /r] WILLAMETTE,SSE2,SO
+CVTPD2PI mmxreg,xmmrm [rm: 66 0f 2d /r] WILLAMETTE,SSE2,SO
+CVTPD2PS xmmreg,xmmrm [rm: 66 0f 5a /r] WILLAMETTE,SSE2,SO
+CVTPI2PD xmmreg,mmxrm [rm: 66 0f 2a /r] WILLAMETTE,SSE2,SQ
+CVTPS2DQ xmmreg,xmmrm [rm: 66 0f 5b /r] WILLAMETTE,SSE2,SO
+CVTPS2PD xmmreg,xmmrm [rm: np 0f 5a /r] WILLAMETTE,SSE2,SQ
+CVTSD2SI reg32,xmmreg [rm: norexw f2 0f 2d /r] WILLAMETTE,SSE2,SQ,AR1
+CVTSD2SI reg32,mem [rm: norexw f2 0f 2d /r] WILLAMETTE,SSE2,SQ,AR1
+CVTSD2SI reg64,xmmreg [rm: o64 f2 0f 2d /r] X86_64,LONG,SSE2,SQ,AR1
+CVTSD2SI reg64,mem [rm: o64 f2 0f 2d /r] X86_64,LONG,SSE2,SQ,AR1
+CVTSD2SS xmmreg,xmmrm [rm: f2 0f 5a /r] WILLAMETTE,SSE2,SQ
+CVTSI2SD xmmreg,mem [rm: f2 0f 2a /r] WILLAMETTE,SSE2,SD,AR1,ND
+CVTSI2SD xmmreg,rm32 [rm: norexw f2 0f 2a /r] WILLAMETTE,SSE2,SD,AR1
+CVTSI2SD xmmreg,rm64 [rm: o64 f2 0f 2a /r] X86_64,LONG,SSE2,SQ,AR1
+CVTSS2SD xmmreg,xmmrm [rm: f3 0f 5a /r] WILLAMETTE,SSE2,SD
+CVTTPD2PI mmxreg,xmmrm [rm: 66 0f 2c /r] WILLAMETTE,SSE2,SO
+CVTTPD2DQ xmmreg,xmmrm [rm: 66 0f e6 /r] WILLAMETTE,SSE2,SO
+CVTTPS2DQ xmmreg,xmmrm [rm: f3 0f 5b /r] WILLAMETTE,SSE2,SO
+CVTTSD2SI reg32,xmmreg [rm: norexw f2 0f 2c /r] WILLAMETTE,SSE2,SQ,AR1
+CVTTSD2SI reg32,mem [rm: norexw f2 0f 2c /r] WILLAMETTE,SSE2,SQ,AR1
+CVTTSD2SI reg64,xmmreg [rm: o64 f2 0f 2c /r] X86_64,LONG,SSE2,SQ,AR1
+CVTTSD2SI reg64,mem [rm: o64 f2 0f 2c /r] X86_64,LONG,SSE2,SQ,AR1
+DIVPD xmmreg,xmmrm [rm: 66 0f 5e /r] WILLAMETTE,SSE2,SO
+DIVSD xmmreg,xmmrm [rm: f2 0f 5e /r] WILLAMETTE,SSE2,SQ
+MAXPD xmmreg,xmmrm [rm: 66 0f 5f /r] WILLAMETTE,SSE2,SO
+MAXSD xmmreg,xmmrm [rm: f2 0f 5f /r] WILLAMETTE,SSE2,SQ
+MINPD xmmreg,xmmrm [rm: 66 0f 5d /r] WILLAMETTE,SSE2,SO
+MINSD xmmreg,xmmrm [rm: f2 0f 5d /r] WILLAMETTE,SSE2,SQ
+MOVAPD xmmreg,xmmrm128 [rm: 66 0f 28 /r] WILLAMETTE,SSE2
+MOVAPD xmmrm128,xmmreg [mr: 66 0f 29 /r] WILLAMETTE,SSE2
+MOVHPD mem64,xmmreg [mr: 66 0f 17 /r] WILLAMETTE,SSE2
+MOVHPD xmmreg,mem64 [rm: 66 0f 16 /r] WILLAMETTE,SSE2
+MOVLPD mem64,xmmreg [mr: 66 0f 13 /r] WILLAMETTE,SSE2
+MOVLPD xmmreg,mem64 [rm: 66 0f 12 /r] WILLAMETTE,SSE2
+MOVMSKPD reg32,xmmreg [rm: 66 0f 50 /r] WILLAMETTE,SSE2
+MOVMSKPD reg64,xmmreg [rm: 66 o64 0f 50 /r] X86_64,LONG,SSE2
+MOVSD xmmreg,xmmrm64 [rm: f2 0f 10 /r] WILLAMETTE,SSE2
+MOVSD xmmrm64,xmmreg [mr: f2 0f 11 /r] WILLAMETTE,SSE2
+MOVUPD xmmreg,xmmrm128 [rm: 66 0f 10 /r] WILLAMETTE,SSE2
+MOVUPD xmmrm128,xmmreg [mr: 66 0f 11 /r] WILLAMETTE,SSE2
+MULPD xmmreg,xmmrm128 [rm: 66 0f 59 /r] WILLAMETTE,SSE2,SO
+MULSD xmmreg,xmmrm64 [rm: f2 0f 59 /r] WILLAMETTE,SSE2,SQ
+ORPD xmmreg,xmmrm128 [rm: 66 0f 56 /r] WILLAMETTE,SSE2,SO
+SHUFPD xmmreg,xmmrm128,imm8 [rmi: 66 0f c6 /r ib,u] WILLAMETTE,SSE2
+SQRTPD xmmreg,xmmrm128 [rm: 66 0f 51 /r] WILLAMETTE,SSE2,SO
+SQRTSD xmmreg,xmmrm64 [rm: f2 0f 51 /r] WILLAMETTE,SSE2
+SUBPD xmmreg,xmmrm128 [rm: 66 0f 5c /r] WILLAMETTE,SSE2,SO
+SUBSD xmmreg,xmmrm64 [rm: f2 0f 5c /r] WILLAMETTE,SSE2
+UCOMISD xmmreg,xmmrm64 [rm: 66 0f 2e /r] WILLAMETTE,SSE2
+UNPCKHPD xmmreg,xmmrm128 [rm: 66 0f 15 /r] WILLAMETTE,SSE2
+UNPCKLPD xmmreg,xmmrm128 [rm: 66 0f 14 /r] WILLAMETTE,SSE2
+XORPD xmmreg,xmmrm128 [rm: 66 0f 57 /r] WILLAMETTE,SSE2
+
+;# Prescott New Instructions (SSE3)
+ADDSUBPD xmmreg,xmmrm128 [rm: 66 0f d0 /r] PRESCOTT,SSE3,SO
+ADDSUBPS xmmreg,xmmrm128 [rm: f2 0f d0 /r] PRESCOTT,SSE3,SO
+HADDPD xmmreg,xmmrm128 [rm: 66 0f 7c /r] PRESCOTT,SSE3,SO
+HADDPS xmmreg,xmmrm128 [rm: f2 0f 7c /r] PRESCOTT,SSE3,SO
+HSUBPD xmmreg,xmmrm128 [rm: 66 0f 7d /r] PRESCOTT,SSE3,SO
+HSUBPS xmmreg,xmmrm128 [rm: f2 0f 7d /r] PRESCOTT,SSE3,SO
+LDDQU xmmreg,mem128 [rm: f2 0f f0 /r] PRESCOTT,SSE3,SO
+MOVDDUP xmmreg,xmmrm64 [rm: f2 0f 12 /r] PRESCOTT,SSE3,SQ
+MOVSHDUP xmmreg,xmmrm128 [rm: f3 0f 16 /r] PRESCOTT,SSE3
+MOVSLDUP xmmreg,xmmrm128 [rm: f3 0f 12 /r] PRESCOTT,SSE3
+
+;# VMX/SVM Instructions
+CLGI void [ 0f 01 dd] VMX,AMD
+STGI void [ 0f 01 dc] VMX,AMD
+VMCALL void [ 0f 01 c1] VMX
+VMCLEAR mem [m: 66 0f c7 /6] VMX
+VMFUNC void [ 0f 01 d4] VMX
+VMLAUNCH void [ 0f 01 c2] VMX
+VMLOAD void [ 0f 01 da] VMX,AMD
+VMMCALL void [ 0f 01 d9] VMX,AMD
+VMPTRLD mem [m: np 0f c7 /6] VMX
+VMPTRST mem [m: np 0f c7 /7] VMX
+VMREAD rm32,reg32 [mr: np 0f 78 /r] VMX,NOLONG,SD
+VMREAD rm64,reg64 [mr: o64nw np 0f 78 /r] X86_64,LONG,VMX,SQ
+VMRESUME void [ 0f 01 c3] VMX
+VMRUN void [ 0f 01 d8] VMX,AMD
+VMSAVE void [ 0f 01 db] VMX,AMD
+VMWRITE reg32,rm32 [rm: np 0f 79 /r] VMX,NOLONG,SD
+VMWRITE reg64,rm64 [rm: o64nw np 0f 79 /r] X86_64,LONG,VMX,SQ
+VMXOFF void [ 0f 01 c4] VMX
+VMXON mem [m: f3 0f c7 /6] VMX
+;# Extended Page Tables VMX instructions
+INVEPT reg32,mem [rm: 66 0f 38 80 /r] VMX,SO,NOLONG
+INVEPT reg64,mem [rm: o64nw 66 0f 38 80 /r] VMX,SO,LONG
+INVVPID reg32,mem [rm: 66 0f 38 81 /r] VMX,SO,NOLONG
+INVVPID reg64,mem [rm: o64nw 66 0f 38 81 /r] VMX,SO,LONG
+;# SEV-SNP AMD instructions
+PVALIDATE void [ f2 0f 01 ff] VMX,AMD
+RMPADJUST void [ f3 0f 01 fe] VMX,AMD
+VMGEXIT void [ f2 0f 01 c1] VMX,AMD
+VMGEXIT void [ f3 0f 01 c1] VMX,AMD
+
+;# Tejas New Instructions (SSSE3)
+PABSB mmxreg,mmxrm [rm: np 0f 38 1c /r] SSSE3,MMX,SQ
+PABSB xmmreg,xmmrm128 [rm: 66 0f 38 1c /r] SSSE3
+PABSW mmxreg,mmxrm [rm: np 0f 38 1d /r] SSSE3,MMX,SQ
+PABSW xmmreg,xmmrm128 [rm: 66 0f 38 1d /r] SSSE3
+PABSD mmxreg,mmxrm [rm: np 0f 38 1e /r] SSSE3,MMX,SQ
+PABSD xmmreg,xmmrm128 [rm: 66 0f 38 1e /r] SSSE3
+PALIGNR mmxreg,mmxrm,imm [rmi: np 0f 3a 0f /r ib,u] SSSE3,MMX,SQ
+PALIGNR xmmreg,xmmrm,imm [rmi: 66 0f 3a 0f /r ib,u] SSSE3
+PHADDW mmxreg,mmxrm [rm: np 0f 38 01 /r] SSSE3,MMX,SQ
+PHADDW xmmreg,xmmrm128 [rm: 66 0f 38 01 /r] SSSE3
+PHADDD mmxreg,mmxrm [rm: np 0f 38 02 /r] SSSE3,MMX,SQ
+PHADDD xmmreg,xmmrm128 [rm: 66 0f 38 02 /r] SSSE3
+PHADDSW mmxreg,mmxrm [rm: np 0f 38 03 /r] SSSE3,MMX,SQ
+PHADDSW xmmreg,xmmrm128 [rm: 66 0f 38 03 /r] SSSE3
+PHSUBW mmxreg,mmxrm [rm: np 0f 38 05 /r] SSSE3,MMX,SQ
+PHSUBW xmmreg,xmmrm128 [rm: 66 0f 38 05 /r] SSSE3
+PHSUBD mmxreg,mmxrm [rm: np 0f 38 06 /r] SSSE3,MMX,SQ
+PHSUBD xmmreg,xmmrm128 [rm: 66 0f 38 06 /r] SSSE3
+PHSUBSW mmxreg,mmxrm [rm: np 0f 38 07 /r] SSSE3,MMX,SQ
+PHSUBSW xmmreg,xmmrm128 [rm: 66 0f 38 07 /r] SSSE3
+PMADDUBSW mmxreg,mmxrm [rm: np 0f 38 04 /r] SSSE3,MMX,SQ
+PMADDUBSW xmmreg,xmmrm128 [rm: 66 0f 38 04 /r] SSSE3
+PMULHRSW mmxreg,mmxrm [rm: np 0f 38 0b /r] SSSE3,MMX,SQ
+PMULHRSW xmmreg,xmmrm128 [rm: 66 0f 38 0b /r] SSSE3
+PSHUFB mmxreg,mmxrm [rm: np 0f 38 00 /r] SSSE3,MMX,SQ
+PSHUFB xmmreg,xmmrm128 [rm: 66 0f 38 00 /r] SSSE3
+PSIGNB mmxreg,mmxrm [rm: np 0f 38 08 /r] SSSE3,MMX,SQ
+PSIGNB xmmreg,xmmrm128 [rm: 66 0f 38 08 /r] SSSE3
+PSIGNW mmxreg,mmxrm [rm: np 0f 38 09 /r] SSSE3,MMX,SQ
+PSIGNW xmmreg,xmmrm128 [rm: 66 0f 38 09 /r] SSSE3
+PSIGND mmxreg,mmxrm [rm: np 0f 38 0a /r] SSSE3,MMX,SQ
+PSIGND xmmreg,xmmrm128 [rm: 66 0f 38 0a /r] SSSE3
+
+;# AMD SSE4A
+EXTRQ xmmreg,imm,imm [mij: 66 0f 78 /0 ib,u ib,u] SSE4A,AMD
+EXTRQ xmmreg,xmmreg [rm: 66 0f 79 /r] SSE4A,AMD
+INSERTQ xmmreg,xmmreg,imm,imm [rmij: f2 0f 78 /r ib,u ib,u] SSE4A,AMD
+INSERTQ xmmreg,xmmreg [rm: f2 0f 79 /r] SSE4A,AMD
+MOVNTSD mem64,xmmreg [mr: f2 0f 2b /r] SSE4A,AMD,SQ
+MOVNTSS mem32,xmmreg [mr: f3 0f 2b /r] SSE4A,AMD,SD
+
+;# New instructions in Barcelona
+LZCNT reg16,rm16 [rm: o16 f3i 0f bd /r] P6,AMD
+LZCNT reg32,rm32 [rm: o32 f3i 0f bd /r] P6,AMD
+LZCNT reg64,rm64 [rm: o64 f3i 0f bd /r] X86_64,LONG,AMD
+
+;# Penryn New Instructions (SSE4.1)
+BLENDPD xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 0d /r ib,u] SSE41
+BLENDPS xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 0c /r ib,u] SSE41
+BLENDVPD xmmreg,xmmrm128,xmm0 [rm-: 66 0f 38 15 /r] SSE41
+BLENDVPD xmmreg,xmmrm128 [rm: 66 0f 38 15 /r] SSE41
+BLENDVPS xmmreg,xmmrm128,xmm0 [rm-: 66 0f 38 14 /r] SSE41
+BLENDVPS xmmreg,xmmrm128 [rm: 66 0f 38 14 /r] SSE41
+DPPD xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 41 /r ib,u] SSE41
+DPPS xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 40 /r ib,u] SSE41
+EXTRACTPS rm32,xmmreg,imm8 [mri: 66 0f 3a 17 /r ib,u] SSE41
+EXTRACTPS reg64,xmmreg,imm8 [mri: o64 66 0f 3a 17 /r ib,u] SSE41,X86_64,LONG
+INSERTPS xmmreg,xmmrm32,imm8 [rmi: 66 0f 3a 21 /r ib,u] SSE41
+MOVNTDQA xmmreg,mem128 [rm: 66 0f 38 2a /r] SSE41
+MPSADBW xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 42 /r ib,u] SSE41
+PACKUSDW xmmreg,xmmrm128 [rm: 66 0f 38 2b /r] SSE41
+PBLENDVB xmmreg,xmmrm,xmm0 [rm-: 66 0f 38 10 /r] SSE41
+PBLENDVB xmmreg,xmmrm128 [rm: 66 0f 38 10 /r] SSE41
+PBLENDW xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 0e /r ib,u] SSE41
+PCMPEQQ xmmreg,xmmrm128 [rm: 66 0f 38 29 /r] SSE41
+PEXTRB reg32,xmmreg,imm8 [mri: 66 0f 3a 14 /r ib,u] SSE41
+PEXTRB mem8,xmmreg,imm8 [mri: 66 0f 3a 14 /r ib,u] SSE41
+PEXTRB reg64,xmmreg,imm8 [mri: o64nw 66 0f 3a 14 /r ib,u] SSE41,X86_64,LONG
+PEXTRD rm32,xmmreg,imm8 [mri: norexw 66 0f 3a 16 /r ib,u] SSE41
+PEXTRQ rm64,xmmreg,imm8 [mri: o64 66 0f 3a 16 /r ib,u] SSE41,X86_64,LONG
+PEXTRW reg32,xmmreg,imm8 [mri: 66 0f 3a 15 /r ib,u] SSE41
+PEXTRW mem16,xmmreg,imm8 [mri: 66 0f 3a 15 /r ib,u] SSE41
+PEXTRW reg64,xmmreg,imm8 [mri: o64 66 0f 3a 15 /r ib,u] SSE41,X86_64,LONG
+PHMINPOSUW xmmreg,xmmrm128 [rm: 66 0f 38 41 /r] SSE41
+PINSRB xmmreg,mem,imm8 [rmi: 66 0f 3a 20 /r ib,u] SSE41,SB,AR2
+PINSRB xmmreg,rm8,imm8 [rmi: nohi 66 0f 3a 20 /r ib,u] SSE41,SB,AR2
+PINSRB xmmreg,reg32,imm8 [rmi: 66 0f 3a 20 /r ib,u] SSE41,SB,AR2
+PINSRD xmmreg,rm32,imm8 [rmi: norexw 66 0f 3a 22 /r ib,u] SSE41,SB,AR2
+PINSRQ xmmreg,rm64,imm8 [rmi: o64 66 0f 3a 22 /r ib,u] SSE41,X86_64,LONG,SB,AR2
+PMAXSB xmmreg,xmmrm128 [rm: 66 0f 38 3c /r] SSE41
+PMAXSD xmmreg,xmmrm128 [rm: 66 0f 38 3d /r] SSE41
+PMAXUD xmmreg,xmmrm128 [rm: 66 0f 38 3f /r] SSE41
+PMAXUW xmmreg,xmmrm128 [rm: 66 0f 38 3e /r] SSE41
+PMINSB xmmreg,xmmrm128 [rm: 66 0f 38 38 /r] SSE41
+PMINSD xmmreg,xmmrm128 [rm: 66 0f 38 39 /r] SSE41
+PMINUD xmmreg,xmmrm128 [rm: 66 0f 38 3b /r] SSE41
+PMINUW xmmreg,xmmrm128 [rm: 66 0f 38 3a /r] SSE41
+PMOVSXBW xmmreg,xmmrm64 [rm: 66 0f 38 20 /r] SSE41,SQ
+PMOVSXBD xmmreg,xmmrm32 [rm: 66 0f 38 21 /r] SSE41,SD
+PMOVSXBQ xmmreg,xmmrm16 [rm: 66 0f 38 22 /r] SSE41,SW
+PMOVSXWD xmmreg,xmmrm64 [rm: 66 0f 38 23 /r] SSE41,SQ
+PMOVSXWQ xmmreg,xmmrm32 [rm: 66 0f 38 24 /r] SSE41,SD
+PMOVSXDQ xmmreg,xmmrm64 [rm: 66 0f 38 25 /r] SSE41,SQ
+PMOVZXBW xmmreg,xmmrm64 [rm: 66 0f 38 30 /r] SSE41,SQ
+PMOVZXBD xmmreg,xmmrm32 [rm: 66 0f 38 31 /r] SSE41,SD
+PMOVZXBQ xmmreg,xmmrm16 [rm: 66 0f 38 32 /r] SSE41,SW
+PMOVZXWD xmmreg,xmmrm64 [rm: 66 0f 38 33 /r] SSE41,SQ
+PMOVZXWQ xmmreg,xmmrm32 [rm: 66 0f 38 34 /r] SSE41,SD
+PMOVZXDQ xmmreg,xmmrm64 [rm: 66 0f 38 35 /r] SSE41,SQ
+PMULDQ xmmreg,xmmrm128 [rm: 66 0f 38 28 /r] SSE41
+PMULLD xmmreg,xmmrm128 [rm: 66 0f 38 40 /r] SSE41
+PTEST xmmreg,xmmrm128 [rm: 66 0f 38 17 /r] SSE41
+ROUNDPD xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 09 /r ib,u] SSE41
+ROUNDPS xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 08 /r ib,u] SSE41
+ROUNDSD xmmreg,xmmrm64,imm8 [rmi: 66 0f 3a 0b /r ib,u] SSE41
+ROUNDSS xmmreg,xmmrm32,imm8 [rmi: 66 0f 3a 0a /r ib,u] SSE41
+
+;# Nehalem New Instructions (SSE4.2)
+CRC32 reg32,rm8 [rm: f2i 0f 38 f0 /r] SSE42
+CRC32 reg32,rm16 [rm: o16 f2i 0f 38 f1 /r] SSE42
+CRC32 reg32,rm32 [rm: o32 f2i 0f 38 f1 /r] SSE42
+CRC32 reg64,rm8 [rm: o64 f2i 0f 38 f0 /r] SSE42,X86_64,LONG
+CRC32 reg64,rm64 [rm: o64 f2i 0f 38 f1 /r] SSE42,X86_64,LONG
+PCMPESTRI xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 61 /r ib,u] SSE42
+PCMPESTRM xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 60 /r ib,u] SSE42
+PCMPISTRI xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 63 /r ib,u] SSE42
+PCMPISTRM xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 62 /r ib,u] SSE42
+PCMPGTQ xmmreg,xmmrm128 [rm: 66 0f 38 37 /r] SSE42
+POPCNT reg16,rm16 [rm: o16 f3i 0f b8 /r] NEHALEM,SW
+POPCNT reg32,rm32 [rm: o32 f3i 0f b8 /r] NEHALEM,SD
+POPCNT reg64,rm64 [rm: o64 f3i 0f b8 /r] NEHALEM,SQ,LONG
+
+;# Intel SMX
+GETSEC void [ 0f 37] KATMAI
+
+;# Geode (Cyrix) 3DNow! additions
+PFRCPV mmxreg,mmxrm [rm: o64nw 0f 0f /r 86] PENT,3DNOW,SQ,CYRIX
+PFRSQRTV mmxreg,mmxrm [rm: o64nw 0f 0f /r 87] PENT,3DNOW,SQ,CYRIX
+
+;# Intel new instructions in ???
+; Is NEHALEM right here?
+MOVBE reg16,mem16 [rm: o16 norep 0f 38 f0 /r] NEHALEM,SM
+MOVBE reg32,mem32 [rm: o32 norep 0f 38 f0 /r] NEHALEM,SM
+MOVBE reg64,mem64 [rm: o64 norep 0f 38 f0 /r] NEHALEM,SM
+MOVBE mem16,reg16 [mr: o16 norep 0f 38 f1 /r] NEHALEM,SM
+MOVBE mem32,reg32 [mr: o32 norep 0f 38 f1 /r] NEHALEM,SM
+MOVBE mem64,reg64 [mr: o64 norep 0f 38 f1 /r] NEHALEM,SM
+
+;# Intel AES instructions
+AESENC xmmreg,xmmrm128 [rm: 66 0f 38 dc /r] SSE,WESTMERE
+AESENCLAST xmmreg,xmmrm128 [rm: 66 0f 38 dd /r] SSE,WESTMERE
+AESDEC xmmreg,xmmrm128 [rm: 66 0f 38 de /r] SSE,WESTMERE
+AESDECLAST xmmreg,xmmrm128 [rm: 66 0f 38 df /r] SSE,WESTMERE
+AESIMC xmmreg,xmmrm128 [rm: 66 0f 38 db /r] SSE,WESTMERE
+AESKEYGENASSIST xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a df /r ib] SSE,WESTMERE
+
+;# Intel AVX AES instructions
+VAESENC xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 dc /r] AVX,SANDYBRIDGE
+VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 dd /r] AVX,SANDYBRIDGE
+VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 de /r] AVX,SANDYBRIDGE
+VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 df /r] AVX,SANDYBRIDGE
+VAESIMC xmmreg,xmmrm128 [rm: vex.128.66.0f38 db /r] AVX,SANDYBRIDGE
+VAESKEYGENASSIST xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a df /r ib] AVX,SANDYBRIDGE
+
+;# Intel instruction extension based on pub number 319433-030 dated October 2017
+
+; Intel VAES instructions
+VAESENC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dc /r] VAES,FUTURE
+VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig dd /r] VAES,FUTURE
+VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig de /r] VAES,FUTURE
+VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.wig df /r] VAES,FUTURE
+
+; Intel VAES + AVX512VL instructions
+VAESENC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE
+VAESENC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dc /r] AVX512VL,AVX512,VAES,FUTURE
+VAESENCLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE
+VAESENCLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig dd /r] AVX512VL,AVX512,VAES,FUTURE
+VAESDEC xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE
+VAESDEC ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig de /r] AVX512VL,AVX512,VAES,FUTURE
+VAESDECLAST xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE
+VAESDECLAST ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f38.wig df /r] AVX512VL,AVX512,VAES,FUTURE
+
+; Intel VAES + AVX512F instructions
+VAESENC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dc /r] AVX512,VAES,FUTURE
+VAESENCLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig dd /r] AVX512,VAES,FUTURE
+VAESDEC zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig de /r] AVX512,VAES,FUTURE
+VAESDECLAST zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f38.wig df /r] AVX512,VAES,FUTURE
+
+;# Intel AVX instructions
+VADDPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 58 /r] AVX,SANDYBRIDGE
+VADDPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 58 /r] AVX,SANDYBRIDGE
+VADDPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 58 /r] AVX,SANDYBRIDGE
+VADDPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 58 /r] AVX,SANDYBRIDGE
+VADDSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 58 /r] AVX,SANDYBRIDGE
+VADDSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 58 /r] AVX,SANDYBRIDGE
+VADDSUBPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d0 /r] AVX,SANDYBRIDGE
+VADDSUBPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f d0 /r] AVX,SANDYBRIDGE
+VADDSUBPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.f2.0f d0 /r] AVX,SANDYBRIDGE
+VADDSUBPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.f2.0f d0 /r] AVX,SANDYBRIDGE
+VANDPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 54 /r] AVX,SANDYBRIDGE
+VANDPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 54 /r] AVX,SANDYBRIDGE
+VANDPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 54 /r] AVX,SANDYBRIDGE
+VANDPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 54 /r] AVX,SANDYBRIDGE
+VANDNPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 55 /r] AVX,SANDYBRIDGE
+VANDNPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 55 /r] AVX,SANDYBRIDGE
+VANDNPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 55 /r] AVX,SANDYBRIDGE
+VANDNPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 55 /r] AVX,SANDYBRIDGE
+VBLENDPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 0d /r ib] AVX,SANDYBRIDGE
+VBLENDPD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a 0d /r ib] AVX,SANDYBRIDGE
+VBLENDPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 0c /r ib] AVX,SANDYBRIDGE
+VBLENDPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a 0c /r ib] AVX,SANDYBRIDGE
+VBLENDVPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.nds.128.66.0f3a.w0 4b /r /is4] AVX,SANDYBRIDGE
+VBLENDVPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.nds.256.66.0f3a.w0 4b /r /is4] AVX,SANDYBRIDGE
+VBLENDVPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.nds.128.66.0f3a.w0 4a /r /is4] AVX,SANDYBRIDGE
+VBLENDVPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.nds.256.66.0f3a.w0 4a /r /is4] AVX,SANDYBRIDGE
+VBROADCASTSS xmmreg,mem32 [rm: vex.128.66.0f38.w0 18 /r] AVX,SANDYBRIDGE
+VBROADCASTSS ymmreg,mem32 [rm: vex.256.66.0f38.w0 18 /r] AVX,SANDYBRIDGE
+VBROADCASTSD ymmreg,mem64 [rm: vex.256.66.0f38.w0 19 /r] AVX,SANDYBRIDGE
+VBROADCASTF128 ymmreg,mem128 [rm: vex.256.66.0f38.w0 1a /r] AVX,SANDYBRIDGE
+; Specific aliases first, then the generic version, to keep the disassembler happy...
+VCMPEQ_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQ_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 00] AVX,SANDYBRIDGE
+VCMPEQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 00] AVX,SANDYBRIDGE
+VCMPLT_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLT_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLTPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLTPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLE_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLE_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLEPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLEPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPUNORD_QPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORD_QPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORDPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORDPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPNEQ_UQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQ_UQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNLT_USPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLT_USPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLTPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLTPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLE_USPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLE_USPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLEPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLEPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPORD_QPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORD_QPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORDPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORDPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPEQ_UQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 08] AVX,SANDYBRIDGE
+VCMPEQ_UQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 08] AVX,SANDYBRIDGE
+VCMPNGE_USPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGE_USPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGEPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGEPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGT_USPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGT_USPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGTPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGTPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPFALSE_OQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSE_OQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSEPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSEPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPNEQ_OQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0c] AVX,SANDYBRIDGE
+VCMPNEQ_OQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0c] AVX,SANDYBRIDGE
+VCMPGE_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGE_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGEPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGEPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGT_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGT_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGTPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGTPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPTRUE_UQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUE_UQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUEPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUEPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPEQ_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQ_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPLT_OQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 11] AVX,SANDYBRIDGE
+VCMPLT_OQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 11] AVX,SANDYBRIDGE
+VCMPLE_OQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 12] AVX,SANDYBRIDGE
+VCMPLE_OQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 12] AVX,SANDYBRIDGE
+VCMPUNORD_SPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 13] AVX,SANDYBRIDGE
+VCMPUNORD_SPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 13] AVX,SANDYBRIDGE
+VCMPNEQ_USPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 14] AVX,SANDYBRIDGE
+VCMPNEQ_USPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 14] AVX,SANDYBRIDGE
+VCMPNLT_UQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 15] AVX,SANDYBRIDGE
+VCMPNLT_UQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 15] AVX,SANDYBRIDGE
+VCMPNLE_UQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 16] AVX,SANDYBRIDGE
+VCMPNLE_UQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 16] AVX,SANDYBRIDGE
+VCMPORD_SPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 17] AVX,SANDYBRIDGE
+VCMPORD_SPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 17] AVX,SANDYBRIDGE
+VCMPEQ_USPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 18] AVX,SANDYBRIDGE
+VCMPEQ_USPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 18] AVX,SANDYBRIDGE
+VCMPNGE_UQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 19] AVX,SANDYBRIDGE
+VCMPNGE_UQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 19] AVX,SANDYBRIDGE
+VCMPNGT_UQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 1a] AVX,SANDYBRIDGE
+VCMPNGT_UQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 1a] AVX,SANDYBRIDGE
+VCMPFALSE_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 1b] AVX,SANDYBRIDGE
+VCMPFALSE_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 1b] AVX,SANDYBRIDGE
+VCMPNEQ_OSPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 1c] AVX,SANDYBRIDGE
+VCMPNEQ_OSPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 1c] AVX,SANDYBRIDGE
+VCMPGE_OQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 1d] AVX,SANDYBRIDGE
+VCMPGE_OQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 1d] AVX,SANDYBRIDGE
+VCMPGT_OQPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 1e] AVX,SANDYBRIDGE
+VCMPGT_OQPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 1e] AVX,SANDYBRIDGE
+VCMPTRUE_USPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f c2 /r 1f] AVX,SANDYBRIDGE
+VCMPTRUE_USPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f c2 /r 1f] AVX,SANDYBRIDGE
+VCMPPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f c2 /r ib] AVX,SANDYBRIDGE
+VCMPPD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f c2 /r ib] AVX,SANDYBRIDGE
+; Specific aliases first, then the generic version, to keep the disassembler happy...
+VCMPEQ_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQ_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 00] AVX,SANDYBRIDGE
+VCMPEQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 00] AVX,SANDYBRIDGE
+VCMPLT_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLT_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLTPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLTPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLE_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLE_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLEPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLEPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPUNORD_QPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORD_QPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORDPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORDPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPNEQ_UQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQ_UQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNLT_USPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLT_USPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLTPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLTPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLE_USPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLE_USPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLEPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLEPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPORD_QPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORD_QPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORDPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORDPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPEQ_UQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 08] AVX,SANDYBRIDGE
+VCMPEQ_UQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 08] AVX,SANDYBRIDGE
+VCMPNGE_USPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGE_USPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGEPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGEPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGT_USPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGT_USPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGTPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGTPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPFALSE_OQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSE_OQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSEPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSEPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPNEQ_OQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0c] AVX,SANDYBRIDGE
+VCMPNEQ_OQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0c] AVX,SANDYBRIDGE
+VCMPGE_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGE_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGEPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGEPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGT_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGT_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGTPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGTPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPTRUE_UQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUE_UQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUEPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUEPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPEQ_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQ_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPLT_OQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 11] AVX,SANDYBRIDGE
+VCMPLT_OQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 11] AVX,SANDYBRIDGE
+VCMPLE_OQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 12] AVX,SANDYBRIDGE
+VCMPLE_OQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 12] AVX,SANDYBRIDGE
+VCMPUNORD_SPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 13] AVX,SANDYBRIDGE
+VCMPUNORD_SPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 13] AVX,SANDYBRIDGE
+VCMPNEQ_USPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 14] AVX,SANDYBRIDGE
+VCMPNEQ_USPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 14] AVX,SANDYBRIDGE
+VCMPNLT_UQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 15] AVX,SANDYBRIDGE
+VCMPNLT_UQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 15] AVX,SANDYBRIDGE
+VCMPNLE_UQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 16] AVX,SANDYBRIDGE
+VCMPNLE_UQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 16] AVX,SANDYBRIDGE
+VCMPORD_SPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 17] AVX,SANDYBRIDGE
+VCMPORD_SPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 17] AVX,SANDYBRIDGE
+VCMPEQ_USPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 18] AVX,SANDYBRIDGE
+VCMPEQ_USPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 18] AVX,SANDYBRIDGE
+VCMPNGE_UQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 19] AVX,SANDYBRIDGE
+VCMPNGE_UQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 19] AVX,SANDYBRIDGE
+VCMPNGT_UQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 1a] AVX,SANDYBRIDGE
+VCMPNGT_UQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 1a] AVX,SANDYBRIDGE
+VCMPFALSE_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 1b] AVX,SANDYBRIDGE
+VCMPFALSE_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 1b] AVX,SANDYBRIDGE
+VCMPNEQ_OSPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 1c] AVX,SANDYBRIDGE
+VCMPNEQ_OSPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 1c] AVX,SANDYBRIDGE
+VCMPGE_OQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 1d] AVX,SANDYBRIDGE
+VCMPGE_OQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 1d] AVX,SANDYBRIDGE
+VCMPGT_OQPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 1e] AVX,SANDYBRIDGE
+VCMPGT_OQPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 1e] AVX,SANDYBRIDGE
+VCMPTRUE_USPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f c2 /r 1f] AVX,SANDYBRIDGE
+VCMPTRUE_USPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f c2 /r 1f] AVX,SANDYBRIDGE
+VCMPPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.0f c2 /r ib] AVX,SANDYBRIDGE
+VCMPPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.0f c2 /r ib] AVX,SANDYBRIDGE
+; Specific aliases first, then the generic version, to keep the disassembler happy...
+VCMPEQ_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 00] AVX,SANDYBRIDGE
+VCMPLT_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLTSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLE_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLESD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPUNORD_QSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORDSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPNEQ_UQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNLT_USSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLTSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLE_USSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLESD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPORD_QSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORDSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPEQ_UQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 08] AVX,SANDYBRIDGE
+VCMPNGE_USSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGESD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGT_USSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGTSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPFALSE_OQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSESD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPNEQ_OQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0c] AVX,SANDYBRIDGE
+VCMPGE_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGESD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGT_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGTSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPTRUE_UQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUESD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPEQ_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPLT_OQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 11] AVX,SANDYBRIDGE
+VCMPLE_OQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 12] AVX,SANDYBRIDGE
+VCMPUNORD_SSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 13] AVX,SANDYBRIDGE
+VCMPNEQ_USSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 14] AVX,SANDYBRIDGE
+VCMPNLT_UQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 15] AVX,SANDYBRIDGE
+VCMPNLE_UQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 16] AVX,SANDYBRIDGE
+VCMPORD_SSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 17] AVX,SANDYBRIDGE
+VCMPEQ_USSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 18] AVX,SANDYBRIDGE
+VCMPNGE_UQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 19] AVX,SANDYBRIDGE
+VCMPNGT_UQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 1a] AVX,SANDYBRIDGE
+VCMPFALSE_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 1b] AVX,SANDYBRIDGE
+VCMPNEQ_OSSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 1c] AVX,SANDYBRIDGE
+VCMPGE_OQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 1d] AVX,SANDYBRIDGE
+VCMPGT_OQSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 1e] AVX,SANDYBRIDGE
+VCMPTRUE_USSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f c2 /r 1f] AVX,SANDYBRIDGE
+VCMPSD xmmreg,xmmreg*,xmmrm64,imm8 [rvmi: vex.nds.lig.f2.0f c2 /r ib] AVX,SANDYBRIDGE
+; Specific aliases first, then the generic version, to keep the disassembler happy...
+VCMPEQ_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPEQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 00] AVX,SANDYBRIDGE
+VCMPLT_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLTSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 01] AVX,SANDYBRIDGE
+VCMPLE_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPLESS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 02] AVX,SANDYBRIDGE
+VCMPUNORD_QSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPUNORDSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 03] AVX,SANDYBRIDGE
+VCMPNEQ_UQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNEQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 04] AVX,SANDYBRIDGE
+VCMPNLT_USSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLTSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 05] AVX,SANDYBRIDGE
+VCMPNLE_USSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPNLESS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 06] AVX,SANDYBRIDGE
+VCMPORD_QSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPORDSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 07] AVX,SANDYBRIDGE
+VCMPEQ_UQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 08] AVX,SANDYBRIDGE
+VCMPNGE_USSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGESS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 09] AVX,SANDYBRIDGE
+VCMPNGT_USSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPNGTSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0a] AVX,SANDYBRIDGE
+VCMPFALSE_OQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPFALSESS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0b] AVX,SANDYBRIDGE
+VCMPNEQ_OQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0c] AVX,SANDYBRIDGE
+VCMPGE_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGESS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0d] AVX,SANDYBRIDGE
+VCMPGT_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPGTSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0e] AVX,SANDYBRIDGE
+VCMPTRUE_UQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPTRUESS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 0f] AVX,SANDYBRIDGE
+VCMPEQ_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 10] AVX,SANDYBRIDGE
+VCMPLT_OQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 11] AVX,SANDYBRIDGE
+VCMPLE_OQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 12] AVX,SANDYBRIDGE
+VCMPUNORD_SSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 13] AVX,SANDYBRIDGE
+VCMPNEQ_USSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 14] AVX,SANDYBRIDGE
+VCMPNLT_UQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 15] AVX,SANDYBRIDGE
+VCMPNLE_UQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 16] AVX,SANDYBRIDGE
+VCMPORD_SSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 17] AVX,SANDYBRIDGE
+VCMPEQ_USSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 18] AVX,SANDYBRIDGE
+VCMPNGE_UQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 19] AVX,SANDYBRIDGE
+VCMPNGT_UQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 1a] AVX,SANDYBRIDGE
+VCMPFALSE_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 1b] AVX,SANDYBRIDGE
+VCMPNEQ_OSSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 1c] AVX,SANDYBRIDGE
+VCMPGE_OQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 1d] AVX,SANDYBRIDGE
+VCMPGT_OQSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 1e] AVX,SANDYBRIDGE
+VCMPTRUE_USSS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f3.0f c2 /r 1f] AVX,SANDYBRIDGE
+VCMPSS xmmreg,xmmreg*,xmmrm64,imm8 [rvmi: vex.nds.lig.f3.0f c2 /r ib] AVX,SANDYBRIDGE
+VCOMISD xmmreg,xmmrm64 [rm: vex.lig.66.0f 2f /r] AVX,SANDYBRIDGE
+VCOMISS xmmreg,xmmrm32 [rm: vex.lig.0f 2f /r] AVX,SANDYBRIDGE
+VCVTDQ2PD xmmreg,xmmrm64 [rm: vex.128.f3.0f e6 /r] AVX,SANDYBRIDGE
+VCVTDQ2PD ymmreg,xmmrm128 [rm: vex.256.f3.0f e6 /r] AVX,SANDYBRIDGE
+VCVTDQ2PS xmmreg,xmmrm128 [rm: vex.128.0f 5b /r] AVX,SANDYBRIDGE
+VCVTDQ2PS ymmreg,ymmrm256 [rm: vex.256.0f 5b /r] AVX,SANDYBRIDGE
+VCVTPD2DQ xmmreg,xmmreg [rm: vex.128.f2.0f e6 /r] AVX,SANDYBRIDGE
+VCVTPD2DQ xmmreg,mem128 [rm: vex.128.f2.0f e6 /r] AVX,SANDYBRIDGE,SO
+VCVTPD2DQ xmmreg,ymmreg [rm: vex.256.f2.0f e6 /r] AVX,SANDYBRIDGE
+VCVTPD2DQ xmmreg,mem256 [rm: vex.256.f2.0f e6 /r] AVX,SANDYBRIDGE,SY
+VCVTPD2PS xmmreg,xmmreg [rm: vex.128.66.0f 5a /r] AVX,SANDYBRIDGE
+VCVTPD2PS xmmreg,mem128 [rm: vex.128.66.0f 5a /r] AVX,SANDYBRIDGE,SO
+VCVTPD2PS xmmreg,ymmreg [rm: vex.256.66.0f 5a /r] AVX,SANDYBRIDGE
+VCVTPD2PS xmmreg,mem256 [rm: vex.256.66.0f 5a /r] AVX,SANDYBRIDGE,SY
+VCVTPS2DQ xmmreg,xmmrm128 [rm: vex.128.66.0f 5b /r] AVX,SANDYBRIDGE
+VCVTPS2DQ ymmreg,ymmrm256 [rm: vex.256.66.0f 5b /r] AVX,SANDYBRIDGE
+VCVTPS2PD xmmreg,xmmrm64 [rm: vex.128.0f 5a /r] AVX,SANDYBRIDGE
+VCVTPS2PD ymmreg,xmmrm128 [rm: vex.256.0f 5a /r] AVX,SANDYBRIDGE
+VCVTSD2SI reg32,xmmrm64 [rm: vex.lig.f2.0f.w0 2d /r] AVX,SANDYBRIDGE
+VCVTSD2SI reg64,xmmrm64 [rm: vex.lig.f2.0f.w1 2d /r] AVX,SANDYBRIDGE,LONG
+VCVTSD2SS xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 5a /r] AVX,SANDYBRIDGE
+VCVTSI2SD xmmreg,xmmreg*,rm32 [rvm: vex.nds.lig.f2.0f.w0 2a /r] AVX,SANDYBRIDGE,SD
+VCVTSI2SD xmmreg,xmmreg*,mem32 [rvm: vex.nds.lig.f2.0f.w0 2a /r] AVX,SANDYBRIDGE,ND,SD
+VCVTSI2SD xmmreg,xmmreg*,rm64 [rvm: vex.nds.lig.f2.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG,SQ
+VCVTSI2SS xmmreg,xmmreg*,rm32 [rvm: vex.nds.lig.f3.0f.w0 2a /r] AVX,SANDYBRIDGE,SD
+VCVTSI2SS xmmreg,xmmreg*,mem32 [rvm: vex.nds.lig.f3.0f.w0 2a /r] AVX,SANDYBRIDGE,ND,SD
+VCVTSI2SS xmmreg,xmmreg*,rm64 [rvm: vex.nds.lig.f3.0f.w1 2a /r] AVX,SANDYBRIDGE,LONG,SQ
+VCVTSS2SD xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 5a /r] AVX,SANDYBRIDGE
+VCVTSS2SI reg32,xmmrm32 [rm: vex.lig.f3.0f.w0 2d /r] AVX,SANDYBRIDGE
+VCVTSS2SI reg64,xmmrm32 [rm: vex.lig.f3.0f.w1 2d /r] AVX,SANDYBRIDGE,LONG
+VCVTTPD2DQ xmmreg,xmmreg [rm: vex.128.66.0f e6 /r] AVX,SANDYBRIDGE
+VCVTTPD2DQ xmmreg,mem128 [rm: vex.128.66.0f e6 /r] AVX,SANDYBRIDGE,SO
+VCVTTPD2DQ xmmreg,ymmreg [rm: vex.256.66.0f e6 /r] AVX,SANDYBRIDGE
+VCVTTPD2DQ xmmreg,mem256 [rm: vex.256.66.0f e6 /r] AVX,SANDYBRIDGE,SY
+VCVTTPS2DQ xmmreg,xmmrm128 [rm: vex.128.f3.0f 5b /r] AVX,SANDYBRIDGE
+VCVTTPS2DQ ymmreg,ymmrm256 [rm: vex.256.f3.0f 5b /r] AVX,SANDYBRIDGE
+VCVTTSD2SI reg32,xmmrm64 [rm: vex.lig.f2.0f.w0 2c /r] AVX,SANDYBRIDGE
+VCVTTSD2SI reg64,xmmrm64 [rm: vex.lig.f2.0f.w1 2c /r] AVX,SANDYBRIDGE,LONG
+VCVTTSS2SI reg32,xmmrm32 [rm: vex.lig.f3.0f.w0 2c /r] AVX,SANDYBRIDGE
+VCVTTSS2SI reg64,xmmrm32 [rm: vex.lig.f3.0f.w1 2c /r] AVX,SANDYBRIDGE,LONG
+VDIVPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 5e /r] AVX,SANDYBRIDGE
+VDIVPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 5e /r] AVX,SANDYBRIDGE
+VDIVPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 5e /r] AVX,SANDYBRIDGE
+VDIVPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 5e /r] AVX,SANDYBRIDGE
+VDIVSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 5e /r] AVX,SANDYBRIDGE
+VDIVSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 5e /r] AVX,SANDYBRIDGE
+VDPPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 41 /r ib] AVX,SANDYBRIDGE
+VDPPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 40 /r ib] AVX,SANDYBRIDGE
+VDPPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a 40 /r ib] AVX,SANDYBRIDGE
+VEXTRACTF128 xmmrm128,ymmreg,imm8 [mri: vex.256.66.0f3a.w0 19 /r ib] AVX,SANDYBRIDGE
+VEXTRACTPS rm32,xmmreg,imm8 [mri: vex.128.66.0f3a 17 /r ib] AVX,SANDYBRIDGE
+VHADDPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 7c /r] AVX,SANDYBRIDGE
+VHADDPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 7c /r] AVX,SANDYBRIDGE
+VHADDPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.f2.0f 7c /r] AVX,SANDYBRIDGE
+VHADDPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.f2.0f 7c /r] AVX,SANDYBRIDGE
+VHSUBPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 7d /r] AVX,SANDYBRIDGE
+VHSUBPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 7d /r] AVX,SANDYBRIDGE
+VHSUBPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.f2.0f 7d /r] AVX,SANDYBRIDGE
+VHSUBPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.f2.0f 7d /r] AVX,SANDYBRIDGE
+VINSERTF128 ymmreg,ymmreg*,xmmrm128,imm8 [rvmi: vex.nds.256.66.0f3a.w0 18 /r ib] AVX,SANDYBRIDGE
+VINSERTPS xmmreg,xmmreg*,xmmrm32,imm8 [rvmi: vex.nds.128.66.0f3a 21 /r ib] AVX,SANDYBRIDGE
+VLDDQU xmmreg,mem128 [rm: vex.128.f2.0f f0 /r] AVX,SANDYBRIDGE
+VLDQQU ymmreg,mem256 [rm: vex.256.f2.0f f0 /r] AVX,SANDYBRIDGE
+VLDDQU ymmreg,mem256 [rm: vex.256.f2.0f f0 /r] AVX,SANDYBRIDGE
+VLDMXCSR mem32 [m: vex.lz.0f ae /2] AVX,SANDYBRIDGE
+VMASKMOVDQU xmmreg,xmmreg [rm: vex.128.66.0f f7 /r] AVX,SANDYBRIDGE
+VMASKMOVPS xmmreg,xmmreg,mem128 [rvm: vex.nds.128.66.0f38.w0 2c /r] AVX,SANDYBRIDGE
+VMASKMOVPS ymmreg,ymmreg,mem256 [rvm: vex.nds.256.66.0f38.w0 2c /r] AVX,SANDYBRIDGE
+VMASKMOVPS mem128,xmmreg,xmmreg [mvr: vex.nds.128.66.0f38.w0 2e /r] AVX,SANDYBRIDGE,SO
+VMASKMOVPS mem256,ymmreg,ymmreg [mvr: vex.nds.256.66.0f38.w0 2e /r] AVX,SANDYBRIDGE,SY
+VMASKMOVPD xmmreg,xmmreg,mem128 [rvm: vex.nds.128.66.0f38.w0 2d /r] AVX,SANDYBRIDGE
+VMASKMOVPD ymmreg,ymmreg,mem256 [rvm: vex.nds.256.66.0f38.w0 2d /r] AVX,SANDYBRIDGE
+VMASKMOVPD mem128,xmmreg,xmmreg [mvr: vex.nds.128.66.0f38.w0 2f /r] AVX,SANDYBRIDGE
+VMASKMOVPD mem256,ymmreg,ymmreg [mvr: vex.nds.256.66.0f38.w0 2f /r] AVX,SANDYBRIDGE
+VMAXPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 5f /r] AVX,SANDYBRIDGE
+VMAXPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 5f /r] AVX,SANDYBRIDGE
+VMAXPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 5f /r] AVX,SANDYBRIDGE
+VMAXPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 5f /r] AVX,SANDYBRIDGE
+VMAXSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 5f /r] AVX,SANDYBRIDGE
+VMAXSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 5f /r] AVX,SANDYBRIDGE
+VMINPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 5d /r] AVX,SANDYBRIDGE
+VMINPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 5d /r] AVX,SANDYBRIDGE
+VMINPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 5d /r] AVX,SANDYBRIDGE
+VMINPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 5d /r] AVX,SANDYBRIDGE
+VMINSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 5d /r] AVX,SANDYBRIDGE
+VMINSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 5d /r] AVX,SANDYBRIDGE
+VMOVAPD xmmreg,xmmrm128 [rm: vex.128.66.0f 28 /r] AVX,SANDYBRIDGE
+VMOVAPD xmmrm128,xmmreg [mr: vex.128.66.0f 29 /r] AVX,SANDYBRIDGE
+VMOVAPD ymmreg,ymmrm256 [rm: vex.256.66.0f 28 /r] AVX,SANDYBRIDGE
+VMOVAPD ymmrm256,ymmreg [mr: vex.256.66.0f 29 /r] AVX,SANDYBRIDGE
+VMOVAPS xmmreg,xmmrm128 [rm: vex.128.0f 28 /r] AVX,SANDYBRIDGE
+VMOVAPS xmmrm128,xmmreg [mr: vex.128.0f 29 /r] AVX,SANDYBRIDGE
+VMOVAPS ymmreg,ymmrm256 [rm: vex.256.0f 28 /r] AVX,SANDYBRIDGE
+VMOVAPS ymmrm256,ymmreg [mr: vex.256.0f 29 /r] AVX,SANDYBRIDGE
+VMOVD xmmreg,rm32 [rm: vex.128.66.0f.w0 6e /r] AVX,SANDYBRIDGE
+VMOVD rm32,xmmreg [mr: vex.128.66.0f.w0 7e /r] AVX,SANDYBRIDGE
+VMOVQ xmmreg,xmmrm64 [rm: vex.128.f3.0f 7e /r] AVX,SANDYBRIDGE,SQ
+VMOVQ xmmrm64,xmmreg [mr: vex.128.66.0f d6 /r] AVX,SANDYBRIDGE,SQ
+VMOVQ xmmreg,rm64 [rm: vex.128.66.0f.w1 6e /r] AVX,SANDYBRIDGE,LONG,SQ
+VMOVQ rm64,xmmreg [mr: vex.128.66.0f.w1 7e /r] AVX,SANDYBRIDGE,LONG,SQ
+VMOVDDUP xmmreg,xmmrm64 [rm: vex.128.f2.0f 12 /r] AVX,SANDYBRIDGE
+VMOVDDUP ymmreg,ymmrm256 [rm: vex.256.f2.0f 12 /r] AVX,SANDYBRIDGE
+VMOVDQA xmmreg,xmmrm128 [rm: vex.128.66.0f 6f /r] AVX,SANDYBRIDGE
+VMOVDQA xmmrm128,xmmreg [mr: vex.128.66.0f 7f /r] AVX,SANDYBRIDGE
+; These are officially documented as VMOVDQA, but VMOVQQA seems more logical to me...
+VMOVQQA ymmreg,ymmrm256 [rm: vex.256.66.0f 6f /r] AVX,SANDYBRIDGE
+VMOVQQA ymmrm256,ymmreg [mr: vex.256.66.0f 7f /r] AVX,SANDYBRIDGE
+VMOVDQA ymmreg,ymmrm256 [rm: vex.256.66.0f 6f /r] AVX,SANDYBRIDGE
+VMOVDQA ymmrm256,ymmreg [mr: vex.256.66.0f 7f /r] AVX,SANDYBRIDGE
+VMOVDQU xmmreg,xmmrm128 [rm: vex.128.f3.0f 6f /r] AVX,SANDYBRIDGE
+VMOVDQU xmmrm128,xmmreg [mr: vex.128.f3.0f 7f /r] AVX,SANDYBRIDGE
+; These are officially documented as VMOVDQU, but VMOVQQU seems more logical to me...
+VMOVQQU ymmreg,ymmrm256 [rm: vex.256.f3.0f 6f /r] AVX,SANDYBRIDGE
+VMOVQQU ymmrm256,ymmreg [mr: vex.256.f3.0f 7f /r] AVX,SANDYBRIDGE
+VMOVDQU ymmreg,ymmrm256 [rm: vex.256.f3.0f 6f /r] AVX,SANDYBRIDGE
+VMOVDQU ymmrm256,ymmreg [mr: vex.256.f3.0f 7f /r] AVX,SANDYBRIDGE
+VMOVHLPS xmmreg,xmmreg*,xmmreg [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE
+VMOVHPD xmmreg,xmmreg*,mem64 [rvm: vex.nds.128.66.0f 16 /r] AVX,SANDYBRIDGE
+VMOVHPD mem64,xmmreg [mr: vex.128.66.0f 17 /r] AVX,SANDYBRIDGE
+VMOVHPS xmmreg,xmmreg*,mem64 [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE
+VMOVHPS mem64,xmmreg [mr: vex.128.0f 17 /r] AVX,SANDYBRIDGE
+VMOVLHPS xmmreg,xmmreg*,xmmreg [rvm: vex.nds.128.0f 16 /r] AVX,SANDYBRIDGE
+VMOVLPD xmmreg,xmmreg*,mem64 [rvm: vex.nds.128.66.0f 12 /r] AVX,SANDYBRIDGE
+VMOVLPD mem64,xmmreg [mr: vex.128.66.0f 13 /r] AVX,SANDYBRIDGE
+VMOVLPS xmmreg,xmmreg*,mem64 [rvm: vex.nds.128.0f 12 /r] AVX,SANDYBRIDGE
+VMOVLPS mem64,xmmreg [mr: vex.128.0f 13 /r] AVX,SANDYBRIDGE
+VMOVMSKPD reg64,xmmreg [rm: vex.128.66.0f 50 /r] AVX,SANDYBRIDGE,LONG
+VMOVMSKPD reg32,xmmreg [rm: vex.128.66.0f 50 /r] AVX,SANDYBRIDGE
+VMOVMSKPD reg64,ymmreg [rm: vex.256.66.0f 50 /r] AVX,SANDYBRIDGE,LONG
+VMOVMSKPD reg32,ymmreg [rm: vex.256.66.0f 50 /r] AVX,SANDYBRIDGE
+VMOVMSKPS reg64,xmmreg [rm: vex.128.0f 50 /r] AVX,SANDYBRIDGE,LONG
+VMOVMSKPS reg32,xmmreg [rm: vex.128.0f 50 /r] AVX,SANDYBRIDGE
+VMOVMSKPS reg64,ymmreg [rm: vex.256.0f 50 /r] AVX,SANDYBRIDGE,LONG
+VMOVMSKPS reg32,ymmreg [rm: vex.256.0f 50 /r] AVX,SANDYBRIDGE
+VMOVNTDQ mem128,xmmreg [mr: vex.128.66.0f e7 /r] AVX,SANDYBRIDGE
+; Officially VMOVNTDQ, but VMOVNTQQ seems more logical to me...
+VMOVNTQQ mem256,ymmreg [mr: vex.256.66.0f e7 /r] AVX,SANDYBRIDGE
+VMOVNTDQ mem256,ymmreg [mr: vex.256.66.0f e7 /r] AVX,SANDYBRIDGE
+VMOVNTDQA xmmreg,mem128 [rm: vex.128.66.0f38 2a /r] AVX,SANDYBRIDGE
+VMOVNTPD mem128,xmmreg [mr: vex.128.66.0f 2b /r] AVX,SANDYBRIDGE
+VMOVNTPD mem256,ymmreg [mr: vex.256.66.0f 2b /r] AVX,SANDYBRIDGE
+VMOVNTPS mem128,xmmreg [mr: vex.128.0f 2b /r] AVX,SANDYBRIDGE
+VMOVNTPS mem256,ymmreg [mr: vex.256.0f 2b /r] AVX,SANDYBRIDGE
+VMOVSD xmmreg,xmmreg*,xmmreg [rvm: vex.nds.lig.f2.0f 10 /r] AVX,SANDYBRIDGE
+VMOVSD xmmreg,mem64 [rm: vex.lig.f2.0f 10 /r] AVX,SANDYBRIDGE
+VMOVSD xmmreg,xmmreg*,xmmreg [mvr: vex.nds.lig.f2.0f 11 /r] AVX,SANDYBRIDGE
+VMOVSD mem64,xmmreg [mr: vex.lig.f2.0f 11 /r] AVX,SANDYBRIDGE
+VMOVSHDUP xmmreg,xmmrm128 [rm: vex.128.f3.0f 16 /r] AVX,SANDYBRIDGE
+VMOVSHDUP ymmreg,ymmrm256 [rm: vex.256.f3.0f 16 /r] AVX,SANDYBRIDGE
+VMOVSLDUP xmmreg,xmmrm128 [rm: vex.128.f3.0f 12 /r] AVX,SANDYBRIDGE
+VMOVSLDUP ymmreg,ymmrm256 [rm: vex.256.f3.0f 12 /r] AVX,SANDYBRIDGE
+VMOVSS xmmreg,xmmreg*,xmmreg [rvm: vex.nds.lig.f3.0f 10 /r] AVX,SANDYBRIDGE
+VMOVSS xmmreg,mem32 [rm: vex.lig.f3.0f 10 /r] AVX,SANDYBRIDGE
+VMOVSS xmmreg,xmmreg*,xmmreg [mvr: vex.nds.lig.f3.0f 11 /r] AVX,SANDYBRIDGE
+VMOVSS mem32,xmmreg [mr: vex.lig.f3.0f 11 /r] AVX,SANDYBRIDGE
+VMOVUPD xmmreg,xmmrm128 [rm: vex.128.66.0f 10 /r] AVX,SANDYBRIDGE
+VMOVUPD xmmrm128,xmmreg [mr: vex.128.66.0f 11 /r] AVX,SANDYBRIDGE
+VMOVUPD ymmreg,ymmrm256 [rm: vex.256.66.0f 10 /r] AVX,SANDYBRIDGE
+VMOVUPD ymmrm256,ymmreg [mr: vex.256.66.0f 11 /r] AVX,SANDYBRIDGE
+VMOVUPS xmmreg,xmmrm128 [rm: vex.128.0f 10 /r] AVX,SANDYBRIDGE
+VMOVUPS xmmrm128,xmmreg [mr: vex.128.0f 11 /r] AVX,SANDYBRIDGE
+VMOVUPS ymmreg,ymmrm256 [rm: vex.256.0f 10 /r] AVX,SANDYBRIDGE
+VMOVUPS ymmrm256,ymmreg [mr: vex.256.0f 11 /r] AVX,SANDYBRIDGE
+VMPSADBW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 42 /r ib] AVX,SANDYBRIDGE
+VMULPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 59 /r] AVX,SANDYBRIDGE
+VMULPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 59 /r] AVX,SANDYBRIDGE
+VMULPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 59 /r] AVX,SANDYBRIDGE
+VMULPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 59 /r] AVX,SANDYBRIDGE
+VMULSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 59 /r] AVX,SANDYBRIDGE
+VMULSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 59 /r] AVX,SANDYBRIDGE
+VORPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 56 /r] AVX,SANDYBRIDGE
+VORPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 56 /r] AVX,SANDYBRIDGE
+VORPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 56 /r] AVX,SANDYBRIDGE
+VORPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 56 /r] AVX,SANDYBRIDGE
+VPABSB xmmreg,xmmrm128 [rm: vex.128.66.0f38 1c /r] AVX,SANDYBRIDGE
+VPABSW xmmreg,xmmrm128 [rm: vex.128.66.0f38 1d /r] AVX,SANDYBRIDGE
+VPABSD xmmreg,xmmrm128 [rm: vex.128.66.0f38 1e /r] AVX,SANDYBRIDGE
+VPACKSSWB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 63 /r] AVX,SANDYBRIDGE
+VPACKSSDW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 6b /r] AVX,SANDYBRIDGE
+VPACKUSWB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 67 /r] AVX,SANDYBRIDGE
+VPACKUSDW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 2b /r] AVX,SANDYBRIDGE
+VPADDB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f fc /r] AVX,SANDYBRIDGE
+VPADDW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f fd /r] AVX,SANDYBRIDGE
+VPADDD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f fe /r] AVX,SANDYBRIDGE
+VPADDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d4 /r] AVX,SANDYBRIDGE
+VPADDSB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f ec /r] AVX,SANDYBRIDGE
+VPADDSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f ed /r] AVX,SANDYBRIDGE
+VPADDUSB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f dc /r] AVX,SANDYBRIDGE
+VPADDUSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f dd /r] AVX,SANDYBRIDGE
+VPALIGNR xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 0f /r ib] AVX,SANDYBRIDGE
+VPAND xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f db /r] AVX,SANDYBRIDGE
+VPANDN xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f df /r] AVX,SANDYBRIDGE
+VPAVGB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e0 /r] AVX,SANDYBRIDGE
+VPAVGW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e3 /r] AVX,SANDYBRIDGE
+VPBLENDVB xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.nds.128.66.0f3a.w0 4c /r /is4] AVX,SANDYBRIDGE
+VPBLENDW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 0e /r ib] AVX,SANDYBRIDGE
+VPCMPESTRI xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a 61 /r ib] AVX,SANDYBRIDGE
+VPCMPESTRM xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a 60 /r ib] AVX,SANDYBRIDGE
+VPCMPISTRI xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a 63 /r ib] AVX,SANDYBRIDGE
+VPCMPISTRM xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a 62 /r ib] AVX,SANDYBRIDGE
+VPCMPEQB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 74 /r] AVX,SANDYBRIDGE
+VPCMPEQW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 75 /r] AVX,SANDYBRIDGE
+VPCMPEQD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 76 /r] AVX,SANDYBRIDGE
+VPCMPEQQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 29 /r] AVX,SANDYBRIDGE
+VPCMPGTB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 64 /r] AVX,SANDYBRIDGE
+VPCMPGTW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 65 /r] AVX,SANDYBRIDGE
+VPCMPGTD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 66 /r] AVX,SANDYBRIDGE
+VPCMPGTQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 37 /r] AVX,SANDYBRIDGE
+VPERMILPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w0 0d /r] AVX,SANDYBRIDGE
+VPERMILPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 0d /r] AVX,SANDYBRIDGE
+VPERMILPD xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a.w0 05 /r ib] AVX,SANDYBRIDGE
+VPERMILPD ymmreg,ymmrm256,imm8 [rmi: vex.256.66.0f3a.w0 05 /r ib] AVX,SANDYBRIDGE
+VPERMILPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w0 0c /r] AVX,SANDYBRIDGE
+VPERMILPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 0c /r] AVX,SANDYBRIDGE
+VPERMILPS xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a.w0 04 /r ib] AVX,SANDYBRIDGE
+VPERMILPS ymmreg,ymmrm256,imm8 [rmi: vex.256.66.0f3a.w0 04 /r ib] AVX,SANDYBRIDGE
+VPERM2F128 ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a.w0 06 /r ib] AVX,SANDYBRIDGE
+VPEXTRB reg64,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 14 /r ib] AVX,SANDYBRIDGE,LONG
+VPEXTRB reg32,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 14 /r ib] AVX,SANDYBRIDGE
+VPEXTRB mem8,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 14 /r ib] AVX,SANDYBRIDGE
+VPEXTRW reg64,xmmreg,imm8 [rmi: vex.128.66.0f.w0 c5 /r ib] AVX,SANDYBRIDGE,LONG
+VPEXTRW reg32,xmmreg,imm8 [rmi: vex.128.66.0f.w0 c5 /r ib] AVX,SANDYBRIDGE
+VPEXTRW reg64,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 15 /r ib] AVX,SANDYBRIDGE,LONG
+VPEXTRW reg32,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 15 /r ib] AVX,SANDYBRIDGE
+VPEXTRW mem16,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 15 /r ib] AVX,SANDYBRIDGE
+VPEXTRD reg64,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 16 /r ib] AVX,SANDYBRIDGE,LONG
+VPEXTRD rm32,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 16 /r ib] AVX,SANDYBRIDGE
+VPEXTRQ rm64,xmmreg,imm8 [mri: vex.128.66.0f3a.w1 16 /r ib] AVX,SANDYBRIDGE,LONG
+VPHADDW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 01 /r] AVX,SANDYBRIDGE
+VPHADDD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 02 /r] AVX,SANDYBRIDGE
+VPHADDSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 03 /r] AVX,SANDYBRIDGE
+VPHMINPOSUW xmmreg,xmmrm128 [rm: vex.128.66.0f38 41 /r] AVX,SANDYBRIDGE
+VPHSUBW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 05 /r] AVX,SANDYBRIDGE
+VPHSUBD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 06 /r] AVX,SANDYBRIDGE
+VPHSUBSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 07 /r] AVX,SANDYBRIDGE
+VPINSRB xmmreg,xmmreg*,mem8,imm8 [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE
+VPINSRB xmmreg,xmmreg*,rm8,imm8 [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE
+VPINSRB xmmreg,xmmreg*,reg32,imm8 [rvmi: vex.nds.128.66.0f3a 20 /r ib] AVX,SANDYBRIDGE
+VPINSRW xmmreg,xmmreg*,mem16,imm8 [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE
+VPINSRW xmmreg,xmmreg*,rm16,imm8 [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE
+VPINSRW xmmreg,xmmreg*,reg32,imm8 [rvmi: vex.nds.128.66.0f c4 /r ib] AVX,SANDYBRIDGE
+VPINSRD xmmreg,xmmreg*,mem32,imm8 [rvmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE
+VPINSRD xmmreg,xmmreg*,rm32,imm8 [rvmi: vex.nds.128.66.0f3a.w0 22 /r ib] AVX,SANDYBRIDGE
+VPINSRQ xmmreg,xmmreg*,mem64,imm8 [rvmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,LONG
+VPINSRQ xmmreg,xmmreg*,rm64,imm8 [rvmi: vex.nds.128.66.0f3a.w1 22 /r ib] AVX,SANDYBRIDGE,LONG
+VPMADDWD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f5 /r] AVX,SANDYBRIDGE
+VPMADDUBSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 04 /r] AVX,SANDYBRIDGE
+VPMAXSB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 3c /r] AVX,SANDYBRIDGE
+VPMAXSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f ee /r] AVX,SANDYBRIDGE
+VPMAXSD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 3d /r] AVX,SANDYBRIDGE
+VPMAXUB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f de /r] AVX,SANDYBRIDGE
+VPMAXUW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 3e /r] AVX,SANDYBRIDGE
+VPMAXUD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 3f /r] AVX,SANDYBRIDGE
+VPMINSB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 38 /r] AVX,SANDYBRIDGE
+VPMINSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f ea /r] AVX,SANDYBRIDGE
+VPMINSD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 39 /r] AVX,SANDYBRIDGE
+VPMINUB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f da /r] AVX,SANDYBRIDGE
+VPMINUW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 3a /r] AVX,SANDYBRIDGE
+VPMINUD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 3b /r] AVX,SANDYBRIDGE
+VPMOVMSKB reg64,xmmreg [rm: vex.128.66.0f d7 /r] AVX,SANDYBRIDGE,LONG
+VPMOVMSKB reg32,xmmreg [rm: vex.128.66.0f d7 /r] AVX,SANDYBRIDGE
+VPMOVSXBW xmmreg,xmmrm64 [rm: vex.128.66.0f38 20 /r] AVX,SANDYBRIDGE
+VPMOVSXBD xmmreg,xmmrm32 [rm: vex.128.66.0f38 21 /r] AVX,SANDYBRIDGE
+VPMOVSXBQ xmmreg,xmmrm16 [rm: vex.128.66.0f38 22 /r] AVX,SANDYBRIDGE
+VPMOVSXWD xmmreg,xmmrm64 [rm: vex.128.66.0f38 23 /r] AVX,SANDYBRIDGE
+VPMOVSXWQ xmmreg,xmmrm32 [rm: vex.128.66.0f38 24 /r] AVX,SANDYBRIDGE
+VPMOVSXDQ xmmreg,xmmrm64 [rm: vex.128.66.0f38 25 /r] AVX,SANDYBRIDGE
+VPMOVZXBW xmmreg,xmmrm64 [rm: vex.128.66.0f38 30 /r] AVX,SANDYBRIDGE
+VPMOVZXBD xmmreg,xmmrm32 [rm: vex.128.66.0f38 31 /r] AVX,SANDYBRIDGE
+VPMOVZXBQ xmmreg,xmmrm16 [rm: vex.128.66.0f38 32 /r] AVX,SANDYBRIDGE
+VPMOVZXWD xmmreg,xmmrm64 [rm: vex.128.66.0f38 33 /r] AVX,SANDYBRIDGE
+VPMOVZXWQ xmmreg,xmmrm32 [rm: vex.128.66.0f38 34 /r] AVX,SANDYBRIDGE
+VPMOVZXDQ xmmreg,xmmrm64 [rm: vex.128.66.0f38 35 /r] AVX,SANDYBRIDGE
+VPMULHUW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e4 /r] AVX,SANDYBRIDGE
+VPMULHRSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 0b /r] AVX,SANDYBRIDGE
+VPMULHW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e5 /r] AVX,SANDYBRIDGE
+VPMULLW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d5 /r] AVX,SANDYBRIDGE
+VPMULLD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 40 /r] AVX,SANDYBRIDGE
+VPMULUDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f4 /r] AVX,SANDYBRIDGE
+VPMULDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 28 /r] AVX,SANDYBRIDGE
+VPOR xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f eb /r] AVX,SANDYBRIDGE
+VPSADBW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f6 /r] AVX,SANDYBRIDGE
+VPSHUFB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 00 /r] AVX,SANDYBRIDGE
+VPSHUFD xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f 70 /r ib] AVX,SANDYBRIDGE
+VPSHUFHW xmmreg,xmmrm128,imm8 [rmi: vex.128.f3.0f 70 /r ib] AVX,SANDYBRIDGE
+VPSHUFLW xmmreg,xmmrm128,imm8 [rmi: vex.128.f2.0f 70 /r ib] AVX,SANDYBRIDGE
+VPSIGNB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 08 /r] AVX,SANDYBRIDGE
+VPSIGNW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 09 /r] AVX,SANDYBRIDGE
+VPSIGND xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38 0a /r] AVX,SANDYBRIDGE
+VPSLLDQ xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 73 /7 ib] AVX,SANDYBRIDGE
+VPSRLDQ xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 73 /3 ib] AVX,SANDYBRIDGE
+VPSLLW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f1 /r] AVX,SANDYBRIDGE
+VPSLLW xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 71 /6 ib] AVX,SANDYBRIDGE
+VPSLLD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f2 /r] AVX,SANDYBRIDGE
+VPSLLD xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 72 /6 ib] AVX,SANDYBRIDGE
+VPSLLQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f3 /r] AVX,SANDYBRIDGE
+VPSLLQ xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 73 /6 ib] AVX,SANDYBRIDGE
+VPSRAW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e1 /r] AVX,SANDYBRIDGE
+VPSRAW xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 71 /4 ib] AVX,SANDYBRIDGE
+VPSRAD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e2 /r] AVX,SANDYBRIDGE
+VPSRAD xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 72 /4 ib] AVX,SANDYBRIDGE
+VPSRLW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d1 /r] AVX,SANDYBRIDGE
+VPSRLW xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 71 /2 ib] AVX,SANDYBRIDGE
+VPSRLD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d2 /r] AVX,SANDYBRIDGE
+VPSRLD xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 72 /2 ib] AVX,SANDYBRIDGE
+VPSRLQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d3 /r] AVX,SANDYBRIDGE
+VPSRLQ xmmreg,xmmreg*,imm8 [vmi: vex.ndd.128.66.0f 73 /2 ib] AVX,SANDYBRIDGE
+VPTEST xmmreg,xmmrm128 [rm: vex.128.66.0f38 17 /r] AVX,SANDYBRIDGE
+VPTEST ymmreg,ymmrm256 [rm: vex.256.66.0f38 17 /r] AVX,SANDYBRIDGE
+VPSUBB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f8 /r] AVX,SANDYBRIDGE
+VPSUBW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f f9 /r] AVX,SANDYBRIDGE
+VPSUBD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f fa /r] AVX,SANDYBRIDGE
+VPSUBQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f fb /r] AVX,SANDYBRIDGE
+VPSUBSB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e8 /r] AVX,SANDYBRIDGE
+VPSUBSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f e9 /r] AVX,SANDYBRIDGE
+VPSUBUSB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d8 /r] AVX,SANDYBRIDGE
+VPSUBUSW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f d9 /r] AVX,SANDYBRIDGE
+VPUNPCKHBW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 68 /r] AVX,SANDYBRIDGE
+VPUNPCKHWD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 69 /r] AVX,SANDYBRIDGE
+VPUNPCKHDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 6a /r] AVX,SANDYBRIDGE
+VPUNPCKHQDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 6d /r] AVX,SANDYBRIDGE
+VPUNPCKLBW xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 60 /r] AVX,SANDYBRIDGE
+VPUNPCKLWD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 61 /r] AVX,SANDYBRIDGE
+VPUNPCKLDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 62 /r] AVX,SANDYBRIDGE
+VPUNPCKLQDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 6c /r] AVX,SANDYBRIDGE
+VPXOR xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f ef /r] AVX,SANDYBRIDGE
+VRCPPS xmmreg,xmmrm128 [rm: vex.128.0f 53 /r] AVX,SANDYBRIDGE
+VRCPPS ymmreg,ymmrm256 [rm: vex.256.0f 53 /r] AVX,SANDYBRIDGE
+VRCPSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 53 /r] AVX,SANDYBRIDGE
+VRSQRTPS xmmreg,xmmrm128 [rm: vex.128.0f 52 /r] AVX,SANDYBRIDGE
+VRSQRTPS ymmreg,ymmrm256 [rm: vex.256.0f 52 /r] AVX,SANDYBRIDGE
+VRSQRTSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 52 /r] AVX,SANDYBRIDGE
+VROUNDPD xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a 09 /r ib] AVX,SANDYBRIDGE
+VROUNDPD ymmreg,ymmrm256,imm8 [rmi: vex.256.66.0f3a 09 /r ib] AVX,SANDYBRIDGE
+VROUNDPS xmmreg,xmmrm128,imm8 [rmi: vex.128.66.0f3a 08 /r ib] AVX,SANDYBRIDGE
+VROUNDPS ymmreg,ymmrm256,imm8 [rmi: vex.256.66.0f3a 08 /r ib] AVX,SANDYBRIDGE
+VROUNDSD xmmreg,xmmreg*,xmmrm64,imm8 [rvmi: vex.nds.128.66.0f3a 0b /r ib] AVX,SANDYBRIDGE
+VROUNDSS xmmreg,xmmreg*,xmmrm32,imm8 [rvmi: vex.nds.128.66.0f3a 0a /r ib] AVX,SANDYBRIDGE
+VSHUFPD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f c6 /r ib] AVX,SANDYBRIDGE
+VSHUFPD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f c6 /r ib] AVX,SANDYBRIDGE
+VSHUFPS xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.0f c6 /r ib] AVX,SANDYBRIDGE
+VSHUFPS ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.0f c6 /r ib] AVX,SANDYBRIDGE
+VSQRTPD xmmreg,xmmrm128 [rm: vex.128.66.0f 51 /r] AVX,SANDYBRIDGE
+VSQRTPD ymmreg,ymmrm256 [rm: vex.256.66.0f 51 /r] AVX,SANDYBRIDGE
+VSQRTPS xmmreg,xmmrm128 [rm: vex.128.0f 51 /r] AVX,SANDYBRIDGE
+VSQRTPS ymmreg,ymmrm256 [rm: vex.256.0f 51 /r] AVX,SANDYBRIDGE
+VSQRTSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 51 /r] AVX,SANDYBRIDGE
+VSQRTSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 51 /r] AVX,SANDYBRIDGE
+VSTMXCSR mem32 [m: vex.128.0f ae /3] AVX,SANDYBRIDGE
+VSUBPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 5c /r] AVX,SANDYBRIDGE
+VSUBPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 5c /r] AVX,SANDYBRIDGE
+VSUBPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 5c /r] AVX,SANDYBRIDGE
+VSUBPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 5c /r] AVX,SANDYBRIDGE
+VSUBSD xmmreg,xmmreg*,xmmrm64 [rvm: vex.nds.lig.f2.0f 5c /r] AVX,SANDYBRIDGE
+VSUBSS xmmreg,xmmreg*,xmmrm32 [rvm: vex.nds.lig.f3.0f 5c /r] AVX,SANDYBRIDGE
+VTESTPS xmmreg,xmmrm128 [rm: vex.128.66.0f38.w0 0e /r] AVX,SANDYBRIDGE
+VTESTPS ymmreg,ymmrm256 [rm: vex.256.66.0f38.w0 0e /r] AVX,SANDYBRIDGE
+VTESTPD xmmreg,xmmrm128 [rm: vex.128.66.0f38.w0 0f /r] AVX,SANDYBRIDGE
+VTESTPD ymmreg,ymmrm256 [rm: vex.256.66.0f38.w0 0f /r] AVX,SANDYBRIDGE
+VUCOMISD xmmreg,xmmrm64 [rm: vex.lig.66.0f 2e /r] AVX,SANDYBRIDGE
+VUCOMISS xmmreg,xmmrm32 [rm: vex.lig.0f 2e /r] AVX,SANDYBRIDGE
+VUNPCKHPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 15 /r] AVX,SANDYBRIDGE
+VUNPCKHPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 15 /r] AVX,SANDYBRIDGE
+VUNPCKHPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 15 /r] AVX,SANDYBRIDGE
+VUNPCKHPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 15 /r] AVX,SANDYBRIDGE
+VUNPCKLPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 14 /r] AVX,SANDYBRIDGE
+VUNPCKLPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 14 /r] AVX,SANDYBRIDGE
+VUNPCKLPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 14 /r] AVX,SANDYBRIDGE
+VUNPCKLPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 14 /r] AVX,SANDYBRIDGE
+VXORPD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f 57 /r] AVX,SANDYBRIDGE
+VXORPD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 57 /r] AVX,SANDYBRIDGE
+VXORPS xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.0f 57 /r] AVX,SANDYBRIDGE
+VXORPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.0f 57 /r] AVX,SANDYBRIDGE
+VZEROALL void [ vex.256.0f.w0 77] AVX,SANDYBRIDGE
+VZEROUPPER void [ vex.128.0f.w0 77] AVX,SANDYBRIDGE
+
+;# Intel Carry-Less Multiplication instructions (CLMUL)
+PCLMULLQLQDQ xmmreg,xmmrm128 [rm: 66 0f 3a 44 /r 00] SSE,WESTMERE
+PCLMULHQLQDQ xmmreg,xmmrm128 [rm: 66 0f 3a 44 /r 01] SSE,WESTMERE
+PCLMULLQHQDQ xmmreg,xmmrm128 [rm: 66 0f 3a 44 /r 10] SSE,WESTMERE
+PCLMULHQHQDQ xmmreg,xmmrm128 [rm: 66 0f 3a 44 /r 11] SSE,WESTMERE
+PCLMULQDQ xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a 44 /r ib] SSE,WESTMERE
+
+;# Intel AVX Carry-Less Multiplication instructions (CLMUL)
+VPCLMULLQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f3a 44 /r 00] AVX,SANDYBRIDGE
+VPCLMULHQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f3a 44 /r 01] AVX,SANDYBRIDGE
+VPCLMULLQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f3a 44 /r 10] AVX,SANDYBRIDGE
+VPCLMULHQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f3a 44 /r 11] AVX,SANDYBRIDGE
+VPCLMULQDQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a 44 /r ib] AVX,SANDYBRIDGE
+
+; Intel VPCLMULQDQ instructions
+VPCLMULLQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: vex.nds.256.66.0f3a.wig 44 /r 00] VPCLMULQDQ,FUTURE
+VPCLMULHQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: vex.nds.256.66.0f3a.wig 44 /r 01] VPCLMULQDQ,FUTURE
+VPCLMULLQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: vex.nds.256.66.0f3a.wig 44 /r 10] VPCLMULQDQ,FUTURE
+VPCLMULHQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: vex.nds.256.66.0f3a.wig 44 /r 11] VPCLMULQDQ,FUTURE
+VPCLMULQDQ ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:fv: vex.nds.256.66.0f3a.wig 44 /r ib] VPCLMULQDQ,FUTURE
+
+; Intel VPCLMULQDQ + AVX512VL instructions
+VPCLMULLQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f3a.wig 44 /r 00] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULHQLQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f3a.wig 44 /r 01] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULLQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f3a.wig 44 /r 10] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULHQHQDQ xmmreg,xmmreg*,xmmrm128 [rvm:fv: evex.nds.128.66.0f3a.wig 44 /r 11] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULQDQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi:fv: evex.nds.128.66.0f3a.wig 44 /r ib] AVX512VL,VPCLMULQDQ,FUTURE
+
+VPCLMULLQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f3a.wig 44 /r 00] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULHQLQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f3a.wig 44 /r 01] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULLQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f3a.wig 44 /r 10] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULHQHQDQ ymmreg,ymmreg*,ymmrm256 [rvm:fv: evex.nds.256.66.0f3a.wig 44 /r 11] AVX512VL,VPCLMULQDQ,FUTURE
+VPCLMULQDQ ymmreg,ymmreg*,ymmrm256,imm8 [rvmi:fv: evex.nds.256.66.0f3a.wig 44 /r ib] AVX512VL,VPCLMULQDQ,FUTURE
+
+; Intel VPCLMULQDQ + AVX512F instructions
+VPCLMULLQLQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f3a.wig 44 /r 00] AVX512,VPCLMULQDQ,FUTURE
+VPCLMULHQLQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f3a.wig 44 /r 01] AVX512,VPCLMULQDQ,FUTURE
+VPCLMULLQHQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f3a.wig 44 /r 10] AVX512,VPCLMULQDQ,FUTURE
+VPCLMULHQHQDQ zmmreg,zmmreg*,zmmrm512 [rvm:fv: evex.nds.512.66.0f3a.wig 44 /r 11] AVX512,VPCLMULQDQ,FUTURE
+VPCLMULQDQ zmmreg,zmmreg*,zmmrm512,imm8 [rvmi:fv: evex.nds.512.66.0f3a.wig 44 /r ib] AVX512,VPCLMULQDQ,FUTURE
+
+;# Intel Fused Multiply-Add instructions (FMA)
+VFMADD132PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE
+VFMADD132PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE
+VFMADD132PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE
+VFMADD132PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE
+VFMADD312PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 98 /r] FMA,FUTURE
+VFMADD312PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 98 /r] FMA,FUTURE
+VFMADD312PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 98 /r] FMA,FUTURE
+VFMADD312PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 98 /r] FMA,FUTURE
+VFMADD213PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE
+VFMADD213PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE
+VFMADD213PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE
+VFMADD213PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE
+VFMADD123PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 a8 /r] FMA,FUTURE
+VFMADD123PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 a8 /r] FMA,FUTURE
+VFMADD123PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 a8 /r] FMA,FUTURE
+VFMADD123PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 a8 /r] FMA,FUTURE
+VFMADD231PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE
+VFMADD231PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE
+VFMADD231PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE
+VFMADD231PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE
+VFMADD321PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 b8 /r] FMA,FUTURE
+VFMADD321PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 b8 /r] FMA,FUTURE
+VFMADD321PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 b8 /r] FMA,FUTURE
+VFMADD321PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 b8 /r] FMA,FUTURE
+VFMADDSUB132PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE
+VFMADDSUB132PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE
+VFMADDSUB132PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE
+VFMADDSUB132PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE
+VFMADDSUB312PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 96 /r] FMA,FUTURE
+VFMADDSUB312PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 96 /r] FMA,FUTURE
+VFMADDSUB312PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 96 /r] FMA,FUTURE
+VFMADDSUB312PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 96 /r] FMA,FUTURE
+VFMADDSUB213PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE
+VFMADDSUB213PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE
+VFMADDSUB213PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE
+VFMADDSUB213PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE
+VFMADDSUB123PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 a6 /r] FMA,FUTURE
+VFMADDSUB123PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 a6 /r] FMA,FUTURE
+VFMADDSUB123PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 a6 /r] FMA,FUTURE
+VFMADDSUB123PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 a6 /r] FMA,FUTURE
+VFMADDSUB231PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE
+VFMADDSUB231PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE
+VFMADDSUB231PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE
+VFMADDSUB231PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE
+VFMADDSUB321PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 b6 /r] FMA,FUTURE
+VFMADDSUB321PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 b6 /r] FMA,FUTURE
+VFMADDSUB321PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 b6 /r] FMA,FUTURE
+VFMADDSUB321PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 b6 /r] FMA,FUTURE
+VFMSUB132PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE
+VFMSUB132PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE
+VFMSUB132PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE
+VFMSUB132PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE
+VFMSUB312PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 9a /r] FMA,FUTURE
+VFMSUB312PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 9a /r] FMA,FUTURE
+VFMSUB312PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 9a /r] FMA,FUTURE
+VFMSUB312PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 9a /r] FMA,FUTURE
+VFMSUB213PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE
+VFMSUB213PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE
+VFMSUB213PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE
+VFMSUB213PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE
+VFMSUB123PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 aa /r] FMA,FUTURE
+VFMSUB123PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 aa /r] FMA,FUTURE
+VFMSUB123PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 aa /r] FMA,FUTURE
+VFMSUB123PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 aa /r] FMA,FUTURE
+VFMSUB231PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE
+VFMSUB231PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE
+VFMSUB231PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE
+VFMSUB231PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE
+VFMSUB321PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 ba /r] FMA,FUTURE
+VFMSUB321PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 ba /r] FMA,FUTURE
+VFMSUB321PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 ba /r] FMA,FUTURE
+VFMSUB321PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 ba /r] FMA,FUTURE
+VFMSUBADD132PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE
+VFMSUBADD132PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE
+VFMSUBADD132PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE
+VFMSUBADD132PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE
+VFMSUBADD312PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 97 /r] FMA,FUTURE
+VFMSUBADD312PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 97 /r] FMA,FUTURE
+VFMSUBADD312PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 97 /r] FMA,FUTURE
+VFMSUBADD312PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 97 /r] FMA,FUTURE
+VFMSUBADD213PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE
+VFMSUBADD213PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE
+VFMSUBADD213PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE
+VFMSUBADD213PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE
+VFMSUBADD123PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 a7 /r] FMA,FUTURE
+VFMSUBADD123PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 a7 /r] FMA,FUTURE
+VFMSUBADD123PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 a7 /r] FMA,FUTURE
+VFMSUBADD123PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 a7 /r] FMA,FUTURE
+VFMSUBADD231PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE
+VFMSUBADD231PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE
+VFMSUBADD231PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE
+VFMSUBADD231PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE
+VFMSUBADD321PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 b7 /r] FMA,FUTURE
+VFMSUBADD321PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 b7 /r] FMA,FUTURE
+VFMSUBADD321PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 b7 /r] FMA,FUTURE
+VFMSUBADD321PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 b7 /r] FMA,FUTURE
+VFNMADD132PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE
+VFNMADD132PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE
+VFNMADD132PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE
+VFNMADD132PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE
+VFNMADD312PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 9c /r] FMA,FUTURE
+VFNMADD312PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 9c /r] FMA,FUTURE
+VFNMADD312PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 9c /r] FMA,FUTURE
+VFNMADD312PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 9c /r] FMA,FUTURE
+VFNMADD213PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE
+VFNMADD213PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE
+VFNMADD213PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE
+VFNMADD213PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE
+VFNMADD123PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 ac /r] FMA,FUTURE
+VFNMADD123PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 ac /r] FMA,FUTURE
+VFNMADD123PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 ac /r] FMA,FUTURE
+VFNMADD123PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 ac /r] FMA,FUTURE
+VFNMADD231PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE
+VFNMADD231PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE
+VFNMADD231PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE
+VFNMADD231PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE
+VFNMADD321PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 bc /r] FMA,FUTURE
+VFNMADD321PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 bc /r] FMA,FUTURE
+VFNMADD321PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 bc /r] FMA,FUTURE
+VFNMADD321PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 bc /r] FMA,FUTURE
+VFNMSUB132PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE
+VFNMSUB132PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE
+VFNMSUB132PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE
+VFNMSUB132PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE
+VFNMSUB312PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 9e /r] FMA,FUTURE
+VFNMSUB312PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 9e /r] FMA,FUTURE
+VFNMSUB312PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 9e /r] FMA,FUTURE
+VFNMSUB312PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 9e /r] FMA,FUTURE
+VFNMSUB213PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE
+VFNMSUB213PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE
+VFNMSUB213PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE
+VFNMSUB213PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE
+VFNMSUB123PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 ae /r] FMA,FUTURE
+VFNMSUB123PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 ae /r] FMA,FUTURE
+VFNMSUB123PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 ae /r] FMA,FUTURE
+VFNMSUB123PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 ae /r] FMA,FUTURE
+VFNMSUB231PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE
+VFNMSUB231PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE
+VFNMSUB231PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE
+VFNMSUB231PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE
+VFNMSUB321PS xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w0 be /r] FMA,FUTURE
+VFNMSUB321PS ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w0 be /r] FMA,FUTURE
+VFNMSUB321PD xmmreg,xmmreg,xmmrm128 [rvm: vex.dds.128.66.0f38.w1 be /r] FMA,FUTURE
+VFNMSUB321PD ymmreg,ymmreg,ymmrm256 [rvm: vex.dds.256.66.0f38.w1 be /r] FMA,FUTURE
+VFMADD132SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE
+VFMADD132SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE
+VFMADD312SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 99 /r] FMA,FUTURE
+VFMADD312SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 99 /r] FMA,FUTURE
+VFMADD213SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE
+VFMADD213SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE
+VFMADD123SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 a9 /r] FMA,FUTURE
+VFMADD123SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 a9 /r] FMA,FUTURE
+VFMADD231SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE
+VFMADD231SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE
+VFMADD321SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 b9 /r] FMA,FUTURE
+VFMADD321SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 b9 /r] FMA,FUTURE
+VFMSUB132SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE
+VFMSUB132SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE
+VFMSUB312SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 9b /r] FMA,FUTURE
+VFMSUB312SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 9b /r] FMA,FUTURE
+VFMSUB213SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE
+VFMSUB213SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE
+VFMSUB123SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 ab /r] FMA,FUTURE
+VFMSUB123SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 ab /r] FMA,FUTURE
+VFMSUB231SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE
+VFMSUB231SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE
+VFMSUB321SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 bb /r] FMA,FUTURE
+VFMSUB321SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 bb /r] FMA,FUTURE
+VFNMADD132SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE
+VFNMADD132SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE
+VFNMADD312SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 9d /r] FMA,FUTURE
+VFNMADD312SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 9d /r] FMA,FUTURE
+VFNMADD213SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE
+VFNMADD213SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE
+VFNMADD123SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 ad /r] FMA,FUTURE
+VFNMADD123SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 ad /r] FMA,FUTURE
+VFNMADD231SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE
+VFNMADD231SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE
+VFNMADD321SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 bd /r] FMA,FUTURE
+VFNMADD321SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 bd /r] FMA,FUTURE
+VFNMSUB132SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE
+VFNMSUB132SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE
+VFNMSUB312SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 9f /r] FMA,FUTURE
+VFNMSUB312SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 9f /r] FMA,FUTURE
+VFNMSUB213SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE
+VFNMSUB213SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE
+VFNMSUB123SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 af /r] FMA,FUTURE
+VFNMSUB123SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 af /r] FMA,FUTURE
+VFNMSUB231SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE
+VFNMSUB231SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE
+VFNMSUB321SS xmmreg,xmmreg,xmmrm32 [rvm: vex.dds.128.66.0f38.w0 bf /r] FMA,FUTURE
+VFNMSUB321SD xmmreg,xmmreg,xmmrm64 [rvm: vex.dds.128.66.0f38.w1 bf /r] FMA,FUTURE
+
+;# Intel post-32 nm processor instructions
+;
+; Per AVX spec revision 7, document 319433-007
+RDFSBASE reg32 [m: norexw f3 0f ae /0] LONG,FUTURE
+RDFSBASE reg64 [m: o64 f3 0f ae /0] LONG,FUTURE
+RDGSBASE reg32 [m: norexw f3 0f ae /1] LONG,FUTURE
+RDGSBASE reg64 [m: o64 f3 0f ae /1] LONG,FUTURE
+RDRAND reg16 [m: o16 0f c7 /6] FUTURE
+RDRAND reg32 [m: o32 0f c7 /6] FUTURE
+RDRAND reg64 [m: o64 0f c7 /6] LONG,FUTURE
+WRFSBASE reg32 [m: norexw f3 0f ae /2] LONG,FUTURE
+WRFSBASE reg64 [m: o64 f3 0f ae /2] LONG,FUTURE
+WRGSBASE reg32 [m: norexw f3 0f ae /3] LONG,FUTURE
+WRGSBASE reg64 [m: o64 f3 0f ae /3] LONG,FUTURE
+VCVTPH2PS ymmreg,xmmrm128 [rm: vex.256.66.0f38.w0 13 /r] AVX,FUTURE
+VCVTPH2PS xmmreg,xmmrm64 [rm: vex.128.66.0f38.w0 13 /r] AVX,FUTURE
+VCVTPS2PH xmmrm128,ymmreg,imm8 [mri: vex.256.66.0f3a.w0 1d /r ib] AVX,FUTURE
+VCVTPS2PH xmmrm64,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 1d /r ib] AVX,FUTURE
+
+; Per AVX spec revision 13, document 319433-013
+ADCX reg32,rm32 [rm: norexw 66 0f 38 f6 /r] FUTURE
+ADCX reg64,rm64 [rm: o64 66 0f 38 f6 /r] LONG,FUTURE
+ADOX reg32,rm32 [rm: norexw f3 0f 38 f6 /r] FUTURE
+ADOX reg64,rm64 [rm: o64 f3 0f 38 f6 /r] LONG,FUTURE
+RDSEED reg16 [m: o16 0f c7 /7] FUTURE
+RDSEED reg32 [m: o32 0f c7 /7] FUTURE
+RDSEED reg64 [m: o64 0f c7 /7] LONG,FUTURE
+
+; Per AVX spec revision 14, document 319433-014
+CLAC void [ 0f 01 ca] PRIV,FUTURE
+STAC void [ 0f 01 cb] PRIV,FUTURE
+
+;# VIA (Centaur) security instructions
+XSTORE void [ 0f a7 c0] PENT,CYRIX
+XCRYPTECB void [ mustrep 0f a7 c8] PENT,CYRIX
+XCRYPTCBC void [ mustrep 0f a7 d0] PENT,CYRIX
+XCRYPTCTR void [ mustrep 0f a7 d8] PENT,CYRIX
+XCRYPTCFB void [ mustrep 0f a7 e0] PENT,CYRIX
+XCRYPTOFB void [ mustrep 0f a7 e8] PENT,CYRIX
+MONTMUL void [ mustrep 0f a6 c0] PENT,CYRIX
+XSHA1 void [ mustrep 0f a6 c8] PENT,CYRIX
+XSHA256 void [ mustrep 0f a6 d0] PENT,CYRIX
+
+;# AMD Lightweight Profiling (LWP) instructions
+;
+; based on pub number 43724 revision 3.04 date August 2009
+;
+; updated to match draft from AMD developer (patch has been
+; sent to binutils
+; 2010-03-22 Quentin Neill <quentin.neill@amd.com>
+; Sebastian Pop <sebastian.pop@amd.com>
+;
+LLWPCB reg32 [m: xop.m9.w0.l0.p0 12 /0] AMD,386
+LLWPCB reg64 [m: xop.m9.w1.l0.p0 12 /0] AMD,X86_64,LONG
+
+SLWPCB reg32 [m: xop.m9.w0.l0.p0 12 /1] AMD,386
+SLWPCB reg64 [m: xop.m9.w1.l0.p0 12 /1] AMD,X86_64,LONG
+
+LWPVAL reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l0.p0 12 /1 id] AMD,386
+LWPVAL reg64,rm32,imm32 [vmi: xop.m10.w1.ndd.l0.p0 12 /1 id] AMD,X86_64,LONG
+
+LWPINS reg32,rm32,imm32 [vmi: xop.m10.w0.ndd.l0.p0 12 /0 id] AMD,386
+LWPINS reg64,rm32,imm32 [vmi: xop.m10.w1.ndd.l0.p0 12 /0 id] AMD,X86_64,LONG
+
+;# AMD XOP and FMA4 instructions (SSE5)
+;
+; based on pub number 43479 revision 3.04 dated November 2009
+;
+VFMADDPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 69 /r /is4] AMD,SSE5
+VFMADDPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 69 /r /is4] AMD,SSE5
+VFMADDPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 69 /r /is4] AMD,SSE5
+VFMADDPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 69 /r /is4] AMD,SSE5
+
+VFMADDPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 68 /r /is4] AMD,SSE5
+VFMADDPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 68 /r /is4] AMD,SSE5
+VFMADDPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 68 /r /is4] AMD,SSE5
+VFMADDPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 68 /r /is4] AMD,SSE5
+
+VFMADDSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6b /r /is4] AMD,SSE5
+VFMADDSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm: vex.m3.w1.nds.l0.p1 6b /r /is4] AMD,SSE5
+
+VFMADDSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6a /r /is4] AMD,SSE5
+VFMADDSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm: vex.m3.w1.nds.l0.p1 6a /r /is4] AMD,SSE5
+
+VFMADDSUBPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5d /r /is4] AMD,SSE5
+VFMADDSUBPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5d /r /is4] AMD,SSE5
+VFMADDSUBPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 5d /r /is4] AMD,SSE5
+VFMADDSUBPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 5d /r /is4] AMD,SSE5
+
+VFMADDSUBPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5c /r /is4] AMD,SSE5
+VFMADDSUBPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5c /r /is4] AMD,SSE5
+VFMADDSUBPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 5c /r /is4] AMD,SSE5
+VFMADDSUBPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 5c /r /is4] AMD,SSE5
+
+VFMSUBADDPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5f /r /is4] AMD,SSE5
+VFMSUBADDPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5f /r /is4] AMD,SSE5
+VFMSUBADDPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 5f /r /is4] AMD,SSE5
+VFMSUBADDPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 5f /r /is4] AMD,SSE5
+
+VFMSUBADDPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 5e /r /is4] AMD,SSE5
+VFMSUBADDPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 5e /r /is4] AMD,SSE5
+VFMSUBADDPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 5e /r /is4] AMD,SSE5
+VFMSUBADDPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 5e /r /is4] AMD,SSE5
+
+VFMSUBPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6d /r /is4] AMD,SSE5
+VFMSUBPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 6d /r /is4] AMD,SSE5
+VFMSUBPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 6d /r /is4] AMD,SSE5
+VFMSUBPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 6d /r /is4] AMD,SSE5
+
+VFMSUBPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6c /r /is4] AMD,SSE5
+VFMSUBPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 6c /r /is4] AMD,SSE5
+VFMSUBPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 6c /r /is4] AMD,SSE5
+VFMSUBPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 6c /r /is4] AMD,SSE5
+
+VFMSUBSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6f /r /is4] AMD,SSE5
+VFMSUBSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm: vex.m3.w1.nds.l0.p1 6f /r /is4] AMD,SSE5
+
+VFMSUBSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms: vex.m3.w0.nds.l0.p1 6e /r /is4] AMD,SSE5
+VFMSUBSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm: vex.m3.w1.nds.l0.p1 6e /r /is4] AMD,SSE5
+
+VFNMADDPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 79 /r /is4] AMD,SSE5
+VFNMADDPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 79 /r /is4] AMD,SSE5
+VFNMADDPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 79 /r /is4] AMD,SSE5
+VFNMADDPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 79 /r /is4] AMD,SSE5
+
+VFNMADDPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 78 /r /is4] AMD,SSE5
+VFNMADDPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 78 /r /is4] AMD,SSE5
+VFNMADDPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 78 /r /is4] AMD,SSE5
+VFNMADDPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 78 /r /is4] AMD,SSE5
+
+VFNMADDSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7b /r /is4] AMD,SSE5
+VFNMADDSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm: vex.m3.w1.nds.l0.p1 7b /r /is4] AMD,SSE5
+
+VFNMADDSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7a /r /is4] AMD,SSE5
+VFNMADDSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm: vex.m3.w1.nds.l0.p1 7a /r /is4] AMD,SSE5
+
+VFNMSUBPD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7d /r /is4] AMD,SSE5
+VFNMSUBPD ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 7d /r /is4] AMD,SSE5
+VFNMSUBPD xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 7d /r /is4] AMD,SSE5
+VFNMSUBPD ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 7d /r /is4] AMD,SSE5
+
+VFNMSUBPS xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7c /r /is4] AMD,SSE5
+VFNMSUBPS ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.m3.w0.nds.l1.p1 7c /r /is4] AMD,SSE5
+VFNMSUBPS xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: vex.m3.w1.nds.l0.p1 7c /r /is4] AMD,SSE5
+VFNMSUBPS ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: vex.m3.w1.nds.l1.p1 7c /r /is4] AMD,SSE5
+
+VFNMSUBSD xmmreg,xmmreg*,xmmrm64,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7f /r /is4] AMD,SSE5
+VFNMSUBSD xmmreg,xmmreg*,xmmreg,xmmrm64 [rvsm: vex.m3.w1.nds.l0.p1 7f /r /is4] AMD,SSE5
+
+VFNMSUBSS xmmreg,xmmreg*,xmmrm32,xmmreg [rvms: vex.m3.w0.nds.l0.p1 7e /r /is4] AMD,SSE5
+VFNMSUBSS xmmreg,xmmreg*,xmmreg,xmmrm32 [rvsm: vex.m3.w1.nds.l0.p1 7e /r /is4] AMD,SSE5
+
+VFRCZPD xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 81 /r] AMD,SSE5
+VFRCZPD ymmreg,ymmrm256* [rm: xop.m9.w0.l1.p0 81 /r] AMD,SSE5
+
+VFRCZPS xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 80 /r] AMD,SSE5
+VFRCZPS ymmreg,ymmrm256* [rm: xop.m9.w0.l1.p0 80 /r] AMD,SSE5
+
+VFRCZSD xmmreg,xmmrm64* [rm: xop.m9.w0.l0.p0 83 /r] AMD,SSE5
+
+VFRCZSS xmmreg,xmmrm32* [rm: xop.m9.w0.l0.p0 82 /r] AMD,SSE5
+;
+; fixed: spec mention imm[7:4] though it should be /is4 even in spec
+VPCMOV xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 a2 /r /is4] AMD,SSE5
+VPCMOV ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: xop.m8.w0.nds.l1.p0 a2 /r /is4] AMD,SSE5
+VPCMOV xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: xop.m8.w1.nds.l0.p0 a2 /r /is4] AMD,SSE5
+VPCMOV ymmreg,ymmreg*,ymmreg,ymmrm256 [rvsm: xop.m8.w1.nds.l1.p0 a2 /r /is4] AMD,SSE5
+
+VPCOMB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 cc /r ib] AMD,SSE5
+VPCOMD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 ce /r ib] AMD,SSE5
+VPCOMQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 cf /r ib] AMD,SSE5
+;
+; fixed: spec mention only 3 operands in mnemonics
+VPCOMUB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 ec /r ib] AMD,SSE5
+VPCOMUD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 ee /r ib] AMD,SSE5
+VPCOMUQ xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 ef /r ib] AMD,SSE5
+;
+; fixed: spec point wrong VPCOMB in mnemonic
+VPCOMUW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 ed /r ib] AMD,SSE5
+VPCOMW xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: xop.m8.w0.nds.l0.p0 cd /r ib] AMD,SSE5
+
+VPHADDBD xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 c2 /r] AMD,SSE5
+VPHADDBQ xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 c3 /r] AMD,SSE5
+VPHADDBW xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 c1 /r] AMD,SSE5
+VPHADDDQ xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 cb /r] AMD,SSE5
+;
+; fixed: spec has ymmreg for l0
+VPHADDUBD xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 d2 /r] AMD,SSE5
+VPHADDUBQ xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 d3 /r] AMD,SSE5
+;
+; fixed: spec has VPHADDUBWD
+VPHADDUBW xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 d1 /r] AMD,SSE5
+;
+; fixed: opcode db
+VPHADDUDQ xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 db /r] AMD,SSE5
+VPHADDUWD xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 d6 /r] AMD,SSE5
+VPHADDUWQ xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 d7 /r] AMD,SSE5
+;
+; fixed: spec has ymmreg for l0
+VPHADDWD xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 c6 /r] AMD,SSE5
+;
+; fixed: spec has d7 opcode
+VPHADDWQ xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 c7 /r] AMD,SSE5
+
+VPHSUBBW xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 e1 /r] AMD,SSE5
+VPHSUBDQ xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 e3 /r] AMD,SSE5
+VPHSUBWD xmmreg,xmmrm128* [rm: xop.m9.w0.l0.p0 e2 /r] AMD,SSE5
+
+VPMACSDD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 9e /r /is4] AMD,SSE5
+;
+; fixed: spec has 97,9f opcodes here
+VPMACSDQH xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 9f /r /is4] AMD,SSE5
+VPMACSDQL xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 97 /r /is4] AMD,SSE5
+VPMACSSDD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 8e /r /is4] AMD,SSE5
+VPMACSSDQH xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 8f /r /is4] AMD,SSE5
+VPMACSSDQL xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 87 /r /is4] AMD,SSE5
+VPMACSSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 86 /r /is4] AMD,SSE5
+VPMACSSWW xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 85 /r /is4] AMD,SSE5
+VPMACSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 96 /r /is4] AMD,SSE5
+VPMACSWW xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 95 /r /is4] AMD,SSE5
+VPMADCSSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 a6 /r /is4] AMD,SSE5
+VPMADCSWD xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 b6 /r /is4] AMD,SSE5
+
+VPPERM xmmreg,xmmreg*,xmmreg,xmmrm128 [rvsm: xop.m8.w1.nds.l0.p0 a3 /r /is4] AMD,SSE5
+VPPERM xmmreg,xmmreg*,xmmrm128,xmmreg [rvms: xop.m8.w0.nds.l0.p0 a3 /r /is4] AMD,SSE5
+
+VPROTB xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 90 /r] AMD,SSE5
+VPROTB xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 90 /r] AMD,SSE5
+;
+; fixed: spec point xmmreg instead of reg/mem
+VPROTB xmmreg,xmmrm128*,imm8 [rmi: xop.m8.w0.l0.p0 c0 /r ib] AMD,SSE5
+
+VPROTD xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 92 /r] AMD,SSE5
+VPROTD xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 92 /r] AMD,SSE5
+;
+; fixed: spec error /r is needed
+VPROTD xmmreg,xmmrm128*,imm8 [rmi: xop.m8.w0.l0.p0 c2 /r ib] AMD,SSE5
+VPROTQ xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 93 /r] AMD,SSE5
+VPROTQ xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 93 /r] AMD,SSE5
+;
+; fixed: spec error /r is needed
+VPROTQ xmmreg,xmmrm128*,imm8 [rmi: xop.m8.w0.l0.p0 c3 /r ib] AMD,SSE5
+VPROTW xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 91 /r] AMD,SSE5
+VPROTW xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 91 /r] AMD,SSE5
+VPROTW xmmreg,xmmrm128*,imm8 [rmi: xop.m8.w0.l0.p0 c1 /r ib] AMD,SSE5
+
+VPSHAB xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 98 /r] AMD,SSE5
+VPSHAB xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 98 /r] AMD,SSE5
+
+VPSHAD xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 9a /r] AMD,SSE5
+VPSHAD xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 9a /r] AMD,SSE5
+
+VPSHAQ xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 9b /r] AMD,SSE5
+VPSHAQ xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 9b /r] AMD,SSE5
+
+VPSHAW xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 99 /r] AMD,SSE5
+VPSHAW xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 99 /r] AMD,SSE5
+
+VPSHLB xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 94 /r] AMD,SSE5
+VPSHLB xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 94 /r] AMD,SSE5
+
+;
+; fixed: spec has ymmreg for l0
+VPSHLD xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 96 /r] AMD,SSE5
+VPSHLD xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 96 /r] AMD,SSE5
+
+VPSHLQ xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 97 /r] AMD,SSE5
+VPSHLQ xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 97 /r] AMD,SSE5
+
+VPSHLW xmmreg,xmmrm128*,xmmreg [rmv: xop.m9.w0.nds.l0.p0 95 /r] AMD,SSE5
+VPSHLW xmmreg,xmmreg*,xmmrm128 [rvm: xop.m9.w1.nds.l0.p0 95 /r] AMD,SSE5
+
+;# Intel AVX2 instructions
+;
+; based on pub number 319433-011 dated July 2011
+;
+VMPSADBW ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a 42 /r ib] FUTURE,AVX2
+VPABSB ymmreg,ymmrm256 [rm: vex.256.66.0f38 1c /r] FUTURE,AVX2
+VPABSW ymmreg,ymmrm256 [rm: vex.256.66.0f38 1d /r] FUTURE,AVX2
+VPABSD ymmreg,ymmrm256 [rm: vex.256.66.0f38 1e /r] FUTURE,AVX2
+VPACKSSWB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 63 /r] FUTURE,AVX2
+VPACKSSDW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 6b /r] FUTURE,AVX2
+VPACKUSDW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 2b /r] FUTURE,AVX2
+VPACKUSWB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 67 /r] FUTURE,AVX2
+VPADDB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f fc /r] FUTURE,AVX2
+VPADDW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f fd /r] FUTURE,AVX2
+VPADDD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f fe /r] FUTURE,AVX2
+VPADDQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f d4 /r] FUTURE,AVX2
+VPADDSB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f ec /r] FUTURE,AVX2
+VPADDSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f ed /r] FUTURE,AVX2
+VPADDUSB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f dc /r] FUTURE,AVX2
+VPADDUSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f dd /r] FUTURE,AVX2
+VPALIGNR ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a 0f /r ib] FUTURE,AVX2
+VPAND ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f db /r] FUTURE,AVX2
+VPANDN ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f df /r] FUTURE,AVX2
+VPAVGB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f e0 /r] FUTURE,AVX2
+VPAVGW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f e3 /r] FUTURE,AVX2
+VPBLENDVB ymmreg,ymmreg*,ymmrm256,ymmreg [rvms: vex.nds.256.66.0f3a 4c /r /is4] FUTURE,AVX2
+VPBLENDW ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a 0e /r ib] FUTURE,AVX2
+VPCMPEQB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 74 /r] FUTURE,AVX2
+VPCMPEQW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 75 /r] FUTURE,AVX2
+VPCMPEQD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 76 /r] FUTURE,AVX2
+VPCMPEQQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 29 /r] FUTURE,AVX2
+VPCMPGTB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 64 /r] FUTURE,AVX2
+VPCMPGTW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 65 /r] FUTURE,AVX2
+VPCMPGTD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 66 /r] FUTURE,AVX2
+VPCMPGTQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 37 /r] FUTURE,AVX2
+VPHADDW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 01 /r] FUTURE,AVX2
+VPHADDD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 02 /r] FUTURE,AVX2
+VPHADDSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 03 /r] FUTURE,AVX2
+VPHSUBW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 05 /r] FUTURE,AVX2
+VPHSUBD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 06 /r] FUTURE,AVX2
+VPHSUBSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 07 /r] FUTURE,AVX2
+VPMADDUBSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 04 /r] FUTURE,AVX2
+VPMADDWD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f f5 /r] FUTURE,AVX2
+VPMAXSB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 3c /r] FUTURE,AVX2
+VPMAXSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f ee /r] FUTURE,AVX2
+VPMAXSD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 3d /r] FUTURE,AVX2
+VPMAXUB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f de /r] FUTURE,AVX2
+VPMAXUW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 3e /r] FUTURE,AVX2
+VPMAXUD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 3f /r] FUTURE,AVX2
+VPMINSB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 38 /r] FUTURE,AVX2
+VPMINSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f ea /r] FUTURE,AVX2
+VPMINSD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 39 /r] FUTURE,AVX2
+VPMINUB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f da /r] FUTURE,AVX2
+VPMINUW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 3a /r] FUTURE,AVX2
+VPMINUD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 3b /r] FUTURE,AVX2
+VPMOVMSKB reg32,ymmreg [rm: vex.256.66.0f d7 /r] FUTURE,AVX2
+VPMOVMSKB reg64,ymmreg [rm: vex.256.66.0f d7 /r] FUTURE,AVX2
+VPMOVSXBW ymmreg,xmmrm128 [rm: vex.256.66.0f38 20 /r] FUTURE,AVX2
+VPMOVSXBD ymmreg,mem64 [rm: vex.256.66.0f38 21 /r] FUTURE,AVX2
+VPMOVSXBD ymmreg,xmmreg [rm: vex.256.66.0f38 21 /r] FUTURE,AVX2
+VPMOVSXBQ ymmreg,mem32 [rm: vex.256.66.0f38 22 /r] FUTURE,AVX2
+VPMOVSXBQ ymmreg,xmmreg [rm: vex.256.66.0f38 22 /r] FUTURE,AVX2
+VPMOVSXWD ymmreg,xmmrm128 [rm: vex.256.66.0f38 23 /r] FUTURE,AVX2
+VPMOVSXWQ ymmreg,mem64 [rm: vex.256.66.0f38 24 /r] FUTURE,AVX2
+VPMOVSXWQ ymmreg,xmmreg [rm: vex.256.66.0f38 24 /r] FUTURE,AVX2
+VPMOVSXDQ ymmreg,xmmrm128 [rm: vex.256.66.0f38 25 /r] FUTURE,AVX2
+VPMOVZXBW ymmreg,xmmrm128 [rm: vex.256.66.0f38 30 /r] FUTURE,AVX2
+VPMOVZXBD ymmreg,mem64 [rm: vex.256.66.0f38 31 /r] FUTURE,AVX2
+VPMOVZXBD ymmreg,xmmreg [rm: vex.256.66.0f38 31 /r] FUTURE,AVX2
+VPMOVZXBQ ymmreg,mem32 [rm: vex.256.66.0f38 32 /r] FUTURE,AVX2
+VPMOVZXBQ ymmreg,xmmreg [rm: vex.256.66.0f38 32 /r] FUTURE,AVX2
+VPMOVZXWD ymmreg,xmmrm128 [rm: vex.256.66.0f38 33 /r] FUTURE,AVX2
+VPMOVZXWQ ymmreg,mem64 [rm: vex.256.66.0f38 34 /r] FUTURE,AVX2
+VPMOVZXWQ ymmreg,xmmreg [rm: vex.256.66.0f38 34 /r] FUTURE,AVX2
+VPMOVZXDQ ymmreg,xmmrm128 [rm: vex.256.66.0f38 35 /r] FUTURE,AVX2
+VPMULDQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 28 /r] FUTURE,AVX2
+VPMULHRSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 0b /r] FUTURE,AVX2
+VPMULHUW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f e4 /r] FUTURE,AVX2
+VPMULHW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f e5 /r] FUTURE,AVX2
+VPMULLW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f d5 /r] FUTURE,AVX2
+VPMULLD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 40 /r] FUTURE,AVX2
+VPMULUDQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f f4 /r] FUTURE,AVX2
+VPOR ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f eb /r] FUTURE,AVX2
+VPSADBW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f f6 /r] FUTURE,AVX2
+VPSHUFB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 00 /r] FUTURE,AVX2
+VPSHUFD ymmreg,ymmrm256,imm8 [rmi: vex.256.66.0f 70 /r ib] FUTURE,AVX2
+VPSHUFHW ymmreg,ymmrm256,imm8 [rmi: vex.256.f3.0f 70 /r ib] FUTURE,AVX2
+VPSHUFLW ymmreg,ymmrm256,imm8 [rmi: vex.256.f2.0f 70 /r ib] FUTURE,AVX2
+VPSIGNB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 08 /r] FUTURE,AVX2
+VPSIGNW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 09 /r] FUTURE,AVX2
+VPSIGND ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38 0a /r] FUTURE,AVX2
+VPSLLDQ ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 73 /7 ib] FUTURE,AVX2
+VPSLLW ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f f1 /r] FUTURE,AVX2
+VPSLLW ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 71 /6 ib] FUTURE,AVX2
+VPSLLD ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f f2 /r] FUTURE,AVX2
+VPSLLD ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 72 /6 ib] FUTURE,AVX2
+VPSLLQ ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f f3 /r] FUTURE,AVX2
+VPSLLQ ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 73 /6 ib] FUTURE,AVX2
+VPSRAW ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f e1 /r] FUTURE,AVX2
+VPSRAW ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 71 /4 ib] FUTURE,AVX2
+VPSRAD ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f e2 /r] FUTURE,AVX2
+VPSRAD ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 72 /4 ib] FUTURE,AVX2
+VPSRLDQ ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 73 /3 ib] FUTURE,AVX2
+VPSRLW ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f d1 /r] FUTURE,AVX2
+VPSRLW ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 71 /2 ib] FUTURE,AVX2
+VPSRLD ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f d2 /r] FUTURE,AVX2
+VPSRLD ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f 72 /2 ib] FUTURE,AVX2
+VPSRLQ ymmreg,ymmreg*,xmmrm128 [rvm: vex.nds.256.66.0f d3 /r] FUTURE,AVX2
+VPSRLQ ymmreg,ymmreg*,imm8 [vmi: vex.ndd.256.66.0f.wig 73 /2 ib] FUTURE,AVX2
+VPSUBB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f f8 /r] FUTURE,AVX2
+VPSUBW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f f9 /r] FUTURE,AVX2
+VPSUBD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f fa /r] FUTURE,AVX2
+VPSUBQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f fb /r] FUTURE,AVX2
+VPSUBSB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f e8 /r] FUTURE,AVX2
+VPSUBSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f e9 /r] FUTURE,AVX2
+VPSUBUSB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f d8 /r] FUTURE,AVX2
+VPSUBUSW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f d9 /r] FUTURE,AVX2
+VPUNPCKHBW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 68 /r] FUTURE,AVX2
+VPUNPCKHWD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 69 /r] FUTURE,AVX2
+VPUNPCKHDQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 6a /r] FUTURE,AVX2
+VPUNPCKHQDQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 6d /r] FUTURE,AVX2
+VPUNPCKLBW ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 60 /r] FUTURE,AVX2
+VPUNPCKLWD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 61 /r] FUTURE,AVX2
+VPUNPCKLDQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 62 /r] FUTURE,AVX2
+VPUNPCKLQDQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f 6c /r] FUTURE,AVX2
+VPXOR ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f ef /r] FUTURE,AVX2
+VMOVNTDQA ymmreg,mem256 [rm: vex.256.66.0f38 2a /r] FUTURE,AVX2
+VBROADCASTSS xmmreg,xmmreg [rm: vex.128.66.0f38.w0 18 /r] FUTURE,AVX2
+VBROADCASTSS ymmreg,xmmreg [rm: vex.256.66.0f38.w0 18 /r] FUTURE,AVX2
+VBROADCASTSD ymmreg,xmmreg [rm: vex.256.66.0f38.w0 19 /r] FUTURE,AVX2
+VBROADCASTI128 ymmreg,mem128 [rm: vex.256.66.0f38.w0 5a /r] FUTURE,AVX2
+VPBLENDD xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a.w0 02 /r ib] FUTURE,AVX2
+VPBLENDD ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a.w0 02 /r ib] FUTURE,AVX2
+VPBROADCASTB xmmreg,mem8 [rm: vex.128.66.0f38.w0 78 /r] FUTURE,AVX2
+VPBROADCASTB xmmreg,xmmreg [rm: vex.128.66.0f38.w0 78 /r] FUTURE,AVX2
+VPBROADCASTB ymmreg,mem8 [rm: vex.256.66.0f38.w0 78 /r] FUTURE,AVX2
+VPBROADCASTB ymmreg,xmmreg [rm: vex.256.66.0f38.w0 78 /r] FUTURE,AVX2
+VPBROADCASTW xmmreg,mem16 [rm: vex.128.66.0f38.w0 79 /r] FUTURE,AVX2
+VPBROADCASTW xmmreg,xmmreg [rm: vex.128.66.0f38.w0 79 /r] FUTURE,AVX2
+VPBROADCASTW ymmreg,mem16 [rm: vex.256.66.0f38.w0 79 /r] FUTURE,AVX2
+VPBROADCASTW ymmreg,xmmreg [rm: vex.256.66.0f38.w0 79 /r] FUTURE,AVX2
+VPBROADCASTD xmmreg,mem32 [rm: vex.128.66.0f38.w0 58 /r] FUTURE,AVX2
+VPBROADCASTD xmmreg,xmmreg [rm: vex.128.66.0f38.w0 58 /r] FUTURE,AVX2
+VPBROADCASTD ymmreg,mem32 [rm: vex.256.66.0f38.w0 58 /r] FUTURE,AVX2
+VPBROADCASTD ymmreg,xmmreg [rm: vex.256.66.0f38.w0 58 /r] FUTURE,AVX2
+VPBROADCASTQ xmmreg,mem64 [rm: vex.128.66.0f38.w0 59 /r] FUTURE,AVX2
+VPBROADCASTQ xmmreg,xmmreg [rm: vex.128.66.0f38.w0 59 /r] FUTURE,AVX2
+VPBROADCASTQ ymmreg,mem64 [rm: vex.256.66.0f38.w0 59 /r] FUTURE,AVX2
+VPBROADCASTQ ymmreg,xmmreg [rm: vex.256.66.0f38.w0 59 /r] FUTURE,AVX2
+
+VPERMD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 36 /r] FUTURE,AVX2
+VPERMPD ymmreg,ymmrm256,imm8 [rmi: vex.256.66.0f3a.w1 01 /r ib] FUTURE,AVX2
+VPERMPS ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 16 /r] FUTURE,AVX2
+VPERMQ ymmreg,ymmrm256,imm8 [rmi: vex.256.66.0f3a.w1 00 /r ib] FUTURE,AVX2
+VPERM2I128 ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a.w0 46 /r ib] FUTURE,AVX2
+VEXTRACTI128 xmmrm128,ymmreg,imm8 [mri: vex.256.66.0f3a.w0 39 /r ib] FUTURE,AVX2
+
+VINSERTI128 ymmreg,ymmreg*,xmmrm128,imm8 [rvmi: vex.nds.256.66.0f3a.w0 38 /r ib] FUTURE,AVX2
+VPMASKMOVD xmmreg,xmmreg*,mem128 [rvm: vex.nds.128.66.0f38.w0 8c /r] FUTURE,AVX2
+VPMASKMOVD ymmreg,ymmreg*,mem256 [rvm: vex.nds.256.66.0f38.w0 8c /r] FUTURE,AVX2
+VPMASKMOVQ xmmreg,xmmreg*,mem128 [rvm: vex.nds.128.66.0f38.w1 8c /r] FUTURE,AVX2
+VPMASKMOVQ ymmreg,ymmreg*,mem256 [rvm: vex.nds.256.66.0f38.w1 8c /r] FUTURE,AVX2
+
+VPMASKMOVD mem128,xmmreg*,xmmreg [mvr: vex.nds.128.66.0f38.w0 8e /r] FUTURE,AVX2
+VPMASKMOVD mem256,ymmreg*,ymmreg [mvr: vex.nds.256.66.0f38.w0 8e /r] FUTURE,AVX2
+VPMASKMOVQ mem128,xmmreg*,xmmreg [mvr: vex.nds.128.66.0f38.w1 8e /r] FUTURE,AVX2
+VPMASKMOVQ mem256,ymmreg*,ymmreg [mvr: vex.nds.256.66.0f38.w1 8e /r] FUTURE,AVX2
+
+VPSLLVD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w0 47 /r] FUTURE,AVX2
+VPSLLVQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w1 47 /r] FUTURE,AVX2
+VPSLLVD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 47 /r] FUTURE,AVX2
+VPSLLVQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w1 47 /r] FUTURE,AVX2
+
+VPSRAVD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w0 46 /r] FUTURE,AVX2
+VPSRAVD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 46 /r] FUTURE,AVX2
+
+VPSRLVD xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w0 45 /r] FUTURE,AVX2
+VPSRLVQ xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w1 45 /r] FUTURE,AVX2
+VPSRLVD ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 45 /r] FUTURE,AVX2
+VPSRLVQ ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w1 45 /r] FUTURE,AVX2
+
+VGATHERDPD xmmreg,xmem64,xmmreg [rmv: vm32x vex.dds.128.66.0f38.w1 92 /r] FUTURE,AVX2
+VGATHERQPD xmmreg,xmem64,xmmreg [rmv: vm64x vex.dds.128.66.0f38.w1 93 /r] FUTURE,AVX2
+VGATHERDPD ymmreg,xmem64,ymmreg [rmv: vm32x vex.dds.256.66.0f38.w1 92 /r] FUTURE,AVX2
+VGATHERQPD ymmreg,ymem64,ymmreg [rmv: vm64y vex.dds.256.66.0f38.w1 93 /r] FUTURE,AVX2
+
+VGATHERDPS xmmreg,xmem32,xmmreg [rmv: vm32x vex.dds.128.66.0f38.w0 92 /r] FUTURE,AVX2
+VGATHERQPS xmmreg,xmem32,xmmreg [rmv: vm64x vex.dds.128.66.0f38.w0 93 /r] FUTURE,AVX2
+VGATHERDPS ymmreg,ymem32,ymmreg [rmv: vm32y vex.dds.256.66.0f38.w0 92 /r] FUTURE,AVX2
+VGATHERQPS xmmreg,ymem32,xmmreg [rmv: vm64y vex.dds.256.66.0f38.w0 93 /r] FUTURE,AVX2
+
+VPGATHERDD xmmreg,xmem32,xmmreg [rmv: vm32x vex.dds.128.66.0f38.w0 90 /r] FUTURE,AVX2
+VPGATHERQD xmmreg,xmem32,xmmreg [rmv: vm64x vex.dds.128.66.0f38.w0 91 /r] FUTURE,AVX2
+VPGATHERDD ymmreg,ymem32,ymmreg [rmv: vm32y vex.dds.256.66.0f38.w0 90 /r] FUTURE,AVX2
+VPGATHERQD xmmreg,ymem32,xmmreg [rmv: vm64y vex.dds.256.66.0f38.w0 91 /r] FUTURE,AVX2
+
+VPGATHERDQ xmmreg,xmem64,xmmreg [rmv: vm32x vex.dds.128.66.0f38.w1 90 /r] FUTURE,AVX2
+VPGATHERQQ xmmreg,xmem64,xmmreg [rmv: vm64x vex.dds.128.66.0f38.w1 91 /r] FUTURE,AVX2
+VPGATHERDQ ymmreg,xmem64,ymmreg [rmv: vm32x vex.dds.256.66.0f38.w1 90 /r] FUTURE,AVX2
+VPGATHERQQ ymmreg,ymem64,ymmreg [rmv: vm64y vex.dds.256.66.0f38.w1 91 /r] FUTURE,AVX2
+
+;# Intel Transactional Synchronization Extensions (TSX)
+XABORT imm [i: c6 f8 ib] FUTURE,RTM
+XABORT imm8 [i: c6 f8 ib] FUTURE,RTM
+XBEGIN imm [i: odf c7 f8 rel] FUTURE,RTM
+XBEGIN imm|near [i: odf c7 f8 rel] FUTURE,RTM,ND
+XBEGIN imm16 [i: o16 c7 f8 rel] FUTURE,RTM,NOLONG
+XBEGIN imm16|near [i: o16 c7 f8 rel] FUTURE,RTM,NOLONG,ND
+XBEGIN imm32 [i: o32 c7 f8 rel] FUTURE,RTM,NOLONG
+XBEGIN imm32|near [i: o32 c7 f8 rel] FUTURE,RTM,NOLONG,ND
+XBEGIN imm64 [i: o64nw c7 f8 rel] FUTURE,RTM,LONG
+XBEGIN imm64|near [i: o64nw c7 f8 rel] FUTURE,RTM,LONG,ND
+XEND void [ 0f 01 d5] FUTURE,RTM
+XTEST void [ 0f 01 d6] FUTURE,HLE,RTM
+
+;# Intel BMI1 and BMI2 instructions, AMD TBM instructions
+;
+; based on pub number 319433-011 dated July 2011
+;
+ANDN reg32,reg32,rm32 [rvm: vex.nds.lz.0f38.w0 f2 /r] FUTURE,BMI1
+ANDN reg64,reg64,rm64 [rvm: vex.nds.lz.0f38.w1 f2 /r] LONG,FUTURE,BMI1
+BEXTR reg32,rm32,reg32 [rmv: vex.nds.lz.0f38.w0 f7 /r] FUTURE,BMI1
+BEXTR reg64,rm64,reg64 [rmv: vex.nds.lz.0f38.w1 f7 /r] LONG,FUTURE,BMI1
+BEXTR reg32,rm32,imm32 [rmi: xop.m10.lz.w0 10 /r id] FUTURE,TBM
+BEXTR reg64,rm64,imm32 [rmi: xop.m10.lz.w1 10 /r id] LONG,FUTURE,TBM
+BLCI reg32,rm32 [vm: xop.ndd.lz.m9.w0 02 /6] FUTURE,TBM
+BLCI reg64,rm64 [vm: xop.ndd.lz.m9.w1 02 /6] LONG,FUTURE,TBM
+BLCIC reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /5] FUTURE,TBM
+BLCIC reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /5] LONG,FUTURE,TBM
+BLSI reg32,rm32 [vm: vex.ndd.lz.0f38.w0 f3 /3] FUTURE,BMI1
+BLSI reg64,rm64 [vm: vex.ndd.lz.0f38.w1 f3 /3] LONG,FUTURE,BMI1
+BLSIC reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /6] FUTURE,TBM
+BLSIC reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /6] LONG,FUTURE,TBM
+BLCFILL reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /1] FUTURE,TBM
+BLCFILL reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /1] LONG,FUTURE,TBM
+BLSFILL reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /2] FUTURE,TBM
+BLSFILL reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /2] LONG,FUTURE,TBM
+BLCMSK reg32,rm32 [vm: xop.ndd.lz.m9.w0 02 /1] FUTURE,TBM
+BLCMSK reg64,rm64 [vm: xop.ndd.lz.m9.w1 02 /1] LONG,FUTURE,TBM
+BLSMSK reg32,rm32 [vm: vex.ndd.lz.0f38.w0 f3 /2] FUTURE,BMI1
+BLSMSK reg64,rm64 [vm: vex.ndd.lz.0f38.w1 f3 /2] LONG,FUTURE,BMI1
+BLSR reg32,rm32 [vm: vex.ndd.lz.0f38.w0 f3 /1] FUTURE,BMI1
+BLSR reg64,rm64 [vm: vex.ndd.lz.0f38.w1 f3 /1] LONG,FUTURE,BMI1
+BLCS reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /3] FUTURE,TBM
+BLCS reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /3] LONG,FUTURE,TBM
+BZHI reg32,rm32,reg32 [rmv: vex.nds.lz.0f38.w0 f5 /r] FUTURE,BMI2
+BZHI reg64,rm64,reg64 [rmv: vex.nds.lz.0f38.w1 f5 /r] LONG,FUTURE,BMI2
+MULX reg32,reg32,rm32 [rvm: vex.ndd.lz.f2.0f38.w0 f6 /r] FUTURE,BMI2
+MULX reg64,reg64,rm64 [rvm: vex.ndd.lz.f2.0f38.w1 f6 /r] LONG,FUTURE,BMI2
+PDEP reg32,reg32,rm32 [rvm: vex.nds.lz.f2.0f38.w0 f5 /r] FUTURE,BMI2
+PDEP reg64,reg64,rm64 [rvm: vex.nds.lz.f2.0f38.w1 f5 /r] LONG,FUTURE,BMI2
+PEXT reg32,reg32,rm32 [rvm: vex.nds.lz.f3.0f38.w0 f5 /r] FUTURE,BMI2
+PEXT reg64,reg64,rm64 [rvm: vex.nds.lz.f3.0f38.w1 f5 /r] LONG,FUTURE,BMI2
+RORX reg32,rm32,imm8 [rmi: vex.lz.f2.0f3a.w0 f0 /r ib] FUTURE,BMI2
+RORX reg64,rm64,imm8 [rmi: vex.lz.f2.0f3a.w1 f0 /r ib] LONG,FUTURE,BMI2
+SARX reg32,rm32,reg32 [rmv: vex.nds.lz.f3.0f38.w0 f7 /r] FUTURE,BMI2
+SARX reg64,rm64,reg64 [rmv: vex.nds.lz.f3.0f38.w1 f7 /r] LONG,FUTURE,BMI2
+SHLX reg32,rm32,reg32 [rmv: vex.nds.lz.66.0f38.w0 f7 /r] FUTURE,BMI2
+SHLX reg64,rm64,reg64 [rmv: vex.nds.lz.66.0f38.w1 f7 /r] LONG,FUTURE,BMI2
+SHRX reg32,rm32,reg32 [rmv: vex.nds.lz.f2.0f38.w0 f7 /r] FUTURE,BMI2
+SHRX reg64,rm64,reg64 [rmv: vex.nds.lz.f2.0f38.w1 f7 /r] LONG,FUTURE,BMI2
+TZCNT reg16,rm16 [rm: o16 f3i 0f bc /r] FUTURE,BMI1
+TZCNT reg32,rm32 [rm: o32 f3i 0f bc /r] FUTURE,BMI1
+TZCNT reg64,rm64 [rm: o64 f3i 0f bc /r] LONG,FUTURE,BMI1
+TZMSK reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /4] FUTURE,TBM
+TZMSK reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /4] LONG,FUTURE,TBM
+T1MSKC reg32,rm32 [vm: xop.ndd.lz.m9.w0 01 /7] FUTURE,TBM
+T1MSKC reg64,rm64 [vm: xop.ndd.lz.m9.w1 01 /7] LONG,FUTURE,TBM
+
+PREFETCHWT1 mem8 [m: 0f 0d /2 ] PREFETCHWT1,FUTURE
+
+;# Intel Memory Protection Extensions (MPX)
+BNDMK bndreg,mem [rm: f3 0f 1b /r ] MPX,MIB,FUTURE
+BNDCL bndreg,mem [rm: f3 0f 1a /r ] MPX,FUTURE
+BNDCL bndreg,reg32 [rm: f3 0f 1a /r ] MPX,NOLONG,FUTURE
+BNDCL bndreg,reg64 [rm: o64nw f3 0f 1a /r ] MPX,LONG,FUTURE
+BNDCU bndreg,mem [rm: f2 0f 1a /r ] MPX,FUTURE
+BNDCU bndreg,reg32 [rm: f2 0f 1a /r ] MPX,NOLONG,FUTURE
+BNDCU bndreg,reg64 [rm: o64nw f2 0f 1a /r ] MPX,LONG,FUTURE
+BNDCN bndreg,mem [rm: f2 0f 1b /r ] MPX,FUTURE
+BNDCN bndreg,reg32 [rm: f2 0f 1b /r ] MPX,NOLONG,FUTURE
+BNDCN bndreg,reg64 [rm: o64nw f2 0f 1b /r ] MPX,LONG,FUTURE
+BNDMOV bndreg,bndreg [rm: 66 0f 1a /r ] MPX,FUTURE
+BNDMOV bndreg,mem [rm: 66 0f 1a /r ] MPX,FUTURE
+BNDMOV bndreg,bndreg [mr: 66 0f 1b /r ] MPX,FUTURE
+BNDMOV mem,bndreg [mr: 66 0f 1b /r ] MPX,FUTURE
+BNDLDX bndreg,mem [rm: 0f 1a /r ] MPX,MIB,FUTURE
+BNDLDX bndreg,mem,reg32 [rmx: 0f 1a /r ] MPX,MIB,NOLONG,FUTURE
+BNDLDX bndreg,mem,reg64 [rmx: 0f 1a /r ] MPX,MIB,LONG,FUTURE
+BNDSTX mem,bndreg [mr: 0f 1b /r ] MPX,MIB,FUTURE
+BNDSTX mem,reg32,bndreg [mxr: 0f 1b /r ] MPX,MIB,NOLONG,FUTURE
+BNDSTX mem,reg64,bndreg [mxr: 0f 1b /r ] MPX,MIB,LONG,FUTURE
+BNDSTX mem,bndreg,reg32 [mrx: 0f 1b /r ] MPX,MIB,NOLONG,FUTURE
+BNDSTX mem,bndreg,reg64 [mrx: 0f 1b /r ] MPX,MIB,LONG,FUTURE
+
+;# Intel SHA acceleration instructions
+SHA1MSG1 xmmreg,xmmrm128 [rm: 0f 38 c9 /r ] SHA,FUTURE
+SHA1MSG2 xmmreg,xmmrm128 [rm: 0f 38 ca /r ] SHA,FUTURE
+SHA1NEXTE xmmreg,xmmrm128 [rm: 0f 38 c8 /r ] SHA,FUTURE
+SHA1RNDS4 xmmreg,xmmrm128,imm8 [rmi: 0f 3a cc /r ib ] SHA,FUTURE
+SHA256MSG1 xmmreg,xmmrm128 [rm: 0f 38 cc /r ] SHA,FUTURE
+SHA256MSG2 xmmreg,xmmrm128 [rm: 0f 38 cd /r ] SHA,FUTURE
+SHA256RNDS2 xmmreg,xmmrm128,xmm0 [rm-: 0f 38 cb /r ] SHA,FUTURE
+SHA256RNDS2 xmmreg,xmmrm128 [rm: 0f 38 cb /r ] SHA,FUTURE
+
+;# AVX no exception conversions
+; Must precede AVX-512 versions
+VBCSTNEBF16PS xmmreg,mem16 [rm: vex.128.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VBCSTNEBF16PS ymmreg,mem16 [rm: vex.256.f3.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VBCSTNESH2PS xmmreg,mem16 [rm: vex.128.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VBCSTNESH2PS ymmreg,mem16 [rm: vex.256.66.0f38.w0 b1 /r] AVXNECONVERT,FUTURE,LATEVEX,SW
+VCVTNEEBF162PS xmmreg,mem128 [rm: vex.128.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEEBF162PS ymmreg,mem256 [rm: vex.256.f3.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEEPH2PS xmmreg,mem128 [rm: vex.128.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEEPH2PS ymmreg,mem256 [rm: vex.256.66.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEOBF162PS xmmreg,mem128 [rm: vex.128.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEOBF162PS ymmreg,mem256 [rm: vex.256.f2.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEOPH2PS xmmreg,mem128 [rm: vex.128.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEOPH2PS ymmreg,mem256 [rm: vex.256.np.0f38.w0 b0 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+VCVTNEPS2BF16 xmmreg,xmmrm128 [rm: vex.128.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,LATEVEX,SX
+VCVTNEPS2BF16 ymmreg,ymmrm256 [rm: vex.256.f3.0f38.w0 72 /r] AVXNECONVERT,FUTURE,LATEVEX,SY
+
+;# AVX Vector Neural Network Instructions
+; Must precede AVX-512 versions
+VPDPBSSD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSSD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBSSDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSSDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f2.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBSUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBSUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBSUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.f3.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBUUD xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBUUD ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 50 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+VPDPBUUDS xmmreg,xmmreg,xmmrm128 [rvm: vex.128.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SX
+VPDPBUUDS ymmreg,ymmreg,ymmrm256 [rvm: vex.256.np.0f38.w0 51 /r] AVXVNNIINT8,FUTURE,LATEVEX,SY
+
+;# AVX Integer Fused Multiply-Add
+; Must precede AVX-512 versions
+VPMADD52HUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,LATEVEX,SX
+VPMADD52HUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b5 /r] AVXIFMA,FUTURE,LATEVEX,SY
+VPMADD52LUQ xmmreg,xmmreg,xmmrm128 [rvm: vex.128.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,LATEVEX,SX
+VPMADD52LUQ ymmreg,ymmreg,ymmrm256 [rvm: vex.256.66.0f38.w1 b4 /r] AVXIFMA,FUTURE,LATEVEX,SY
+
+;# AVX-512 mask register instructions
+KADDB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 4a /r ] FUTURE
+KADDD kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 4a /r ] FUTURE
+KADDQ kreg,kreg,kreg [rvm: vex.nds.l1.0f.w1 4a /r ] FUTURE
+KADDW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 4a /r ] FUTURE
+KANDB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 41 /r ] FUTURE
+KANDD kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 41 /r ] FUTURE
+KANDNB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 42 /r ] FUTURE
+KANDND kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 42 /r ] FUTURE
+KANDNQ kreg,kreg,kreg [rvm: vex.nds.l1.0f.w1 42 /r ] FUTURE
+KANDNW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 42 /r ] FUTURE
+KANDQ kreg,kreg,kreg [rvm: vex.nds.l1.0f.w1 41 /r ] FUTURE
+KANDW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 41 /r ] FUTURE
+KMOVB kreg,krm8 [rm: vex.l0.66.0f.w0 90 /r ] FUTURE
+KMOVB mem8,kreg [mr: vex.l0.66.0f.w0 91 /r ] FUTURE
+KMOVB kreg,reg32 [rm: vex.l0.66.0f.w0 92 /r ] FUTURE
+KMOVB kreg,reg8 [rm: vex.l0.66.0f.w0 92 nohi /r ] FUTURE,ND
+KMOVB reg32,kreg [rm: vex.l0.66.0f.w0 93 /r ] FUTURE
+KMOVD kreg,krm32 [rm: vex.l0.66.0f.w1 90 /r ] FUTURE
+KMOVD mem32,kreg [mr: vex.l0.66.0f.w1 91 /r ] FUTURE
+KMOVD kreg,reg32 [rm: vex.l0.f2.0f.w0 92 /r ] FUTURE
+KMOVD reg32,kreg [rm: vex.l0.f2.0f.w0 93 /r ] FUTURE
+KMOVQ kreg,krm64 [rm: vex.l0.0f.w1 90 /r ] FUTURE
+KMOVQ mem64,kreg [mr: vex.l0.0f.w1 91 /r ] FUTURE
+KMOVQ kreg,reg64 [rm: vex.l0.f2.0f.w1 92 /r ] FUTURE
+KMOVQ reg64,kreg [rm: vex.l0.f2.0f.w1 93 /r ] FUTURE
+KMOVW kreg,krm16 [rm: vex.l0.0f.w0 90 /r ] FUTURE
+KMOVW mem16,kreg [mr: vex.l0.0f.w0 91 /r ] FUTURE
+KMOVW kreg,reg32 [rm: vex.l0.0f.w0 92 /r ] FUTURE
+KMOVW kreg,reg16 [rm: vex.l0.0f.w0 92 /r ] FUTURE,ND
+KMOVW reg32,kreg [rm: vex.l0.0f.w0 93 /r ] FUTURE
+KNOTB kreg,kreg [rm: vex.l0.66.0f.w0 44 /r ] FUTURE
+KNOTD kreg,kreg [rm: vex.l0.66.0f.w1 44 /r ] FUTURE
+KNOTQ kreg,kreg [rm: vex.l0.0f.w1 44 /r ] FUTURE
+KNOTW kreg,kreg [rm: vex.l0.0f.w0 44 /r ] FUTURE
+KORB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 45 /r ] FUTURE
+KORD kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 45 /r ] FUTURE
+KORQ kreg,kreg,kreg [rvm: vex.nds.l1.0f.w1 45 /r ] FUTURE
+KORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 45 /r ] FUTURE
+KORTESTB kreg,kreg [rm: vex.l0.66.0f.w0 98 /r ] FUTURE
+KORTESTD kreg,kreg [rm: vex.l0.66.0f.w1 98 /r ] FUTURE
+KORTESTQ kreg,kreg [rm: vex.l0.0f.w1 98 /r ] FUTURE
+KORTESTW kreg,kreg [rm: vex.l0.0f.w0 98 /r ] FUTURE
+KSHIFTLB kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 32 /r ib ] FUTURE
+KSHIFTLD kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 33 /r ib ] FUTURE
+KSHIFTLQ kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 33 /r ib ] FUTURE
+KSHIFTLW kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 32 /r ib ] FUTURE
+KSHIFTRB kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 30 /r ib ] FUTURE
+KSHIFTRD kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 31 /r ib ] FUTURE
+KSHIFTRQ kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 31 /r ib ] FUTURE
+KSHIFTRW kreg,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 30 /r ib ] FUTURE
+KTESTB kreg,kreg [rm: vex.l0.66.0f.w0 99 /r ] FUTURE
+KTESTD kreg,kreg [rm: vex.l0.66.0f.w1 99 /r ] FUTURE
+KTESTQ kreg,kreg [rm: vex.l0.0f.w1 99 /r ] FUTURE
+KTESTW kreg,kreg [rm: vex.l0.0f.w0 99 /r ] FUTURE
+KUNPCKBW kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 4b /r ] FUTURE
+KUNPCKDQ kreg,kreg,kreg [rvm: vex.nds.l1.0f.w1 4b /r ] FUTURE
+KUNPCKWD kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 4b /r ] FUTURE
+KXNORB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 46 /r ] FUTURE
+KXNORD kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 46 /r ] FUTURE
+KXNORQ kreg,kreg,kreg [rvm: vex.nds.l1.0f.w1 46 /r ] FUTURE
+KXNORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 46 /r ] FUTURE
+KXORB kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 47 /r ] FUTURE
+KXORD kreg,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 47 /r ] FUTURE
+KXORQ kreg,kreg,kreg [rvm: vex.nds.l1.0f.w1 47 /r ] FUTURE
+KXORW kreg,kreg,kreg [rvm: vex.nds.l1.0f.w0 47 /r ] FUTURE
+
+;# AVX-512 mask register instructions (aliases requiring explicit size support)
+KADD kreg8,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 4a /r ] FUTURE,ND,SM
+KADD kreg32,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 4a /r ] FUTURE,ND,SM
+KADD kreg64,kreg,kreg [rvm: vex.nds.l1.0f.w1 4a /r ] FUTURE,ND,SM
+KADD kreg16,kreg,kreg [rvm: vex.nds.l1.0f.w0 4a /r ] FUTURE,ND,SM
+KAND kreg8,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 41 /r ] FUTURE,ND,SM
+KAND kreg32,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 41 /r ] FUTURE,ND,SM
+KANDN kreg64,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 42 /r ] FUTURE,ND,SM
+KANDN kreg16,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 42 /r ] FUTURE,ND,SM
+KANDN kreg8,kreg,kreg [rvm: vex.nds.l1.0f.w1 42 /r ] FUTURE,ND,SM
+KANDN kreg32,kreg,kreg [rvm: vex.nds.l1.0f.w0 42 /r ] FUTURE,ND,SM
+KAND kreg64,kreg,kreg [rvm: vex.nds.l1.0f.w1 41 /r ] FUTURE,ND,SM
+KAND kreg16,kreg,kreg [rvm: vex.nds.l1.0f.w0 41 /r ] FUTURE,ND,SM
+KMOV kreg8,krm8 [rm: vex.l0.66.0f.w0 90 /r ] FUTURE,ND,SM
+KMOV mem8,kreg8 [mr: vex.l0.66.0f.w0 91 /r ] FUTURE,ND,SB,SM
+KMOV kreg8,reg32 [rm: vex.l0.66.0f.w0 92 /r ] FUTURE,ND,SX
+KMOV kreg8,reg8 [rm: vex.l0.66.0f.w0 92 /r ] FUTURE,ND,SM
+KMOV reg32,kreg8 [rm: vex.l0.66.0f.w0 93 /r ] FUTURE,ND,SX
+KMOV kreg32,krm32 [rm: vex.l0.66.0f.w1 90 /r ] FUTURE,ND,SM
+KMOV mem32,kreg32 [mr: vex.l0.66.0f.w1 91 /r ] FUTURE,ND,SM
+KMOV kreg32,reg32 [rm: vex.l0.f2.0f.w0 92 /r ] FUTURE,ND,SM
+KMOV reg32,kreg32 [rm: vex.l0.f2.0f.w0 93 /r ] FUTURE,ND,SM
+KMOV kreg64,krm64 [rm: vex.l0.0f.w1 90 /r ] FUTURE,ND,SM
+KMOV mem64,kreg64 [mr: vex.l0.0f.w1 91 /r ] FUTURE,ND,SM
+KMOV kreg64,reg64 [rm: vex.l0.f2.0f.w1 92 /r ] FUTURE,ND,SM
+KMOV reg64,kreg64 [rm: vex.l0.f2.0f.w1 93 /r ] FUTURE,ND,SM
+KMOV kreg16,krm16 [rm: vex.l0.0f.w0 90 /r ] FUTURE,ND,SM
+KMOV mem16,kreg16 [mr: vex.l0.0f.w0 91 /r ] FUTURE,ND,SM
+KMOV kreg16,reg32 [rm: vex.l0.0f.w0 92 /r ] FUTURE,ND,SX
+KMOV reg32,kreg16 [rm: vex.l0.0f.w0 93 /r ] FUTURE,ND,SX
+KMOV kreg16,reg32 [rm: vex.l0.0f.w0 92 /r ] FUTURE,ND,SX
+KMOV kreg16,reg16 [rm: vex.l0.0f.w0 92 /r ] FUTURE,ND,SM
+KNOT kreg8,kreg8 [rm: vex.l0.66.0f.w0 44 /r ] FUTURE,ND,SM
+KNOT kreg32,kreg32 [rm: vex.l0.66.0f.w1 44 /r ] FUTURE,ND,SM
+KNOT kreg64,kreg64 [rm: vex.l0.0f.w1 44 /r ] FUTURE,ND,SM
+KNOT kreg16,kreg16 [rm: vex.l0.0f.w0 44 /r ] FUTURE,ND,SM
+KOR kreg8,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 45 /r ] FUTURE,ND,SM
+KOR kreg32,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 45 /r ] FUTURE,ND,SM
+KOR kreg64,kreg,kreg [rvm: vex.nds.l1.0f.w1 45 /r ] FUTURE,ND,SM
+KOR kreg16,kreg,kreg [rvm: vex.nds.l1.0f.w0 45 /r ] FUTURE,ND,SM
+KORTEST kreg8,kreg [rm: vex.l0.66.0f.w0 98 /r ] FUTURE,ND,SM
+KORTEST kreg32,kreg [rm: vex.l0.66.0f.w1 98 /r ] FUTURE,ND,SM
+KORTEST kreg64,kreg [rm: vex.l0.0f.w1 98 /r ] FUTURE,ND,SM
+KORTEST kreg16,kreg [rm: vex.l0.0f.w0 98 /r ] FUTURE,ND,SM
+KSHIFTL kreg8,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 32 /r ib ] FUTURE,ND,SM2
+KSHIFTL kreg32,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 33 /r ib ] FUTURE,ND,SM2
+KSHIFTL kreg64,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 33 /r ib ] FUTURE,ND,SM2
+KSHIFTL kreg16,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 32 /r ib ] FUTURE,ND,SM2
+KSHIFTR kreg8,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 30 /r ib ] FUTURE,ND,SM2
+KSHIFTR kreg32,kreg,imm8 [rmi: vex.l0.66.0f3a.w0 31 /r ib ] FUTURE,ND,SM2
+KSHIFTR kreg64,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 31 /r ib ] FUTURE,ND,SM2
+KSHIFTR kreg16,kreg,imm8 [rmi: vex.l0.66.0f3a.w1 30 /r ib ] FUTURE,ND,SM2
+KTEST kreg8,kreg [rm: vex.l0.66.0f.w0 99 /r ] FUTURE,ND,SM
+KTEST kreg32,kreg [rm: vex.l0.66.0f.w1 99 /r ] FUTURE,ND,SM
+KTEST kreg64,kreg [rm: vex.l0.0f.w1 99 /r ] FUTURE,ND,SM
+KTEST kreg16,kreg [rm: vex.l0.0f.w0 99 /r ] FUTURE,ND,SM
+KUNPCK kreg16,kreg8,kreg8 [rvm: vex.nds.l1.66.0f.w0 4b /r ] FUTURE,ND
+KUNPCK kreg64,kreg32,kreg32 [rvm: vex.nds.l1.0f.w1 4b /r ] FUTURE,ND
+KUNPCK kreg32,kreg16,kreg16 [rvm: vex.nds.l1.0f.w0 4b /r ] FUTURE,ND
+KXNOR kreg8,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 46 /r ] FUTURE,ND,SM
+KXNOR kreg32,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 46 /r ] FUTURE,ND,SM
+KXNOR kreg64,kreg,kreg [rvm: vex.nds.l1.0f.w1 46 /r ] FUTURE,ND,SM
+KXNOR kreg16,kreg,kreg [rvm: vex.nds.l1.0f.w0 46 /r ] FUTURE,ND,SM
+KXOR kreg8,kreg,kreg [rvm: vex.nds.l1.66.0f.w0 47 /r ] FUTURE,ND,SM
+KXOR kreg32,kreg,kreg [rvm: vex.nds.l1.66.0f.w1 47 /r ] FUTURE,ND,SM
+KXOR kreg64,kreg,kreg [rvm: vex.nds.l1.0f.w1 47 /r ] FUTURE,ND,SM
+KXOR kreg16,kreg,kreg [rvm: vex.nds.l1.0f.w0 47 /r ] FUTURE,ND,SM
+
+;# AVX-512 instructions
+VADDPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 58 /r ] AVX512VL,AVX512,FUTURE
+VADDPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 58 /r ] AVX512VL,AVX512,FUTURE
+VADDPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f.w1 58 /r ] AVX512,FUTURE
+VADDPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 58 /r ] AVX512VL,AVX512,FUTURE
+VADDPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 58 /r ] AVX512VL,AVX512,FUTURE
+VADDPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.0f.w0 58 /r ] AVX512,FUTURE
+VADDSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.128.f2.0f.w1 58 /r ] AVX512,FUTURE
+VADDSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.128.f3.0f.w0 58 /r ] AVX512,FUTURE
+VALIGND xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 03 /r ib ] AVX512VL,AVX512,FUTURE
+VALIGND ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 03 /r ib ] AVX512VL,AVX512,FUTURE
+VALIGND zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 03 /r ib ] AVX512,FUTURE
+VALIGNQ xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 03 /r ib ] AVX512VL,AVX512,FUTURE
+VALIGNQ ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 03 /r ib ] AVX512VL,AVX512,FUTURE
+VALIGNQ zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 03 /r ib ] AVX512,FUTURE
+VANDNPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 55 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDNPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 55 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDNPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 55 /r ] AVX512DQ,FUTURE
+VANDNPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 55 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDNPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 55 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDNPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.0f.w0 55 /r ] AVX512DQ,FUTURE
+VANDPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 54 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 54 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 54 /r ] AVX512DQ,FUTURE
+VANDPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 54 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 54 /r ] AVX512VL,AVX512DQ,FUTURE
+VANDPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.0f.w0 54 /r ] AVX512DQ,FUTURE
+VBLENDMPD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 65 /r ] AVX512VL,AVX512,FUTURE
+VBLENDMPD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 65 /r ] AVX512VL,AVX512,FUTURE
+VBLENDMPD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 65 /r ] AVX512,FUTURE
+VBLENDMPS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 65 /r ] AVX512VL,AVX512,FUTURE
+VBLENDMPS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 65 /r ] AVX512VL,AVX512,FUTURE
+VBLENDMPS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 65 /r ] AVX512,FUTURE
+VBROADCASTF32X2 ymmreg|mask|z,xmmrm64 [rm:t2: evex.256.66.0f38.w0 19 /r ] AVX512VL,AVX512DQ,FUTURE
+VBROADCASTF32X2 zmmreg|mask|z,xmmrm64 [rm:t2: evex.512.66.0f38.w0 19 /r ] AVX512DQ,FUTURE
+VBROADCASTF32X4 ymmreg|mask|z,mem128 [rm:t4: evex.256.66.0f38.w0 1a /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTF32X4 zmmreg|mask|z,mem128 [rm:t4: evex.512.66.0f38.w0 1a /r ] AVX512,FUTURE
+VBROADCASTF32X8 zmmreg|mask|z,mem256 [rm:t8: evex.512.66.0f38.w0 1b /r ] AVX512DQ,FUTURE
+VBROADCASTF64X2 ymmreg|mask|z,mem128 [rm:t2: evex.256.66.0f38.w1 1a /r ] AVX512VL,AVX512DQ,FUTURE
+VBROADCASTF64X2 zmmreg|mask|z,mem128 [rm:t2: evex.512.66.0f38.w1 1a /r ] AVX512DQ,FUTURE
+VBROADCASTF64X4 zmmreg|mask|z,mem256 [rm:t4: evex.512.66.0f38.w1 1b /r ] AVX512,FUTURE
+VBROADCASTI32X2 xmmreg|mask|z,xmmrm64 [rm:t2: evex.128.66.0f38.w0 59 /r ] AVX512VL,AVX512DQ,FUTURE
+VBROADCASTI32X2 ymmreg|mask|z,xmmrm64 [rm:t2: evex.256.66.0f38.w0 59 /r ] AVX512VL,AVX512DQ,FUTURE
+VBROADCASTI32X2 zmmreg|mask|z,xmmrm64 [rm:t2: evex.512.66.0f38.w0 59 /r ] AVX512DQ,FUTURE
+VBROADCASTI32X4 ymmreg|mask|z,mem128 [rm:t4: evex.256.66.0f38.w0 5a /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTI32X4 zmmreg|mask|z,mem128 [rm:t4: evex.512.66.0f38.w0 5a /r ] AVX512,FUTURE
+VBROADCASTI32X8 zmmreg|mask|z,mem256 [rm:t8: evex.512.66.0f38.w0 5b /r ] AVX512DQ,FUTURE
+VBROADCASTI64X2 ymmreg|mask|z,mem128 [rm:t2: evex.256.66.0f38.w1 5a /r ] AVX512VL,AVX512DQ,FUTURE
+VBROADCASTI64X2 zmmreg|mask|z,mem128 [rm:t2: evex.512.66.0f38.w1 5a /r ] AVX512DQ,FUTURE
+VBROADCASTI64X4 zmmreg|mask|z,mem256 [rm:t4: evex.512.66.0f38.w1 5b /r ] AVX512,FUTURE
+VBROADCASTSD ymmreg|mask|z,mem64 [rm:t1s: evex.256.66.0f38.w1 19 /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTSD zmmreg|mask|z,mem64 [rm:t1s: evex.512.66.0f38.w1 19 /r ] AVX512,FUTURE
+VBROADCASTSD ymmreg|mask|z,xmmreg [rm: evex.256.66.0f38.w1 19 /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTSD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 19 /r ] AVX512,FUTURE
+VBROADCASTSS xmmreg|mask|z,mem32 [rm:t1s: evex.128.66.0f38.w0 18 /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTSS ymmreg|mask|z,mem32 [rm:t1s: evex.256.66.0f38.w0 18 /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTSS zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE
+VBROADCASTSS xmmreg|mask|z,xmmreg [rm: evex.128.66.0f38.w0 18 /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTSS ymmreg|mask|z,xmmreg [rm: evex.256.66.0f38.w0 18 /r ] AVX512VL,AVX512,FUTURE
+VBROADCASTSS zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 18 /r ] AVX512,FUTURE
+VCMPEQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 00 ] AVX512,FUTURE
+VCMPEQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 00 ] AVX512,FUTURE
+VCMPEQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 00 ] AVX512,FUTURE
+VCMPEQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 00 ] AVX512,FUTURE
+VCMPEQ_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 00 ] AVX512,FUTURE
+VCMPEQ_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 00 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 00 ] AVX512,FUTURE
+VCMPEQ_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 00 ] AVX512,FUTURE
+VCMPEQ_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 00 ] AVX512,FUTURE
+VCMPLTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 01 ] AVX512,FUTURE
+VCMPLTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 01 ] AVX512,FUTURE
+VCMPLTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 01 ] AVX512,FUTURE
+VCMPLTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 01 ] AVX512,FUTURE
+VCMPLT_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 01 ] AVX512,FUTURE
+VCMPLT_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 01 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 01 ] AVX512,FUTURE
+VCMPLT_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 01 ] AVX512,FUTURE
+VCMPLT_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 01 ] AVX512,FUTURE
+VCMPLEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 02 ] AVX512,FUTURE
+VCMPLEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 02 ] AVX512,FUTURE
+VCMPLESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 02 ] AVX512,FUTURE
+VCMPLESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 02 ] AVX512,FUTURE
+VCMPLE_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 02 ] AVX512,FUTURE
+VCMPLE_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 02 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 02 ] AVX512,FUTURE
+VCMPLE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 02 ] AVX512,FUTURE
+VCMPLE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 02 ] AVX512,FUTURE
+VCMPUNORDPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORDPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 03 ] AVX512,FUTURE
+VCMPUNORDPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORDPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 03 ] AVX512,FUTURE
+VCMPUNORDSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 03 ] AVX512,FUTURE
+VCMPUNORDSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 03 ] AVX512,FUTURE
+VCMPUNORD_QPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_QPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_QPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 03 ] AVX512,FUTURE
+VCMPUNORD_QPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_QPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 03 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_QPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 03 ] AVX512,FUTURE
+VCMPUNORD_QSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 03 ] AVX512,FUTURE
+VCMPUNORD_QSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 03 ] AVX512,FUTURE
+VCMPNEQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 04 ] AVX512,FUTURE
+VCMPNEQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 04 ] AVX512,FUTURE
+VCMPNEQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 04 ] AVX512,FUTURE
+VCMPNEQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 04 ] AVX512,FUTURE
+VCMPNEQ_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 04 ] AVX512,FUTURE
+VCMPNEQ_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 04 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 04 ] AVX512,FUTURE
+VCMPNEQ_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 04 ] AVX512,FUTURE
+VCMPNEQ_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 04 ] AVX512,FUTURE
+VCMPNLTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 05 ] AVX512,FUTURE
+VCMPNLTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 05 ] AVX512,FUTURE
+VCMPNLTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 05 ] AVX512,FUTURE
+VCMPNLTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 05 ] AVX512,FUTURE
+VCMPNLT_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 05 ] AVX512,FUTURE
+VCMPNLT_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 05 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 05 ] AVX512,FUTURE
+VCMPNLT_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 05 ] AVX512,FUTURE
+VCMPNLT_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 05 ] AVX512,FUTURE
+VCMPNLEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 06 ] AVX512,FUTURE
+VCMPNLEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 06 ] AVX512,FUTURE
+VCMPNLESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 06 ] AVX512,FUTURE
+VCMPNLESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 06 ] AVX512,FUTURE
+VCMPNLE_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 06 ] AVX512,FUTURE
+VCMPNLE_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 06 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 06 ] AVX512,FUTURE
+VCMPNLE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 06 ] AVX512,FUTURE
+VCMPNLE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 06 ] AVX512,FUTURE
+VCMPORDPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORDPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORDPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 07 ] AVX512,FUTURE
+VCMPORDPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORDPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORDPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 07 ] AVX512,FUTURE
+VCMPORDSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 07 ] AVX512,FUTURE
+VCMPORDSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 07 ] AVX512,FUTURE
+VCMPORD_QPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORD_QPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORD_QPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 07 ] AVX512,FUTURE
+VCMPORD_QPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORD_QPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 07 ] AVX512VL,AVX512,FUTURE
+VCMPORD_QPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 07 ] AVX512,FUTURE
+VCMPORD_QSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 07 ] AVX512,FUTURE
+VCMPORD_QSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 07 ] AVX512,FUTURE
+VCMPEQ_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 08 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 08 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 08 ] AVX512,FUTURE
+VCMPEQ_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 08 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 08 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 08 ] AVX512,FUTURE
+VCMPEQ_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 08 ] AVX512,FUTURE
+VCMPEQ_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 08 ] AVX512,FUTURE
+VCMPNGEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 09 ] AVX512,FUTURE
+VCMPNGEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 09 ] AVX512,FUTURE
+VCMPNGESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 09 ] AVX512,FUTURE
+VCMPNGESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 09 ] AVX512,FUTURE
+VCMPNGE_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 09 ] AVX512,FUTURE
+VCMPNGE_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 09 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 09 ] AVX512,FUTURE
+VCMPNGE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 09 ] AVX512,FUTURE
+VCMPNGE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 09 ] AVX512,FUTURE
+VCMPNGTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0a ] AVX512,FUTURE
+VCMPNGTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0a ] AVX512,FUTURE
+VCMPNGTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0a ] AVX512,FUTURE
+VCMPNGTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0a ] AVX512,FUTURE
+VCMPNGT_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0a ] AVX512,FUTURE
+VCMPNGT_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0a ] AVX512,FUTURE
+VCMPNGT_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0a ] AVX512,FUTURE
+VCMPNGT_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0a ] AVX512,FUTURE
+VCMPFALSEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0b ] AVX512,FUTURE
+VCMPFALSEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0b ] AVX512,FUTURE
+VCMPFALSESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0b ] AVX512,FUTURE
+VCMPFALSESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0b ] AVX512,FUTURE
+VCMPFALSE_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0b ] AVX512,FUTURE
+VCMPFALSE_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0b ] AVX512,FUTURE
+VCMPFALSE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0b ] AVX512,FUTURE
+VCMPFALSE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0b ] AVX512,FUTURE
+VCMPNEQ_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0c ] AVX512,FUTURE
+VCMPNEQ_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0c ] AVX512,FUTURE
+VCMPNEQ_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0c ] AVX512,FUTURE
+VCMPNEQ_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0c ] AVX512,FUTURE
+VCMPGEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0d ] AVX512,FUTURE
+VCMPGEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0d ] AVX512,FUTURE
+VCMPGESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0d ] AVX512,FUTURE
+VCMPGESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0d ] AVX512,FUTURE
+VCMPGE_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0d ] AVX512,FUTURE
+VCMPGE_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0d ] AVX512,FUTURE
+VCMPGE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0d ] AVX512,FUTURE
+VCMPGE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0d ] AVX512,FUTURE
+VCMPGTPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGTPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGTPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0e ] AVX512,FUTURE
+VCMPGTPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGTPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGTPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0e ] AVX512,FUTURE
+VCMPGTSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0e ] AVX512,FUTURE
+VCMPGTSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0e ] AVX512,FUTURE
+VCMPGT_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0e ] AVX512,FUTURE
+VCMPGT_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0e ] AVX512,FUTURE
+VCMPGT_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0e ] AVX512,FUTURE
+VCMPGT_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0e ] AVX512,FUTURE
+VCMPTRUEPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUEPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUEPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0f ] AVX512,FUTURE
+VCMPTRUEPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUEPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUEPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0f ] AVX512,FUTURE
+VCMPTRUESD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0f ] AVX512,FUTURE
+VCMPTRUESS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0f ] AVX512,FUTURE
+VCMPTRUE_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 0f ] AVX512,FUTURE
+VCMPTRUE_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 0f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 0f ] AVX512,FUTURE
+VCMPTRUE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 0f ] AVX512,FUTURE
+VCMPTRUE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 0f ] AVX512,FUTURE
+VCMPEQ_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 10 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 10 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 10 ] AVX512,FUTURE
+VCMPEQ_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 10 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 10 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 10 ] AVX512,FUTURE
+VCMPEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 10 ] AVX512,FUTURE
+VCMPEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 10 ] AVX512,FUTURE
+VCMPLT_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 11 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 11 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 11 ] AVX512,FUTURE
+VCMPLT_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 11 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 11 ] AVX512VL,AVX512,FUTURE
+VCMPLT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 11 ] AVX512,FUTURE
+VCMPLT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 11 ] AVX512,FUTURE
+VCMPLT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 11 ] AVX512,FUTURE
+VCMPLE_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 12 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 12 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 12 ] AVX512,FUTURE
+VCMPLE_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 12 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 12 ] AVX512VL,AVX512,FUTURE
+VCMPLE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 12 ] AVX512,FUTURE
+VCMPLE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 12 ] AVX512,FUTURE
+VCMPLE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 12 ] AVX512,FUTURE
+VCMPUNORD_SPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 13 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_SPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 13 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 13 ] AVX512,FUTURE
+VCMPUNORD_SPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 13 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_SPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 13 ] AVX512VL,AVX512,FUTURE
+VCMPUNORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 13 ] AVX512,FUTURE
+VCMPUNORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 13 ] AVX512,FUTURE
+VCMPUNORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 13 ] AVX512,FUTURE
+VCMPNEQ_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 14 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 14 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 14 ] AVX512,FUTURE
+VCMPNEQ_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 14 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 14 ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 14 ] AVX512,FUTURE
+VCMPNEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 14 ] AVX512,FUTURE
+VCMPNEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 14 ] AVX512,FUTURE
+VCMPNLT_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 15 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 15 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 15 ] AVX512,FUTURE
+VCMPNLT_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 15 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 15 ] AVX512VL,AVX512,FUTURE
+VCMPNLT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 15 ] AVX512,FUTURE
+VCMPNLT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 15 ] AVX512,FUTURE
+VCMPNLT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 15 ] AVX512,FUTURE
+VCMPNLE_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 16 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 16 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 16 ] AVX512,FUTURE
+VCMPNLE_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 16 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 16 ] AVX512VL,AVX512,FUTURE
+VCMPNLE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 16 ] AVX512,FUTURE
+VCMPNLE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 16 ] AVX512,FUTURE
+VCMPNLE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 16 ] AVX512,FUTURE
+VCMPORD_SPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 17 ] AVX512VL,AVX512,FUTURE
+VCMPORD_SPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 17 ] AVX512VL,AVX512,FUTURE
+VCMPORD_SPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 17 ] AVX512,FUTURE
+VCMPORD_SPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 17 ] AVX512VL,AVX512,FUTURE
+VCMPORD_SPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 17 ] AVX512VL,AVX512,FUTURE
+VCMPORD_SPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 17 ] AVX512,FUTURE
+VCMPORD_SSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 17 ] AVX512,FUTURE
+VCMPORD_SSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 17 ] AVX512,FUTURE
+VCMPEQ_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 18 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 18 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 18 ] AVX512,FUTURE
+VCMPEQ_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 18 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 18 ] AVX512VL,AVX512,FUTURE
+VCMPEQ_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 18 ] AVX512,FUTURE
+VCMPEQ_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 18 ] AVX512,FUTURE
+VCMPEQ_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 18 ] AVX512,FUTURE
+VCMPNGE_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 19 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 19 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 19 ] AVX512,FUTURE
+VCMPNGE_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 19 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 19 ] AVX512VL,AVX512,FUTURE
+VCMPNGE_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 19 ] AVX512,FUTURE
+VCMPNGE_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 19 ] AVX512,FUTURE
+VCMPNGE_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 19 ] AVX512,FUTURE
+VCMPNGT_UQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 1a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_UQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 1a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_UQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 1a ] AVX512,FUTURE
+VCMPNGT_UQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 1a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_UQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 1a ] AVX512VL,AVX512,FUTURE
+VCMPNGT_UQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 1a ] AVX512,FUTURE
+VCMPNGT_UQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 1a ] AVX512,FUTURE
+VCMPNGT_UQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 1a ] AVX512,FUTURE
+VCMPFALSE_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 1b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 1b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 1b ] AVX512,FUTURE
+VCMPFALSE_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 1b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 1b ] AVX512VL,AVX512,FUTURE
+VCMPFALSE_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 1b ] AVX512,FUTURE
+VCMPFALSE_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 1b ] AVX512,FUTURE
+VCMPFALSE_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 1b ] AVX512,FUTURE
+VCMPNEQ_OSPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 1c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OSPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 1c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OSPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 1c ] AVX512,FUTURE
+VCMPNEQ_OSPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 1c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OSPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 1c ] AVX512VL,AVX512,FUTURE
+VCMPNEQ_OSPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 1c ] AVX512,FUTURE
+VCMPNEQ_OSSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 1c ] AVX512,FUTURE
+VCMPNEQ_OSSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 1c ] AVX512,FUTURE
+VCMPGE_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 1d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 1d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 1d ] AVX512,FUTURE
+VCMPGE_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 1d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 1d ] AVX512VL,AVX512,FUTURE
+VCMPGE_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 1d ] AVX512,FUTURE
+VCMPGE_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 1d ] AVX512,FUTURE
+VCMPGE_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 1d ] AVX512,FUTURE
+VCMPGT_OQPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 1e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OQPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 1e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OQPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 1e ] AVX512,FUTURE
+VCMPGT_OQPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 1e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OQPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 1e ] AVX512VL,AVX512,FUTURE
+VCMPGT_OQPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 1e ] AVX512,FUTURE
+VCMPGT_OQSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 1e ] AVX512,FUTURE
+VCMPGT_OQSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 1e ] AVX512,FUTURE
+VCMPTRUE_USPD kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r 1f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_USPD kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r 1f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_USPD kreg|mask,zmmreg,zmmrm512|b64|sae [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r 1f ] AVX512,FUTURE
+VCMPTRUE_USPS kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.0f.w0 c2 /r 1f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_USPS kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.0f.w0 c2 /r 1f ] AVX512VL,AVX512,FUTURE
+VCMPTRUE_USPS kreg|mask,zmmreg,zmmrm512|b32|sae [rvmi:fv: evex.nds.512.0f.w0 c2 /r 1f ] AVX512,FUTURE
+VCMPTRUE_USSD kreg|mask,xmmreg,xmmrm64|sae [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r 1f ] AVX512,FUTURE
+VCMPTRUE_USSS kreg|mask,xmmreg,xmmrm32|sae [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r 1f ] AVX512,FUTURE
+VCMPPD kreg|mask,xmmreg,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f.w1 c2 /r ib ] AVX512VL,AVX512,FUTURE
+VCMPPD kreg|mask,ymmreg,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f.w1 c2 /r ib ] AVX512VL,AVX512,FUTURE
+VCMPPD kreg|mask,zmmreg,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f.w1 c2 /r ib ] AVX512,FUTURE
+VCMPPS kreg|mask,xmmreg,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.0f.w0 c2 /r ib ] AVX512VL,AVX512,FUTURE
+VCMPPS kreg|mask,ymmreg,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.0f.w0 c2 /r ib ] AVX512VL,AVX512,FUTURE
+VCMPPS kreg|mask,zmmreg,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.0f.w0 c2 /r ib ] AVX512,FUTURE
+VCMPSD kreg|mask,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.128.f2.0f.w1 c2 /r ib ] AVX512,FUTURE
+VCMPSS kreg|mask,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.128.f3.0f.w0 c2 /r ib ] AVX512,FUTURE
+VCOMISD xmmreg,xmmrm64|sae [rm:t1s: evex.128.66.0f.w1 2f /r ] AVX512,FUTURE
+VCOMISS xmmreg,xmmrm32|sae [rm:t1s: evex.128.0f.w0 2f /r ] AVX512,FUTURE
+VCOMPRESSPD mem128|mask,xmmreg [mr:t1s: evex.128.66.0f38.w1 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPD mem256|mask,ymmreg [mr:t1s: evex.256.66.0f38.w1 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w1 8a /r ] AVX512,FUTURE
+VCOMPRESSPD xmmreg|mask|z,xmmreg [mr: evex.128.66.0f38.w1 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPD ymmreg|mask|z,ymmreg [mr: evex.256.66.0f38.w1 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w1 8a /r ] AVX512,FUTURE
+VCOMPRESSPS mem128|mask,xmmreg [mr:t1s: evex.128.66.0f38.w0 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPS mem256|mask,ymmreg [mr:t1s: evex.256.66.0f38.w0 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPS mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w0 8a /r ] AVX512,FUTURE
+VCOMPRESSPS xmmreg|mask|z,xmmreg [mr: evex.128.66.0f38.w0 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPS ymmreg|mask|z,ymmreg [mr: evex.256.66.0f38.w0 8a /r ] AVX512VL,AVX512,FUTURE
+VCOMPRESSPS zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w0 8a /r ] AVX512,FUTURE
+VCVTDQ2PD xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.f3.0f.w0 e6 /r ] AVX512VL,AVX512,FUTURE
+VCVTDQ2PD ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.f3.0f.w0 e6 /r ] AVX512VL,AVX512,FUTURE
+VCVTDQ2PD zmmreg|mask|z,ymmrm256|b32|er [rm:hv: evex.512.f3.0f.w0 e6 /r ] AVX512,FUTURE
+VCVTDQ2PS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.0f.w0 5b /r ] AVX512VL,AVX512,FUTURE
+VCVTDQ2PS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.0f.w0 5b /r ] AVX512VL,AVX512,FUTURE
+VCVTDQ2PS zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.0f.w0 5b /r ] AVX512,FUTURE
+VCVTPD2DQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.f2.0f.w1 e6 /r ] AVX512VL,AVX512,FUTURE
+VCVTPD2DQ xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.f2.0f.w1 e6 /r ] AVX512VL,AVX512,FUTURE
+VCVTPD2DQ ymmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.f2.0f.w1 e6 /r ] AVX512,FUTURE
+VCVTPD2PS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f.w1 5a /r ] AVX512VL,AVX512,FUTURE
+VCVTPD2PS xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f.w1 5a /r ] AVX512VL,AVX512,FUTURE
+VCVTPD2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.66.0f.w1 5a /r ] AVX512,FUTURE
+VCVTPD2QQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f.w1 7b /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPD2QQ ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f.w1 7b /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPD2QQ zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.66.0f.w1 7b /r ] AVX512DQ,FUTURE
+VCVTPD2UDQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.0f.w1 79 /r ] AVX512VL,AVX512,FUTURE
+VCVTPD2UDQ xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.0f.w1 79 /r ] AVX512VL,AVX512,FUTURE
+VCVTPD2UDQ ymmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.0f.w1 79 /r ] AVX512,FUTURE
+VCVTPD2UQQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f.w1 79 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPD2UQQ ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f.w1 79 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPD2UQQ zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.66.0f.w1 79 /r ] AVX512DQ,FUTURE
+VCVTPH2PS xmmreg|mask|z,xmmrm64 [rm:hvm: evex.128.66.0f38.w0 13 /r ] AVX512VL,AVX512,FUTURE
+VCVTPH2PS ymmreg|mask|z,xmmrm128 [rm:hvm: evex.256.66.0f38.w0 13 /r ] AVX512VL,AVX512,FUTURE
+VCVTPH2PS zmmreg|mask|z,ymmrm256|sae [rm:hvm: evex.512.66.0f38.w0 13 /r ] AVX512,FUTURE
+VCVTPS2DQ xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.0f.w0 5b /r ] AVX512VL,AVX512,FUTURE
+VCVTPS2DQ ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.0f.w0 5b /r ] AVX512VL,AVX512,FUTURE
+VCVTPS2DQ zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.66.0f.w0 5b /r ] AVX512,FUTURE
+VCVTPS2PD xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.0f.w0 5a /r ] AVX512VL,AVX512,FUTURE
+VCVTPS2PD ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.0f.w0 5a /r ] AVX512VL,AVX512,FUTURE
+VCVTPS2PD zmmreg|mask|z,ymmrm256|b32|sae [rm:hv: evex.512.0f.w0 5a /r ] AVX512,FUTURE
+VCVTPS2PH xmmreg|mask|z,xmmreg,imm8 [mri:hvm: evex.128.66.0f3a.w0 1d /r ib ] AVX512VL,AVX512,FUTURE
+VCVTPS2PH xmmreg|mask|z,ymmreg,imm8 [mri:hvm: evex.256.66.0f3a.w0 1d /r ib ] AVX512VL,AVX512,FUTURE
+VCVTPS2PH ymmreg|mask|z,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib ] AVX512,FUTURE
+VCVTPS2PH mem64|mask,xmmreg,imm8 [mri:hvm: evex.128.66.0f3a.w0 1d /r ib ] AVX512VL,AVX512,FUTURE
+VCVTPS2PH mem128|mask,ymmreg,imm8 [mri:hvm: evex.256.66.0f3a.w0 1d /r ib ] AVX512VL,AVX512,FUTURE
+VCVTPS2PH mem256|mask,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib ] AVX512,FUTURE
+VCVTPS2QQ xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.66.0f.w0 7b /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPS2QQ ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.66.0f.w0 7b /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPS2QQ zmmreg|mask|z,ymmrm256|b32|er [rm:hv: evex.512.66.0f.w0 7b /r ] AVX512DQ,FUTURE
+VCVTPS2UDQ xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.0f.w0 79 /r ] AVX512VL,AVX512,FUTURE
+VCVTPS2UDQ ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.0f.w0 79 /r ] AVX512VL,AVX512,FUTURE
+VCVTPS2UDQ zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.0f.w0 79 /r ] AVX512,FUTURE
+VCVTPS2UQQ xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.66.0f.w0 79 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPS2UQQ ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.66.0f.w0 79 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTPS2UQQ zmmreg|mask|z,ymmrm256|b32|er [rm:hv: evex.512.66.0f.w0 79 /r ] AVX512DQ,FUTURE
+VCVTQQ2PD xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.f3.0f.w1 e6 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTQQ2PD ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.f3.0f.w1 e6 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTQQ2PD zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.f3.0f.w1 e6 /r ] AVX512DQ,FUTURE
+VCVTQQ2PS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.0f.w1 5b /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTQQ2PS xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.0f.w1 5b /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTQQ2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.0f.w1 5b /r ] AVX512DQ,FUTURE
+VCVTSD2SI reg32,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w0 2d /r ] AVX512,FUTURE
+VCVTSD2SI reg64,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w1 2d /r ] AVX512,FUTURE
+VCVTSD2SS xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.f2.0f.w1 5a /r ] AVX512,FUTURE
+VCVTSD2USI reg32,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w0 79 /r ] AVX512,FUTURE
+VCVTSD2USI reg64,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w1 79 /r ] AVX512,FUTURE
+VCVTSI2SD xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.128.f2.0f.w0 2a /r ] AVX512,FUTURE
+VCVTSI2SD xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.128.f2.0f.w1 2a /r ] AVX512,FUTURE
+VCVTSI2SS xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.128.f3.0f.w0 2a /r ] AVX512,FUTURE
+VCVTSI2SS xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.128.f3.0f.w1 2a /r ] AVX512,FUTURE
+VCVTSS2SD xmmreg|mask|z,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.128.f3.0f.w0 5a /r ] AVX512,FUTURE
+VCVTSS2SI reg32,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w0 2d /r ] AVX512,FUTURE
+VCVTSS2SI reg64,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w1 2d /r ] AVX512,FUTURE
+VCVTSS2USI reg32,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w0 79 /r ] AVX512,FUTURE
+VCVTSS2USI reg64,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w1 79 /r ] AVX512,FUTURE
+VCVTTPD2DQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f.w1 e6 /r ] AVX512VL,AVX512,FUTURE
+VCVTTPD2DQ xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f.w1 e6 /r ] AVX512VL,AVX512,FUTURE
+VCVTTPD2DQ ymmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f.w1 e6 /r ] AVX512,FUTURE
+VCVTTPD2QQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f.w1 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPD2QQ ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f.w1 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPD2QQ zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f.w1 7a /r ] AVX512DQ,FUTURE
+VCVTTPD2UDQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.0f.w1 78 /r ] AVX512VL,AVX512,FUTURE
+VCVTTPD2UDQ xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.0f.w1 78 /r ] AVX512VL,AVX512,FUTURE
+VCVTTPD2UDQ ymmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.0f.w1 78 /r ] AVX512,FUTURE
+VCVTTPD2UQQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f.w1 78 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPD2UQQ ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f.w1 78 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPD2UQQ zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f.w1 78 /r ] AVX512DQ,FUTURE
+VCVTTPS2DQ xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.f3.0f.w0 5b /r ] AVX512VL,AVX512,FUTURE
+VCVTTPS2DQ ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.f3.0f.w0 5b /r ] AVX512VL,AVX512,FUTURE
+VCVTTPS2DQ zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.f3.0f.w0 5b /r ] AVX512,FUTURE
+VCVTTPS2QQ xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.66.0f.w0 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPS2QQ ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.66.0f.w0 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPS2QQ zmmreg|mask|z,ymmrm256|b32|sae [rm:hv: evex.512.66.0f.w0 7a /r ] AVX512DQ,FUTURE
+VCVTTPS2UDQ xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.0f.w0 78 /r ] AVX512VL,AVX512,FUTURE
+VCVTTPS2UDQ ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.0f.w0 78 /r ] AVX512VL,AVX512,FUTURE
+VCVTTPS2UDQ zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.0f.w0 78 /r ] AVX512,FUTURE
+VCVTTPS2UQQ xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.66.0f.w0 78 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPS2UQQ ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.66.0f.w0 78 /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTTPS2UQQ zmmreg|mask|z,ymmrm256|b32|sae [rm:hv: evex.512.66.0f.w0 78 /r ] AVX512DQ,FUTURE
+VCVTTSD2SI reg32,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w0 2c /r ] AVX512,FUTURE
+VCVTTSD2SI reg64,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w1 2c /r ] AVX512,FUTURE
+VCVTTSD2USI reg32,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w0 78 /r ] AVX512,FUTURE
+VCVTTSD2USI reg64,xmmrm64|sae [rm:t1f64: evex.128.f2.0f.w1 78 /r ] AVX512,FUTURE
+VCVTTSS2SI reg32,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w0 2c /r ] AVX512,FUTURE
+VCVTTSS2SI reg64,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w1 2c /r ] AVX512,FUTURE
+VCVTTSS2USI reg32,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w0 78 /r ] AVX512,FUTURE
+VCVTTSS2USI reg64,xmmrm32|sae [rm:t1f32: evex.128.f3.0f.w1 78 /r ] AVX512,FUTURE
+VCVTUDQ2PD xmmreg|mask|z,xmmrm64|b32 [rm:hv: evex.128.f3.0f.w0 7a /r ] AVX512VL,AVX512,FUTURE
+VCVTUDQ2PD ymmreg|mask|z,xmmrm128|b32 [rm:hv: evex.256.f3.0f.w0 7a /r ] AVX512VL,AVX512,FUTURE
+VCVTUDQ2PD zmmreg|mask|z,ymmrm256|b32|er [rm:hv: evex.512.f3.0f.w0 7a /r ] AVX512,FUTURE
+VCVTUDQ2PS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.f2.0f.w0 7a /r ] AVX512VL,AVX512,FUTURE
+VCVTUDQ2PS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.f2.0f.w0 7a /r ] AVX512VL,AVX512,FUTURE
+VCVTUDQ2PS zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.f2.0f.w0 7a /r ] AVX512,FUTURE
+VCVTUQQ2PD xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.f3.0f.w1 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTUQQ2PD ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.f3.0f.w1 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTUQQ2PD zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.f3.0f.w1 7a /r ] AVX512DQ,FUTURE
+VCVTUQQ2PS xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.f2.0f.w1 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTUQQ2PS xmmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.f2.0f.w1 7a /r ] AVX512VL,AVX512DQ,FUTURE
+VCVTUQQ2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.f2.0f.w1 7a /r ] AVX512DQ,FUTURE
+VCVTUSI2SD xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.128.f2.0f.w0 7b /r ] AVX512,FUTURE
+VCVTUSI2SD xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.128.f2.0f.w1 7b /r ] AVX512,FUTURE
+VCVTUSI2SS xmmreg,xmmreg|er,rm32 [rvm:t1s: evex.nds.128.f3.0f.w0 7b /r ] AVX512,FUTURE
+VCVTUSI2SS xmmreg,xmmreg|er,rm64 [rvm:t1s: evex.nds.128.f3.0f.w1 7b /r ] AVX512,FUTURE
+VDBPSADBW xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w0 42 /r ib ] AVX512VL,AVX512BW,FUTURE
+VDBPSADBW ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w0 42 /r ib ] AVX512VL,AVX512BW,FUTURE
+VDBPSADBW zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w0 42 /r ib ] AVX512BW,FUTURE
+VDIVPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 5e /r ] AVX512VL,AVX512,FUTURE
+VDIVPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 5e /r ] AVX512VL,AVX512,FUTURE
+VDIVPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f.w1 5e /r ] AVX512,FUTURE
+VDIVPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 5e /r ] AVX512VL,AVX512,FUTURE
+VDIVPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 5e /r ] AVX512VL,AVX512,FUTURE
+VDIVPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.0f.w0 5e /r ] AVX512,FUTURE
+VDIVSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.128.f2.0f.w1 5e /r ] AVX512,FUTURE
+VDIVSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.128.f3.0f.w0 5e /r ] AVX512,FUTURE
+VEXP2PD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f38.w1 c8 /r ] AVX512ER,FUTURE
+VEXP2PS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.66.0f38.w0 c8 /r ] AVX512ER,FUTURE
+VEXPANDPD xmmreg|mask|z,mem128 [rm:t1s: evex.128.66.0f38.w1 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPD ymmreg|mask|z,mem256 [rm:t1s: evex.256.66.0f38.w1 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPD zmmreg|mask|z,mem512 [rm:t1s: evex.512.66.0f38.w1 88 /r ] AVX512,FUTURE
+VEXPANDPD xmmreg|mask|z,xmmreg [rm:t1s: evex.128.66.0f38.w1 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPD ymmreg|mask|z,ymmreg [rm:t1s: evex.256.66.0f38.w1 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPD zmmreg|mask|z,zmmreg [rm:t1s: evex.512.66.0f38.w1 88 /r ] AVX512,FUTURE
+VEXPANDPS xmmreg|mask|z,mem128 [rm:t1s: evex.128.66.0f38.w0 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPS ymmreg|mask|z,mem256 [rm:t1s: evex.256.66.0f38.w0 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPS zmmreg|mask|z,mem512 [rm:t1s: evex.512.66.0f38.w0 88 /r ] AVX512,FUTURE
+VEXPANDPS xmmreg|mask|z,xmmreg [rm:t1s: evex.128.66.0f38.w0 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPS ymmreg|mask|z,ymmreg [rm:t1s: evex.256.66.0f38.w0 88 /r ] AVX512VL,AVX512,FUTURE
+VEXPANDPS zmmreg|mask|z,zmmreg [rm:t1s: evex.512.66.0f38.w0 88 /r ] AVX512,FUTURE
+VEXTRACTF32X4 xmmreg|mask|z,ymmreg,imm8 [mri: evex.256.66.0f3a.w0 19 /r ib ] AVX512VL,AVX512,FUTURE
+VEXTRACTF32X4 xmmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w0 19 /r ib ] AVX512,FUTURE
+VEXTRACTF32X4 mem128|mask,ymmreg,imm8 [mri:t4: evex.256.66.0f3a.w0 19 /r ib ] AVX512VL,AVX512,FUTURE
+VEXTRACTF32X4 mem128|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w0 19 /r ib ] AVX512,FUTURE
+VEXTRACTF32X8 ymmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w0 1b /r ib ] AVX512DQ,FUTURE
+VEXTRACTF32X8 mem256|mask,zmmreg,imm8 [mri:t8: evex.512.66.0f3a.w0 1b /r ib ] AVX512DQ,FUTURE
+VEXTRACTF64X2 xmmreg|mask|z,ymmreg,imm8 [mri: evex.256.66.0f3a.w1 19 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VEXTRACTF64X2 xmmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w1 19 /r ib ] AVX512DQ,FUTURE
+VEXTRACTF64X2 mem128|mask,ymmreg,imm8 [mri:t2: evex.256.66.0f3a.w1 19 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VEXTRACTF64X2 mem128|mask,zmmreg,imm8 [mri:t2: evex.512.66.0f3a.w1 19 /r ib ] AVX512DQ,FUTURE
+VEXTRACTF64X4 ymmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w1 1b /r ib ] AVX512,FUTURE
+VEXTRACTF64X4 mem256|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w1 1b /r ib ] AVX512,FUTURE
+VEXTRACTI32X4 xmmreg|mask|z,ymmreg,imm8 [mri: evex.256.66.0f3a.w0 39 /r ib ] AVX512VL,AVX512,FUTURE
+VEXTRACTI32X4 xmmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w0 39 /r ib ] AVX512,FUTURE
+VEXTRACTI32X4 mem128|mask,ymmreg,imm8 [mri:t4: evex.256.66.0f3a.w0 39 /r ib ] AVX512VL,AVX512,FUTURE
+VEXTRACTI32X4 mem128|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w0 39 /r ib ] AVX512,FUTURE
+VEXTRACTI32X8 ymmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w0 3b /r ib ] AVX512DQ,FUTURE
+VEXTRACTI32X8 mem256|mask,zmmreg,imm8 [mri:t8: evex.512.66.0f3a.w0 3b /r ib ] AVX512DQ,FUTURE
+VEXTRACTI64X2 xmmreg|mask|z,ymmreg,imm8 [mri: evex.256.66.0f3a.w1 39 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VEXTRACTI64X2 xmmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w1 39 /r ib ] AVX512DQ,FUTURE
+VEXTRACTI64X2 mem128|mask,ymmreg,imm8 [mri:t2: evex.256.66.0f3a.w1 39 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VEXTRACTI64X2 mem128|mask,zmmreg,imm8 [mri:t2: evex.512.66.0f3a.w1 39 /r ib ] AVX512DQ,FUTURE
+VEXTRACTI64X4 ymmreg|mask|z,zmmreg,imm8 [mri: evex.512.66.0f3a.w1 3b /r ib ] AVX512,FUTURE
+VEXTRACTI64X4 mem256|mask,zmmreg,imm8 [mri:t4: evex.512.66.0f3a.w1 3b /r ib ] AVX512,FUTURE
+VEXTRACTPS reg32,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.wig 17 /r ib ] AVX512,FUTURE
+VEXTRACTPS reg64,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.wig 17 /r ib ] AVX512,FUTURE
+VEXTRACTPS mem32,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.wig 17 /r ib ] AVX512,FUTURE
+VFIXUPIMMPD xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 54 /r ib ] AVX512VL,AVX512,FUTURE
+VFIXUPIMMPD ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 54 /r ib ] AVX512VL,AVX512,FUTURE
+VFIXUPIMMPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 54 /r ib ] AVX512,FUTURE
+VFIXUPIMMPS xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 54 /r ib ] AVX512VL,AVX512,FUTURE
+VFIXUPIMMPS ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 54 /r ib ] AVX512VL,AVX512,FUTURE
+VFIXUPIMMPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 54 /r ib ] AVX512,FUTURE
+VFIXUPIMMSD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w1 55 /r ib ] AVX512,FUTURE
+VFIXUPIMMSS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 55 /r ib ] AVX512,FUTURE
+VFMADD132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 98 /r ] AVX512VL,AVX512,FUTURE
+VFMADD132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 98 /r ] AVX512VL,AVX512,FUTURE
+VFMADD132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 98 /r ] AVX512,FUTURE
+VFMADD132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 98 /r ] AVX512VL,AVX512,FUTURE
+VFMADD132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 98 /r ] AVX512VL,AVX512,FUTURE
+VFMADD132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 98 /r ] AVX512,FUTURE
+VFMADD132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 99 /r ] AVX512,FUTURE
+VFMADD132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 99 /r ] AVX512,FUTURE
+VFMADD213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 a8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 a8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 a8 /r ] AVX512,FUTURE
+VFMADD213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 a8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 a8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 a8 /r ] AVX512,FUTURE
+VFMADD213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 a9 /r ] AVX512,FUTURE
+VFMADD213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 a9 /r ] AVX512,FUTURE
+VFMADD231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 b8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 b8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 b8 /r ] AVX512,FUTURE
+VFMADD231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 b8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 b8 /r ] AVX512VL,AVX512,FUTURE
+VFMADD231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 b8 /r ] AVX512,FUTURE
+VFMADD231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 b9 /r ] AVX512,FUTURE
+VFMADD231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 b9 /r ] AVX512,FUTURE
+VFMADDSUB132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 96 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 96 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 96 /r ] AVX512,FUTURE
+VFMADDSUB132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 96 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 96 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 96 /r ] AVX512,FUTURE
+VFMADDSUB213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 a6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 a6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 a6 /r ] AVX512,FUTURE
+VFMADDSUB213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 a6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 a6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 a6 /r ] AVX512,FUTURE
+VFMADDSUB231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 b6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 b6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 b6 /r ] AVX512,FUTURE
+VFMADDSUB231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 b6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 b6 /r ] AVX512VL,AVX512,FUTURE
+VFMADDSUB231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 b6 /r ] AVX512,FUTURE
+VFMSUB132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 9a /r ] AVX512VL,AVX512,FUTURE
+VFMSUB132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 9a /r ] AVX512VL,AVX512,FUTURE
+VFMSUB132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 9a /r ] AVX512,FUTURE
+VFMSUB132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 9a /r ] AVX512VL,AVX512,FUTURE
+VFMSUB132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 9a /r ] AVX512VL,AVX512,FUTURE
+VFMSUB132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 9a /r ] AVX512,FUTURE
+VFMSUB132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 9b /r ] AVX512,FUTURE
+VFMSUB132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 9b /r ] AVX512,FUTURE
+VFMSUB213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 aa /r ] AVX512VL,AVX512,FUTURE
+VFMSUB213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 aa /r ] AVX512VL,AVX512,FUTURE
+VFMSUB213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 aa /r ] AVX512,FUTURE
+VFMSUB213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 aa /r ] AVX512VL,AVX512,FUTURE
+VFMSUB213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 aa /r ] AVX512VL,AVX512,FUTURE
+VFMSUB213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 aa /r ] AVX512,FUTURE
+VFMSUB213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 ab /r ] AVX512,FUTURE
+VFMSUB213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 ab /r ] AVX512,FUTURE
+VFMSUB231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 ba /r ] AVX512VL,AVX512,FUTURE
+VFMSUB231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 ba /r ] AVX512VL,AVX512,FUTURE
+VFMSUB231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 ba /r ] AVX512,FUTURE
+VFMSUB231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 ba /r ] AVX512VL,AVX512,FUTURE
+VFMSUB231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 ba /r ] AVX512VL,AVX512,FUTURE
+VFMSUB231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 ba /r ] AVX512,FUTURE
+VFMSUB231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 bb /r ] AVX512,FUTURE
+VFMSUB231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 bb /r ] AVX512,FUTURE
+VFMSUBADD132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 97 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 97 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 97 /r ] AVX512,FUTURE
+VFMSUBADD132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 97 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 97 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 97 /r ] AVX512,FUTURE
+VFMSUBADD213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 a7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 a7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 a7 /r ] AVX512,FUTURE
+VFMSUBADD213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 a7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 a7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 a7 /r ] AVX512,FUTURE
+VFMSUBADD231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 b7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 b7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 b7 /r ] AVX512,FUTURE
+VFMSUBADD231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 b7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 b7 /r ] AVX512VL,AVX512,FUTURE
+VFMSUBADD231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 b7 /r ] AVX512,FUTURE
+VFNMADD132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 9c /r ] AVX512VL,AVX512,FUTURE
+VFNMADD132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 9c /r ] AVX512VL,AVX512,FUTURE
+VFNMADD132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 9c /r ] AVX512,FUTURE
+VFNMADD132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 9c /r ] AVX512VL,AVX512,FUTURE
+VFNMADD132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 9c /r ] AVX512VL,AVX512,FUTURE
+VFNMADD132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 9c /r ] AVX512,FUTURE
+VFNMADD132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 9d /r ] AVX512,FUTURE
+VFNMADD132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 9d /r ] AVX512,FUTURE
+VFNMADD213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 ac /r ] AVX512VL,AVX512,FUTURE
+VFNMADD213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 ac /r ] AVX512VL,AVX512,FUTURE
+VFNMADD213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 ac /r ] AVX512,FUTURE
+VFNMADD213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 ac /r ] AVX512VL,AVX512,FUTURE
+VFNMADD213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 ac /r ] AVX512VL,AVX512,FUTURE
+VFNMADD213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 ac /r ] AVX512,FUTURE
+VFNMADD213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 ad /r ] AVX512,FUTURE
+VFNMADD213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 ad /r ] AVX512,FUTURE
+VFNMADD231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 bc /r ] AVX512VL,AVX512,FUTURE
+VFNMADD231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 bc /r ] AVX512VL,AVX512,FUTURE
+VFNMADD231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 bc /r ] AVX512,FUTURE
+VFNMADD231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 bc /r ] AVX512VL,AVX512,FUTURE
+VFNMADD231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 bc /r ] AVX512VL,AVX512,FUTURE
+VFNMADD231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 bc /r ] AVX512,FUTURE
+VFNMADD231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 bd /r ] AVX512,FUTURE
+VFNMADD231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 bd /r ] AVX512,FUTURE
+VFNMSUB132PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 9e /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB132PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 9e /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB132PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 9e /r ] AVX512,FUTURE
+VFNMSUB132PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 9e /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB132PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 9e /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB132PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 9e /r ] AVX512,FUTURE
+VFNMSUB132SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 9f /r ] AVX512,FUTURE
+VFNMSUB132SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 9f /r ] AVX512,FUTURE
+VFNMSUB213PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 ae /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB213PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 ae /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB213PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 ae /r ] AVX512,FUTURE
+VFNMSUB213PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 ae /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB213PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 ae /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB213PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 ae /r ] AVX512,FUTURE
+VFNMSUB213SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 af /r ] AVX512,FUTURE
+VFNMSUB213SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 af /r ] AVX512,FUTURE
+VFNMSUB231PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 be /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB231PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 be /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB231PD zmmreg|mask|z,zmmreg,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 be /r ] AVX512,FUTURE
+VFNMSUB231PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 be /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB231PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 be /r ] AVX512VL,AVX512,FUTURE
+VFNMSUB231PS zmmreg|mask|z,zmmreg,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 be /r ] AVX512,FUTURE
+VFNMSUB231SD xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 bf /r ] AVX512,FUTURE
+VFNMSUB231SS xmmreg|mask|z,xmmreg,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 bf /r ] AVX512,FUTURE
+VFPCLASSPD kreg|mask,xmmrm128|b64,imm8 [rmi:fv: evex.128.66.0f3a.w1 66 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VFPCLASSPD kreg|mask,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 66 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VFPCLASSPD kreg|mask,zmmrm512|b64,imm8 [rmi:fv: evex.512.66.0f3a.w1 66 /r ib ] AVX512DQ,FUTURE
+VFPCLASSPS kreg|mask,xmmrm128|b32,imm8 [rmi:fv: evex.128.66.0f3a.w0 66 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VFPCLASSPS kreg|mask,ymmrm256|b32,imm8 [rmi:fv: evex.256.66.0f3a.w0 66 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VFPCLASSPS kreg|mask,zmmrm512|b32,imm8 [rmi:fv: evex.512.66.0f3a.w0 66 /r ib ] AVX512DQ,FUTURE
+VFPCLASSSD kreg|mask,xmmrm64,imm8 [rmi:t1s: evex.128.66.0f3a.w1 67 /r ib ] AVX512DQ,FUTURE
+VFPCLASSSS kreg|mask,xmmrm32,imm8 [rmi:t1s: evex.128.66.0f3a.w0 67 /r ib ] AVX512DQ,FUTURE
+VGATHERDPD xmmreg|mask,xmem64 [rm:t1s: vsibx evex.128.66.0f38.w1 92 /r ] AVX512VL,AVX512,FUTURE
+VGATHERDPD ymmreg|mask,xmem64 [rm:t1s: vsibx evex.256.66.0f38.w1 92 /r ] AVX512VL,AVX512,FUTURE
+VGATHERDPD zmmreg|mask,ymem64 [rm:t1s: vsiby evex.512.66.0f38.w1 92 /r ] AVX512,FUTURE
+VGATHERDPS xmmreg|mask,xmem32 [rm:t1s: vsibx evex.128.66.0f38.w0 92 /r ] AVX512VL,AVX512,FUTURE
+VGATHERDPS ymmreg|mask,ymem32 [rm:t1s: vsiby evex.256.66.0f38.w0 92 /r ] AVX512VL,AVX512,FUTURE
+VGATHERDPS zmmreg|mask,zmem32 [rm:t1s: vsibz evex.512.66.0f38.w0 92 /r ] AVX512,FUTURE
+VGATHERPF0DPD ymem64|mask [m:t1s: vsiby evex.512.66.0f38.w1 c6 /1 ] AVX512PF,FUTURE
+VGATHERPF0DPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c6 /1 ] AVX512PF,FUTURE
+VGATHERPF0QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /1 ] AVX512PF,FUTURE
+VGATHERPF0QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /1 ] AVX512PF,FUTURE
+VGATHERPF1DPD ymem64|mask [m:t1s: vsiby evex.512.66.0f38.w1 c6 /2 ] AVX512PF,FUTURE
+VGATHERPF1DPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c6 /2 ] AVX512PF,FUTURE
+VGATHERPF1QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /2 ] AVX512PF,FUTURE
+VGATHERPF1QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /2 ] AVX512PF,FUTURE
+VGATHERQPD xmmreg|mask,xmem64 [rm:t1s: vsibx evex.128.66.0f38.w1 93 /r ] AVX512VL,AVX512,FUTURE
+VGATHERQPD ymmreg|mask,ymem64 [rm:t1s: vsiby evex.256.66.0f38.w1 93 /r ] AVX512VL,AVX512,FUTURE
+VGATHERQPD zmmreg|mask,zmem64 [rm:t1s: vsibz evex.512.66.0f38.w1 93 /r ] AVX512,FUTURE
+VGATHERQPS xmmreg|mask,xmem32 [rm:t1s: vsibx evex.128.66.0f38.w0 93 /r ] AVX512VL,AVX512,FUTURE
+VGATHERQPS xmmreg|mask,ymem32 [rm:t1s: vsiby evex.256.66.0f38.w0 93 /r ] AVX512VL,AVX512,FUTURE
+VGATHERQPS ymmreg|mask,zmem32 [rm:t1s: vsibz evex.512.66.0f38.w0 93 /r ] AVX512,FUTURE
+VGETEXPPD xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f38.w1 42 /r ] AVX512VL,AVX512,FUTURE
+VGETEXPPD ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f38.w1 42 /r ] AVX512VL,AVX512,FUTURE
+VGETEXPPD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f38.w1 42 /r ] AVX512,FUTURE
+VGETEXPPS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.0f38.w0 42 /r ] AVX512VL,AVX512,FUTURE
+VGETEXPPS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.0f38.w0 42 /r ] AVX512VL,AVX512,FUTURE
+VGETEXPPS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.66.0f38.w0 42 /r ] AVX512,FUTURE
+VGETEXPSD xmmreg|mask|z,xmmreg,xmmrm64|sae [rvm:t1s: evex.nds.128.66.0f38.w1 43 /r ] AVX512,FUTURE
+VGETEXPSS xmmreg|mask|z,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.128.66.0f38.w0 43 /r ] AVX512,FUTURE
+VGETMANTPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv: evex.128.66.0f3a.w1 26 /r ib ] AVX512VL,AVX512,FUTURE
+VGETMANTPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 26 /r ib ] AVX512VL,AVX512,FUTURE
+VGETMANTPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [rmi:fv: evex.512.66.0f3a.w1 26 /r ib ] AVX512,FUTURE
+VGETMANTPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv: evex.128.66.0f3a.w0 26 /r ib ] AVX512VL,AVX512,FUTURE
+VGETMANTPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv: evex.256.66.0f3a.w0 26 /r ib ] AVX512VL,AVX512,FUTURE
+VGETMANTPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [rmi:fv: evex.512.66.0f3a.w0 26 /r ib ] AVX512,FUTURE
+VGETMANTSD xmmreg|mask|z,xmmreg,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w1 27 /r ib ] AVX512,FUTURE
+VGETMANTSS xmmreg|mask|z,xmmreg,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 27 /r ib ] AVX512,FUTURE
+VINSERTF32X4 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t4: evex.nds.256.66.0f3a.w0 18 /r ib ] AVX512VL,AVX512,FUTURE
+VINSERTF32X4 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t4: evex.nds.512.66.0f3a.w0 18 /r ib ] AVX512,FUTURE
+VINSERTF32X8 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t8: evex.nds.512.66.0f3a.w0 1a /r ib ] AVX512DQ,FUTURE
+VINSERTF64X2 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t2: evex.nds.256.66.0f3a.w1 18 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VINSERTF64X2 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t2: evex.nds.512.66.0f3a.w1 18 /r ib ] AVX512DQ,FUTURE
+VINSERTF64X4 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t4: evex.nds.512.66.0f3a.w1 1a /r ib ] AVX512,FUTURE
+VINSERTI32X4 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t4: evex.nds.256.66.0f3a.w0 38 /r ib ] AVX512VL,AVX512,FUTURE
+VINSERTI32X4 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t4: evex.nds.512.66.0f3a.w0 38 /r ib ] AVX512,FUTURE
+VINSERTI32X8 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t8: evex.nds.512.66.0f3a.w0 3a /r ib ] AVX512DQ,FUTURE
+VINSERTI64X2 ymmreg|mask|z,ymmreg*,xmmrm128,imm8 [rvmi:t2: evex.nds.256.66.0f3a.w1 38 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VINSERTI64X2 zmmreg|mask|z,zmmreg*,xmmrm128,imm8 [rvmi:t2: evex.nds.512.66.0f3a.w1 38 /r ib ] AVX512DQ,FUTURE
+VINSERTI64X4 zmmreg|mask|z,zmmreg*,ymmrm256,imm8 [rvmi:t4: evex.nds.512.66.0f3a.w1 3a /r ib ] AVX512,FUTURE
+VINSERTPS xmmreg,xmmreg*,xmmrm32,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 21 /r ib ] AVX512,FUTURE
+VMAXPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 5f /r ] AVX512VL,AVX512,FUTURE
+VMAXPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 5f /r ] AVX512VL,AVX512,FUTURE
+VMAXPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 5f /r ] AVX512,FUTURE
+VMAXPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 5f /r ] AVX512VL,AVX512,FUTURE
+VMAXPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 5f /r ] AVX512VL,AVX512,FUTURE
+VMAXPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 5f /r ] AVX512,FUTURE
+VMAXSD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s: evex.nds.128.f2.0f.w1 5f /r ] AVX512,FUTURE
+VMAXSS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s: evex.nds.128.f3.0f.w0 5f /r ] AVX512,FUTURE
+VMINPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 5d /r ] AVX512VL,AVX512,FUTURE
+VMINPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 5d /r ] AVX512VL,AVX512,FUTURE
+VMINPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae [rvm:fv: evex.nds.512.66.0f.w1 5d /r ] AVX512,FUTURE
+VMINPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 5d /r ] AVX512VL,AVX512,FUTURE
+VMINPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 5d /r ] AVX512VL,AVX512,FUTURE
+VMINPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae [rvm:fv: evex.nds.512.0f.w0 5d /r ] AVX512,FUTURE
+VMINSD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s: evex.nds.128.f2.0f.w1 5d /r ] AVX512,FUTURE
+VMINSS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s: evex.nds.128.f3.0f.w0 5d /r ] AVX512,FUTURE
+VMOVAPD xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f.w1 28 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPD ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f.w1 28 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPD zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 28 /r ] AVX512,FUTURE
+VMOVAPD xmmreg|mask|z,xmmreg [mr: evex.128.66.0f.w1 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPD ymmreg|mask|z,ymmreg [mr: evex.256.66.0f.w1 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f.w1 29 /r ] AVX512,FUTURE
+VMOVAPD mem128|mask,xmmreg [mr:fvm: evex.128.66.0f.w1 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPD mem256|mask,ymmreg [mr:fvm: evex.256.66.0f.w1 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPD mem512|mask,zmmreg [mr:fvm: evex.512.66.0f.w1 29 /r ] AVX512,FUTURE
+VMOVAPS xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.0f.w0 28 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPS ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.0f.w0 28 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPS zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.0f.w0 28 /r ] AVX512,FUTURE
+VMOVAPS xmmreg|mask|z,xmmreg [mr: evex.128.0f.w0 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPS ymmreg|mask|z,ymmreg [mr: evex.256.0f.w0 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPS zmmreg|mask|z,zmmreg [mr: evex.512.0f.w0 29 /r ] AVX512,FUTURE
+VMOVAPS mem128|mask,xmmreg [mr:fvm: evex.128.0f.w0 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPS mem256|mask,ymmreg [mr:fvm: evex.256.0f.w0 29 /r ] AVX512VL,AVX512,FUTURE
+VMOVAPS mem512|mask,zmmreg [mr:fvm: evex.512.0f.w0 29 /r ] AVX512,FUTURE
+VMOVD xmmreg,rm32 [rm:t1s: evex.128.66.0f.w0 6e /r ] AVX512,FUTURE
+VMOVD rm32,xmmreg [mr:t1s: evex.128.66.0f.w0 7e /r ] AVX512,FUTURE
+VMOVDDUP xmmreg|mask|z,xmmrm64 [rm:dup: evex.128.f2.0f.w1 12 /r ] AVX512VL,AVX512,FUTURE
+VMOVDDUP ymmreg|mask|z,ymmrm256 [rm:dup: evex.256.f2.0f.w1 12 /r ] AVX512VL,AVX512,FUTURE
+VMOVDDUP zmmreg|mask|z,zmmrm512 [rm:dup: evex.512.f2.0f.w1 12 /r ] AVX512,FUTURE
+VMOVDQA32 xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f.w0 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA32 ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f.w0 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA32 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w0 6f /r ] AVX512,FUTURE
+VMOVDQA32 xmmrm128|mask|z,xmmreg [mr:fvm: evex.128.66.0f.w0 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA32 ymmrm256|mask|z,ymmreg [mr:fvm: evex.256.66.0f.w0 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA32 zmmrm512|mask|z,zmmreg [mr:fvm: evex.512.66.0f.w0 7f /r ] AVX512,FUTURE
+VMOVDQA64 xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f.w1 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA64 ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f.w1 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA64 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 6f /r ] AVX512,FUTURE
+VMOVDQA64 xmmrm128|mask|z,xmmreg [mr:fvm: evex.128.66.0f.w1 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA64 ymmrm256|mask|z,ymmreg [mr:fvm: evex.256.66.0f.w1 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQA64 zmmrm512|mask|z,zmmreg [mr:fvm: evex.512.66.0f.w1 7f /r ] AVX512,FUTURE
+VMOVDQU16 xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.f2.0f.w1 6f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU16 ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.f2.0f.w1 6f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU16 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f2.0f.w1 6f /r ] AVX512BW,FUTURE
+VMOVDQU16 xmmrm128|mask|z,xmmreg [mr:fvm: evex.128.f2.0f.w1 7f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU16 ymmrm256|mask|z,ymmreg [mr:fvm: evex.256.f2.0f.w1 7f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU16 zmmrm512|mask|z,zmmreg [mr:fvm: evex.512.f2.0f.w1 7f /r ] AVX512BW,FUTURE
+VMOVDQU32 xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.f3.0f.w0 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU32 ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.f3.0f.w0 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU32 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w0 6f /r ] AVX512,FUTURE
+VMOVDQU32 xmmrm128|mask|z,xmmreg [mr:fvm: evex.128.f3.0f.w0 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU32 ymmrm256|mask|z,ymmreg [mr:fvm: evex.256.f3.0f.w0 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU32 zmmrm512|mask|z,zmmreg [mr:fvm: evex.512.f3.0f.w0 7f /r ] AVX512,FUTURE
+VMOVDQU64 xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.f3.0f.w1 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU64 ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.f3.0f.w1 6f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU64 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w1 6f /r ] AVX512,FUTURE
+VMOVDQU64 xmmrm128|mask|z,xmmreg [mr:fvm: evex.128.f3.0f.w1 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU64 ymmrm256|mask|z,ymmreg [mr:fvm: evex.256.f3.0f.w1 7f /r ] AVX512VL,AVX512,FUTURE
+VMOVDQU64 zmmrm512|mask|z,zmmreg [mr:fvm: evex.512.f3.0f.w1 7f /r ] AVX512,FUTURE
+VMOVDQU8 xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.f2.0f.w0 6f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU8 ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.f2.0f.w0 6f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU8 zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f2.0f.w0 6f /r ] AVX512BW,FUTURE
+VMOVDQU8 xmmrm128|mask|z,xmmreg [mr:fvm: evex.128.f2.0f.w0 7f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU8 ymmrm256|mask|z,ymmreg [mr:fvm: evex.256.f2.0f.w0 7f /r ] AVX512VL,AVX512BW,FUTURE
+VMOVDQU8 zmmrm512|mask|z,zmmreg [mr:fvm: evex.512.f2.0f.w0 7f /r ] AVX512BW,FUTURE
+VMOVHLPS xmmreg,xmmreg*,xmmreg [rvm: evex.nds.128.0f.w0 12 /r ] AVX512,FUTURE
+VMOVHPD xmmreg,xmmreg*,mem64 [rvm:t1s: evex.nds.128.66.0f.w1 16 /r ] AVX512,FUTURE
+VMOVHPD mem64,xmmreg [mr:t1s: evex.128.66.0f.w1 17 /r ] AVX512,FUTURE
+VMOVHPS xmmreg,xmmreg*,mem64 [rvm:t2: evex.nds.128.0f.w0 16 /r ] AVX512,FUTURE
+VMOVHPS mem64,xmmreg [mr:t2: evex.128.0f.w0 17 /r ] AVX512,FUTURE
+VMOVLHPS xmmreg,xmmreg*,xmmreg [rvm: evex.nds.128.0f.w0 16 /r ] AVX512,FUTURE
+VMOVLPD xmmreg,xmmreg*,mem64 [rvm:t1s: evex.nds.128.66.0f.w1 12 /r ] AVX512,FUTURE
+VMOVLPD mem64,xmmreg [mr:t1s: evex.128.66.0f.w1 13 /r ] AVX512,FUTURE
+VMOVLPS xmmreg,xmmreg*,mem64 [rvm:t2: evex.nds.128.0f.w0 12 /r ] AVX512,FUTURE
+VMOVLPS mem64,xmmreg [mr:t2: evex.128.0f.w0 13 /r ] AVX512,FUTURE
+VMOVNTDQ mem128,xmmreg [mr:fvm: evex.128.66.0f.w0 e7 /r ] AVX512VL,AVX512,FUTURE
+VMOVNTDQ mem256,ymmreg [mr:fvm: evex.256.66.0f.w0 e7 /r ] AVX512VL,AVX512,FUTURE
+VMOVNTDQ mem512,zmmreg [mr:fvm: evex.512.66.0f.w0 e7 /r ] AVX512,FUTURE
+VMOVNTDQA xmmreg,mem128 [rm:fvm: evex.128.66.0f38.w0 2a /r ] AVX512VL,AVX512,FUTURE
+VMOVNTDQA ymmreg,mem256 [rm:fvm: evex.256.66.0f38.w0 2a /r ] AVX512VL,AVX512,FUTURE
+VMOVNTDQA zmmreg,mem512 [rm:fvm: evex.512.66.0f38.w0 2a /r ] AVX512,FUTURE
+VMOVNTPD mem128,xmmreg [mr:fvm: evex.128.66.0f.w1 2b /r ] AVX512VL,AVX512,FUTURE
+VMOVNTPD mem256,ymmreg [mr:fvm: evex.256.66.0f.w1 2b /r ] AVX512VL,AVX512,FUTURE
+VMOVNTPD mem512,zmmreg [mr:fvm: evex.512.66.0f.w1 2b /r ] AVX512,FUTURE
+VMOVNTPS mem128,xmmreg [mr:fvm: evex.128.0f.w0 2b /r ] AVX512VL,AVX512,FUTURE
+VMOVNTPS mem256,ymmreg [mr:fvm: evex.256.0f.w0 2b /r ] AVX512VL,AVX512,FUTURE
+VMOVNTPS mem512,zmmreg [mr:fvm: evex.512.0f.w0 2b /r ] AVX512,FUTURE
+VMOVQ xmmreg,rm64 [rm:t1s: evex.128.66.0f.w1 6e /r ] AVX512,FUTURE
+VMOVQ rm64,xmmreg [mr:t1s: evex.128.66.0f.w1 7e /r ] AVX512,FUTURE
+VMOVQ xmmreg,xmmrm64 [rm:t1s: evex.128.f3.0f.w1 7e /r ] AVX512,FUTURE
+VMOVQ xmmrm64,xmmreg [mr:t1s: evex.128.66.0f.w1 d6 /r ] AVX512,FUTURE
+VMOVSD xmmreg|mask|z,mem64 [rm:t1s: evex.128.f2.0f.w1 10 /r ] AVX512,FUTURE
+VMOVSD mem64|mask,xmmreg [mr:t1s: evex.128.f2.0f.w1 11 /r ] AVX512,FUTURE
+VMOVSD xmmreg|mask|z,xmmreg*,xmmreg [rvm: evex.nds.128.f2.0f.w1 10 /r ] AVX512,FUTURE
+VMOVSD xmmreg|mask|z,xmmreg*,xmmreg [mvr: evex.nds.128.f2.0f.w1 11 /r ] AVX512,FUTURE
+VMOVSHDUP xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.f3.0f.w0 16 /r ] AVX512VL,AVX512,FUTURE
+VMOVSHDUP ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.f3.0f.w0 16 /r ] AVX512VL,AVX512,FUTURE
+VMOVSHDUP zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w0 16 /r ] AVX512,FUTURE
+VMOVSLDUP xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.f3.0f.w0 12 /r ] AVX512VL,AVX512,FUTURE
+VMOVSLDUP ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.f3.0f.w0 12 /r ] AVX512VL,AVX512,FUTURE
+VMOVSLDUP zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.f3.0f.w0 12 /r ] AVX512,FUTURE
+VMOVSS xmmreg|mask|z,mem32 [rm:t1s: evex.128.f3.0f.w0 10 /r ] AVX512,FUTURE
+VMOVSS mem32|mask,xmmreg [mr:t1s: evex.128.f3.0f.w0 11 /r ] AVX512,FUTURE
+VMOVSS xmmreg|mask|z,xmmreg*,xmmreg [rvm: evex.nds.128.f3.0f.w0 10 /r ] AVX512,FUTURE
+VMOVSS xmmreg|mask|z,xmmreg*,xmmreg [mvr: evex.nds.128.f3.0f.w0 11 /r ] AVX512,FUTURE
+VMOVUPD xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f.w1 10 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPD ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f.w1 10 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPD zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f.w1 10 /r ] AVX512,FUTURE
+VMOVUPD xmmreg|mask|z,xmmreg [mr: evex.128.66.0f.w1 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPD ymmreg|mask|z,ymmreg [mr: evex.256.66.0f.w1 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f.w1 11 /r ] AVX512,FUTURE
+VMOVUPD mem128|mask,xmmreg [mr:fvm: evex.128.66.0f.w1 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPD mem256|mask,ymmreg [mr:fvm: evex.256.66.0f.w1 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPD mem512|mask,zmmreg [mr:fvm: evex.512.66.0f.w1 11 /r ] AVX512,FUTURE
+VMOVUPS xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.0f.w0 10 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPS ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.0f.w0 10 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPS zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.0f.w0 10 /r ] AVX512,FUTURE
+VMOVUPS xmmreg|mask|z,xmmreg [mr: evex.128.0f.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPS ymmreg|mask|z,ymmreg [mr: evex.256.0f.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPS zmmreg|mask|z,zmmreg [mr: evex.512.0f.w0 11 /r ] AVX512,FUTURE
+VMOVUPS mem128|mask,xmmreg [mr:fvm: evex.128.0f.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPS mem256|mask,ymmreg [mr:fvm: evex.256.0f.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VMOVUPS mem512|mask,zmmreg [mr:fvm: evex.512.0f.w0 11 /r ] AVX512,FUTURE
+VMULPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 59 /r ] AVX512VL,AVX512,FUTURE
+VMULPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 59 /r ] AVX512VL,AVX512,FUTURE
+VMULPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f.w1 59 /r ] AVX512,FUTURE
+VMULPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 59 /r ] AVX512VL,AVX512,FUTURE
+VMULPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 59 /r ] AVX512VL,AVX512,FUTURE
+VMULPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.0f.w0 59 /r ] AVX512,FUTURE
+VMULSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.128.f2.0f.w1 59 /r ] AVX512,FUTURE
+VMULSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.128.f3.0f.w0 59 /r ] AVX512,FUTURE
+VORPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 56 /r ] AVX512VL,AVX512DQ,FUTURE
+VORPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 56 /r ] AVX512VL,AVX512DQ,FUTURE
+VORPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 56 /r ] AVX512DQ,FUTURE
+VORPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 56 /r ] AVX512VL,AVX512DQ,FUTURE
+VORPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 56 /r ] AVX512VL,AVX512DQ,FUTURE
+VORPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.0f.w0 56 /r ] AVX512DQ,FUTURE
+VPABSB xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f38.wig 1c /r ] AVX512VL,AVX512BW,FUTURE
+VPABSB ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f38.wig 1c /r ] AVX512VL,AVX512BW,FUTURE
+VPABSB zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f38.wig 1c /r ] AVX512BW,FUTURE
+VPABSD xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.0f38.w0 1e /r ] AVX512VL,AVX512,FUTURE
+VPABSD ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.0f38.w0 1e /r ] AVX512VL,AVX512,FUTURE
+VPABSD zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 1e /r ] AVX512,FUTURE
+VPABSQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f38.w1 1f /r ] AVX512VL,AVX512,FUTURE
+VPABSQ ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f38.w1 1f /r ] AVX512VL,AVX512,FUTURE
+VPABSQ zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 1f /r ] AVX512,FUTURE
+VPABSW xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f38.wig 1d /r ] AVX512VL,AVX512BW,FUTURE
+VPABSW ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f38.wig 1d /r ] AVX512VL,AVX512BW,FUTURE
+VPABSW zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f38.wig 1d /r ] AVX512BW,FUTURE
+VPACKSSDW xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 6b /r ] AVX512VL,AVX512BW,FUTURE
+VPACKSSDW ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 6b /r ] AVX512VL,AVX512BW,FUTURE
+VPACKSSDW zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 6b /r ] AVX512BW,FUTURE
+VPACKSSWB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 63 /r ] AVX512VL,AVX512BW,FUTURE
+VPACKSSWB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 63 /r ] AVX512VL,AVX512BW,FUTURE
+VPACKSSWB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 63 /r ] AVX512BW,FUTURE
+VPACKUSDW xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 2b /r ] AVX512VL,AVX512BW,FUTURE
+VPACKUSDW ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 2b /r ] AVX512VL,AVX512BW,FUTURE
+VPACKUSDW zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 2b /r ] AVX512BW,FUTURE
+VPACKUSWB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 67 /r ] AVX512VL,AVX512BW,FUTURE
+VPACKUSWB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 67 /r ] AVX512VL,AVX512BW,FUTURE
+VPACKUSWB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 67 /r ] AVX512BW,FUTURE
+VPADDB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig fc /r ] AVX512VL,AVX512BW,FUTURE
+VPADDB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig fc /r ] AVX512VL,AVX512BW,FUTURE
+VPADDB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig fc /r ] AVX512BW,FUTURE
+VPADDD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 fe /r ] AVX512VL,AVX512,FUTURE
+VPADDD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 fe /r ] AVX512VL,AVX512,FUTURE
+VPADDD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 fe /r ] AVX512,FUTURE
+VPADDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 d4 /r ] AVX512VL,AVX512,FUTURE
+VPADDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 d4 /r ] AVX512VL,AVX512,FUTURE
+VPADDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 d4 /r ] AVX512,FUTURE
+VPADDSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig ec /r ] AVX512VL,AVX512BW,FUTURE
+VPADDSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig ec /r ] AVX512VL,AVX512BW,FUTURE
+VPADDSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig ec /r ] AVX512BW,FUTURE
+VPADDSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig ed /r ] AVX512VL,AVX512BW,FUTURE
+VPADDSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig ed /r ] AVX512VL,AVX512BW,FUTURE
+VPADDSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig ed /r ] AVX512BW,FUTURE
+VPADDUSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig dc /r ] AVX512VL,AVX512BW,FUTURE
+VPADDUSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig dc /r ] AVX512VL,AVX512BW,FUTURE
+VPADDUSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig dc /r ] AVX512BW,FUTURE
+VPADDUSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig dd /r ] AVX512VL,AVX512BW,FUTURE
+VPADDUSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig dd /r ] AVX512VL,AVX512BW,FUTURE
+VPADDUSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig dd /r ] AVX512BW,FUTURE
+VPADDW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig fd /r ] AVX512VL,AVX512BW,FUTURE
+VPADDW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig fd /r ] AVX512VL,AVX512BW,FUTURE
+VPADDW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig fd /r ] AVX512BW,FUTURE
+VPALIGNR xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.wig 0f /r ib ] AVX512VL,AVX512BW,FUTURE
+VPALIGNR ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.wig 0f /r ib ] AVX512VL,AVX512BW,FUTURE
+VPALIGNR zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.wig 0f /r ib ] AVX512BW,FUTURE
+VPANDD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 db /r ] AVX512VL,AVX512,FUTURE
+VPANDD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 db /r ] AVX512VL,AVX512,FUTURE
+VPANDD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 db /r ] AVX512,FUTURE
+VPANDND xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 df /r ] AVX512VL,AVX512,FUTURE
+VPANDND ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 df /r ] AVX512VL,AVX512,FUTURE
+VPANDND zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 df /r ] AVX512,FUTURE
+VPANDNQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 df /r ] AVX512VL,AVX512,FUTURE
+VPANDNQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 df /r ] AVX512VL,AVX512,FUTURE
+VPANDNQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 df /r ] AVX512,FUTURE
+VPANDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 db /r ] AVX512VL,AVX512,FUTURE
+VPANDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 db /r ] AVX512VL,AVX512,FUTURE
+VPANDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 db /r ] AVX512,FUTURE
+VPAVGB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig e0 /r ] AVX512VL,AVX512BW,FUTURE
+VPAVGB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig e0 /r ] AVX512VL,AVX512BW,FUTURE
+VPAVGB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig e0 /r ] AVX512BW,FUTURE
+VPAVGW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig e3 /r ] AVX512VL,AVX512BW,FUTURE
+VPAVGW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig e3 /r ] AVX512VL,AVX512BW,FUTURE
+VPAVGW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig e3 /r ] AVX512BW,FUTURE
+VPBLENDMB xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w0 66 /r ] AVX512VL,AVX512BW,FUTURE
+VPBLENDMB ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w0 66 /r ] AVX512VL,AVX512BW,FUTURE
+VPBLENDMB zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w0 66 /r ] AVX512BW,FUTURE
+VPBLENDMD xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 64 /r ] AVX512VL,AVX512,FUTURE
+VPBLENDMD ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 64 /r ] AVX512VL,AVX512,FUTURE
+VPBLENDMD zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 64 /r ] AVX512,FUTURE
+VPBLENDMQ xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 64 /r ] AVX512VL,AVX512,FUTURE
+VPBLENDMQ ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 64 /r ] AVX512VL,AVX512,FUTURE
+VPBLENDMQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 64 /r ] AVX512,FUTURE
+VPBLENDMW xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 66 /r ] AVX512VL,AVX512BW,FUTURE
+VPBLENDMW ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 66 /r ] AVX512VL,AVX512BW,FUTURE
+VPBLENDMW zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 66 /r ] AVX512BW,FUTURE
+VPBROADCASTB xmmreg|mask|z,xmmrm8 [rm:t1s8: evex.128.66.0f38.w0 78 /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB ymmreg|mask|z,xmmrm8 [rm:t1s8: evex.256.66.0f38.w0 78 /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB zmmreg|mask|z,xmmrm8 [rm:t1s8: evex.512.66.0f38.w0 78 /r ] AVX512BW,FUTURE
+VPBROADCASTB xmmreg|mask|z,reg8 [rm: evex.128.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB xmmreg|mask|z,reg16 [rm: evex.128.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB xmmreg|mask|z,reg32 [rm: evex.128.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB xmmreg|mask|z,reg64 [rm: evex.128.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB ymmreg|mask|z,reg8 [rm: evex.256.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB ymmreg|mask|z,reg16 [rm: evex.256.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB ymmreg|mask|z,reg32 [rm: evex.256.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB ymmreg|mask|z,reg64 [rm: evex.256.66.0f38.w0 7a /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTB zmmreg|mask|z,reg8 [rm: evex.512.66.0f38.w0 7a /r ] AVX512BW,FUTURE
+VPBROADCASTB zmmreg|mask|z,reg16 [rm: evex.512.66.0f38.w0 7a /r ] AVX512BW,FUTURE
+VPBROADCASTB zmmreg|mask|z,reg32 [rm: evex.512.66.0f38.w0 7a /r ] AVX512BW,FUTURE
+VPBROADCASTB zmmreg|mask|z,reg64 [rm: evex.512.66.0f38.w0 7a /r ] AVX512BW,FUTURE
+VPBROADCASTD xmmreg|mask|z,mem32 [rm:t1s: evex.128.66.0f38.w0 58 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTD ymmreg|mask|z,mem32 [rm:t1s: evex.256.66.0f38.w0 58 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTD zmmreg|mask|z,mem32 [rm:t1s: evex.512.66.0f38.w0 58 /r ] AVX512,FUTURE
+VPBROADCASTD xmmreg|mask|z,xmmreg [rm: evex.128.66.0f38.w0 58 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTD ymmreg|mask|z,xmmreg [rm: evex.256.66.0f38.w0 58 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTD zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w0 58 /r ] AVX512,FUTURE
+VPBROADCASTD xmmreg|mask|z,reg32 [rm: evex.128.66.0f38.w0 7c /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTD ymmreg|mask|z,reg32 [rm: evex.256.66.0f38.w0 7c /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTD zmmreg|mask|z,reg32 [rm: evex.512.66.0f38.w0 7c /r ] AVX512,FUTURE
+VPBROADCASTMB2Q xmmreg,kreg [rm: evex.128.f3.0f38.w1 2a /r ] AVX512VL,AVX512CD,FUTURE
+VPBROADCASTMB2Q ymmreg,kreg [rm: evex.256.f3.0f38.w1 2a /r ] AVX512VL,AVX512CD,FUTURE
+VPBROADCASTMB2Q zmmreg,kreg [rm: evex.512.f3.0f38.w1 2a /r ] AVX512CD,FUTURE
+VPBROADCASTMW2D xmmreg,kreg [rm: evex.128.f3.0f38.w0 3a /r ] AVX512VL,AVX512CD,FUTURE
+VPBROADCASTMW2D ymmreg,kreg [rm: evex.256.f3.0f38.w0 3a /r ] AVX512VL,AVX512CD,FUTURE
+VPBROADCASTMW2D zmmreg,kreg [rm: evex.512.f3.0f38.w0 3a /r ] AVX512CD,FUTURE
+VPBROADCASTQ xmmreg|mask|z,mem64 [rm:t1s: evex.128.66.0f38.w1 59 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTQ ymmreg|mask|z,mem64 [rm:t1s: evex.256.66.0f38.w1 59 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTQ zmmreg|mask|z,mem64 [rm:t1s: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE
+VPBROADCASTQ xmmreg|mask|z,xmmreg [rm: evex.128.66.0f38.w1 59 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTQ ymmreg|mask|z,xmmreg [rm: evex.256.66.0f38.w1 59 /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTQ zmmreg|mask|z,xmmreg [rm: evex.512.66.0f38.w1 59 /r ] AVX512,FUTURE
+VPBROADCASTQ xmmreg|mask|z,reg64 [rm: evex.128.66.0f38.w1 7c /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTQ ymmreg|mask|z,reg64 [rm: evex.256.66.0f38.w1 7c /r ] AVX512VL,AVX512,FUTURE
+VPBROADCASTQ zmmreg|mask|z,reg64 [rm: evex.512.66.0f38.w1 7c /r ] AVX512,FUTURE
+VPBROADCASTW xmmreg|mask|z,xmmrm16 [rm:t1s16: evex.128.66.0f38.w0 79 /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW ymmreg|mask|z,xmmrm16 [rm:t1s16: evex.256.66.0f38.w0 79 /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW zmmreg|mask|z,xmmrm16 [rm:t1s16: evex.512.66.0f38.w0 79 /r ] AVX512BW,FUTURE
+VPBROADCASTW xmmreg|mask|z,reg16 [rm: evex.128.66.0f38.w0 7b /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW xmmreg|mask|z,reg32 [rm: evex.128.66.0f38.w0 7b /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW xmmreg|mask|z,reg64 [rm: evex.128.66.0f38.w0 7b /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW ymmreg|mask|z,reg16 [rm: evex.256.66.0f38.w0 7b /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW ymmreg|mask|z,reg32 [rm: evex.256.66.0f38.w0 7b /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW ymmreg|mask|z,reg64 [rm: evex.256.66.0f38.w0 7b /r ] AVX512VL,AVX512BW,FUTURE
+VPBROADCASTW zmmreg|mask|z,reg16 [rm: evex.512.66.0f38.w0 7b /r ] AVX512BW,FUTURE
+VPBROADCASTW zmmreg|mask|z,reg32 [rm: evex.512.66.0f38.w0 7b /r ] AVX512BW,FUTURE
+VPBROADCASTW zmmreg|mask|z,reg64 [rm: evex.512.66.0f38.w0 7b /r ] AVX512BW,FUTURE
+; VPCMPEQx and VPCMPGTx come in two flavors: SSE-like, and VPCMP with immediate. They are both
+; valid, but prefer the SSE version as it is one byte shorter.
+VPCMPEQB kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 74 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQB kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 74 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQB kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 74 /r ] AVX512BW,FUTURE
+VPCMPEQD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 76 /r ] AVX512VL,AVX512,FUTURE
+VPCMPEQD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 76 /r ] AVX512VL,AVX512,FUTURE
+VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 76 /r ] AVX512,FUTURE
+VPCMPEQQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 29 /r ] AVX512VL,AVX512,FUTURE
+VPCMPEQQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 29 /r ] AVX512VL,AVX512,FUTURE
+VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 29 /r ] AVX512,FUTURE
+VPCMPEQW kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 75 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQW kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 75 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQW kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 75 /r ] AVX512BW,FUTURE
+VPCMPGTB kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 64 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTB kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 64 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTB kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 64 /r ] AVX512BW,FUTURE
+VPCMPGTD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 66 /r ] AVX512VL,AVX512,FUTURE
+VPCMPGTD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 66 /r ] AVX512VL,AVX512,FUTURE
+VPCMPGTD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 66 /r ] AVX512,FUTURE
+VPCMPGTQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 37 /r ] AVX512VL,AVX512,FUTURE
+VPCMPGTQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 37 /r ] AVX512VL,AVX512,FUTURE
+VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 37 /r ] AVX512,FUTURE
+VPCMPGTW kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 65 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTW kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 65 /r ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTW kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 65 /r ] AVX512BW,FUTURE
+; The systematic VPCMP with immediate instructions
+VPCMPEQB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 00 ] AVX512BW,FUTURE
+VPCMPEQD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 00 ] AVX512,FUTURE
+VPCMPEQQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 00 ] AVX512,FUTURE
+VPCMPEQUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 00 ] AVX512BW,FUTURE
+VPCMPEQUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 00 ] AVX512,FUTURE
+VPCMPEQUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 00 ] AVX512VL,AVX512,FUTURE
+VPCMPEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 00 ] AVX512,FUTURE
+VPCMPEQUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 00 ] AVX512BW,FUTURE
+VPCMPEQW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 00 ] AVX512VL,AVX512BW,FUTURE
+VPCMPEQW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 00 ] AVX512BW,FUTURE
+VPCMPGEB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 05 ] AVX512BW,FUTURE
+VPCMPGED kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGED kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGED kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 05 ] AVX512,FUTURE
+VPCMPGEQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGEQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGEQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 05 ] AVX512,FUTURE
+VPCMPGEUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 05 ] AVX512BW,FUTURE
+VPCMPGEUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGEUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGEUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 05 ] AVX512,FUTURE
+VPCMPGEUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGEUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPGEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 05 ] AVX512,FUTURE
+VPCMPGEUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 05 ] AVX512BW,FUTURE
+VPCMPGEW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGEW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 05 ] AVX512BW,FUTURE
+VPCMPGTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 06 ] AVX512BW,FUTURE
+VPCMPGTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 06 ] AVX512,FUTURE
+VPCMPGTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 06 ] AVX512,FUTURE
+VPCMPGTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 06 ] AVX512BW,FUTURE
+VPCMPGTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 06 ] AVX512,FUTURE
+VPCMPGTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPGTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 06 ] AVX512,FUTURE
+VPCMPGTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 06 ] AVX512BW,FUTURE
+VPCMPGTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPGTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 06 ] AVX512BW,FUTURE
+VPCMPLEB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 02 ] AVX512BW,FUTURE
+VPCMPLED kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLED kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLED kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 02 ] AVX512,FUTURE
+VPCMPLEQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLEQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 02 ] AVX512,FUTURE
+VPCMPLEUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 02 ] AVX512BW,FUTURE
+VPCMPLEUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLEUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 02 ] AVX512,FUTURE
+VPCMPLEUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLEUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 02 ] AVX512,FUTURE
+VPCMPLEUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 02 ] AVX512BW,FUTURE
+VPCMPLEW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLEW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 02 ] AVX512BW,FUTURE
+VPCMPLTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 01 ] AVX512BW,FUTURE
+VPCMPLTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 01 ] AVX512,FUTURE
+VPCMPLTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 01 ] AVX512,FUTURE
+VPCMPLTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 01 ] AVX512BW,FUTURE
+VPCMPLTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 01 ] AVX512,FUTURE
+VPCMPLTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 01 ] AVX512VL,AVX512,FUTURE
+VPCMPLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 01 ] AVX512,FUTURE
+VPCMPLTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 01 ] AVX512BW,FUTURE
+VPCMPLTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 01 ] AVX512VL,AVX512BW,FUTURE
+VPCMPLTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 01 ] AVX512BW,FUTURE
+VPCMPNEQB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 04 ] AVX512BW,FUTURE
+VPCMPNEQD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 04 ] AVX512,FUTURE
+VPCMPNEQQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 04 ] AVX512,FUTURE
+VPCMPNEQUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 04 ] AVX512BW,FUTURE
+VPCMPNEQUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 04 ] AVX512,FUTURE
+VPCMPNEQUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 04 ] AVX512VL,AVX512,FUTURE
+VPCMPNEQUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 04 ] AVX512,FUTURE
+VPCMPNEQUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 04 ] AVX512BW,FUTURE
+VPCMPNEQW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 04 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNEQW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 04 ] AVX512BW,FUTURE
+VPCMPNGTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 02 ] AVX512BW,FUTURE
+VPCMPNGTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 02 ] AVX512,FUTURE
+VPCMPNGTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 02 ] AVX512,FUTURE
+VPCMPNGTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 02 ] AVX512BW,FUTURE
+VPCMPNGTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 02 ] AVX512,FUTURE
+VPCMPNGTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 02 ] AVX512VL,AVX512,FUTURE
+VPCMPNGTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 02 ] AVX512,FUTURE
+VPCMPNGTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 02 ] AVX512BW,FUTURE
+VPCMPNGTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 02 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNGTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 02 ] AVX512BW,FUTURE
+VPCMPNLEB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 06 ] AVX512BW,FUTURE
+VPCMPNLED kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLED kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLED kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 06 ] AVX512,FUTURE
+VPCMPNLEQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLEQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLEQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 06 ] AVX512,FUTURE
+VPCMPNLEUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 06 ] AVX512BW,FUTURE
+VPCMPNLEUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLEUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLEUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 06 ] AVX512,FUTURE
+VPCMPNLEUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLEUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 06 ] AVX512VL,AVX512,FUTURE
+VPCMPNLEUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 06 ] AVX512,FUTURE
+VPCMPNLEUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 06 ] AVX512BW,FUTURE
+VPCMPNLEW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 06 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLEW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 06 ] AVX512BW,FUTURE
+VPCMPNLTB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r 05 ] AVX512BW,FUTURE
+VPCMPNLTD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r 05 ] AVX512,FUTURE
+VPCMPNLTQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r 05 ] AVX512,FUTURE
+VPCMPNLTUB kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTUB kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTUB kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r 05 ] AVX512BW,FUTURE
+VPCMPNLTUD kreg|mask,xmmreg,xmmrm128|b32 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTUD kreg|mask,ymmreg,ymmrm256|b32 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTUD kreg|mask,zmmreg,zmmrm512|b32 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r 05 ] AVX512,FUTURE
+VPCMPNLTUQ kreg|mask,xmmreg,xmmrm128|b64 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTUQ kreg|mask,ymmreg,ymmrm256|b64 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r 05 ] AVX512VL,AVX512,FUTURE
+VPCMPNLTUQ kreg|mask,zmmreg,zmmrm512|b64 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r 05 ] AVX512,FUTURE
+VPCMPNLTUW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTUW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTUW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r 05 ] AVX512BW,FUTURE
+VPCMPNLTW kreg|mask,xmmreg,xmmrm128 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTW kreg|mask,ymmreg,ymmrm256 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r 05 ] AVX512VL,AVX512BW,FUTURE
+VPCMPNLTW kreg|mask,zmmreg,zmmrm512 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r 05 ] AVX512BW,FUTURE
+VPCMPB kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3f /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPB kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3f /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPB kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3f /r ib ] AVX512BW,FUTURE
+VPCMPD kreg|mask,xmmreg,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 1f /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPD kreg|mask,ymmreg,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 1f /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1f /r ib ] AVX512,FUTURE
+VPCMPQ kreg|mask,xmmreg,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 1f /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPQ kreg|mask,ymmreg,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 1f /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1f /r ib ] AVX512,FUTURE
+VPCMPUB kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w0 3e /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPUB kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w0 3e /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPUB kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w0 3e /r ib ] AVX512BW,FUTURE
+VPCMPUD kreg|mask,xmmreg,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 1e /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPUD kreg|mask,ymmreg,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 1e /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPUD kreg|mask,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 1e /r ib ] AVX512,FUTURE
+VPCMPUQ kreg|mask,xmmreg,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 1e /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPUQ kreg|mask,ymmreg,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 1e /r ib ] AVX512VL,AVX512,FUTURE
+VPCMPUQ kreg|mask,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 1e /r ib ] AVX512,FUTURE
+VPCMPUW kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3e /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPUW kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3e /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPUW kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3e /r ib ] AVX512BW,FUTURE
+VPCMPW kreg|mask,xmmreg,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 3f /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPW kreg|mask,ymmreg,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 3f /r ib ] AVX512VL,AVX512BW,FUTURE
+VPCMPW kreg|mask,zmmreg,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 3f /r ib ] AVX512BW,FUTURE
+VPCOMPRESSD mem128|mask,xmmreg [mr:t1s: evex.128.66.0f38.w0 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSD mem256|mask,ymmreg [mr:t1s: evex.256.66.0f38.w0 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSD mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE
+VPCOMPRESSD xmmreg|mask|z,xmmreg [mr: evex.128.66.0f38.w0 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSD ymmreg|mask|z,ymmreg [mr: evex.256.66.0f38.w0 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSD zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w0 8b /r ] AVX512,FUTURE
+VPCOMPRESSQ mem128|mask,xmmreg [mr:t1s: evex.128.66.0f38.w1 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSQ mem256|mask,ymmreg [mr:t1s: evex.256.66.0f38.w1 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSQ mem512|mask,zmmreg [mr:t1s: evex.512.66.0f38.w1 8b /r ] AVX512,FUTURE
+VPCOMPRESSQ xmmreg|mask|z,xmmreg [mr: evex.128.66.0f38.w1 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSQ ymmreg|mask|z,ymmreg [mr: evex.256.66.0f38.w1 8b /r ] AVX512VL,AVX512,FUTURE
+VPCOMPRESSQ zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w1 8b /r ] AVX512,FUTURE
+VPCONFLICTD xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.0f38.w0 c4 /r ] AVX512VL,AVX512CD,FUTURE
+VPCONFLICTD ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.0f38.w0 c4 /r ] AVX512VL,AVX512CD,FUTURE
+VPCONFLICTD zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 c4 /r ] AVX512CD,FUTURE
+VPCONFLICTQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f38.w1 c4 /r ] AVX512VL,AVX512CD,FUTURE
+VPCONFLICTQ ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f38.w1 c4 /r ] AVX512VL,AVX512CD,FUTURE
+VPCONFLICTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 c4 /r ] AVX512CD,FUTURE
+VPERMB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w0 8d /r ] AVX512VL,AVX512VBMI,FUTURE
+VPERMB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w0 8d /r ] AVX512VL,AVX512VBMI,FUTURE
+VPERMB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w0 8d /r ] AVX512VBMI,FUTURE
+VPERMD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 36 /r ] AVX512VL,AVX512,FUTURE
+VPERMD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 36 /r ] AVX512,FUTURE
+VPERMI2B xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w0 75 /r ] AVX512VL,AVX512VBMI,FUTURE
+VPERMI2B ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w0 75 /r ] AVX512VL,AVX512VBMI,FUTURE
+VPERMI2B zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w0 75 /r ] AVX512VBMI,FUTURE
+VPERMI2D xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 76 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2D ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 76 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2D zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 76 /r ] AVX512,FUTURE
+VPERMI2PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 77 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 77 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2PD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 77 /r ] AVX512,FUTURE
+VPERMI2PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 77 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 77 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2PS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 77 /r ] AVX512,FUTURE
+VPERMI2Q xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 76 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2Q ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 76 /r ] AVX512VL,AVX512,FUTURE
+VPERMI2Q zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 76 /r ] AVX512,FUTURE
+VPERMI2W xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 75 /r ] AVX512VL,AVX512BW,FUTURE
+VPERMI2W ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 75 /r ] AVX512VL,AVX512BW,FUTURE
+VPERMI2W zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 75 /r ] AVX512BW,FUTURE
+VPERMILPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv: evex.128.66.0f3a.w1 05 /r ib ] AVX512VL,AVX512,FUTURE
+VPERMILPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 05 /r ib ] AVX512VL,AVX512,FUTURE
+VPERMILPD zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv: evex.512.66.0f3a.w1 05 /r ib ] AVX512,FUTURE
+VPERMILPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 0d /r ] AVX512VL,AVX512,FUTURE
+VPERMILPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 0d /r ] AVX512VL,AVX512,FUTURE
+VPERMILPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 0d /r ] AVX512,FUTURE
+VPERMILPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv: evex.128.66.0f3a.w0 04 /r ib ] AVX512VL,AVX512,FUTURE
+VPERMILPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv: evex.256.66.0f3a.w0 04 /r ib ] AVX512VL,AVX512,FUTURE
+VPERMILPS zmmreg|mask|z,zmmrm512|b32,imm8 [rmi:fv: evex.512.66.0f3a.w0 04 /r ib ] AVX512,FUTURE
+VPERMILPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 0c /r ] AVX512VL,AVX512,FUTURE
+VPERMILPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 0c /r ] AVX512VL,AVX512,FUTURE
+VPERMILPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 0c /r ] AVX512,FUTURE
+VPERMPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 01 /r ib ] AVX512VL,AVX512,FUTURE
+VPERMPD zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv: evex.512.66.0f3a.w1 01 /r ib ] AVX512,FUTURE
+VPERMPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 16 /r ] AVX512VL,AVX512,FUTURE
+VPERMPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 16 /r ] AVX512,FUTURE
+VPERMPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 16 /r ] AVX512VL,AVX512,FUTURE
+VPERMPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 16 /r ] AVX512,FUTURE
+VPERMQ ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 00 /r ib ] AVX512VL,AVX512,FUTURE
+VPERMQ zmmreg|mask|z,zmmrm512|b64,imm8 [rmi:fv: evex.512.66.0f3a.w1 00 /r ib ] AVX512,FUTURE
+VPERMQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 36 /r ] AVX512VL,AVX512,FUTURE
+VPERMQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 36 /r ] AVX512,FUTURE
+VPERMT2B xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w0 7d /r ] AVX512VL,AVX512VBMI,FUTURE
+VPERMT2B ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w0 7d /r ] AVX512VL,AVX512VBMI,FUTURE
+VPERMT2B zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w0 7d /r ] AVX512VBMI,FUTURE
+VPERMT2D xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 7e /r ] AVX512VL,AVX512,FUTURE
+VPERMT2D ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 7e /r ] AVX512VL,AVX512,FUTURE
+VPERMT2D zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 7e /r ] AVX512,FUTURE
+VPERMT2PD xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 7f /r ] AVX512VL,AVX512,FUTURE
+VPERMT2PD ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 7f /r ] AVX512VL,AVX512,FUTURE
+VPERMT2PD zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 7f /r ] AVX512,FUTURE
+VPERMT2PS xmmreg|mask|z,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 7f /r ] AVX512VL,AVX512,FUTURE
+VPERMT2PS ymmreg|mask|z,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 7f /r ] AVX512VL,AVX512,FUTURE
+VPERMT2PS zmmreg|mask|z,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 7f /r ] AVX512,FUTURE
+VPERMT2Q xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 7e /r ] AVX512VL,AVX512,FUTURE
+VPERMT2Q ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 7e /r ] AVX512VL,AVX512,FUTURE
+VPERMT2Q zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 7e /r ] AVX512,FUTURE
+VPERMT2W xmmreg|mask|z,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 7d /r ] AVX512VL,AVX512BW,FUTURE
+VPERMT2W ymmreg|mask|z,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 7d /r ] AVX512VL,AVX512BW,FUTURE
+VPERMT2W zmmreg|mask|z,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 7d /r ] AVX512BW,FUTURE
+VPERMW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 8d /r ] AVX512VL,AVX512BW,FUTURE
+VPERMW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 8d /r ] AVX512VL,AVX512BW,FUTURE
+VPERMW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 8d /r ] AVX512BW,FUTURE
+VPEXPANDD xmmreg|mask|z,mem128 [rm:t1s: evex.128.66.0f38.w0 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDD ymmreg|mask|z,mem256 [rm:t1s: evex.256.66.0f38.w0 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDD zmmreg|mask|z,mem512 [rm:t1s: evex.512.66.0f38.w0 89 /r ] AVX512,FUTURE
+VPEXPANDD xmmreg|mask|z,xmmreg [rm:t1s: evex.128.66.0f38.w0 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDD ymmreg|mask|z,ymmreg [rm:t1s: evex.256.66.0f38.w0 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDD zmmreg|mask|z,zmmreg [rm:t1s: evex.512.66.0f38.w0 89 /r ] AVX512,FUTURE
+VPEXPANDQ xmmreg|mask|z,mem128 [rm:t1s: evex.128.66.0f38.w1 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDQ ymmreg|mask|z,mem256 [rm:t1s: evex.256.66.0f38.w1 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDQ zmmreg|mask|z,mem512 [rm:t1s: evex.512.66.0f38.w1 89 /r ] AVX512,FUTURE
+VPEXPANDQ xmmreg|mask|z,xmmreg [rm:t1s: evex.128.66.0f38.w1 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDQ ymmreg|mask|z,ymmreg [rm:t1s: evex.256.66.0f38.w1 89 /r ] AVX512VL,AVX512,FUTURE
+VPEXPANDQ zmmreg|mask|z,zmmreg [rm:t1s: evex.512.66.0f38.w1 89 /r ] AVX512,FUTURE
+VPEXTRB reg8,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib ] AVX512BW,FUTURE
+VPEXTRB reg16,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib ] AVX512BW,FUTURE
+VPEXTRB reg32,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib ] AVX512BW,FUTURE
+VPEXTRB reg64,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib ] AVX512BW,FUTURE
+VPEXTRB mem8,xmmreg,imm8 [mri:t1s8: evex.128.66.0f3a.wig 14 /r ib ] AVX512BW,FUTURE
+VPEXTRD rm32,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.w0 16 /r ib ] AVX512DQ,FUTURE
+VPEXTRQ rm64,xmmreg,imm8 [mri:t1s: evex.128.66.0f3a.w1 16 /r ib ] AVX512DQ,FUTURE
+VPEXTRW reg16,xmmreg,imm8 [mri:t1s16: evex.128.66.0f3a.wig 15 /r ib ] AVX512BW,FUTURE
+VPEXTRW reg32,xmmreg,imm8 [mri:t1s16: evex.128.66.0f3a.wig 15 /r ib ] AVX512BW,FUTURE
+VPEXTRW reg64,xmmreg,imm8 [mri:t1s16: evex.128.66.0f3a.wig 15 /r ib ] AVX512BW,FUTURE
+VPEXTRW mem16,xmmreg,imm8 [mri:t1s16: evex.128.66.0f3a.wig 15 /r ib ] AVX512BW,FUTURE
+VPEXTRW reg16,xmmreg,imm8 [rmi: evex.128.66.0f.wig c5 /r ib ] AVX512BW,FUTURE
+VPEXTRW reg32,xmmreg,imm8 [rmi: evex.128.66.0f.wig c5 /r ib ] AVX512BW,FUTURE
+VPEXTRW reg64,xmmreg,imm8 [rmi: evex.128.66.0f.wig c5 /r ib ] AVX512BW,FUTURE
+VPGATHERDD xmmreg|mask,xmem32 [rm:t1s: vsibx evex.128.66.0f38.w0 90 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERDD ymmreg|mask,ymem32 [rm:t1s: vsiby evex.256.66.0f38.w0 90 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERDD zmmreg|mask,zmem32 [rm:t1s: vsibz evex.512.66.0f38.w0 90 /r ] AVX512,FUTURE
+VPGATHERDQ xmmreg|mask,xmem64 [rm:t1s: vsibx evex.128.66.0f38.w1 90 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERDQ ymmreg|mask,xmem64 [rm:t1s: vsibx evex.256.66.0f38.w1 90 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERDQ zmmreg|mask,ymem64 [rm:t1s: vsiby evex.512.66.0f38.w1 90 /r ] AVX512,FUTURE
+VPGATHERQD xmmreg|mask,xmem32 [rm:t1s: vsibx evex.128.66.0f38.w0 91 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERQD xmmreg|mask,ymem32 [rm:t1s: vsiby evex.256.66.0f38.w0 91 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERQD ymmreg|mask,zmem32 [rm:t1s: vsibz evex.512.66.0f38.w0 91 /r ] AVX512,FUTURE
+VPGATHERQQ xmmreg|mask,xmem64 [rm:t1s: vsibx evex.128.66.0f38.w1 91 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERQQ ymmreg|mask,ymem64 [rm:t1s: vsiby evex.256.66.0f38.w1 91 /r ] AVX512VL,AVX512,FUTURE
+VPGATHERQQ zmmreg|mask,zmem64 [rm:t1s: vsibz evex.512.66.0f38.w1 91 /r ] AVX512,FUTURE
+VPINSRB xmmreg,xmmreg*,reg32,imm8 [rvmi:t1s8: evex.nds.128.66.0f3a.wig 20 /r ib ] AVX512BW,FUTURE
+VPINSRB xmmreg,xmmreg*,mem8,imm8 [rvmi:t1s8: evex.nds.128.66.0f3a.wig 20 /r ib ] AVX512BW,FUTURE
+VPINSRD xmmreg,xmmreg*,rm32,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 22 /r ib ] AVX512DQ,FUTURE
+VPINSRQ xmmreg,xmmreg*,rm64,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w1 22 /r ib ] AVX512DQ,FUTURE
+VPINSRW xmmreg,xmmreg*,reg32,imm8 [rvmi:t1s16: evex.nds.128.66.0f.wig c4 /r ib ] AVX512BW,FUTURE
+VPINSRW xmmreg,xmmreg*,mem16,imm8 [rvmi:t1s16: evex.nds.128.66.0f.wig c4 /r ib ] AVX512BW,FUTURE
+VPLZCNTD xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.0f38.w0 44 /r ] AVX512VL,AVX512CD,FUTURE
+VPLZCNTD ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.0f38.w0 44 /r ] AVX512VL,AVX512CD,FUTURE
+VPLZCNTD zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 44 /r ] AVX512CD,FUTURE
+VPLZCNTQ xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f38.w1 44 /r ] AVX512VL,AVX512CD,FUTURE
+VPLZCNTQ ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f38.w1 44 /r ] AVX512VL,AVX512CD,FUTURE
+VPLZCNTQ zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 44 /r ] AVX512CD,FUTURE
+VPMADD52HUQ xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 b5 /r ] AVX512VL,AVX512IFMA,FUTURE
+VPMADD52HUQ ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 b5 /r ] AVX512VL,AVX512IFMA,FUTURE
+VPMADD52HUQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 b5 /r ] AVX512IFMA,FUTURE
+VPMADD52LUQ xmmreg|mask|z,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 b4 /r ] AVX512VL,AVX512IFMA,FUTURE
+VPMADD52LUQ ymmreg|mask|z,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 b4 /r ] AVX512VL,AVX512IFMA,FUTURE
+VPMADD52LUQ zmmreg|mask|z,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 b4 /r ] AVX512IFMA,FUTURE
+VPMADDUBSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.wig 04 /r ] AVX512VL,AVX512BW,FUTURE
+VPMADDUBSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.wig 04 /r ] AVX512VL,AVX512BW,FUTURE
+VPMADDUBSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.wig 04 /r ] AVX512BW,FUTURE
+VPMADDWD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig f5 /r ] AVX512VL,AVX512BW,FUTURE
+VPMADDWD ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig f5 /r ] AVX512VL,AVX512BW,FUTURE
+VPMADDWD zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig f5 /r ] AVX512BW,FUTURE
+VPMAXSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.wig 3c /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.wig 3c /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.wig 3c /r ] AVX512BW,FUTURE
+VPMAXSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 3d /r ] AVX512VL,AVX512,FUTURE
+VPMAXSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 3d /r ] AVX512VL,AVX512,FUTURE
+VPMAXSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 3d /r ] AVX512,FUTURE
+VPMAXSQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 3d /r ] AVX512VL,AVX512,FUTURE
+VPMAXSQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 3d /r ] AVX512VL,AVX512,FUTURE
+VPMAXSQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 3d /r ] AVX512,FUTURE
+VPMAXSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig ee /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig ee /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig ee /r ] AVX512BW,FUTURE
+VPMAXUB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig de /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXUB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig de /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXUB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig de /r ] AVX512BW,FUTURE
+VPMAXUD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 3f /r ] AVX512VL,AVX512,FUTURE
+VPMAXUD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 3f /r ] AVX512VL,AVX512,FUTURE
+VPMAXUD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 3f /r ] AVX512,FUTURE
+VPMAXUQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 3f /r ] AVX512VL,AVX512,FUTURE
+VPMAXUQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 3f /r ] AVX512VL,AVX512,FUTURE
+VPMAXUQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 3f /r ] AVX512,FUTURE
+VPMAXUW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.wig 3e /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXUW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.wig 3e /r ] AVX512VL,AVX512BW,FUTURE
+VPMAXUW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.wig 3e /r ] AVX512BW,FUTURE
+VPMINSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.wig 38 /r ] AVX512VL,AVX512BW,FUTURE
+VPMINSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.wig 38 /r ] AVX512VL,AVX512BW,FUTURE
+VPMINSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.wig 38 /r ] AVX512BW,FUTURE
+VPMINSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 39 /r ] AVX512VL,AVX512,FUTURE
+VPMINSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 39 /r ] AVX512VL,AVX512,FUTURE
+VPMINSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 39 /r ] AVX512,FUTURE
+VPMINSQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 39 /r ] AVX512VL,AVX512,FUTURE
+VPMINSQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 39 /r ] AVX512VL,AVX512,FUTURE
+VPMINSQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 39 /r ] AVX512,FUTURE
+VPMINSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig ea /r ] AVX512VL,AVX512BW,FUTURE
+VPMINSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig ea /r ] AVX512VL,AVX512BW,FUTURE
+VPMINSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig ea /r ] AVX512BW,FUTURE
+VPMINUB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig da /r ] AVX512VL,AVX512BW,FUTURE
+VPMINUB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig da /r ] AVX512VL,AVX512BW,FUTURE
+VPMINUB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig da /r ] AVX512BW,FUTURE
+VPMINUD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 3b /r ] AVX512VL,AVX512,FUTURE
+VPMINUD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 3b /r ] AVX512VL,AVX512,FUTURE
+VPMINUD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 3b /r ] AVX512,FUTURE
+VPMINUQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 3b /r ] AVX512VL,AVX512,FUTURE
+VPMINUQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 3b /r ] AVX512VL,AVX512,FUTURE
+VPMINUQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 3b /r ] AVX512,FUTURE
+VPMINUW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.wig 3a /r ] AVX512VL,AVX512BW,FUTURE
+VPMINUW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.wig 3a /r ] AVX512VL,AVX512BW,FUTURE
+VPMINUW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.wig 3a /r ] AVX512BW,FUTURE
+VPMOVB2M kreg,xmmreg [rm: evex.128.f3.0f38.w0 29 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVB2M kreg,ymmreg [rm: evex.256.f3.0f38.w0 29 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVB2M kreg,zmmreg [rm: evex.512.f3.0f38.w0 29 /r ] AVX512BW,FUTURE
+VPMOVD2M kreg,xmmreg [rm: evex.128.f3.0f38.w0 39 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVD2M kreg,ymmreg [rm: evex.256.f3.0f38.w0 39 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVD2M kreg,zmmreg [rm: evex.512.f3.0f38.w0 39 /r ] AVX512DQ,FUTURE
+VPMOVDB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 31 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 31 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 31 /r ] AVX512,FUTURE
+VPMOVDB mem32|mask,xmmreg [mr:qvm: evex.128.f3.0f38.w0 31 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDB mem64|mask,ymmreg [mr:qvm: evex.256.f3.0f38.w0 31 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 31 /r ] AVX512,FUTURE
+VPMOVDW xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 33 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDW xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 33 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDW ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 33 /r ] AVX512,FUTURE
+VPMOVDW mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 33 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDW mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 33 /r ] AVX512VL,AVX512,FUTURE
+VPMOVDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 33 /r ] AVX512,FUTURE
+VPMOVM2B xmmreg,kreg [rm: evex.128.f3.0f38.w0 28 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVM2B ymmreg,kreg [rm: evex.256.f3.0f38.w0 28 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVM2B zmmreg,kreg [rm: evex.512.f3.0f38.w0 28 /r ] AVX512BW,FUTURE
+VPMOVM2D xmmreg,kreg [rm: evex.128.f3.0f38.w0 38 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVM2D ymmreg,kreg [rm: evex.256.f3.0f38.w0 38 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVM2D zmmreg,kreg [rm: evex.512.f3.0f38.w0 38 /r ] AVX512DQ,FUTURE
+VPMOVM2Q xmmreg,kreg [rm: evex.128.f3.0f38.w1 38 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVM2Q ymmreg,kreg [rm: evex.256.f3.0f38.w1 38 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVM2Q zmmreg,kreg [rm: evex.512.f3.0f38.w1 38 /r ] AVX512DQ,FUTURE
+VPMOVM2W xmmreg,kreg [rm: evex.128.f3.0f38.w1 28 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVM2W ymmreg,kreg [rm: evex.256.f3.0f38.w1 28 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVM2W zmmreg,kreg [rm: evex.512.f3.0f38.w1 28 /r ] AVX512BW,FUTURE
+VPMOVQ2M kreg,xmmreg [rm: evex.128.f3.0f38.w1 39 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVQ2M kreg,ymmreg [rm: evex.256.f3.0f38.w1 39 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMOVQ2M kreg,zmmreg [rm: evex.512.f3.0f38.w1 39 /r ] AVX512DQ,FUTURE
+VPMOVQB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 32 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 32 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 32 /r ] AVX512,FUTURE
+VPMOVQB mem16|mask,xmmreg [mr:ovm: evex.128.f3.0f38.w0 32 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQB mem32|mask,ymmreg [mr:ovm: evex.256.f3.0f38.w0 32 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQB mem64|mask,zmmreg [mr:ovm: evex.512.f3.0f38.w0 32 /r ] AVX512,FUTURE
+VPMOVQD xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 35 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQD xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 35 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQD ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 35 /r ] AVX512,FUTURE
+VPMOVQD mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 35 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQD mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 35 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 35 /r ] AVX512,FUTURE
+VPMOVQW xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 34 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQW xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 34 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQW xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 34 /r ] AVX512,FUTURE
+VPMOVQW mem32|mask,xmmreg [mr:qvm: evex.128.f3.0f38.w0 34 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQW mem64|mask,ymmreg [mr:qvm: evex.256.f3.0f38.w0 34 /r ] AVX512VL,AVX512,FUTURE
+VPMOVQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 34 /r ] AVX512,FUTURE
+VPMOVSDB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 21 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 21 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 21 /r ] AVX512,FUTURE
+VPMOVSDB mem32|mask,xmmreg [mr:qvm: evex.128.f3.0f38.w0 21 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDB mem64|mask,ymmreg [mr:qvm: evex.256.f3.0f38.w0 21 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 21 /r ] AVX512,FUTURE
+VPMOVSDW xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 23 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDW xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 23 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDW ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 23 /r ] AVX512,FUTURE
+VPMOVSDW mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 23 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDW mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 23 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 23 /r ] AVX512,FUTURE
+VPMOVSQB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 22 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 22 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 22 /r ] AVX512,FUTURE
+VPMOVSQB mem16|mask,xmmreg [mr:ovm: evex.128.f3.0f38.w0 22 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQB mem32|mask,ymmreg [mr:ovm: evex.256.f3.0f38.w0 22 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQB mem64|mask,zmmreg [mr:ovm: evex.512.f3.0f38.w0 22 /r ] AVX512,FUTURE
+VPMOVSQD xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 25 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQD xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 25 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQD ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 25 /r ] AVX512,FUTURE
+VPMOVSQD mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 25 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQD mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 25 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 25 /r ] AVX512,FUTURE
+VPMOVSQW xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 24 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQW xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 24 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQW xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 24 /r ] AVX512,FUTURE
+VPMOVSQW mem32|mask,xmmreg [mr:qvm: evex.128.f3.0f38.w0 24 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQW mem64|mask,ymmreg [mr:qvm: evex.256.f3.0f38.w0 24 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 24 /r ] AVX512,FUTURE
+VPMOVSWB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 20 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVSWB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 20 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVSWB ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 20 /r ] AVX512BW,FUTURE
+VPMOVSWB mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 20 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVSWB mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 20 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVSWB mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 20 /r ] AVX512BW,FUTURE
+VPMOVSXBD xmmreg|mask|z,xmmrm32 [rm:qvm: evex.128.66.0f38.wig 21 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXBD ymmreg|mask|z,xmmrm64 [rm:qvm: evex.256.66.0f38.wig 21 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXBD zmmreg|mask|z,xmmrm128 [rm:qvm: evex.512.66.0f38.wig 21 /r ] AVX512,FUTURE
+VPMOVSXBQ xmmreg|mask|z,xmmrm16 [rm:ovm: evex.128.66.0f38.wig 22 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXBQ ymmreg|mask|z,xmmrm32 [rm:ovm: evex.256.66.0f38.wig 22 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXBQ zmmreg|mask|z,xmmrm64 [rm:ovm: evex.512.66.0f38.wig 22 /r ] AVX512,FUTURE
+VPMOVSXBW xmmreg|mask|z,xmmrm64 [rm:hvm: evex.128.66.0f38.wig 20 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVSXBW ymmreg|mask|z,xmmrm128 [rm:hvm: evex.256.66.0f38.wig 20 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVSXBW zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.wig 20 /r ] AVX512BW,FUTURE
+VPMOVSXDQ xmmreg|mask|z,xmmrm64 [rm:hvm: evex.128.66.0f38.w0 25 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXDQ ymmreg|mask|z,xmmrm128 [rm:hvm: evex.256.66.0f38.w0 25 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXDQ zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.w0 25 /r ] AVX512,FUTURE
+VPMOVSXWD xmmreg|mask|z,xmmrm64 [rm:hvm: evex.128.66.0f38.wig 23 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXWD ymmreg|mask|z,xmmrm128 [rm:hvm: evex.256.66.0f38.wig 23 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXWD zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.wig 23 /r ] AVX512,FUTURE
+VPMOVSXWQ xmmreg|mask|z,xmmrm32 [rm:qvm: evex.128.66.0f38.wig 24 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXWQ ymmreg|mask|z,xmmrm64 [rm:qvm: evex.256.66.0f38.wig 24 /r ] AVX512VL,AVX512,FUTURE
+VPMOVSXWQ zmmreg|mask|z,xmmrm128 [rm:qvm: evex.512.66.0f38.wig 24 /r ] AVX512,FUTURE
+VPMOVUSDB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 11 /r ] AVX512,FUTURE
+VPMOVUSDB mem32|mask,xmmreg [mr:qvm: evex.128.f3.0f38.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDB mem64|mask,ymmreg [mr:qvm: evex.256.f3.0f38.w0 11 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDB mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 11 /r ] AVX512,FUTURE
+VPMOVUSDW xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 13 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDW xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 13 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDW ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 13 /r ] AVX512,FUTURE
+VPMOVUSDW mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 13 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDW mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 13 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSDW mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 13 /r ] AVX512,FUTURE
+VPMOVUSQB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 12 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 12 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQB xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 12 /r ] AVX512,FUTURE
+VPMOVUSQB mem16|mask,xmmreg [mr:ovm: evex.128.f3.0f38.w0 12 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQB mem32|mask,ymmreg [mr:ovm: evex.256.f3.0f38.w0 12 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQB mem64|mask,zmmreg [mr:ovm: evex.512.f3.0f38.w0 12 /r ] AVX512,FUTURE
+VPMOVUSQD xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQD xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQD ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 15 /r ] AVX512,FUTURE
+VPMOVUSQD mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQD mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQD mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 15 /r ] AVX512,FUTURE
+VPMOVUSQW xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQW xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQW xmmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 14 /r ] AVX512,FUTURE
+VPMOVUSQW mem32|mask,xmmreg [mr:qvm: evex.128.f3.0f38.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQW mem64|mask,ymmreg [mr:qvm: evex.256.f3.0f38.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VPMOVUSQW mem128|mask,zmmreg [mr:qvm: evex.512.f3.0f38.w0 14 /r ] AVX512,FUTURE
+VPMOVUSWB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 10 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVUSWB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 10 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVUSWB ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 10 /r ] AVX512BW,FUTURE
+VPMOVUSWB mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 10 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVUSWB mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 10 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVUSWB mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 10 /r ] AVX512BW,FUTURE
+VPMOVW2M kreg,xmmreg [rm: evex.128.f3.0f38.w1 29 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVW2M kreg,ymmreg [rm: evex.256.f3.0f38.w1 29 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVW2M kreg,zmmreg [rm: evex.512.f3.0f38.w1 29 /r ] AVX512BW,FUTURE
+VPMOVWB xmmreg|mask|z,xmmreg [mr: evex.128.f3.0f38.w0 30 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVWB xmmreg|mask|z,ymmreg [mr: evex.256.f3.0f38.w0 30 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVWB ymmreg|mask|z,zmmreg [mr: evex.512.f3.0f38.w0 30 /r ] AVX512BW,FUTURE
+VPMOVWB mem64|mask,xmmreg [mr:hvm: evex.128.f3.0f38.w0 30 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVWB mem128|mask,ymmreg [mr:hvm: evex.256.f3.0f38.w0 30 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVWB mem256|mask,zmmreg [mr:hvm: evex.512.f3.0f38.w0 30 /r ] AVX512BW,FUTURE
+VPMOVZXBD xmmreg|mask|z,xmmrm32 [rm:qvm: evex.128.66.0f38.wig 31 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXBD ymmreg|mask|z,xmmrm64 [rm:qvm: evex.256.66.0f38.wig 31 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXBD zmmreg|mask|z,xmmrm128 [rm:qvm: evex.512.66.0f38.wig 31 /r ] AVX512,FUTURE
+VPMOVZXBQ xmmreg|mask|z,xmmrm16 [rm:ovm: evex.128.66.0f38.wig 32 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXBQ ymmreg|mask|z,xmmrm32 [rm:ovm: evex.256.66.0f38.wig 32 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXBQ zmmreg|mask|z,xmmrm64 [rm:ovm: evex.512.66.0f38.wig 32 /r ] AVX512,FUTURE
+VPMOVZXBW xmmreg|mask|z,xmmrm64 [rm:hvm: evex.128.66.0f38.wig 30 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVZXBW ymmreg|mask|z,xmmrm128 [rm:hvm: evex.256.66.0f38.wig 30 /r ] AVX512VL,AVX512BW,FUTURE
+VPMOVZXBW zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.wig 30 /r ] AVX512BW,FUTURE
+VPMOVZXDQ xmmreg|mask|z,xmmrm64 [rm:hvm: evex.128.66.0f38.w0 35 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXDQ ymmreg|mask|z,xmmrm128 [rm:hvm: evex.256.66.0f38.w0 35 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXDQ zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.w0 35 /r ] AVX512,FUTURE
+VPMOVZXWD xmmreg|mask|z,xmmrm64 [rm:hvm: evex.128.66.0f38.wig 33 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXWD ymmreg|mask|z,xmmrm128 [rm:hvm: evex.256.66.0f38.wig 33 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXWD zmmreg|mask|z,ymmrm256 [rm:hvm: evex.512.66.0f38.wig 33 /r ] AVX512,FUTURE
+VPMOVZXWQ xmmreg|mask|z,xmmrm32 [rm:qvm: evex.128.66.0f38.wig 34 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXWQ ymmreg|mask|z,xmmrm64 [rm:qvm: evex.256.66.0f38.wig 34 /r ] AVX512VL,AVX512,FUTURE
+VPMOVZXWQ zmmreg|mask|z,xmmrm128 [rm:qvm: evex.512.66.0f38.wig 34 /r ] AVX512,FUTURE
+VPMULDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 28 /r ] AVX512VL,AVX512,FUTURE
+VPMULDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 28 /r ] AVX512VL,AVX512,FUTURE
+VPMULDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 28 /r ] AVX512,FUTURE
+VPMULHRSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.wig 0b /r ] AVX512VL,AVX512BW,FUTURE
+VPMULHRSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.wig 0b /r ] AVX512VL,AVX512BW,FUTURE
+VPMULHRSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.wig 0b /r ] AVX512BW,FUTURE
+VPMULHUW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig e4 /r ] AVX512VL,AVX512BW,FUTURE
+VPMULHUW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig e4 /r ] AVX512VL,AVX512BW,FUTURE
+VPMULHUW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig e4 /r ] AVX512BW,FUTURE
+VPMULHW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig e5 /r ] AVX512VL,AVX512BW,FUTURE
+VPMULHW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig e5 /r ] AVX512VL,AVX512BW,FUTURE
+VPMULHW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig e5 /r ] AVX512BW,FUTURE
+VPMULLD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 40 /r ] AVX512VL,AVX512,FUTURE
+VPMULLD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 40 /r ] AVX512VL,AVX512,FUTURE
+VPMULLD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 40 /r ] AVX512,FUTURE
+VPMULLQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 40 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMULLQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 40 /r ] AVX512VL,AVX512DQ,FUTURE
+VPMULLQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 40 /r ] AVX512DQ,FUTURE
+VPMULLW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig d5 /r ] AVX512VL,AVX512BW,FUTURE
+VPMULLW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig d5 /r ] AVX512VL,AVX512BW,FUTURE
+VPMULLW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig d5 /r ] AVX512BW,FUTURE
+VPMULTISHIFTQB xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 83 /r ] AVX512VL,AVX512VBMI,FUTURE
+VPMULTISHIFTQB ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 83 /r ] AVX512VL,AVX512VBMI,FUTURE
+VPMULTISHIFTQB zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 83 /r ] AVX512VBMI,FUTURE
+VPMULUDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 f4 /r ] AVX512VL,AVX512,FUTURE
+VPMULUDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 f4 /r ] AVX512VL,AVX512,FUTURE
+VPMULUDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 f4 /r ] AVX512,FUTURE
+VPORD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 eb /r ] AVX512VL,AVX512,FUTURE
+VPORD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 eb /r ] AVX512VL,AVX512,FUTURE
+VPORD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 eb /r ] AVX512,FUTURE
+VPORQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 eb /r ] AVX512VL,AVX512,FUTURE
+VPORQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 eb /r ] AVX512VL,AVX512,FUTURE
+VPORQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 eb /r ] AVX512,FUTURE
+VPROLD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv: evex.nds.128.66.0f.w0 72 /1 ib ] AVX512VL,AVX512,FUTURE
+VPROLD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv: evex.nds.256.66.0f.w0 72 /1 ib ] AVX512VL,AVX512,FUTURE
+VPROLD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv: evex.nds.512.66.0f.w0 72 /1 ib ] AVX512,FUTURE
+VPROLQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv: evex.nds.128.66.0f.w1 72 /1 ib ] AVX512VL,AVX512,FUTURE
+VPROLQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv: evex.nds.256.66.0f.w1 72 /1 ib ] AVX512VL,AVX512,FUTURE
+VPROLQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv: evex.nds.512.66.0f.w1 72 /1 ib ] AVX512,FUTURE
+VPROLVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VPROLVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VPROLVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 15 /r ] AVX512,FUTURE
+VPROLVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 15 /r ] AVX512VL,AVX512,FUTURE
+VPROLVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 15 /r ] AVX512VL,AVX512,FUTURE
+VPROLVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 15 /r ] AVX512,FUTURE
+VPRORD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv: evex.nds.128.66.0f.w0 72 /0 ib ] AVX512VL,AVX512,FUTURE
+VPRORD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv: evex.nds.256.66.0f.w0 72 /0 ib ] AVX512VL,AVX512,FUTURE
+VPRORD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv: evex.nds.512.66.0f.w0 72 /0 ib ] AVX512,FUTURE
+VPRORQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv: evex.nds.128.66.0f.w1 72 /0 ib ] AVX512VL,AVX512,FUTURE
+VPRORQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv: evex.nds.256.66.0f.w1 72 /0 ib ] AVX512VL,AVX512,FUTURE
+VPRORQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv: evex.nds.512.66.0f.w1 72 /0 ib ] AVX512,FUTURE
+VPRORVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VPRORVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VPRORVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 14 /r ] AVX512,FUTURE
+VPRORVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 14 /r ] AVX512VL,AVX512,FUTURE
+VPRORVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 14 /r ] AVX512VL,AVX512,FUTURE
+VPRORVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 14 /r ] AVX512,FUTURE
+VPSADBW xmmreg,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig f6 /r ] AVX512VL,AVX512BW,FUTURE
+VPSADBW ymmreg,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig f6 /r ] AVX512VL,AVX512BW,FUTURE
+VPSADBW zmmreg,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig f6 /r ] AVX512BW,FUTURE
+VPSCATTERDD xmem32|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w0 a0 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERDD ymem32|mask,ymmreg [mr:t1s: vsiby evex.256.66.0f38.w0 a0 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERDD zmem32|mask,zmmreg [mr:t1s: vsibz evex.512.66.0f38.w0 a0 /r ] AVX512,FUTURE
+VPSCATTERDQ xmem64|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w1 a0 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERDQ xmem64|mask,ymmreg [mr:t1s: vsibx evex.256.66.0f38.w1 a0 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERDQ ymem64|mask,zmmreg [mr:t1s: vsiby evex.512.66.0f38.w1 a0 /r ] AVX512,FUTURE
+VPSCATTERQD xmem32|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w0 a1 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERQD ymem32|mask,xmmreg [mr:t1s: vsiby evex.256.66.0f38.w0 a1 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERQD zmem32|mask,ymmreg [mr:t1s: vsibz evex.512.66.0f38.w0 a1 /r ] AVX512,FUTURE
+VPSCATTERQQ xmem64|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w1 a1 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERQQ ymem64|mask,ymmreg [mr:t1s: vsiby evex.256.66.0f38.w1 a1 /r ] AVX512VL,AVX512,FUTURE
+VPSCATTERQQ zmem64|mask,zmmreg [mr:t1s: vsibz evex.512.66.0f38.w1 a1 /r ] AVX512,FUTURE
+VPSHUFB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.wig 00 /r ] AVX512VL,AVX512BW,FUTURE
+VPSHUFB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.wig 00 /r ] AVX512VL,AVX512BW,FUTURE
+VPSHUFB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.wig 00 /r ] AVX512BW,FUTURE
+VPSHUFD xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv: evex.128.66.0f.w0 70 /r ib ] AVX512VL,AVX512,FUTURE
+VPSHUFD ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv: evex.256.66.0f.w0 70 /r ib ] AVX512VL,AVX512,FUTURE
+VPSHUFD zmmreg|mask|z,zmmrm512|b32,imm8 [rmi:fv: evex.512.66.0f.w0 70 /r ib ] AVX512,FUTURE
+VPSHUFHW xmmreg|mask|z,xmmrm128,imm8 [rmi:fvm: evex.128.f3.0f.wig 70 /r ib ] AVX512VL,AVX512BW,FUTURE
+VPSHUFHW ymmreg|mask|z,ymmrm256,imm8 [rmi:fvm: evex.256.f3.0f.wig 70 /r ib ] AVX512VL,AVX512BW,FUTURE
+VPSHUFHW zmmreg|mask|z,zmmrm512,imm8 [rmi:fvm: evex.512.f3.0f.wig 70 /r ib ] AVX512BW,FUTURE
+VPSHUFLW xmmreg|mask|z,xmmrm128,imm8 [rmi:fvm: evex.128.f2.0f.wig 70 /r ib ] AVX512VL,AVX512BW,FUTURE
+VPSHUFLW ymmreg|mask|z,ymmrm256,imm8 [rmi:fvm: evex.256.f2.0f.wig 70 /r ib ] AVX512VL,AVX512BW,FUTURE
+VPSHUFLW zmmreg|mask|z,zmmrm512,imm8 [rmi:fvm: evex.512.f2.0f.wig 70 /r ib ] AVX512BW,FUTURE
+VPSLLD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w0 f2 /r ] AVX512VL,AVX512,FUTURE
+VPSLLD ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w0 f2 /r ] AVX512VL,AVX512,FUTURE
+VPSLLD zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 f2 /r ] AVX512,FUTURE
+VPSLLD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv: evex.nds.128.66.0f.w0 72 /6 ib ] AVX512VL,AVX512,FUTURE
+VPSLLD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv: evex.nds.256.66.0f.w0 72 /6 ib ] AVX512VL,AVX512,FUTURE
+VPSLLD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv: evex.nds.512.66.0f.w0 72 /6 ib ] AVX512,FUTURE
+VPSLLDQ xmmreg,xmmrm128*,imm8 [vmi:fvm: evex.nds.128.66.0f.wig 73 /7 ib ] AVX512VL,AVX512BW,FUTURE
+VPSLLDQ ymmreg,ymmrm256*,imm8 [vmi:fvm: evex.nds.256.66.0f.wig 73 /7 ib ] AVX512VL,AVX512BW,FUTURE
+VPSLLDQ zmmreg,zmmrm512*,imm8 [vmi:fvm: evex.nds.512.66.0f.wig 73 /7 ib ] AVX512BW,FUTURE
+VPSLLQ xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w1 f3 /r ] AVX512VL,AVX512,FUTURE
+VPSLLQ ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w1 f3 /r ] AVX512VL,AVX512,FUTURE
+VPSLLQ zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 f3 /r ] AVX512,FUTURE
+VPSLLQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv: evex.nds.128.66.0f.w1 73 /6 ib ] AVX512VL,AVX512,FUTURE
+VPSLLQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv: evex.nds.256.66.0f.w1 73 /6 ib ] AVX512VL,AVX512,FUTURE
+VPSLLQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv: evex.nds.512.66.0f.w1 73 /6 ib ] AVX512,FUTURE
+VPSLLVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 47 /r ] AVX512VL,AVX512,FUTURE
+VPSLLVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 47 /r ] AVX512VL,AVX512,FUTURE
+VPSLLVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 47 /r ] AVX512,FUTURE
+VPSLLVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 47 /r ] AVX512VL,AVX512,FUTURE
+VPSLLVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 47 /r ] AVX512VL,AVX512,FUTURE
+VPSLLVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 47 /r ] AVX512,FUTURE
+VPSLLVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 12 /r ] AVX512VL,AVX512BW,FUTURE
+VPSLLVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 12 /r ] AVX512VL,AVX512BW,FUTURE
+VPSLLVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 12 /r ] AVX512BW,FUTURE
+VPSLLW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.wig f1 /r ] AVX512VL,AVX512BW,FUTURE
+VPSLLW ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.wig f1 /r ] AVX512VL,AVX512BW,FUTURE
+VPSLLW zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.wig f1 /r ] AVX512BW,FUTURE
+VPSLLW xmmreg|mask|z,xmmrm128*,imm8 [vmi:fvm: evex.nds.128.66.0f.wig 71 /6 ib ] AVX512VL,AVX512BW,FUTURE
+VPSLLW ymmreg|mask|z,ymmrm256*,imm8 [vmi:fvm: evex.nds.256.66.0f.wig 71 /6 ib ] AVX512VL,AVX512BW,FUTURE
+VPSLLW zmmreg|mask|z,zmmrm512*,imm8 [vmi:fvm: evex.nds.512.66.0f.wig 71 /6 ib ] AVX512BW,FUTURE
+VPSRAD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w0 e2 /r ] AVX512VL,AVX512,FUTURE
+VPSRAD ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w0 e2 /r ] AVX512VL,AVX512,FUTURE
+VPSRAD zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 e2 /r ] AVX512,FUTURE
+VPSRAD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv: evex.nds.128.66.0f.w0 72 /4 ib ] AVX512VL,AVX512,FUTURE
+VPSRAD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv: evex.nds.256.66.0f.w0 72 /4 ib ] AVX512VL,AVX512,FUTURE
+VPSRAD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv: evex.nds.512.66.0f.w0 72 /4 ib ] AVX512,FUTURE
+VPSRAQ xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w1 e2 /r ] AVX512VL,AVX512,FUTURE
+VPSRAQ ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w1 e2 /r ] AVX512VL,AVX512,FUTURE
+VPSRAQ zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 e2 /r ] AVX512,FUTURE
+VPSRAQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv: evex.nds.128.66.0f.w1 72 /4 ib ] AVX512VL,AVX512,FUTURE
+VPSRAQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv: evex.nds.256.66.0f.w1 72 /4 ib ] AVX512VL,AVX512,FUTURE
+VPSRAQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv: evex.nds.512.66.0f.w1 72 /4 ib ] AVX512,FUTURE
+VPSRAVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 46 /r ] AVX512VL,AVX512,FUTURE
+VPSRAVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 46 /r ] AVX512VL,AVX512,FUTURE
+VPSRAVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 46 /r ] AVX512,FUTURE
+VPSRAVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 46 /r ] AVX512VL,AVX512,FUTURE
+VPSRAVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 46 /r ] AVX512VL,AVX512,FUTURE
+VPSRAVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 46 /r ] AVX512,FUTURE
+VPSRAVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 11 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRAVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 11 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRAVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 11 /r ] AVX512BW,FUTURE
+VPSRAW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.wig e1 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRAW ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.wig e1 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRAW zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.wig e1 /r ] AVX512BW,FUTURE
+VPSRAW xmmreg|mask|z,xmmrm128*,imm8 [vmi:fvm: evex.nds.128.66.0f.wig 71 /4 ib ] AVX512VL,AVX512BW,FUTURE
+VPSRAW ymmreg|mask|z,ymmrm256*,imm8 [vmi:fvm: evex.nds.256.66.0f.wig 71 /4 ib ] AVX512VL,AVX512BW,FUTURE
+VPSRAW zmmreg|mask|z,zmmrm512*,imm8 [vmi:fvm: evex.nds.512.66.0f.wig 71 /4 ib ] AVX512BW,FUTURE
+VPSRLD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w0 d2 /r ] AVX512VL,AVX512,FUTURE
+VPSRLD ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w0 d2 /r ] AVX512VL,AVX512,FUTURE
+VPSRLD zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w0 d2 /r ] AVX512,FUTURE
+VPSRLD xmmreg|mask|z,xmmrm128|b32*,imm8 [vmi:fv: evex.nds.128.66.0f.w0 72 /2 ib ] AVX512VL,AVX512,FUTURE
+VPSRLD ymmreg|mask|z,ymmrm256|b32*,imm8 [vmi:fv: evex.nds.256.66.0f.w0 72 /2 ib ] AVX512VL,AVX512,FUTURE
+VPSRLD zmmreg|mask|z,zmmrm512|b32*,imm8 [vmi:fv: evex.nds.512.66.0f.w0 72 /2 ib ] AVX512,FUTURE
+VPSRLDQ xmmreg,xmmrm128*,imm8 [vmi:fvm: evex.nds.128.66.0f.wig 73 /3 ib ] AVX512VL,AVX512BW,FUTURE
+VPSRLDQ ymmreg,ymmrm256*,imm8 [vmi:fvm: evex.nds.256.66.0f.wig 73 /3 ib ] AVX512VL,AVX512BW,FUTURE
+VPSRLDQ zmmreg,zmmrm512*,imm8 [vmi:fvm: evex.nds.512.66.0f.wig 73 /3 ib ] AVX512BW,FUTURE
+VPSRLQ xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.w1 d3 /r ] AVX512VL,AVX512,FUTURE
+VPSRLQ ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.w1 d3 /r ] AVX512VL,AVX512,FUTURE
+VPSRLQ zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.w1 d3 /r ] AVX512,FUTURE
+VPSRLQ xmmreg|mask|z,xmmrm128|b64*,imm8 [vmi:fv: evex.nds.128.66.0f.w1 73 /2 ib ] AVX512VL,AVX512,FUTURE
+VPSRLQ ymmreg|mask|z,ymmrm256|b64*,imm8 [vmi:fv: evex.nds.256.66.0f.w1 73 /2 ib ] AVX512VL,AVX512,FUTURE
+VPSRLQ zmmreg|mask|z,zmmrm512|b64*,imm8 [vmi:fv: evex.nds.512.66.0f.w1 73 /2 ib ] AVX512,FUTURE
+VPSRLVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 45 /r ] AVX512VL,AVX512,FUTURE
+VPSRLVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 45 /r ] AVX512VL,AVX512,FUTURE
+VPSRLVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 45 /r ] AVX512,FUTURE
+VPSRLVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 45 /r ] AVX512VL,AVX512,FUTURE
+VPSRLVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 45 /r ] AVX512VL,AVX512,FUTURE
+VPSRLVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 45 /r ] AVX512,FUTURE
+VPSRLVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 10 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRLVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 10 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRLVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 10 /r ] AVX512BW,FUTURE
+VPSRLW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:m128: evex.nds.128.66.0f.wig d1 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRLW ymmreg|mask|z,ymmreg*,xmmrm128 [rvm:m128: evex.nds.256.66.0f.wig d1 /r ] AVX512VL,AVX512BW,FUTURE
+VPSRLW zmmreg|mask|z,zmmreg*,xmmrm128 [rvm:m128: evex.nds.512.66.0f.wig d1 /r ] AVX512BW,FUTURE
+VPSRLW xmmreg|mask|z,xmmrm128*,imm8 [vmi:fvm: evex.nds.128.66.0f.wig 71 /2 ib ] AVX512VL,AVX512BW,FUTURE
+VPSRLW ymmreg|mask|z,ymmrm256*,imm8 [vmi:fvm: evex.nds.256.66.0f.wig 71 /2 ib ] AVX512VL,AVX512BW,FUTURE
+VPSRLW zmmreg|mask|z,zmmrm512*,imm8 [vmi:fvm: evex.nds.512.66.0f.wig 71 /2 ib ] AVX512BW,FUTURE
+VPSUBB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig f8 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig f8 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig f8 /r ] AVX512BW,FUTURE
+VPSUBD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 fa /r ] AVX512VL,AVX512,FUTURE
+VPSUBD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 fa /r ] AVX512VL,AVX512,FUTURE
+VPSUBD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 fa /r ] AVX512,FUTURE
+VPSUBQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 fb /r ] AVX512VL,AVX512,FUTURE
+VPSUBQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 fb /r ] AVX512VL,AVX512,FUTURE
+VPSUBQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 fb /r ] AVX512,FUTURE
+VPSUBSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig e8 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig e8 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig e8 /r ] AVX512BW,FUTURE
+VPSUBSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig e9 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig e9 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig e9 /r ] AVX512BW,FUTURE
+VPSUBUSB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig d8 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBUSB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig d8 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBUSB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig d8 /r ] AVX512BW,FUTURE
+VPSUBUSW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig d9 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBUSW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig d9 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBUSW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig d9 /r ] AVX512BW,FUTURE
+VPSUBW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig f9 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig f9 /r ] AVX512VL,AVX512BW,FUTURE
+VPSUBW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig f9 /r ] AVX512BW,FUTURE
+VPTERNLOGD xmmreg|mask|z,xmmreg,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 25 /r ib ] AVX512VL,AVX512,FUTURE
+VPTERNLOGD ymmreg|mask|z,ymmreg,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 25 /r ib ] AVX512VL,AVX512,FUTURE
+VPTERNLOGD zmmreg|mask|z,zmmreg,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 25 /r ib ] AVX512,FUTURE
+VPTERNLOGQ xmmreg|mask|z,xmmreg,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 25 /r ib ] AVX512VL,AVX512,FUTURE
+VPTERNLOGQ ymmreg|mask|z,ymmreg,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 25 /r ib ] AVX512VL,AVX512,FUTURE
+VPTERNLOGQ zmmreg|mask|z,zmmreg,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 25 /r ib ] AVX512,FUTURE
+VPTESTMB kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w0 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTMB kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w0 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTMB kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w0 26 /r ] AVX512BW,FUTURE
+VPTESTMD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTMD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f38.w0 27 /r ] AVX512,FUTURE
+VPTESTMQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTMQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f38.w1 27 /r ] AVX512,FUTURE
+VPTESTMW kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w1 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTMW kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w1 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTMW kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w1 26 /r ] AVX512BW,FUTURE
+VPTESTNMB kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.f3.0f38.w0 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTNMB kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.f3.0f38.w0 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTNMB kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.f3.0f38.w0 26 /r ] AVX512BW,FUTURE
+VPTESTNMD kreg|mask,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.f3.0f38.w0 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTNMD kreg|mask,ymmreg,ymmrm256|b32 [rvm:fv: evex.nds.256.f3.0f38.w0 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTNMD kreg|mask,zmmreg,zmmrm512|b32 [rvm:fv: evex.nds.512.f3.0f38.w0 27 /r ] AVX512,FUTURE
+VPTESTNMQ kreg|mask,xmmreg,xmmrm128|b64 [rvm:fv: evex.nds.128.f3.0f38.w1 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTNMQ kreg|mask,ymmreg,ymmrm256|b64 [rvm:fv: evex.nds.256.f3.0f38.w1 27 /r ] AVX512VL,AVX512,FUTURE
+VPTESTNMQ kreg|mask,zmmreg,zmmrm512|b64 [rvm:fv: evex.nds.512.f3.0f38.w1 27 /r ] AVX512,FUTURE
+VPTESTNMW kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.f3.0f38.w1 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTNMW kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.f3.0f38.w1 26 /r ] AVX512VL,AVX512BW,FUTURE
+VPTESTNMW kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.f3.0f38.w1 26 /r ] AVX512BW,FUTURE
+VPUNPCKHBW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 68 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKHBW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 68 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKHBW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 68 /r ] AVX512BW,FUTURE
+VPUNPCKHDQ xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 6a /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKHDQ ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 6a /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKHDQ zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 6a /r ] AVX512,FUTURE
+VPUNPCKHQDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 6d /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKHQDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 6d /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKHQDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 6d /r ] AVX512,FUTURE
+VPUNPCKHWD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 69 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKHWD ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 69 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKHWD zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 69 /r ] AVX512BW,FUTURE
+VPUNPCKLBW xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 60 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKLBW ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 60 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKLBW zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 60 /r ] AVX512BW,FUTURE
+VPUNPCKLDQ xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 62 /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKLDQ ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 62 /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKLDQ zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 62 /r ] AVX512,FUTURE
+VPUNPCKLQDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 6c /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKLQDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 6c /r ] AVX512VL,AVX512,FUTURE
+VPUNPCKLQDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 6c /r ] AVX512,FUTURE
+VPUNPCKLWD xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f.wig 61 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKLWD ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f.wig 61 /r ] AVX512VL,AVX512BW,FUTURE
+VPUNPCKLWD zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f.wig 61 /r ] AVX512BW,FUTURE
+VPXORD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f.w0 ef /r ] AVX512VL,AVX512,FUTURE
+VPXORD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f.w0 ef /r ] AVX512VL,AVX512,FUTURE
+VPXORD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.66.0f.w0 ef /r ] AVX512,FUTURE
+VPXORQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 ef /r ] AVX512VL,AVX512,FUTURE
+VPXORQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 ef /r ] AVX512VL,AVX512,FUTURE
+VPXORQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 ef /r ] AVX512,FUTURE
+VRANGEPD xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 50 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VRANGEPD ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 50 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VRANGEPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|sae,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 50 /r ib ] AVX512DQ,FUTURE
+VRANGEPS xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 50 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VRANGEPS ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 50 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VRANGEPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|sae,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 50 /r ib ] AVX512DQ,FUTURE
+VRANGESD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w1 51 /r ib ] AVX512DQ,FUTURE
+VRANGESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 51 /r ib ] AVX512DQ,FUTURE
+VRCP14PD xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f38.w1 4c /r ] AVX512VL,AVX512,FUTURE
+VRCP14PD ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f38.w1 4c /r ] AVX512VL,AVX512,FUTURE
+VRCP14PD zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 4c /r ] AVX512,FUTURE
+VRCP14PS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.0f38.w0 4c /r ] AVX512VL,AVX512,FUTURE
+VRCP14PS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.0f38.w0 4c /r ] AVX512VL,AVX512,FUTURE
+VRCP14PS zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 4c /r ] AVX512,FUTURE
+VRCP14SD xmmreg|mask|z,xmmreg*,xmmrm64 [rvm:t1s: evex.nds.128.66.0f38.w1 4d /r ] AVX512,FUTURE
+VRCP14SS xmmreg|mask|z,xmmreg*,xmmrm32 [rvm:t1s: evex.nds.128.66.0f38.w0 4d /r ] AVX512,FUTURE
+VRCP28PD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f38.w1 ca /r ] AVX512ER,FUTURE
+VRCP28PS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.66.0f38.w0 ca /r ] AVX512ER,FUTURE
+VRCP28SD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s: evex.nds.128.66.0f38.w1 cb /r ] AVX512ER,FUTURE
+VRCP28SS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s: evex.nds.128.66.0f38.w0 cb /r ] AVX512ER,FUTURE
+VREDUCEPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv: evex.128.66.0f3a.w1 56 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VREDUCEPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 56 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VREDUCEPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [rmi:fv: evex.512.66.0f3a.w1 56 /r ib ] AVX512DQ,FUTURE
+VREDUCEPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv: evex.128.66.0f3a.w0 56 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VREDUCEPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv: evex.256.66.0f3a.w0 56 /r ib ] AVX512VL,AVX512DQ,FUTURE
+VREDUCEPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [rmi:fv: evex.512.66.0f3a.w0 56 /r ib ] AVX512DQ,FUTURE
+VREDUCESD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w1 57 /r ib ] AVX512DQ,FUTURE
+VREDUCESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 57 /r ib ] AVX512DQ,FUTURE
+VRNDSCALEPD xmmreg|mask|z,xmmrm128|b64,imm8 [rmi:fv: evex.128.66.0f3a.w1 09 /r ib ] AVX512VL,AVX512,FUTURE
+VRNDSCALEPD ymmreg|mask|z,ymmrm256|b64,imm8 [rmi:fv: evex.256.66.0f3a.w1 09 /r ib ] AVX512VL,AVX512,FUTURE
+VRNDSCALEPD zmmreg|mask|z,zmmrm512|b64|sae,imm8 [rmi:fv: evex.512.66.0f3a.w1 09 /r ib ] AVX512,FUTURE
+VRNDSCALEPS xmmreg|mask|z,xmmrm128|b32,imm8 [rmi:fv: evex.128.66.0f3a.w0 08 /r ib ] AVX512VL,AVX512,FUTURE
+VRNDSCALEPS ymmreg|mask|z,ymmrm256|b32,imm8 [rmi:fv: evex.256.66.0f3a.w0 08 /r ib ] AVX512VL,AVX512,FUTURE
+VRNDSCALEPS zmmreg|mask|z,zmmrm512|b32|sae,imm8 [rmi:fv: evex.512.66.0f3a.w0 08 /r ib ] AVX512,FUTURE
+VRNDSCALESD xmmreg|mask|z,xmmreg*,xmmrm64|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w1 0b /r ib ] AVX512,FUTURE
+VRNDSCALESS xmmreg|mask|z,xmmreg*,xmmrm32|sae,imm8 [rvmi:t1s: evex.nds.128.66.0f3a.w0 0a /r ib ] AVX512,FUTURE
+VRSQRT14PD xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f38.w1 4e /r ] AVX512VL,AVX512,FUTURE
+VRSQRT14PD ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f38.w1 4e /r ] AVX512VL,AVX512,FUTURE
+VRSQRT14PD zmmreg|mask|z,zmmrm512|b64 [rm:fv: evex.512.66.0f38.w1 4e /r ] AVX512,FUTURE
+VRSQRT14PS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.0f38.w0 4e /r ] AVX512VL,AVX512,FUTURE
+VRSQRT14PS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.0f38.w0 4e /r ] AVX512VL,AVX512,FUTURE
+VRSQRT14PS zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.66.0f38.w0 4e /r ] AVX512,FUTURE
+VRSQRT14SD xmmreg|mask|z,xmmreg*,xmmrm64 [rvm:t1s: evex.nds.128.66.0f38.w1 4f /r ] AVX512,FUTURE
+VRSQRT14SS xmmreg|mask|z,xmmreg*,xmmrm32 [rvm:t1s: evex.nds.128.66.0f38.w0 4f /r ] AVX512,FUTURE
+VRSQRT28PD zmmreg|mask|z,zmmrm512|b64|sae [rm:fv: evex.512.66.0f38.w1 cc /r ] AVX512ER,FUTURE
+VRSQRT28PS zmmreg|mask|z,zmmrm512|b32|sae [rm:fv: evex.512.66.0f38.w0 cc /r ] AVX512ER,FUTURE
+VRSQRT28SD xmmreg|mask|z,xmmreg*,xmmrm64|sae [rvm:t1s: evex.nds.128.66.0f38.w1 cd /r ] AVX512ER,FUTURE
+VRSQRT28SS xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s: evex.nds.128.66.0f38.w0 cd /r ] AVX512ER,FUTURE
+VSCALEFPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f38.w1 2c /r ] AVX512VL,AVX512,FUTURE
+VSCALEFPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f38.w1 2c /r ] AVX512VL,AVX512,FUTURE
+VSCALEFPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f38.w1 2c /r ] AVX512,FUTURE
+VSCALEFPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.66.0f38.w0 2c /r ] AVX512VL,AVX512,FUTURE
+VSCALEFPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.66.0f38.w0 2c /r ] AVX512VL,AVX512,FUTURE
+VSCALEFPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.66.0f38.w0 2c /r ] AVX512,FUTURE
+VSCALEFSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.128.66.0f38.w1 2d /r ] AVX512,FUTURE
+VSCALEFSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.128.66.0f38.w0 2d /r ] AVX512,FUTURE
+VSCATTERDPD xmem64|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w1 a2 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERDPD xmem64|mask,ymmreg [mr:t1s: vsibx evex.256.66.0f38.w1 a2 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERDPD ymem64|mask,zmmreg [mr:t1s: vsiby evex.512.66.0f38.w1 a2 /r ] AVX512,FUTURE
+VSCATTERDPS xmem32|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w0 a2 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERDPS ymem32|mask,ymmreg [mr:t1s: vsiby evex.256.66.0f38.w0 a2 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERDPS zmem32|mask,zmmreg [mr:t1s: vsibz evex.512.66.0f38.w0 a2 /r ] AVX512,FUTURE
+VSCATTERPF0DPD ymem64|mask [m:t1s: vsiby evex.512.66.0f38.w1 c6 /5 ] AVX512PF,FUTURE
+VSCATTERPF0DPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c6 /5 ] AVX512PF,FUTURE
+VSCATTERPF0QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /5 ] AVX512PF,FUTURE
+VSCATTERPF0QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /5 ] AVX512PF,FUTURE
+VSCATTERPF1DPD ymem64|mask [m:t1s: vsiby evex.512.66.0f38.w1 c6 /6 ] AVX512PF,FUTURE
+VSCATTERPF1DPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c6 /6 ] AVX512PF,FUTURE
+VSCATTERPF1QPD zmem64|mask [m:t1s: vsibz evex.512.66.0f38.w1 c7 /6 ] AVX512PF,FUTURE
+VSCATTERPF1QPS zmem32|mask [m:t1s: vsibz evex.512.66.0f38.w0 c7 /6 ] AVX512PF,FUTURE
+VSCATTERQPD xmem64|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w1 a3 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERQPD ymem64|mask,ymmreg [mr:t1s: vsiby evex.256.66.0f38.w1 a3 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERQPD zmem64|mask,zmmreg [mr:t1s: vsibz evex.512.66.0f38.w1 a3 /r ] AVX512,FUTURE
+VSCATTERQPS xmem32|mask,xmmreg [mr:t1s: vsibx evex.128.66.0f38.w0 a3 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERQPS ymem32|mask,xmmreg [mr:t1s: vsiby evex.256.66.0f38.w0 a3 /r ] AVX512VL,AVX512,FUTURE
+VSCATTERQPS zmem32|mask,ymmreg [mr:t1s: vsibz evex.512.66.0f38.w0 a3 /r ] AVX512,FUTURE
+VSHUFF32X4 ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 23 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFF32X4 zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 23 /r ib ] AVX512,FUTURE
+VSHUFF64X2 ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 23 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFF64X2 zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 23 /r ib ] AVX512,FUTURE
+VSHUFI32X4 ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 43 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFI32X4 zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 43 /r ib ] AVX512,FUTURE
+VSHUFI64X2 ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 43 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFI64X2 zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 43 /r ib ] AVX512,FUTURE
+VSHUFPD xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f.w1 c6 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFPD ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f.w1 c6 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFPD zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f.w1 c6 /r ib ] AVX512,FUTURE
+VSHUFPS xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.0f.w0 c6 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFPS ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.0f.w0 c6 /r ib ] AVX512VL,AVX512,FUTURE
+VSHUFPS zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.0f.w0 c6 /r ib ] AVX512,FUTURE
+VSQRTPD xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.0f.w1 51 /r ] AVX512VL,AVX512,FUTURE
+VSQRTPD ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.0f.w1 51 /r ] AVX512VL,AVX512,FUTURE
+VSQRTPD zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.66.0f.w1 51 /r ] AVX512,FUTURE
+VSQRTPS xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.0f.w0 51 /r ] AVX512VL,AVX512,FUTURE
+VSQRTPS ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.0f.w0 51 /r ] AVX512VL,AVX512,FUTURE
+VSQRTPS zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.0f.w0 51 /r ] AVX512,FUTURE
+VSQRTSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.128.f2.0f.w1 51 /r ] AVX512,FUTURE
+VSQRTSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.128.f3.0f.w0 51 /r ] AVX512,FUTURE
+VSUBPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 5c /r ] AVX512VL,AVX512,FUTURE
+VSUBPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 5c /r ] AVX512VL,AVX512,FUTURE
+VSUBPD zmmreg|mask|z,zmmreg*,zmmrm512|b64|er [rvm:fv: evex.nds.512.66.0f.w1 5c /r ] AVX512,FUTURE
+VSUBPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 5c /r ] AVX512VL,AVX512,FUTURE
+VSUBPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 5c /r ] AVX512VL,AVX512,FUTURE
+VSUBPS zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.0f.w0 5c /r ] AVX512,FUTURE
+VSUBSD xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.128.f2.0f.w1 5c /r ] AVX512,FUTURE
+VSUBSS xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.128.f3.0f.w0 5c /r ] AVX512,FUTURE
+VUCOMISD xmmreg,xmmrm64|sae [rm:t1s: evex.128.66.0f.w1 2e /r ] AVX512,FUTURE
+VUCOMISS xmmreg,xmmrm32|sae [rm:t1s: evex.128.0f.w0 2e /r ] AVX512,FUTURE
+VUNPCKHPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 15 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKHPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 15 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKHPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 15 /r ] AVX512,FUTURE
+VUNPCKHPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKHPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 15 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKHPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.0f.w0 15 /r ] AVX512,FUTURE
+VUNPCKLPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 14 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKLPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 14 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKLPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 14 /r ] AVX512,FUTURE
+VUNPCKLPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKLPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 14 /r ] AVX512VL,AVX512,FUTURE
+VUNPCKLPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.0f.w0 14 /r ] AVX512,FUTURE
+VXORPD xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvm:fv: evex.nds.128.66.0f.w1 57 /r ] AVX512VL,AVX512DQ,FUTURE
+VXORPD ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvm:fv: evex.nds.256.66.0f.w1 57 /r ] AVX512VL,AVX512DQ,FUTURE
+VXORPD zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvm:fv: evex.nds.512.66.0f.w1 57 /r ] AVX512DQ,FUTURE
+VXORPS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.0f.w0 57 /r ] AVX512VL,AVX512DQ,FUTURE
+VXORPS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.0f.w0 57 /r ] AVX512VL,AVX512DQ,FUTURE
+VXORPS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.nds.512.0f.w0 57 /r ] AVX512DQ,FUTURE
+; MJC PUBLIC END
+
+;# Intel memory protection keys for userspace (PKU aka PKEYs)
+RDPKRU void [ 0f 01 ee] LONG,FUTURE
+WRPKRU void [ 0f 01 ef] LONG,FUTURE
+
+;# Read Processor ID
+RDPID reg32 [m: f3 0f c7 /7] NOLONG,FUTURE
+RDPID reg64 [m: o64nw f3 0f c7 /7] LONG,FUTURE
+RDPID reg32 [m: f3 0f c7 /7] LONG,UNDOC,FUTURE
+
+;# New memory instructions
+CLFLUSHOPT mem [m: 66 0f ae /7] FUTURE
+CLWB mem [m: 66 0f ae /6] FUTURE
+; This one was killed before it saw the light of day
+PCOMMIT void [ 66 0f ae f8] FUTURE,NEVER,NOP
+
+; AMD Zen v1
+CLZERO void [ 0f 01 fc] FUTURE,AMD
+CLZERO reg_ax [-: a16 0f 01 fc] FUTURE,AMD,ND,NOLONG
+CLZERO reg_eax [-: a32 0f 01 fc] FUTURE,AMD,ND
+CLZERO reg_rax [-: a64 0f 01 fc] FUTURE,AMD,ND,LONG
+
+;# Processor trace write
+PTWRITE rm32 [m: np 0f ae /4] FUTURE
+PTWRITE rm64 [m: o64 np 0f ae /4] LONG,FUTURE
+
+;# Instructions from the Intel Instruction Set Extensions,
+;# doc 319433-034 May 2018
+CLDEMOTE mem [m: np 0f 1c /0] FUTURE
+MOVDIRI mem32,reg32 [mr: np 0f 38 f9 /r] FUTURE,SD
+MOVDIRI mem64,reg64 [mr: o64 0f 38 f9 /r] FUTURE,LONG,SQ
+MOVDIR64B reg16,mem512 [rm: a16 66 0f 38 f8 /r] FUTURE,NOLONG
+MOVDIR64B reg32,mem512 [rm: a32 66 0f 38 f8 /r] FUTURE
+MOVDIR64B reg64,mem512 [rm: o64nw a64 66 0f 38 f8 /r] FUTURE,LONG
+PCONFIG void [ np 0f 01 c5] FUTURE
+TPAUSE reg32 [m: 66 0f ae /6] FUTURE
+TPAUSE reg32,reg_edx,reg_eax [m--: 66 0f ae /6] FUTURE,ND
+UMONITOR reg16 [m: a16 f3 0f ae /6] FUTURE,NOLONG
+UMONITOR reg32 [m: a32 f3 0f ae /6] FUTURE
+UMONITOR reg64 [m: o64nw a64 f3 0f ae /6] FUTURE,LONG
+UMWAIT reg32 [m: f2 0f ae /6] FUTURE
+UMWAIT reg32,reg_edx,reg_eax [m--: f2 0f ae /6] FUTURE,ND
+WBNOINVD void [ f3 0f 09] FUTURE
+
+;# Galois field operations (GFNI)
+GF2P8AFFINEINVQB xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a cf /r ib] GFNI,SSE,FUTURE
+VGF2P8AFFINEINVQB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a.w1 cf /r ib] GFNI,AVX,FUTURE
+VGF2P8AFFINEINVQB ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a.w1 cf /r ib] GFNI,AVX,FUTURE
+VGF2P8AFFINEINVQB xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 cf /r ib] GFNI,AVX512VL,FUTURE
+VGF2P8AFFINEINVQB ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 cf /r ib] GFNI,AVX512VL,FUTURE
+VGF2P8AFFINEINVQB zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 cf /r ib] GFNI,AVX512,FUTURE
+GF2P8AFFINEQB xmmreg,xmmrm128,imm8 [rmi: 66 0f 3a ce /r ib] GFNI,SSE,FUTURE
+VGF2P8AFFINEQB xmmreg,xmmreg*,xmmrm128,imm8 [rvmi: vex.nds.128.66.0f3a.w1 ce /r ib] GFNI,AVX,FUTURE
+VGF2P8AFFINEQB ymmreg,ymmreg*,ymmrm256,imm8 [rvmi: vex.nds.256.66.0f3a.w1 ce /r ib] GFNI,AVX,FUTURE
+VGF2P8AFFINEQB xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 ce /r ib] GFNI,AVX512VL,FUTURE
+VGF2P8AFFINEQB ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 ce /r ib] GFNI,AVX512VL,FUTURE
+VGF2P8AFFINEQB zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 ce /r ib] GFNI,AVX512,FUTURE
+GF2P8MULB xmmreg,xmmrm128 [rm: 66 0f 38 cf /r] GFNI,SSE,FUTURE
+VGF2P8MULB xmmreg,xmmreg*,xmmrm128 [rvm: vex.nds.128.66.0f38.w0 cf /r] GFNI,AVX,FUTURE
+VGF2P8MULB ymmreg,ymmreg*,ymmrm256 [rvm: vex.nds.256.66.0f38.w0 cf /r] GFNI,AVX,FUTURE
+VGF2P8MULB xmmreg|mask|z,xmmreg*,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w0 cf /r] GFNI,AVX512VL,FUTURE
+VGF2P8MULB ymmreg|mask|z,ymmreg*,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w0 cf /r] GFNI,AVX512VL,FUTURE
+VGF2P8MULB zmmreg|mask|z,zmmreg*,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w0 cf /r] GFNI,AVX512,FUTURE
+
+;# AVX512 Vector Bit Manipulation Instructions 2
+VPCOMPRESSB mem128|mask,xmmreg [mr:t1s8: evex.128.66.0f38.w0 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSB mem256|mask,ymmreg [mr:t1s8: evex.256.66.0f38.w0 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSB mem512|mask,zmmreg [mr:t1s8: evex.512.66.0f38.w0 63 /r] AVX512VBMI2,FUTURE
+VPCOMPRESSB xmmreg|mask|z,xmmreg [mr: evex.128.66.0f38.w0 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSB ymmreg|mask|z,ymmreg [mr: evex.256.66.0f38.w0 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSB zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w0 63 /r] AVX512VBMI2,FUTURE
+VPCOMPRESSW mem128|mask,xmmreg [mr:t1s16: evex.128.66.0f38.w1 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSW mem256|mask,ymmreg [mr:t1s16: evex.256.66.0f38.w1 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSW mem512|mask,zmmreg [mr:t1s16: evex.512.66.0f38.w1 63 /r] AVX512VBMI2,FUTURE
+VPCOMPRESSW xmmreg|mask|z,xmmreg [mr: evex.128.66.0f38.w1 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSW ymmreg|mask|z,ymmreg [mr: evex.256.66.0f38.w1 63 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPCOMPRESSW zmmreg|mask|z,zmmreg [mr: evex.512.66.0f38.w1 63 /r] AVX512VBMI2,FUTURE
+VPEXPANDB xmmreg|mask|z,xmmrm128 [rm:t1s8: evex.128.66.0f38.w0 62 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPEXPANDB ymmreg|mask|z,ymmrm256 [rm:t1s8: evex.256.66.0f38.w0 62 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPEXPANDB zmmreg|mask|z,zmmrm512 [rm:t1s8: evex.512.66.0f38.w0 62 /r] AVX512VBMI2,FUTURE
+VPEXPANDW xmmreg|mask|z,xmmrm128 [rm:t1s16: evex.128.66.0f38.w1 62 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPEXPANDW ymmreg|mask|z,ymmrm256 [rm:t1s16: evex.256.66.0f38.w1 62 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPEXPANDW zmmreg|mask|z,zmmrm512 [rm:t1s16: evex.512.66.0f38.w1 62 /r] AVX512VBMI2,FUTURE
+VPSHLDW xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 70 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDW ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 70 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDW zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 70 /r ib] AVX512VBMI2,FUTURE
+VPSHLDD xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 71 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDD ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 71 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDD zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 71 /r ib] AVX512VBMI2,FUTURE
+VPSHLDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 71 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 71 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 71 /r ib] AVX512VBMI2,FUTURE
+VPSHLDVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvmi:fvm: evex.dds.128.66.0f38.w1 70 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvmi:fvm: evex.dds.256.66.0f38.w1 70 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvmi:fvm: evex.dds.512.66.0f38.w1 70 /r] AVX512VBMI2,FUTURE
+VPSHLDVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvmi:fv: evex.dds.128.66.0f38.w0 71 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvmi:fv: evex.dds.256.66.0f38.w0 71 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvmi:fv: evex.dds.512.66.0f38.w0 71 /r] AVX512VBMI2,FUTURE
+VPSHLDVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvmi:fv: evex.dds.128.66.0f38.w1 71 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvmi:fv: evex.dds.256.66.0f38.w1 71 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHLDVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvmi:fv: evex.dds.512.66.0f38.w1 71 /r] AVX512VBMI2,FUTURE
+VPSHRDW xmmreg|mask|z,xmmreg*,xmmrm128,imm8 [rvmi:fvm: evex.nds.128.66.0f3a.w1 72 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDW ymmreg|mask|z,ymmreg*,ymmrm256,imm8 [rvmi:fvm: evex.nds.256.66.0f3a.w1 72 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDW zmmreg|mask|z,zmmreg*,zmmrm512,imm8 [rvmi:fvm: evex.nds.512.66.0f3a.w1 72 /r ib] AVX512VBMI2,FUTURE
+VPSHRDD xmmreg|mask|z,xmmreg*,xmmrm128|b32,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w0 73 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDD ymmreg|mask|z,ymmreg*,ymmrm256|b32,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w0 73 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDD zmmreg|mask|z,zmmreg*,zmmrm512|b32,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w0 73 /r ib] AVX512VBMI2,FUTURE
+VPSHRDQ xmmreg|mask|z,xmmreg*,xmmrm128|b64,imm8 [rvmi:fv: evex.nds.128.66.0f3a.w1 73 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDQ ymmreg|mask|z,ymmreg*,ymmrm256|b64,imm8 [rvmi:fv: evex.nds.256.66.0f3a.w1 73 /r ib] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDQ zmmreg|mask|z,zmmreg*,zmmrm512|b64,imm8 [rvmi:fv: evex.nds.512.66.0f3a.w1 73 /r ib] AVX512VBMI2,FUTURE
+VPSHRDVW xmmreg|mask|z,xmmreg*,xmmrm128 [rvmi:fvm: evex.dds.128.66.0f38.w1 72 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDVW ymmreg|mask|z,ymmreg*,ymmrm256 [rvmi:fvm: evex.dds.256.66.0f38.w1 72 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDVW zmmreg|mask|z,zmmreg*,zmmrm512 [rvmi:fvm: evex.dds.512.66.0f38.w1 72 /r] AVX512VBMI2,FUTURE
+VPSHRDVD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvmi:fv: evex.dds.128.66.0f38.w0 73 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDVD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvmi:fv: evex.dds.256.66.0f38.w0 73 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDVD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvmi:fv: evex.dds.512.66.0f38.w0 73 /r] AVX512VBMI2,FUTURE
+VPSHRDVQ xmmreg|mask|z,xmmreg*,xmmrm128|b64 [rvmi:fv: evex.dds.128.66.0f38.w1 73 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDVQ ymmreg|mask|z,ymmreg*,ymmrm256|b64 [rvmi:fv: evex.dds.256.66.0f38.w1 73 /r] AVX512VBMI2,AVX512VL,FUTURE
+VPSHRDVQ zmmreg|mask|z,zmmreg*,zmmrm512|b64 [rvmi:fv: evex.dds.512.66.0f38.w1 73 /r] AVX512VBMI2,FUTURE
+
+;# AVX512 VNNI
+VPDPBUSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.dds.128.66.0f38.w0 50 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPBUSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.dds.256.66.0f38.w0 50 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPBUSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.dds.512.66.0f38.w0 50 /r] AVX512VNNI,FUTURE
+VPDPBUSDS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.dds.128.66.0f38.w0 51 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPBUSDS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.dds.256.66.0f38.w0 51 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPBUSDS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.dds.512.66.0f38.w0 51 /r] AVX512VNNI,FUTURE
+VPDPWSSD xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.dds.128.66.0f38.w0 52 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPWSSD ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.dds.256.66.0f38.w0 52 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPWSSD zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.dds.512.66.0f38.w0 52 /r] AVX512VNNI,FUTURE
+VPDPWSSDS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.dds.128.66.0f38.w0 53 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPWSSDS ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.dds.256.66.0f38.w0 53 /r] AVX512VNNI,AVX512VL,FUTURE
+VPDPWSSDS zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.dds.512.66.0f38.w0 53 /r] AVX512VNNI,FUTURE
+
+;# AVX512 Bit Algorithms
+VPOPCNTB xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f38.w0 54 /r] AVX512BITALG,AVX512VL,FUTURE
+VPOPCNTB ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f38.w0 54 /r] AVX512BITALG,AVX512VL,FUTURE
+VPOPCNTB zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f38.w0 54 /r] AVX512BITALG,FUTURE
+VPOPCNTW xmmreg|mask|z,xmmrm128 [rm:fvm: evex.128.66.0f38.w1 54 /r] AVX512BITALG,AVX512VL,FUTURE
+VPOPCNTW ymmreg|mask|z,ymmrm256 [rm:fvm: evex.256.66.0f38.w1 54 /r] AVX512BITALG,AVX512VL,FUTURE
+VPOPCNTW zmmreg|mask|z,zmmrm512 [rm:fvm: evex.512.66.0f38.w1 54 /r] AVX512BITALG,FUTURE
+VPOPCNTD xmmreg|mask|z,xmmrm128 [rm:fv: evex.128.66.0f38.w0 55 /r] AVX512VPOPCNTDQ,AVX512VL,FUTURE
+VPOPCNTD ymmreg|mask|z,ymmrm256 [rm:fv: evex.256.66.0f38.w0 55 /r] AVX512VPOPCNTDQ,AVX512VL,FUTURE
+VPOPCNTD zmmreg|mask|z,zmmrm512 [rm:fv: evex.512.66.0f38.w0 55 /r] AVX512VPOPCNTDQ,FUTURE
+VPOPCNTQ xmmreg|mask|z,xmmrm128 [rm:fv: evex.128.66.0f38.w1 55 /r] AVX512VPOPCNTDQ,AVX512VL,FUTURE
+VPOPCNTQ ymmreg|mask|z,ymmrm256 [rm:fv: evex.256.66.0f38.w1 55 /r] AVX512VPOPCNTDQ,AVX512VL,FUTURE
+VPOPCNTQ zmmreg|mask|z,zmmrm512 [rm:fv: evex.512.66.0f38.w1 55 /r] AVX512VPOPCNTDQ,FUTURE
+VPSHUFBITQMB kreg|mask,xmmreg,xmmrm128 [rvm:fvm: evex.nds.128.66.0f38.w0 8f /r] AVX512BITALG,AVX512VL,FUTURE
+VPSHUFBITQMB kreg|mask,ymmreg,ymmrm256 [rvm:fvm: evex.nds.256.66.0f38.w0 8f /r] AVX512BITALG,AVX512VL,FUTURE
+VPSHUFBITQMB kreg|mask,zmmreg,zmmrm512 [rvm:fvm: evex.nds.512.66.0f38.w0 8f /r] AVX512BITALG,FUTURE
+
+;# AVX512 4-iteration Multiply-Add
+V4FMADDPS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128:evex.dds.512.f2.0f38.w0 9a /r] AVX5124FMAPS,FUTURE,SO
+V4FNMADDPS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128:evex.dds.512.f2.0f38.w0 aa /r] AVX5124FMAPS,FUTURE,SO
+V4FMADDSS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128:evex.dds.lig.f2.0f38.w0 9b /r] AVX5124FMAPS,FUTURE,SO
+V4FNMADDSS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128:evex.dds.lig.f2.0f38.w0 ab /r] AVX5124FMAPS,FUTURE,SO
+
+;# AVX512 4-iteration Dot Product
+V4DPWSSDS zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128:evex.dds.512.f2.0f38.w0 53 /r] AVX5124VNNIW,FUTURE,SO
+V4DPWSSD zmmreg|mask|z,zmmreg|rs4,mem [rvm:m128:evex.dds.512.f2.0f38.w0 52 /r] AVX5124VNNIW,FUTURE,SO
+
+;# Intel Software Guard Extensions (SGX)
+ENCLS void [ np 0f 01 cf] SGX,FUTURE
+ENCLU void [ np 0f 01 d7] SGX,FUTURE
+ENCLV void [ np 0f 01 c0] SGX,FUTURE
+
+;# Intel Control-Flow Enforcement Technology (CET)
+CLRSSBSY mem64 [m: f3 0f ae /6] CET,FUTURE
+ENDBR32 void [ f3 0f 1e fb] CET,FUTURE
+ENDBR64 void [ f3 0f 1e fa] CET,FUTURE
+INCSSPD reg32 [m: o32 f3 0f ae /5] CET,FUTURE
+INCSSPQ reg64 [m: o64 f3 0f ae /5] CET,FUTURE,LONG
+RDSSPD reg32 [m: o32 f3 0f 1e /1] CET,FUTURE
+RDSSPQ reg64 [m: o64 f3 0f 1e /1] CET,FUTURE,LONG
+RSTORSSP mem64 [m: f3 0f 01 /5] CET,FUTURE
+SAVEPREVSSP void [ f3 0f 01 ea] CET,FUTURE
+SETSSBSY void [ f3 0f 01 e8] CET,FUTURE
+WRUSSD mem32,reg32 [mr: o32 66 0f 38 f5 /r] CET,FUTURE
+WRUSSQ mem64,reg64 [mr: o64 66 0f 38 f5 /r] CET,FUTURE,LONG
+WRSSD mem32,reg32 [mr: o32 0f 38 f6 /r] CET,FUTURE
+WRSSQ mem64,reg64 [mr: o64 0f 38 f6 /r] CET,FUTURE,LONG
+
+;# Instructions from ISE doc 319433-040, June 2020
+ENQCMD reg16,mem512 [rm: a16 f2 0f 38 f8 /r] ENQCMD,FUTURE,SZ,NOLONG
+ENQCMD reg32,mem512 [rm: a16 f2 0f 38 f8 /r] ENQCMD,FUTURE,SZ,NOLONG,ND
+ENQCMD reg32,mem512 [rm: a32 f2 0f 38 f8 /r] ENQCMD,FUTURE,SZ
+ENQCMD reg64,mem512 [rm: a64 f2 0f 38 f8 /r] ENQCMD,FUTURE,SZ,LONG
+ENQCMDS reg16,mem512 [rm: a16 f3 0f 38 f8 /r] ENQCMD,FUTURE,SZ,NOLONG,PRIV
+ENQCMDS reg32,mem512 [rm: a16 f3 0f 38 f8 /r] ENQCMD,FUTURE,SZ,NOLONG,PRIV,ND
+ENQCMDS reg32,mem512 [rm: a32 f3 0f 38 f8 /r] ENQCMD,FUTURE,SZ,PRIV
+ENQCMDS reg64,mem512 [rm: a64 f3 0f 38 f8 /r] ENQCMD,FUTURE,SZ,PRIV,LONG
+PCONFIG void [ np 0f 01 c5] PCONFIG,FUTURE,PRIV
+SERIALIZE void [ np 0f 01 e8] SERIALIZE,FUTURE
+WBNOINVD void [ f3 0f 09] WBNOINVD,FUTURE,PRIV
+XRESLDTRK void [ f2 0f 01 e9] TSXLDTRK,FUTURE
+XSUSLDTRK void [ f2 0f 01 e8] TSXLDTRK,FUTURE
+
+;# AVX512 Bfloat16 instructions
+VCVTNE2PS2BF16 xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.128.f2.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNE2PS2BF16 ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.256.f2.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNE2PS2BF16 zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.512.f2.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNEPS2BF16 xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.128.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNEPS2BF16 ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.256.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
+VCVTNEPS2BF16 zmmreg|mask|z,zmmreg*,zmmrm512|b32 [rvm:fv: evex.512.f3.0f38.w0 72 /r] AVX512BF16,FUTURE
+VDPBF16PS xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.128.f3.0f38.w0 52 /r] AVX512BF16,FUTURE
+VDPBF16PS ymmreg|mask|z,ymmreg*,ymmrm128|b32 [rvm:fv: evex.256.f3.0f38.w0 52 /r] AVX512BF16,FUTURE
+VDPBF16PS zmmreg|mask|z,zmmreg*,zmmrm128|b32 [rvm:fv: evex.512.f3.0f38.w0 52 /r] AVX512BF16,FUTURE
+
+;# AVX512 mask intersect instructions
+VP2INTERSECTD kreg|rs2,xmmreg,xmmrm128|b32 [rvm:fv: evex.nds.128.f2.0f38.w0 68 /r] AVX512BF16,FUTURE
+VP2INTERSECTD kreg|rs2,ymmreg,ymmrm128|b32 [rvm:fv: evex.nds.256.f2.0f38.w0 68 /r] AVX512BF16,FUTURE
+VP2INTERSECTD kreg|rs2,zmmreg,zmmrm128|b32 [rvm:fv: evex.nds.512.f2.0f38.w0 68 /r] AVX512BF16,FUTURE
+
+;# Intel Advanced Matrix Extensions (AMX)
+LDTILECFG mem512 [m: vex.128.np.0f38.w0 49 /0] AMXTILE,FUTURE,SZ,LONG
+STTILECFG mem512 [m: vex.128.66.0f38.w0 49 /0] AMXTILE,FUTURE,SZ,LONG
+TDPBF16PS tmmreg,tmmreg,tmmreg [rmv: vex.128.f3.0f38.w0 5c /r] AMXBF16,FUTURE,LONG
+TDPBSSD tmmreg,tmmreg,tmmreg [rmv: vex.128.f2.0f38.w0 5e /r] AMXINT8,FUTURE,LONG
+TDPBSUD tmmreg,tmmreg,tmmreg [rmv: vex.128.f3.0f38.w0 5e /r] AMXINT8,FUTURE,LONG
+TDPBUSD tmmreg,tmmreg,tmmreg [rmv: vex.128.66.0f38.w0 5e /r] AMXINT8,FUTURE,LONG
+TDPBUUD tmmreg,tmmreg,tmmreg [rmv: vex.128.np.0f38.w0 5e /r] AMXINT8,FUTURE,LONG
+TILELOADD tmmreg,mem [rm: vex.128.f2.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG
+TILELOADDT1 tmmreg,mem [rm: vex.128.66.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG
+TILERELEASE void [ vex.128.np.0f38.w0 49 c0] AMXTILE,FUTURE,LONG
+TILESTORED mem,tmmreg [mr: vex.128.f3.0f38.w0 4b /r] AMXTILE,MIB,SIB,FUTURE,SX,LONG
+TILEZERO tmmreg [r: vex.128.f2.0f38.w0 49 /3r0] AMXTILE,FUTURE,LONG
+
+;# Intel AVX512-FP16 instructions
+VADDPH xmmreg|mask|z,xmmreg*,xmmrm16|b16 [rvm:fv: evex.nds.128.np.map5.w0 58 /r] AVX512FP16,AVX512VL,FUTURE
+VADDPH ymmreg|mask|z,ymmreg*,ymmrm16|b16 [rvm:fv: evex.nds.256.np.map5.w0 58 /r] AVX512FP16,AVX512VL,FUTURE
+VADDPH zmmreg|mask|z,zmmreg*,zmmrm16|b16|er [rvm:fv: evex.nds.512.np.map5.w0 58 /r] AVX512FP16,FUTURE
+VADDSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5.w0 58 /r] AVX512FP16,FUTURE
+VCMPPH kreg|mask,xmmreg*,xmmrm16|b16,imm8 [rvmi:fv: evex.nds.128.np.0f3a.w0 C2 /r ib] AVX512FP16,AVX512VL,FUTURE
+VCMPPH kreg|mask,ymmreg*,ymmrm16|b16,imm8 [rvmi:fv: evex.nds.256.np.0f3a.w0 C2 /r ib] AVX512FP16,AVX512VL,FUTURE
+VCMPPH kreg|mask,zmmreg*,zmmrm16|b16|sae,imm8 [rvmi:fv: evex.nds.512.np.0f3a.w0 C2 /r ib] AVX512FP16,FUTURE
+VCMPSH kreg|mask,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.f3.0f3a.w0 C2 /r ib] AVX512FP16,FUTURE
+VCOMISH xmmreg,xmmrm16|sae [rm:fv: evex.lig.np.map5.w0 2F /r] AVX512FP16,FUTURE
+VCVTDQ2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.np.map5.w0 5B /r] AVX512FP16,AVX512VL,FUTURE
+VCVTDQ2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.np.map5.w0 5B /r] AVX512FP16,AVX512VL,FUTURE
+VCVTDQ2PH zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.np.map5.w0 5B /r] AVX512FP16,FUTURE
+VCVTPD2PH xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.66.map5.w1 5A /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPD2PH ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.66.map5.w1 5A /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPD2PH zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.66.map5.w1 5A /r] AVX512FP16,FUTURE
+VCVTPH2DQ xmmreg|mask|z,xmmrm64|b16 [rm:hv: evex.128.66.map5.w0 5B /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2DQ ymmreg|mask|z,xmmrm128|b16 [rm:hv: evex.256.66.map5.w0 5B /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2DQ zmmreg|mask|z,ymmrm256|b16|er [rm:hv: evex.512.66.map5.w0 5B /r] AVX512FP16,FUTURE
+VCVTPH2PD xmmreg|mask|z,xmmrm32|b16 [rm:qvm: evex.128.np.map5.w0 5A /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2PD ymmreg|mask|z,xmmrm64|b16 [rm:qvm: evex.256.np.map5.w0 5A /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2PD zmmreg|mask|z,xmmrm128|b16|sae [rm:qvm: evex.512.np.map5.w0 5A /r] AVX512FP16,FUTURE
+VCVTPH2PS xmmreg,xmmrm64 [rm: vex.128.66.0f38.w0 13 /r] AVX512FC16,FUTURE
+VCVTPH2PS ymmreg,xmmrm128 [rm: vex.256.66.0f38.w0 13 /r] AVX512FC16,FUTURE
+VCVTPH2PS xmmreg|mask|z,xmmrm64 [rm:hvm:evex.128.66.0f38.w0 13 /r] AVX512,AVX512VL,FUTURE
+VCVTPH2PS ymmreg|mask|z,xmmrm128 [rm:hvm:evex.256.66.0f38.w0 13 /r] AVX512,AVX512VL,FUTURE
+VCVTPH2PS zmmreg|mask|z,ymmrm256|sae [rm:hvm:evex.512.66.0f38.w0 13 /r] AVX512,FUTURE
+VCVTPH2PSX xmmreg|mask|z,xmmrm64|b16 [rm:hv: evex.128.66.map6.w0 13 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2PSX ymmreg|mask|z,xmmrm128|b16 [rm:hv: evex.256.66.map6.w0 13 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2PSX zmmreg|mask|z,ymmrm256|b16|sae [rm:hv: evex.512.66.map6.w0 13 /r] AVX512FP16,FUTURE
+VCVTPH2QQ xmmreg|mask|z,xmmrm32|b16 [rm:qvm:evex.128.66.map5.w0 7b /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2QQ ymmreg|mask|z,xmmrm64|b16 [rm:qvm:evex.256.66.map5.w0 7b /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2QQ zmmreg|mask|z,xmmrm128|b16|er [rm:qvm:evex.512.66.map5.w0 7b /r] AVX512FP16,FUTURE
+VCVTPH2UDQ xmmreg|mask|z,xmmrm32|b16 [rm:hv: evex.128.map5.w0 79 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2UDQ ymmreg|mask|z,xmmrm64|b16 [rm:hv: evex.256.map5.w0 79 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2UDQ zmmreg|mask|z,xmmrm128|b16|er [rm:hv: evex.512.map5.w0 79 /r] AVX512FP16,FUTURE
+VCVTPH2UQQ xmmreg|mask|z,xmmrm32|b16 [rm:qvm:evex.128.66.map5.w0 79 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2UQQ ymmreg|mask|z,xmmrm64|b16 [rm:qvm:evex.256.66.map5.w0 79 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2UQQ zmmreg|mask|z,xmmrm128|b16|er [rm:qvm:evex.512.66.map5.w0 79 /r] AVX512FP16,FUTURE
+VCVTPH2UW xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2UW ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2UW zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.np.map5.w0 7d /r] AVX512FP16,FUTURE
+VCVTPH2W xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.66.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2W ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.66.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPH2W zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.66.map5.w0 7d /r] AVX512FP16,FUTURE
+VCVTPS2PH xmmrm64,xmmreg,imm8 [mri: vex.128.66.0f3a.w0 1d /r ib] AVX512FC16,AVX512VL,FUTURE
+VCVTPS2PH xmmrm128,ymmreg,imm8 [mri: vex.256.66.0f3a.w0 1d /r ib] AVX512FC16,AVX512VL,FUTURE
+VCVTPS2PH xmmreg|mask|z,xmmreg,imm8 [mri:hvm: evex.128.66.0f3a.w0 1d /r ib] AVX512,AVX512VL,FUTURE
+VCVTPS2PH mem64|mask,xmmreg,imm8 [mri:hvm: evex.128.66.0f3a.w0 1d /r ib] AVX512,AVX512VL,FUTURE
+VCVTPS2PH xmmreg|mask|z,ymmreg,imm8 [mri:hvm: evex.256.66.0f3a.w0 1d /r ib] AVX512,AVX512VL,FUTURE
+VCVTPS2PH mem128|mask,ymmreg,imm8 [mri:hvm: evex.256.66.0f3a.w0 1d /r ib] AVX512,AVX512VL,FUTURE
+VCVTPS2PH ymmreg|mask|z,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib] AVX512,FUTURE
+VCVTPS2PH mem256|mask,zmmreg|sae,imm8 [mri:hvm: evex.512.66.0f3a.w0 1d /r ib] AVX512,FUTURE
+VCVTPS2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.66.map5.w0 1d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPS2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.66.map5.w0 1d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTPS2PH zmmreg|mask|z,zmmrm512|b32|er [rm:fv: evex.512.66.map5.w0 1d /r] AVX512FP16,FUTURE
+VCVTQQ2PH xmmreg|mask|z,xmmrm128|b64 [rm:fv: evex.128.np.map5.w1 5b /r] AVX512FP16,AVX512VL,FUTURE
+VCVTQQ2PH ymmreg|mask|z,ymmrm256|b64 [rm:fv: evex.256.np.map5.w1 5b /r] AVX512FP16,AVX512VL,FUTURE
+VCVTQQ2PH zmmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.np.map5.w1 5b /r] AVX512FP16,AVX512VL,FUTURE
+VCVTSD2SH xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.lig.f2.map5.w1 5a /r] AVX512FP16,FUTURE
+VCVTSH2SD xmmreg,xmmreg*,xmmrm16|sae [rvm:t1s: evex.nds.lig.f3.map5.w0 5a /r] AVX512FP16,FUTURE
+VCVTSH2SI reg32,xmmrm16|er [rm:t1s:evex.lig.f3.map5.w0 2d /r] AVX512FP16,FUTURE
+VCVTSH2SI reg64,xmmrm16|er [rm:t1s:evex.lig.f3.map5.w1 2d /r] AVX512FP16,FUTURE
+VCVTSH2SS xmmreg|mask|z,xmmreg*,xmmrm16|sae [rvm:t1s: evex.nds.lig.map6.w0 13 /r] AVX512FP16,FUTURE
+VCVTSH2USI reg32,xmmrm16|er [rm:t1s:evex.lig.f3.map5.w0 79 /r] AVX512FP16,FUTURE
+VCVTSH2USI reg64,xmmrm16|er [rm:t1s:evex.lig.f3.map5.w1 79 /r] AVX512FP16,FUTURE
+VCVTSI2SH xmmreg,xmmreg*,rm32|er [rvm:t1s: evex.nds.lig.f3.map5.w0 2a /r] AVX512FP16,FUTURE
+VCVTSI2SH xmmreg,xmmreg*,rm64|er [rvm:t1s: evex.nds.lig.f3.map5.w1 2a /r] AVX512FP16,FUTURE
+VCVTSS2SH xmmreg,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.lig.np.map5 1d /r] AVX512FP16,FUTURE
+VCVTTPH2DQ xmmreg|mask|z,xmmrm64|b16 [rm:hv: evex.128.f3.map5.w0 5b /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2DQ ymmreg|mask|z,xmmrm128|b16 [rm:hv: evex.256.f3.map5.w0 5b /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2DQ zmmreg|mask|z,ymmrm256|b16|sae [rm:hv: evex.512.f3.map5.w0 5b /r] AVX512FP16,FUTURE
+VCVTTPH2QQ xmmreg|mask|z,xmmrm32|b16 [rm:t1s:evex.128.66.map5.w0 7a /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2QQ ymmreg|mask|z,xmmrm64|b16 [rm:t1s:evex.256.66.map5.w0 7a /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2QQ zmmreg|mask|z,xmmrm128|b16|sae [rm:t1s:evex.512.66.map5.w0 7a /r] AVX512FP16,FUTURE
+VCVTTPH2UDQ xmmreg|mask|z,xmmrm64|b16 [rm:hv: evex.128.np.map5.w0 78 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2UDQ ymmreg|mask|z,xmmrm128|b16 [rm:hv: evex.256.np.map5.w0 78 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2UDQ zmmreg|mask|z,ymmrm256|b16|sae [rm:hv: evex.512.np.map5.w0 78 /r] AVX512FP16,FUTURE
+VCVTTPH2UQQ xmmreg|mask|z,xmmrm32|b16 [rm:t1s: evex.128.66.map5.w0 78 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2UQQ ymmreg|mask|z,xmmrm64|b16 [rm:t1s: evex.256.66.map5.w0 78 /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2UQQ zmmreg|mask|z,xmmrm128|b16|sae [rm:t1s: evex.512.66.map5.w0 78 /r] AVX512FP16,FUTURE
+VCVTTPH2UW xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 7c /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2UW ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 7c /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2UW zmmreg|mask|z,zmmrm512|b16|sae [rm:fv: evex.512.np.map5.w0 7c /r] AVX512FP16,FUTURE
+VCVTTPH2W xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.66.map5.w0 7c /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2W ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.66.map5.w0 7c /r] AVX512FP16,AVX512VL,FUTURE
+VCVTTPH2W zmmreg|mask|z,zmmrm512|b16|sae [rm:fv: evex.512.66.map5.w0 7c /r] AVX512FP16,FUTURE
+VCVTTSH2SI reg32,xmmrm16|sae [rm:t1s:evex.lig.f3.map5.w0 2c /r] AVX512FP16,FUTURE
+VCVTTSH2SI reg64,xmmrm16|sae [rm:t1s:evex.lig.f3.map5.w1 2c /r] AVX512FP16,FUTURE
+VCVTTSH2USI reg32,xmmrm16|sae [rm:t1s:evex.lig.f3.map5.w0 78 /r] AVX512FP16,FUTURE
+VCVTTSH2USI reg64,xmmrm16|sae [rm:t1s:evex.lig.f3.map5.w1 78 /r] AVX512FP16,FUTURE
+VCVTUDQ2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.f2.map5.w0 7a /r] AVX512FP16,AVX512VL,FUTURE
+VCVTUDQ2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.f2.map5.w0 7a /r] AVX512FP16,AVX512VL,FUTURE
+VCVTUDQ2PH zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.f2.map5.w0 7a /r] AVX512FP16,FUTURE
+VCVTUQQ2PH xmmreg|mask|z,xmmrm128|b32 [rm:fv: evex.128.f2.map5.w1 7a /r] AVX512FP16,AVX512VL,FUTURE
+VCVTUQQ2PH ymmreg|mask|z,ymmrm256|b32 [rm:fv: evex.256.f2.map5.w1 7a /r] AVX512FP16,AVX512VL,FUTURE
+VCVTUQQ2PH zmmreg|mask|z,zmmrm512|b32 [rm:fv: evex.512.f2.map5.w1 7a /r] AVX512FP16,FUTURE
+VCVTUSI2SH xmmreg,xmmreg|er,rm32|er [rvm:t1s: evex.nds.lig.f3.map5.w0 7b /r] AVX512FP16,FUTURE
+VCVTUSI2SS xmmreg,xmmreg|er,rm64|er [rvm:t1s: evex.nds.lig.f3.map5.w1 7b /r] AVX512FP16,FUTURE
+VCVTUW2PH xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f2.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTUW2PH ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f2.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTUW2PH zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.f2.map5.w0 7d /r] AVX512FP16,FUTURE
+VCVTW2PH xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.f3.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTW2PH ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.f3.map5.w0 7d /r] AVX512FP16,AVX512VL,FUTURE
+VCVTW2PH zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.f3.map5.w0 7d /r] AVX512FP16,FUTURE
+VDIVPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.np.map5 5e /r] AVX512FP16,AVX512VL,FUTURE
+VDIVPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.np.map5 5e /r] AVX512FP16,AVX512VL,FUTURE
+VDIVPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.np.map5 5e /r] AVX512FP16,FUTURE
+VDIVSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5 5e /r] AVX512FP16,FUTURE
+VFCMADDCPH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.f2.map6.w0 56 /r] AVX512FP16,AVX512VL,FUTURE
+VFCMADDCPH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.f2.map6.w0 56 /r] AVX512FP16,AVX512VL,FUTURE
+VFCMADDCPH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.f2.map6.w0 56 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDCPH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.f3.map6.w0 56 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDCPH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.f3.map6.w0 56 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDCPH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.f3.map6.w0 56 /r] AVX512FP16,AVX512VL,FUTURE
+VFCMADDCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.lig.f2.map6.w0 57 /r] AVX512FP16,FUTURE
+VFMADDCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.lig.f3.map6.w0 57 /r] AVX512FP16,FUTURE
+VFCMULCPCH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.f2.map6.w0 d6 /r] AVX512FP16,AVX512VL,FUTURE
+VFCMULCPCH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.f2.map6.w0 d6 /r] AVX512FP16,AVX512VL,FUTURE
+VFCMULCPCH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.f2.map6.w0 d6 /r] AVX512FP16,AVX512VL,FUTURE
+VFMULCPCH xmmreg|mask|z,xmmreg*,xmmrm128|b32 [rvm:fv: evex.nds.128.f3.map6.w0 d6 /r] AVX512FP16,AVX512VL,FUTURE
+VFMULCPCH ymmreg|mask|z,ymmreg*,ymmrm256|b32 [rvm:fv: evex.nds.256.f3.map6.w0 d6 /r] AVX512FP16,AVX512VL,FUTURE
+VFMULCPCH zmmreg|mask|z,zmmreg*,zmmrm512|b32|er [rvm:fv: evex.nds.512.f3.map6.w0 d6 /r] AVX512FP16,AVX512VL,FUTURE
+VFCMULCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.lig.f2.map6.w0 d7 /r] AVX512FP16,FUTURE
+VFMULCSH xmmreg|mask|z,xmmreg*,xmmrm32|er [rvm:t1s: evex.nds.lig.f3.map6.w0 d7 /r] AVX512FP16,FUTURE
+VFMADDSUB132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 96 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDSUB132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 96 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDSUB132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 96 /r] AVX512FP16,FUTURE
+VFMADDSUB213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 a6 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDSUB213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 a6 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDSUB213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 a6 /r] AVX512FP16,FUTURE
+VFMADDSUB231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 b6 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDSUB231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 b6 /r] AVX512FP16,AVX512VL,FUTURE
+VFMADDSUB231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 b6 /r] AVX512FP16,FUTURE
+VFMSUBADD132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 97 /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUBADD132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 97 /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUBADD132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 97 /r] AVX512FP16,FUTURE
+VFMSUBADD213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 a7 /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUBADD213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 a7 /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUBADD213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 a7 /r] AVX512FP16,FUTURE
+VFMSUBADD231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 b7 /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUBADD231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 b7 /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUBADD231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 b7 /r] AVX512FP16,FUTURE
+VPMADD132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 98 /r] AVX512FP16,AVX512VL,FUTURE
+VPMADD132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 98 /r] AVX512FP16,AVX512VL,FUTURE
+VPMADD132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 98 /r] AVX512FP16,FUTURE
+VPMADD213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 a8 /r] AVX512FP16,AVX512VL,FUTURE
+VPMADD213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 a8 /r] AVX512FP16,AVX512VL,FUTURE
+VPMADD213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 a8 /r] AVX512FP16,FUTURE
+VPMADD231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 b8 /r] AVX512FP16,AVX512VL,FUTURE
+VPMADD231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 b8 /r] AVX512FP16,AVX512VL,FUTURE
+VPMADD231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 b8 /r] AVX512FP16,FUTURE
+VFMADD132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 9c /r] AVX512FP16,AVX512VL,FUTURE
+VFMADD132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 9c /r] AVX512FP16,AVX512VL,FUTURE
+VFMADD132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 9c /r] AVX512FP16,FUTURE
+VFMADD213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 ac /r] AVX512FP16,AVX512VL,FUTURE
+VFMADD213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 ac /r] AVX512FP16,AVX512VL,FUTURE
+VFMADD213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 ac /r] AVX512FP16,FUTURE
+VFMADD231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 bc /r] AVX512FP16,AVX512VL,FUTURE
+VFMADD231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 bc /r] AVX512FP16,AVX512VL,FUTURE
+VFMADD231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 bc /r] AVX512FP16,FUTURE
+VPMADD132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 99 /r] AVX512FP16,FUTURE
+VPMADD213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 a9 /r] AVX512FP16,FUTURE
+VPMADD231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 b9 /r] AVX512FP16,FUTURE
+VPNMADD132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 9d /r] AVX512FP16,FUTURE
+VPNMADD213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 ad /r] AVX512FP16,FUTURE
+VPNMADD231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 bd /r] AVX512FP16,FUTURE
+VPMSUB132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 9a /r] AVX512FP16,AVX512VL,FUTURE
+VPMSUB132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 9a /r] AVX512FP16,AVX512VL,FUTURE
+VPMSUB132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 9a /r] AVX512FP16,FUTURE
+VPMSUB213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 aa /r] AVX512FP16,AVX512VL,FUTURE
+VPMSUB213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 aa /r] AVX512FP16,AVX512VL,FUTURE
+VPMSUB213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 aa /r] AVX512FP16,FUTURE
+VPMSUB231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 ba /r] AVX512FP16,AVX512VL,FUTURE
+VPMSUB231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 ba /r] AVX512FP16,AVX512VL,FUTURE
+VPMSUB231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 ba /r] AVX512FP16,FUTURE
+VFMSUB132PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 9e /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUB132PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 9e /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUB132PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 9e /r] AVX512FP16,FUTURE
+VFMSUB213PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 ae /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUB213PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 ae /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUB213PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 ae /r] AVX512FP16,FUTURE
+VFMSUB231PH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 be /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUB231PH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 be /r] AVX512FP16,AVX512VL,FUTURE
+VFMSUB231PH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 be /r] AVX512FP16,FUTURE
+VPMSUB132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 9b /r] AVX512FP16,FUTURE
+VPMSUB213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 ab /r] AVX512FP16,FUTURE
+VPMSUB231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 bb /r] AVX512FP16,FUTURE
+VPNMSUB132SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 9f /r] AVX512FP16,FUTURE
+VPNMSUB213SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 af /r] AVX512FP16,FUTURE
+VPNMSUB231SH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 bf /r] AVX512FP16,FUTURE
+VFPCLASSPH kreg|mask,xmmrm128|b16,imm8 [rmi:fv: evex.128.np.0f3a.w0 66 /r ib] AVX512FP16,AVX512VL,FUTURE
+VFPCLASSPH kreg|mask,ymmrm256|b16,imm8 [rmi:fv: evex.256.np.0f3a.w0 66 /r ib] AVX512FP16,AVX512VL,FUTURE
+VFPCLASSPH kreg|mask,zmmrm512|b16,imm8 [rmi:fv: evex.512.np.0f3a.w0 66 /r ib] AVX512FP16,FUTURE
+VFPCLASSSH kreg|mask,xmmrm16,imm8 [rmi:t1s: evex.lig.np.0f3a.w0 67 /r ib] AVX512FP16,FUTURE
+VGETEXPPH xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.66.map6.w0 42 /r] AVX512FP16,AVX512VL,FUTURE
+VGETEXPPH ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.66.map6.w0 42 /r] AVX512FP16,AVX512VL,FUTURE
+VGETEXPPH zmmreg|mask|z,zmmrm512|b16|sae [rm:fv: evex.512.66.map6.w0 42 /r] AVX512FP16,FUTURE
+VGETEXPSH xmmreg|mask|z,xmmrm16|sae [rm:t1s: evex.128.66.map6.w0 43 /r] AVX512FP16,FUTURE
+VGETMANTPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.np.0f3a.w0 25 /r ib] AVX512FP16,AVX512VL,FUTURE
+VGETMANTPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.np.0f3a.w0 25 /r ib] AVX512FP16,AVX512VL,FUTURE
+VGETMANTPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv: evex.512.np.0f3a.w0 25 /r ib] AVX512FP16,FUTURE
+VGETMANTSH xmmreg|mask|z,xmmrm16|sae,imm8 [rmi:t1s: evex.128.np.0f3a.w0 27 /r ib] AVX512FP16,FUTURE
+VGETMAXPH xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 5f /r] AVX512FP16,AVX512VL,FUTURE
+VGETMAXPH ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 5f /r] AVX512FP16,AVX512VL,FUTURE
+VGETMAXPH zmmreg|mask|z,zmmrm512|b16|sae [rm:fv: evex.512.np.map5.w0 5f /r] AVX512FP16,FUTURE
+VGETMAXSH xmmreg|mask|z,xmmrm16|sae [rm:t1s: evex.lig.f3.map5.w0 5f /r] AVX512FP16,FUTURE
+VGETMINPH xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 5d /r] AVX512FP16,AVX512VL,FUTURE
+VGETMINPH ymmreg|mask|z,xmmrm256|b16 [rm:fv: evex.256.np.map5.w0 5d /r] AVX512FP16,AVX512VL,FUTURE
+VGETMINPH zmmreg|mask|z,zmmrm512|b16|sae [rm:fv: evex.512.np.map5.w0 5d /r] AVX512FP16,FUTURE
+VGETMINSH xmmreg|mask|z,xmmrm16|sae [rm:t1s: evex.lig.f3.map5.w0 5d /r] AVX512FP16,FUTURE
+VMOVSH xmmreg|mask|z,mem16 [rm:t1s: evex.lig.f3.map5.w0 10 /r] AVX512FP16,FUTURE
+VMOVSH mem16|mask,xmmreg [mr:t1s: evex.lig.f3.map5.w0 11 /r] AVX512FP16,FUTURE
+VMOVSH xmmreg|mask|z,xmmreg*,xmmreg [rvm: evex.nds.lig.f3.map5.w0 10 /r] AVX512FP16,FUTURE
+VMOVSH xmmreg|mask|z,xmmreg*,xmmreg [rvm: evex.nds.lig.f3.map5.w0 11 /r] AVX512FP16,FUTURE
+VMOVW xmmreg|mask|z,rm16 [rm:t1s: evex.128.66.map5.wig 6e /r] AVX512FP16,FUTURE
+VMOVW rm16,xmmreg [mr:t1s: evex.128.66.map5.wig 7e /r] AVX512FP16,FUTURE
+VMULPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.np.map5.w0 59 /r] AVX512FP16,AVX512VL,FUTURE
+VMULPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.np.map5.w0 59 /r] AVX512FP16,AVX512VL,FUTURE
+VMULPH zmmreg|mask|z,zmmreg*,zmmrm512|b16 [rvm:fv: evex.nds.512.np.map5.w0 59 /r] AVX512FP16,FUTURE
+VMULSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5.w0 59 /r] AVX512FP16,FUTURE
+VRCPPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 4c /r] AVX512FP16,AVX512VL,FUTURE
+VRCPPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 4c /r] AVX512FP16,AVX512VL,FUTURE
+VRCPPH zmmreg|mask|z,zmmreg*,zmmrm512|b16 [rvm:fv: evex.nds.512.66.map6.w0 4c /r] AVX512FP16,FUTURE
+VRCPSH xmmreg|mask|z,xmmreg*,xmmrm16|sae [rvm:t1s: evex.nds.lig.66.map6.w0 4d /r] AVX512FP16,FUTURE
+VREDUCEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.np.0f3a.w0 56 /r ib] AVX512FP16,AVX512VL,FUTURE
+VREDUCEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.np.0f3a.w0 56 /r ib] AVX512FP16,AVX512VL,FUTURE
+VREDUCEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv: evex.512.np.0f3a.w0 56 /r ib] AVX512FP16,FUTURE
+VREDUCESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rmvi:t1s: evex.nds.lig.np.0f3a.w0 57 /r ib] AVX512FP16,FUTURE
+VENDSCALEPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.np.0f3a.w0 08 /r ib] AVX512FP16,AVX512VL,FUTURE
+VENDSCALEPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.np.0f3a.w0 08 /r ib] AVX512FP16,AVX512VL,FUTURE
+VENDSCALEPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv: evex.512.np.0f3a.w0 08 /r ib] AVX512FP16,FUTURE
+VENDSCALESH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.np.0f3a.w0 0a /r ib] AVX512FP16,FUTURE
+VRSQRTPH xmmreg|mask|z,xmmrm128|b16,imm8 [rmi:fv: evex.128.66.map6.w0 4e /r ib] AVX512FP16,AVX512VL,FUTURE
+VRSQRTPH ymmreg|mask|z,ymmrm256|b16,imm8 [rmi:fv: evex.256.66.map6.w0 4e /r ib] AVX512FP16,AVX512VL,FUTURE
+VRSQRTPH zmmreg|mask|z,zmmrm512|b16|sae,imm8 [rmi:fv: evex.512.66.map6.w0 4e /r ib] AVX512FP16,FUTURE
+VRSQRTSH xmmreg|mask|z,xmmreg*,xmmrm16|sae,imm8 [rvmi:t1s: evex.nds.lig.66.map6.w0 4f /r ib] AVX512FP16,FUTURE
+VSCALEFPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.66.map6.w0 2c /r] AVX512FP16,AVX512VL,FUTURE
+VSCALEFPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.66.map6.w0 2c /r] AVX512FP16,AVX512VL,FUTURE
+VSCALEFPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.66.map6.w0 2c /r] AVX512FP16,FUTURE
+VSCALEFSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.66.map6.w0 2d /r] AVX512FP16,FUTURE
+VSQRTPH xmmreg|mask|z,xmmrm128|b16 [rm:fv: evex.128.np.map5.w0 51 /r] AVX512FP16,AVX512VL,FUTURE
+VSQRTPH ymmreg|mask|z,ymmrm256|b16 [rm:fv: evex.256.np.map5.w0 51 /r] AVX512FP16,AVX512VL,FUTURE
+VSQRTPH zmmreg|mask|z,zmmrm512|b16|er [rm:fv: evex.512.np.map5.w0 51 /r] AVX512FP16,FUTURE
+VSQRTSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5.w0 51 /r] AVX512FP16,FUTURE
+VSUBPH xmmreg|mask|z,xmmreg*,xmmrm128|b16 [rvm:fv: evex.nds.128.np.map5.w0 5c /r] AVX512FP16,AVX512VL,FUTURE
+VSUBPH ymmreg|mask|z,ymmreg*,ymmrm256|b16 [rvm:fv: evex.nds.256.np.map5.w0 5c /r] AVX512FP16,AVX512VL,FUTURE
+VSUBPH zmmreg|mask|z,zmmreg*,zmmrm512|b16|er [rvm:fv: evex.nds.512.np.map5.w0 5c /r] AVX512FP16,FUTURE
+VSUBSH xmmreg|mask|z,xmmreg*,xmmrm16|er [rvm:t1s: evex.nds.lig.f3.map5.w0 5c /r] AVX512FP16,FUTURE
+VUCOMISH xmmreg,xmmrm16|sae [rm:t1s: evex.lig.np.map5.w0 2e /r] AVX512FP16,FUTURE
+
+;# RAO-INT weakly ordered atomic operations
+AADD mem32,reg32 [mr: norexw np 0f 38 fc /r ] RAOINT,FUTURE,SD
+AADD mem64,reg64 [mr: o64 np 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG
+AAND mem32,reg32 [mr: norexw 66 0f 38 fc /r ] RAOINT,FUTURE,SD
+AAND mem64,reg64 [mr: o64 66 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG
+AXOR mem32,reg32 [mr: norexw f3 0f 38 fc /r ] RAOINT,FUTURE,SD
+AXOR mem64,reg64 [mr: o64 f3 0f 38 fc /r ] RAOINT,FUTURE,SQ,LONG
+
+;# User interrupts
+CLUI void [ f3 0f 01 ee ] UINTR,FUTURE,LONG
+SENDUIPI reg64 [m: o64nw f3 0f c7 /6 ] UINTR,FUTURE,LONG
+STUI void [ f3 0f 01 ef ] UINTR,FUTURE,LONG
+TESTUI void [ f3 0f 01 ed ] UINTR,FUTURE,LONG
+UIRET void [ f3 0f 01 ec ] UINTR,FUTURE,LONG
+
+;# Compare, exchange and add conditional
+CMPccXADD mem32,reg32,reg32 [mrv: vex.128.66.0f38.w0 e0+c /r] CMPCCXADD,FUTURE,LONG,SD
+CMPccXADD mem64,reg64,reg64 [mrv: vex.128.66.0f38.w1 e0+c /r] CMPCCXADD,FUTURE,LONG,SQ
+
+;# WRMSRNS and MSRLIST instructions
+WRMSRNS void [ np 0f 01 c6 ] WRMSRNS,FUTURE,PRIV,LONG
+RDMSRLIST void [ f2 0f 01 c6 ] MSRLIST,FUTURE,PRIV,LONG
+WRMSRLIST void [ f3 0f 01 c6 ] MSRLIST,FUTURE,PRIV,LONG
+
+;# History reset
+HRESET imm,reg_eax [i-: f3 0f 3a f0 c0 ib ] HRESET,FUTURE,PRIV,SB
+HRESET imm [i: f3 0f 3a f0 c0 ib ] HRESET,FUTURE,PRIV,SB,ND
+
+;# Systematic names for the hinting nop instructions
+; These should be last in the file
+HINT_NOP0 rm16 [m: o16 0f 18 /0] P6,UNDOC
+HINT_NOP0 rm32 [m: o32 0f 18 /0] P6,UNDOC
+HINT_NOP0 rm64 [m: o64 0f 18 /0] X86_64,LONG,UNDOC
+HINT_NOP1 rm16 [m: o16 0f 18 /1] P6,UNDOC
+HINT_NOP1 rm32 [m: o32 0f 18 /1] P6,UNDOC
+HINT_NOP1 rm64 [m: o64 0f 18 /1] X86_64,LONG,UNDOC
+HINT_NOP2 rm16 [m: o16 0f 18 /2] P6,UNDOC
+HINT_NOP2 rm32 [m: o32 0f 18 /2] P6,UNDOC
+HINT_NOP2 rm64 [m: o64 0f 18 /2] X86_64,LONG,UNDOC
+HINT_NOP3 rm16 [m: o16 0f 18 /3] P6,UNDOC
+HINT_NOP3 rm32 [m: o32 0f 18 /3] P6,UNDOC
+HINT_NOP3 rm64 [m: o64 0f 18 /3] X86_64,LONG,UNDOC
+HINT_NOP4 rm16 [m: o16 0f 18 /4] P6,UNDOC
+HINT_NOP4 rm32 [m: o32 0f 18 /4] P6,UNDOC
+HINT_NOP4 rm64 [m: o64 0f 18 /4] X86_64,LONG,UNDOC
+HINT_NOP5 rm16 [m: o16 0f 18 /5] P6,UNDOC
+HINT_NOP5 rm32 [m: o32 0f 18 /5] P6,UNDOC
+HINT_NOP5 rm64 [m: o64 0f 18 /5] X86_64,LONG,UNDOC
+HINT_NOP6 rm16 [m: o16 0f 18 /6] P6,UNDOC
+HINT_NOP6 rm32 [m: o32 0f 18 /6] P6,UNDOC
+HINT_NOP6 rm64 [m: o64 0f 18 /6] X86_64,LONG,UNDOC
+HINT_NOP7 rm16 [m: o16 0f 18 /7] P6,UNDOC
+HINT_NOP7 rm32 [m: o32 0f 18 /7] P6,UNDOC
+HINT_NOP7 rm64 [m: o64 0f 18 /7] X86_64,LONG,UNDOC
+HINT_NOP8 rm16 [m: o16 0f 19 /0] P6,UNDOC
+HINT_NOP8 rm32 [m: o32 0f 19 /0] P6,UNDOC
+HINT_NOP8 rm64 [m: o64 0f 19 /0] X86_64,LONG,UNDOC
+HINT_NOP9 rm16 [m: o16 0f 19 /1] P6,UNDOC
+HINT_NOP9 rm32 [m: o32 0f 19 /1] P6,UNDOC
+HINT_NOP9 rm64 [m: o64 0f 19 /1] X86_64,LONG,UNDOC
+HINT_NOP10 rm16 [m: o16 0f 19 /2] P6,UNDOC
+HINT_NOP10 rm32 [m: o32 0f 19 /2] P6,UNDOC
+HINT_NOP10 rm64 [m: o64 0f 19 /2] X86_64,LONG,UNDOC
+HINT_NOP11 rm16 [m: o16 0f 19 /3] P6,UNDOC
+HINT_NOP11 rm32 [m: o32 0f 19 /3] P6,UNDOC
+HINT_NOP11 rm64 [m: o64 0f 19 /3] X86_64,LONG,UNDOC
+HINT_NOP12 rm16 [m: o16 0f 19 /4] P6,UNDOC
+HINT_NOP12 rm32 [m: o32 0f 19 /4] P6,UNDOC
+HINT_NOP12 rm64 [m: o64 0f 19 /4] X86_64,LONG,UNDOC
+HINT_NOP13 rm16 [m: o16 0f 19 /5] P6,UNDOC
+HINT_NOP13 rm32 [m: o32 0f 19 /5] P6,UNDOC
+HINT_NOP13 rm64 [m: o64 0f 19 /5] X86_64,LONG,UNDOC
+HINT_NOP14 rm16 [m: o16 0f 19 /6] P6,UNDOC
+HINT_NOP14 rm32 [m: o32 0f 19 /6] P6,UNDOC
+HINT_NOP14 rm64 [m: o64 0f 19 /6] X86_64,LONG,UNDOC
+HINT_NOP15 rm16 [m: o16 0f 19 /7] P6,UNDOC
+HINT_NOP15 rm32 [m: o32 0f 19 /7] P6,UNDOC
+HINT_NOP15 rm64 [m: o64 0f 19 /7] X86_64,LONG,UNDOC
+HINT_NOP16 rm16 [m: o16 0f 1a /0] P6,UNDOC
+HINT_NOP16 rm32 [m: o32 0f 1a /0] P6,UNDOC
+HINT_NOP16 rm64 [m: o64 0f 1a /0] X86_64,LONG,UNDOC
+HINT_NOP17 rm16 [m: o16 0f 1a /1] P6,UNDOC
+HINT_NOP17 rm32 [m: o32 0f 1a /1] P6,UNDOC
+HINT_NOP17 rm64 [m: o64 0f 1a /1] X86_64,LONG,UNDOC
+HINT_NOP18 rm16 [m: o16 0f 1a /2] P6,UNDOC
+HINT_NOP18 rm32 [m: o32 0f 1a /2] P6,UNDOC
+HINT_NOP18 rm64 [m: o64 0f 1a /2] X86_64,LONG,UNDOC
+HINT_NOP19 rm16 [m: o16 0f 1a /3] P6,UNDOC
+HINT_NOP19 rm32 [m: o32 0f 1a /3] P6,UNDOC
+HINT_NOP19 rm64 [m: o64 0f 1a /3] X86_64,LONG,UNDOC
+HINT_NOP20 rm16 [m: o16 0f 1a /4] P6,UNDOC
+HINT_NOP20 rm32 [m: o32 0f 1a /4] P6,UNDOC
+HINT_NOP20 rm64 [m: o64 0f 1a /4] X86_64,LONG,UNDOC
+HINT_NOP21 rm16 [m: o16 0f 1a /5] P6,UNDOC
+HINT_NOP21 rm32 [m: o32 0f 1a /5] P6,UNDOC
+HINT_NOP21 rm64 [m: o64 0f 1a /5] X86_64,LONG,UNDOC
+HINT_NOP22 rm16 [m: o16 0f 1a /6] P6,UNDOC
+HINT_NOP22 rm32 [m: o32 0f 1a /6] P6,UNDOC
+HINT_NOP22 rm64 [m: o64 0f 1a /6] X86_64,LONG,UNDOC
+HINT_NOP23 rm16 [m: o16 0f 1a /7] P6,UNDOC
+HINT_NOP23 rm32 [m: o32 0f 1a /7] P6,UNDOC
+HINT_NOP23 rm64 [m: o64 0f 1a /7] X86_64,LONG,UNDOC
+HINT_NOP24 rm16 [m: o16 0f 1b /0] P6,UNDOC
+HINT_NOP24 rm32 [m: o32 0f 1b /0] P6,UNDOC
+HINT_NOP24 rm64 [m: o64 0f 1b /0] X86_64,LONG,UNDOC
+HINT_NOP25 rm16 [m: o16 0f 1b /1] P6,UNDOC
+HINT_NOP25 rm32 [m: o32 0f 1b /1] P6,UNDOC
+HINT_NOP25 rm64 [m: o64 0f 1b /1] X86_64,LONG,UNDOC
+HINT_NOP26 rm16 [m: o16 0f 1b /2] P6,UNDOC
+HINT_NOP26 rm32 [m: o32 0f 1b /2] P6,UNDOC
+HINT_NOP26 rm64 [m: o64 0f 1b /2] X86_64,LONG,UNDOC
+HINT_NOP27 rm16 [m: o16 0f 1b /3] P6,UNDOC
+HINT_NOP27 rm32 [m: o32 0f 1b /3] P6,UNDOC
+HINT_NOP27 rm64 [m: o64 0f 1b /3] X86_64,LONG,UNDOC
+HINT_NOP28 rm16 [m: o16 0f 1b /4] P6,UNDOC
+HINT_NOP28 rm32 [m: o32 0f 1b /4] P6,UNDOC
+HINT_NOP28 rm64 [m: o64 0f 1b /4] X86_64,LONG,UNDOC
+HINT_NOP29 rm16 [m: o16 0f 1b /5] P6,UNDOC
+HINT_NOP29 rm32 [m: o32 0f 1b /5] P6,UNDOC
+HINT_NOP29 rm64 [m: o64 0f 1b /5] X86_64,LONG,UNDOC
+HINT_NOP30 rm16 [m: o16 0f 1b /6] P6,UNDOC
+HINT_NOP30 rm32 [m: o32 0f 1b /6] P6,UNDOC
+HINT_NOP30 rm64 [m: o64 0f 1b /6] X86_64,LONG,UNDOC
+HINT_NOP31 rm16 [m: o16 0f 1b /7] P6,UNDOC
+HINT_NOP31 rm32 [m: o32 0f 1b /7] P6,UNDOC
+HINT_NOP31 rm64 [m: o64 0f 1b /7] X86_64,LONG,UNDOC
+HINT_NOP32 rm16 [m: o16 0f 1c /0] P6,UNDOC
+HINT_NOP32 rm32 [m: o32 0f 1c /0] P6,UNDOC
+HINT_NOP32 rm64 [m: o64 0f 1c /0] X86_64,LONG,UNDOC
+HINT_NOP33 rm16 [m: o16 0f 1c /1] P6,UNDOC
+HINT_NOP33 rm32 [m: o32 0f 1c /1] P6,UNDOC
+HINT_NOP33 rm64 [m: o64 0f 1c /1] X86_64,LONG,UNDOC
+HINT_NOP34 rm16 [m: o16 0f 1c /2] P6,UNDOC
+HINT_NOP34 rm32 [m: o32 0f 1c /2] P6,UNDOC
+HINT_NOP34 rm64 [m: o64 0f 1c /2] X86_64,LONG,UNDOC
+HINT_NOP35 rm16 [m: o16 0f 1c /3] P6,UNDOC
+HINT_NOP35 rm32 [m: o32 0f 1c /3] P6,UNDOC
+HINT_NOP35 rm64 [m: o64 0f 1c /3] X86_64,LONG,UNDOC
+HINT_NOP36 rm16 [m: o16 0f 1c /4] P6,UNDOC
+HINT_NOP36 rm32 [m: o32 0f 1c /4] P6,UNDOC
+HINT_NOP36 rm64 [m: o64 0f 1c /4] X86_64,LONG,UNDOC
+HINT_NOP37 rm16 [m: o16 0f 1c /5] P6,UNDOC
+HINT_NOP37 rm32 [m: o32 0f 1c /5] P6,UNDOC
+HINT_NOP37 rm64 [m: o64 0f 1c /5] X86_64,LONG,UNDOC
+HINT_NOP38 rm16 [m: o16 0f 1c /6] P6,UNDOC
+HINT_NOP38 rm32 [m: o32 0f 1c /6] P6,UNDOC
+HINT_NOP38 rm64 [m: o64 0f 1c /6] X86_64,LONG,UNDOC
+HINT_NOP39 rm16 [m: o16 0f 1c /7] P6,UNDOC
+HINT_NOP39 rm32 [m: o32 0f 1c /7] P6,UNDOC
+HINT_NOP39 rm64 [m: o64 0f 1c /7] X86_64,LONG,UNDOC
+HINT_NOP40 rm16 [m: o16 0f 1d /0] P6,UNDOC
+HINT_NOP40 rm32 [m: o32 0f 1d /0] P6,UNDOC
+HINT_NOP40 rm64 [m: o64 0f 1d /0] X86_64,LONG,UNDOC
+HINT_NOP41 rm16 [m: o16 0f 1d /1] P6,UNDOC
+HINT_NOP41 rm32 [m: o32 0f 1d /1] P6,UNDOC
+HINT_NOP41 rm64 [m: o64 0f 1d /1] X86_64,LONG,UNDOC
+HINT_NOP42 rm16 [m: o16 0f 1d /2] P6,UNDOC
+HINT_NOP42 rm32 [m: o32 0f 1d /2] P6,UNDOC
+HINT_NOP42 rm64 [m: o64 0f 1d /2] X86_64,LONG,UNDOC
+HINT_NOP43 rm16 [m: o16 0f 1d /3] P6,UNDOC
+HINT_NOP43 rm32 [m: o32 0f 1d /3] P6,UNDOC
+HINT_NOP43 rm64 [m: o64 0f 1d /3] X86_64,LONG,UNDOC
+HINT_NOP44 rm16 [m: o16 0f 1d /4] P6,UNDOC
+HINT_NOP44 rm32 [m: o32 0f 1d /4] P6,UNDOC
+HINT_NOP44 rm64 [m: o64 0f 1d /4] X86_64,LONG,UNDOC
+HINT_NOP45 rm16 [m: o16 0f 1d /5] P6,UNDOC
+HINT_NOP45 rm32 [m: o32 0f 1d /5] P6,UNDOC
+HINT_NOP45 rm64 [m: o64 0f 1d /5] X86_64,LONG,UNDOC
+HINT_NOP46 rm16 [m: o16 0f 1d /6] P6,UNDOC
+HINT_NOP46 rm32 [m: o32 0f 1d /6] P6,UNDOC
+HINT_NOP46 rm64 [m: o64 0f 1d /6] X86_64,LONG,UNDOC
+HINT_NOP47 rm16 [m: o16 0f 1d /7] P6,UNDOC
+HINT_NOP47 rm32 [m: o32 0f 1d /7] P6,UNDOC
+HINT_NOP47 rm64 [m: o64 0f 1d /7] X86_64,LONG,UNDOC
+HINT_NOP48 rm16 [m: o16 0f 1e /0] P6,UNDOC
+HINT_NOP48 rm32 [m: o32 0f 1e /0] P6,UNDOC
+HINT_NOP48 rm64 [m: o64 0f 1e /0] X86_64,LONG,UNDOC
+HINT_NOP49 rm16 [m: o16 0f 1e /1] P6,UNDOC
+HINT_NOP49 rm32 [m: o32 0f 1e /1] P6,UNDOC
+HINT_NOP49 rm64 [m: o64 0f 1e /1] X86_64,LONG,UNDOC
+HINT_NOP50 rm16 [m: o16 0f 1e /2] P6,UNDOC
+HINT_NOP50 rm32 [m: o32 0f 1e /2] P6,UNDOC
+HINT_NOP50 rm64 [m: o64 0f 1e /2] X86_64,LONG,UNDOC
+HINT_NOP51 rm16 [m: o16 0f 1e /3] P6,UNDOC
+HINT_NOP51 rm32 [m: o32 0f 1e /3] P6,UNDOC
+HINT_NOP51 rm64 [m: o64 0f 1e /3] X86_64,LONG,UNDOC
+HINT_NOP52 rm16 [m: o16 0f 1e /4] P6,UNDOC
+HINT_NOP52 rm32 [m: o32 0f 1e /4] P6,UNDOC
+HINT_NOP52 rm64 [m: o64 0f 1e /4] X86_64,LONG,UNDOC
+HINT_NOP53 rm16 [m: o16 0f 1e /5] P6,UNDOC
+HINT_NOP53 rm32 [m: o32 0f 1e /5] P6,UNDOC
+HINT_NOP53 rm64 [m: o64 0f 1e /5] X86_64,LONG,UNDOC
+HINT_NOP54 rm16 [m: o16 0f 1e /6] P6,UNDOC
+HINT_NOP54 rm32 [m: o32 0f 1e /6] P6,UNDOC
+HINT_NOP54 rm64 [m: o64 0f 1e /6] X86_64,LONG,UNDOC
+HINT_NOP55 rm16 [m: o16 0f 1e /7] P6,UNDOC
+HINT_NOP55 rm32 [m: o32 0f 1e /7] P6,UNDOC
+HINT_NOP55 rm64 [m: o64 0f 1e /7] X86_64,LONG,UNDOC
+HINT_NOP56 rm16 [m: o16 0f 1f /0] P6,UNDOC
+HINT_NOP56 rm32 [m: o32 0f 1f /0] P6,UNDOC
+HINT_NOP56 rm64 [m: o64 0f 1f /0] X86_64,LONG,UNDOC
+HINT_NOP57 rm16 [m: o16 0f 1f /1] P6,UNDOC
+HINT_NOP57 rm32 [m: o32 0f 1f /1] P6,UNDOC
+HINT_NOP57 rm64 [m: o64 0f 1f /1] X86_64,LONG,UNDOC
+HINT_NOP58 rm16 [m: o16 0f 1f /2] P6,UNDOC
+HINT_NOP58 rm32 [m: o32 0f 1f /2] P6,UNDOC
+HINT_NOP58 rm64 [m: o64 0f 1f /2] X86_64,LONG,UNDOC
+HINT_NOP59 rm16 [m: o16 0f 1f /3] P6,UNDOC
+HINT_NOP59 rm32 [m: o32 0f 1f /3] P6,UNDOC
+HINT_NOP59 rm64 [m: o64 0f 1f /3] X86_64,LONG,UNDOC
+HINT_NOP60 rm16 [m: o16 0f 1f /4] P6,UNDOC
+HINT_NOP60 rm32 [m: o32 0f 1f /4] P6,UNDOC
+HINT_NOP60 rm64 [m: o64 0f 1f /4] X86_64,LONG,UNDOC
+HINT_NOP61 rm16 [m: o16 0f 1f /5] P6,UNDOC
+HINT_NOP61 rm32 [m: o32 0f 1f /5] P6,UNDOC
+HINT_NOP61 rm64 [m: o64 0f 1f /5] X86_64,LONG,UNDOC
+HINT_NOP62 rm16 [m: o16 0f 1f /6] P6,UNDOC
+HINT_NOP62 rm32 [m: o32 0f 1f /6] P6,UNDOC
+HINT_NOP62 rm64 [m: o64 0f 1f /6] X86_64,LONG,UNDOC
+HINT_NOP63 rm16 [m: o16 0f 1f /7] P6,UNDOC
+HINT_NOP63 rm32 [m: o32 0f 1f /7] P6,UNDOC
+HINT_NOP63 rm64 [m: o64 0f 1f /7] X86_64,LONG,UNDOC
diff --git a/vere/ext/nasm/x86/insns.pl b/vere/ext/nasm/x86/insns.pl
new file mode 100755
index 0000000..1663428
--- /dev/null
+++ b/vere/ext/nasm/x86/insns.pl
@@ -0,0 +1,1167 @@
+#!/usr/bin/perl
+## --------------------------------------------------------------------------
+##
+## Copyright 1996-2020 The NASM Authors - All Rights Reserved
+## See the file AUTHORS included with the NASM distribution for
+## the specific copyright holders.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following
+## conditions are met:
+##
+## * Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## * Redistributions in binary form must reproduce the above
+## copyright notice, this list of conditions and the following
+## disclaimer in the documentation and/or other materials provided
+## with the distribution.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##
+## --------------------------------------------------------------------------
+
+#
+# insns.pl
+#
+# Parse insns.dat and produce generated source code files
+
+require 'x86/insns-iflags.ph';
+
+# Opcode prefixes which need their own opcode tables
+# LONGER PREFIXES FIRST!
+@disasm_prefixes = qw(0F24 0F25 0F38 0F3A 0F7A 0FA6 0FA7 0F);
+
+# This should match MAX_OPERANDS from nasm.h
+$MAX_OPERANDS = 5;
+
+# Add VEX/XOP prefixes
+@vex_class = ( 'vex', 'xop', 'evex' );
+$vex_classes = scalar(@vex_class);
+@vexlist = ();
+%vexmap = ();
+for ($c = 0; $c < $vex_classes; $c++) {
+ $vexmap{$vex_class[$c]} = $c;
+ for ($m = 0; $m < 32; $m++) {
+ for ($p = 0; $p < 4; $p++) {
+ push(@vexlist, sprintf("%s%02X%01X", $vex_class[$c], $m, $p));
+ }
+ }
+}
+@disasm_prefixes = (@vexlist, @disasm_prefixes, '');
+%disasm_prefixes = map { $_ => 1 } @disasm_prefixes;
+
+@bytecode_count = (0) x 256;
+
+# Push to an array reference, creating the array if needed
+sub xpush($@) {
+ my $ref = shift @_;
+
+ $$ref = [] unless (defined($$ref));
+ return push(@$$ref, @_);
+}
+
+# Generate relaxed form patterns if applicable
+sub relaxed_forms(@) {
+ my @field_list = @_;
+
+ foreach my $fields (@_) {
+ next unless ($fields->[1] =~ /\*/);
+
+ # This instruction has relaxed form(s)
+ if ($fields->[2] !~ /^\[/) {
+ warn "$fname:$line: has an * operand but uses raw bytecodes\n";
+ next;
+ }
+
+ my $opmask = 0;
+ my @ops = split(/,/, $fields->[1]);
+ for (my $oi = 0; $oi < scalar @ops; $oi++) {
+ if ($ops[$oi] =~ /\*$/) {
+ if ($oi == 0) {
+ warn "$fname:$line: has a first operand with a *\n";
+ next;
+ }
+ $opmask |= 1 << $oi;
+ }
+ }
+
+ for (my $oi = 1; $oi < (1 << scalar @ops); $oi++) {
+ if (($oi & ~$opmask) == 0) {
+ my @xops = ();
+ my $omask = ~$oi;
+ for ($oj = 0; $oj < scalar(@ops); $oj++) {
+ if ($omask & 1) {
+ push(@xops, $ops[$oj]);
+ }
+ $omask >>= 1;
+ }
+ my @ff = @$fields;
+ $ff[1] = join(',', @xops);
+ $ff[4] = $oi;
+ push(@field_list, [@ff]);
+ }
+ }
+ }
+
+ return @field_list;
+}
+
+# Condition codes used by the disassembler
+my %condd = ( 'o' => 0, 'no' => 1, 'c' => 2, 'nc' => 3,
+ 'z' => 4, 'nz' => 5, 'na' => 6, 'a' => 7,
+ 's' => 8, 'ns' => 9, 'pe' => 10, 'po' => 11,
+ 'l' => 12, 'nl' => 13, 'ng' => 14, 'g' => 15 );
+
+# All condition code aliases
+my %conds = ( %condd,
+ 'ae' => 3, 'b' => 2, 'be' => 6, 'e' => 4,
+ 'ge' => 13, 'le' => 14, 'nae' => 2, 'nb' => 3,
+ 'nbe' => 7, 'ne' => 5, 'nge' => 12, 'nle' => 15,
+ 'np' => 11, 'p' => 10 );
+
+my @conds = sort keys(%conds);
+
+# Generate conditional form patterns if applicable
+sub conditional_forms(@) {
+ my @field_list = ();
+
+ foreach my $fields (@_) {
+ # This is a case sensitive match!
+ if ($fields->[0] !~ /cc/) {
+ # Not a conditional instruction pattern
+ push(@field_list, $fields);
+ next;
+ }
+
+ if ($fields->[2] !~ /^\[/) {
+ warn "$fname:$line: conditional instruction using raw bytecodes\n";
+ next;
+ }
+
+ foreach my $cc (@conds) {
+ my @ff = @$fields;
+
+ $ff[0] =~ s/cc/\U$cc/;
+
+ unless ($ff[2] =~ /^(\[.*?)\b([0-9a-f]{2})\+c\b(.*\])$/) {
+ warn "$fname:$line: invalid conditional encoding";
+ next;
+ }
+ $ff[2] = $1.sprintf('%02x', hex($2)^$conds{$cc}).$3;
+
+ unless (defined($condd{$cc}) || $ff[3] =~ /\bND\b/) {
+ $ff[3] .= ',ND';
+ }
+
+ push(@field_list, [@ff]);
+ }
+ }
+ return @field_list;
+}
+
+print STDERR "Reading insns.dat...\n";
+
+@args = ();
+undef $output;
+foreach $arg ( @ARGV ) {
+ if ( $arg =~ /^\-/ ) {
+ if ( $arg =~ /^\-([abdin]|f[hc])$/ ) {
+ $output = $1;
+ } else {
+ die "$0: Unknown option: ${arg}\n";
+ }
+ } else {
+ push (@args, $arg);
+ }
+}
+
+die if (scalar(@args) != 2); # input output
+($fname, $oname) = @args;
+
+open(F, '<', $fname) || die "unable to open $fname";
+
+%dinstables = ();
+@bytecode_list = ();
+%aname = ();
+
+$line = 0;
+$insns = 0;
+$n_opcodes = 0;
+my @allpatterns = ();
+
+while (<F>) {
+ $line++;
+ chomp;
+ next if ( /^\s*(\;.*|)$/ ); # comments or blank lines
+
+ unless (/^\s*(\S+)\s+(\S+)\s+(\S+|\[.*\])\s+(\S+)\s*$/) {
+ warn "line $line does not contain four fields\n";
+ next;
+ }
+ my @field_list = ([$1, $2, $3, $4, 0]);
+ @field_list = relaxed_forms(@field_list);
+ @field_list = conditional_forms(@field_list);
+
+ foreach my $fields (@field_list) {
+ ($formatted, $nd) = format_insn(@$fields);
+ if ($formatted) {
+ $insns++;
+ xpush(\$aname{$fields->[0]}, $formatted);
+ }
+ if (!defined($k_opcodes{$fields->[0]})) {
+ $k_opcodes{$fields->[0]} = $n_opcodes++;
+ }
+ if ($formatted && !$nd) {
+ push @big, $formatted;
+ my @sseq = startseq($fields->[2], $fields->[4]);
+ foreach my $i (@sseq) {
+ xpush(\$dinstables{$i}, $#big);
+ }
+ }
+ }
+}
+
+close F;
+
+#
+# Generate the bytecode array. At this point, @bytecode_list contains
+# the full set of bytecodes.
+#
+
+# Sort by descending length
+@bytecode_list = sort { scalar(@$b) <=> scalar(@$a) } @bytecode_list;
+@bytecode_array = ();
+%bytecode_pos = ();
+$bytecode_next = 0;
+foreach $bl (@bytecode_list) {
+ my $h = hexstr(@$bl);
+ next if (defined($bytecode_pos{$h}));
+
+ push(@bytecode_array, $bl);
+ while ($h ne '') {
+ $bytecode_pos{$h} = $bytecode_next;
+ $h = substr($h, 2);
+ $bytecode_next++;
+ }
+}
+undef @bytecode_list;
+
+@opcodes = sort { $k_opcodes{$a} <=> $k_opcodes{$b} } keys(%k_opcodes);
+
+if ( $output eq 'b') {
+ print STDERR "Writing $oname...\n";
+
+ open(B, '>', $oname);
+
+ print B "/* This file auto-generated from insns.dat by insns.pl" .
+ " - don't edit it */\n\n";
+
+ print B "#include \"nasm.h\"\n";
+ print B "#include \"insns.h\"\n\n";
+
+ print B "const uint8_t nasm_bytecodes[$bytecode_next] = {\n";
+
+ $p = 0;
+ foreach $bl (@bytecode_array) {
+ printf B " /* %5d */ ", $p;
+ foreach $d (@$bl) {
+ printf B "%#o,", $d;
+ $p++;
+ }
+ printf B "\n";
+ }
+ print B "};\n";
+
+ print B "\n";
+ print B "/*\n";
+ print B " * Bytecode frequencies (including reuse):\n";
+ print B " *\n";
+ for ($i = 0; $i < 32; $i++) {
+ print B " *";
+ for ($j = 0; $j < 256; $j += 32) {
+ print B " |" if ($j);
+ printf B " %3o:%4d", $i+$j, $bytecode_count[$i+$j];
+ }
+ print B "\n";
+ }
+ print B " */\n";
+
+ close B;
+}
+
+if ( $output eq 'a' ) {
+ print STDERR "Writing $oname...\n";
+
+ open(A, '>', $oname);
+
+ print A "/* This file auto-generated from insns.dat by insns.pl" .
+ " - don't edit it */\n\n";
+
+ print A "#include \"nasm.h\"\n";
+ print A "#include \"insns.h\"\n\n";
+
+ foreach $i (@opcodes) {
+ print A "static const struct itemplate instrux_${i}[] = {\n";
+ foreach $j (@{$aname{$i}}) {
+ print A " ", codesubst($j), "\n";
+ }
+ print A " ITEMPLATE_END\n};\n\n";
+ }
+ print A "const struct itemplate * const nasm_instructions[] = {\n";
+ foreach $i (@opcodes) {
+ print A " instrux_${i},\n";
+ }
+ print A "};\n";
+
+ close A;
+}
+
+if ( $output eq 'd' ) {
+ print STDERR "Writing $oname...\n";
+
+ open(D, '>', $oname);
+
+ print D "/* This file auto-generated from insns.dat by insns.pl" .
+ " - don't edit it */\n\n";
+
+ print D "#include \"nasm.h\"\n";
+ print D "#include \"insns.h\"\n\n";
+
+ print D "static const struct itemplate instrux[] = {\n";
+ $n = 0;
+ foreach $j (@big) {
+ printf D " /* %4d */ %s\n", $n++, codesubst($j);
+ }
+ print D "};\n";
+
+ foreach $h (sort(keys(%dinstables))) {
+ next if ($h eq ''); # Skip pseudo-instructions
+ print D "\nstatic const struct itemplate * const itable_${h}[] = {\n";
+ foreach $j (@{$dinstables{$h}}) {
+ print D " instrux + $j,\n";
+ }
+ print D "};\n";
+ }
+
+ @prefix_list = ();
+ foreach $h (@disasm_prefixes) {
+ for ($c = 0; $c < 256; $c++) {
+ $nn = sprintf("%s%02X", $h, $c);
+ if ($is_prefix{$nn} || defined($dinstables{$nn})) {
+ # At least one entry in this prefix table
+ push(@prefix_list, $h);
+ $is_prefix{$h} = 1;
+ last;
+ }
+ }
+ }
+
+ foreach $h (@prefix_list) {
+ print D "\n";
+ print D "static " unless ($h eq '');
+ print D "const struct disasm_index ";
+ print D ($h eq '') ? 'itable' : "itable_$h";
+ print D "[256] = {\n";
+ for ($c = 0; $c < 256; $c++) {
+ $nn = sprintf("%s%02X", $h, $c);
+ if ($is_prefix{$nn}) {
+ if ($dinstables{$nn}) {
+ print STDERR "$fname: ambiguous decoding, prefix $nn aliases:\n";
+ foreach my $dc (@{$dinstables{$nn}}) {
+ print STDERR codesubst($big[$dc]), "\n";
+ }
+ exit 1;
+ }
+ printf D " /* 0x%02x */ { itable_%s, -1 },\n", $c, $nn;
+ } elsif ($dinstables{$nn}) {
+ printf D " /* 0x%02x */ { itable_%s, %u },\n", $c,
+ $nn, scalar(@{$dinstables{$nn}});
+ } else {
+ printf D " /* 0x%02x */ { NULL, 0 },\n", $c;
+ }
+ }
+ print D "};\n";
+ }
+
+ printf D "\nconst struct disasm_index * const itable_vex[NASM_VEX_CLASSES][32][4] =\n";
+ print D "{\n";
+ for ($c = 0; $c < $vex_classes; $c++) {
+ print D " {\n";
+ for ($m = 0; $m < 32; $m++) {
+ print D " { ";
+ for ($p = 0; $p < 4; $p++) {
+ $vp = sprintf("%s%02X%01X", $vex_class[$c], $m, $p);
+ printf D "%-15s",
+ ($is_prefix{$vp} ? sprintf("itable_%s,", $vp) : 'NULL,');
+ }
+ print D "},\n";
+ }
+ print D " },\n";
+ }
+ print D "};\n";
+
+ close D;
+}
+
+if ( $output eq 'i' ) {
+ print STDERR "Writing $oname...\n";
+
+ open(I, '>', $oname);
+
+ print I "/* This file is auto-generated from insns.dat by insns.pl" .
+ " - don't edit it */\n\n";
+ print I "/* This file in included by nasm.h */\n\n";
+
+ print I "/* Instruction names */\n\n";
+ print I "#ifndef NASM_INSNSI_H\n";
+ print I "#define NASM_INSNSI_H 1\n\n";
+ print I "enum opcode {\n";
+ $maxlen = 0;
+ foreach $i (@opcodes) {
+ print I "\tI_${i},\n";
+ $len = length($i);
+ $maxlen = $len if ( $len > $maxlen );
+ }
+ print I "\tI_none = -1\n";
+ print I "};\n\n";
+ print I "#define MAX_INSLEN ", $maxlen, "\n";
+ print I "#define NASM_VEX_CLASSES ", $vex_classes, "\n";
+ print I "#define NO_DECORATOR\t{", join(',',(0) x $MAX_OPERANDS), "}\n";
+ print I "#endif /* NASM_INSNSI_H */\n";
+
+ close I;
+}
+
+if ( $output eq 'n' ) {
+ print STDERR "Writing $oname...\n";
+
+ open(N, '>', $oname);
+
+ print N "/* This file is auto-generated from insns.dat by insns.pl" .
+ " - don't edit it */\n\n";
+ print N "#include \"tables.h\"\n\n";
+
+ print N "const char * const nasm_insn_names[] = {";
+ foreach $i (@opcodes) {
+ print N "\n\t\"\L$i\"";
+ print N ',' if ($i < $#opcodes);
+ }
+ print N "\n};\n";
+ close N;
+}
+
+if ( $output eq 'fh') {
+ write_iflaggen_h();
+}
+
+if ( $output eq 'fc') {
+ write_iflag_c();
+}
+
+printf STDERR "Done: %d instructions\n", $insns;
+
+# Count primary bytecodes, for statistics
+sub count_bytecodes(@) {
+ my $skip = 0;
+ foreach my $bc (@_) {
+ if ($skip) {
+ $skip--;
+ next;
+ }
+ $bytecode_count[$bc]++;
+ if ($bc >= 01 && $bc <= 04) {
+ $skip = $bc;
+ } elsif (($bc & ~03) == 010) {
+ $skip = 1;
+ } elsif (($bc & ~013) == 0144) {
+ $skip = 1;
+ } elsif ($bc == 0172 || $bc == 0173) {
+ $skip = 1;
+ } elsif (($bc & ~3) == 0260 || $bc == 0270) { # VEX
+ $skip = 2;
+ } elsif (($bc & ~3) == 0240 || $bc == 0250) { # EVEX
+ $skip = 3;
+ } elsif ($bc == 0330) {
+ $skip = 1;
+ }
+ }
+}
+
+sub format_insn($$$$$) {
+ my ($opcode, $operands, $codes, $flags, $relax) = @_;
+ my $nd = 0;
+ my ($num, $flagsindex);
+ my @bytecode;
+ my ($op, @ops, @opsize, $opp, @opx, @oppx, @decos, @opevex);
+
+ return (undef, undef) if $operands eq "ignore";
+
+ # format the operands
+ $operands =~ s/\*//g;
+ $operands =~ s/:/|colon,/g;
+ @ops = ();
+ @opsize = ();
+ @decos = ();
+ if ($operands ne 'void') {
+ foreach $op (split(/,/, $operands)) {
+ my $opsz = 0;
+ @opx = ();
+ @opevex = ();
+ foreach $opp (split(/\|/, $op)) {
+ @oppx = ();
+ if ($opp =~ s/^(b(16|32|64)|mask|z|er|sae)$//) {
+ push(@opevex, $1);
+ }
+
+ if ($opp =~ s/(?<!\d)(8|16|32|64|80|128|256|512)$//) {
+ push(@oppx, "bits$1");
+ $opsz = $1 + 0;
+ }
+ $opp =~ s/^mem$/memory/;
+ $opp =~ s/^memory_offs$/mem_offs/;
+ $opp =~ s/^imm$/immediate/;
+ $opp =~ s/^([a-z]+)rm$/rm_$1/;
+ $opp =~ s/^rm$/rm_gpr/;
+ $opp =~ s/^reg$/reg_gpr/;
+ # only for evex insns, high-16 regs are allowed
+ if ($codes !~ /(^|\s)evex\./) {
+ $opp =~ s/^(rm_[xyz]mm)$/$1_l16/;
+ $opp =~ s/^([xyz]mm)reg$/$1_l16/;
+ }
+ push(@opx, $opp, @oppx) if $opp;
+ }
+ $op = join('|', @opx);
+ push(@ops, $op);
+ push(@opsize, $opsz);
+ push(@decos, (@opevex ? join('|', @opevex) : '0'));
+ }
+ }
+
+ $num = scalar(@ops);
+ while (scalar(@ops) < $MAX_OPERANDS) {
+ push(@ops, '0');
+ push(@opsize, 0);
+ push(@decos, '0');
+ }
+ $operands = join(',', @ops);
+ $operands =~ tr/a-z/A-Z/;
+
+ $decorators = "{" . join(',', @decos) . "}";
+ if ($decorators =~ /^{(0,)+0}$/) {
+ $decorators = "NO_DECORATOR";
+ }
+ $decorators =~ tr/a-z/A-Z/;
+
+ # Remember if we have an ARx flag
+ my $arx = undef;
+
+ # expand and uniqify the flags
+ my %flags;
+ foreach my $flag (split(',', $flags)) {
+ next if ($flag eq '');
+
+ if ($flag eq 'ND') {
+ $nd = 1;
+ } else {
+ $flags{$flag}++;
+ }
+
+ if ($flag eq 'NEVER' || $flag eq 'NOP') {
+ # These flags imply OBSOLETE
+ $flags{'OBSOLETE'}++;
+ }
+
+ if ($flag =~ /^AR([0-9]+)$/) {
+ $arx = $1+0;
+ }
+ }
+
+ if ($codes =~ /evex\./) {
+ $flags{'EVEX'}++;
+ } elsif ($codes =~ /(vex|xop)\./) {
+ $flags{'VEX'}++;
+ }
+
+ # Look for SM flags clearly inconsistent with operand bitsizes
+ if ($flags{'SM'} || $flags{'SM2'}) {
+ my $ssize = 0;
+ my $e = $flags{'SM2'} ? 2 : $MAX_OPERANDS;
+ for (my $i = 0; $i < $e; $i++) {
+ next if (!$opsize[$i]);
+ if (!$ssize) {
+ $ssize = $opsize[$i];
+ } elsif ($opsize[$i] != $ssize) {
+ die "$fname:$line: inconsistent SM flag for argument $i\n";
+ }
+ }
+ }
+
+ # Look for Sx flags that can never match operand bitsizes. If the
+ # intent is to never match (require explicit sizes), use the SX flag.
+ # This doesn't apply to registers that pre-define specific sizes;
+ # this should really be derived from include/opflags.h...
+ my %sflags = ( 'SB' => 8, 'SW' => 16, 'SD' => 32, 'SQ' => 64,
+ 'SO' => 128, 'SY' => 256, 'SZ' => 512 );
+ my $s = defined($arx) ? $arx : 0;
+ my $e = defined($arx) ? $arx : $MAX_OPERANDS - 1;
+
+ foreach my $sf (keys(%sflags)) {
+ next if (!$flags{$sf});
+ for (my $i = $s; $i <= $e; $i++) {
+ if ($opsize[$i] && $ops[$i] !~ /\breg_(gpr|[cdts]reg)\b/) {
+ die "$fname:$line: inconsistent $sf flag for argument $i ($ops[$i])\n"
+ if ($opsize[$i] != $sflags{$sf});
+ }
+ }
+ }
+
+ $flagsindex = insns_flag_index(keys %flags);
+ die "$fname:$line: error in flags $flags\n" unless (defined($flagsindex));
+
+ @bytecode = (decodify($codes, $relax), 0);
+ push(@bytecode_list, [@bytecode]);
+ $codes = hexstr(@bytecode);
+ count_bytecodes(@bytecode);
+
+ ("{I_$opcode, $num, {$operands}, $decorators, \@\@CODES-$codes\@\@, $flagsindex},", $nd);
+}
+
+#
+# Look for @@CODES-xxx@@ sequences and replace them with the appropriate
+# offset into nasm_bytecodes
+#
+sub codesubst($) {
+ my($s) = @_;
+ my $n;
+
+ while ($s =~ /\@\@CODES-([0-9A-F]+)\@\@/) {
+ my $pos = $bytecode_pos{$1};
+ if (!defined($pos)) {
+ die "$fname:$line: no position assigned to byte code $1\n";
+ }
+ $s = $` . "nasm_bytecodes+${pos}" . "$'";
+ }
+ return $s;
+}
+
+sub addprefix ($@) {
+ my ($prefix, @list) = @_;
+ my $x;
+ my @l = ();
+
+ foreach $x (@list) {
+ push(@l, sprintf("%s%02X", $prefix, $x));
+ }
+
+ return @l;
+}
+
+#
+# Turn a code string into a sequence of bytes
+#
+sub decodify($$) {
+ # Although these are C-syntax strings, by convention they should have
+ # only octal escapes (for directives) and hexadecimal escapes
+ # (for verbatim bytes)
+ my($codestr, $relax) = @_;
+
+ if ($codestr =~ /^\s*\[([^\]]*)\]\s*$/) {
+ return byte_code_compile($1, $relax);
+ }
+
+ my $c = $codestr;
+ my @codes = ();
+
+ unless ($codestr eq 'ignore') {
+ while ($c ne '') {
+ if ($c =~ /^\\x([0-9a-f]+)(.*)$/i) {
+ push(@codes, hex $1);
+ $c = $2;
+ next;
+ } elsif ($c =~ /^\\([0-7]{1,3})(.*)$/) {
+ push(@codes, oct $1);
+ $c = $2;
+ next;
+ } else {
+ die "$fname:$line: unknown code format in \"$codestr\"\n";
+ }
+ }
+ }
+
+ return @codes;
+}
+
+# Turn a numeric list into a hex string
+sub hexstr(@) {
+ my $s = '';
+ my $c;
+
+ foreach $c (@_) {
+ $s .= sprintf("%02X", $c);
+ }
+ return $s;
+}
+
+# Here we determine the range of possible starting bytes for a given
+# instruction. We need only consider the codes:
+# \[1234] mean literal bytes, of course
+# \1[0123] mean byte plus register value
+# \0 or \340 mean give up and return empty set
+# \34[4567] mean PUSH/POP of segment registers: special case
+# \17[234] skip is4 control byte
+# \26x \270 skip VEX control bytes
+# \24x \250 skip EVEX control bytes
+sub startseq($$) {
+ my ($codestr, $relax) = @_;
+ my $word;
+ my @codes = ();
+ my $c = $codestr;
+ my($c0, $c1, $i);
+ my $prefix = '';
+
+ @codes = decodify($codestr, $relax);
+
+ while (defined($c0 = shift(@codes))) {
+ $c1 = $codes[0];
+ if ($c0 >= 01 && $c0 <= 04) {
+ # Fixed byte string
+ my $fbs = $prefix;
+ while (defined($c0)) {
+ if ($c0 >= 01 && $c0 <= 04) {
+ while ($c0--) {
+ $fbs .= sprintf("%02X", shift(@codes));
+ }
+ } else {
+ last;
+ }
+ $c0 = shift(@codes);
+ }
+
+ foreach $pfx (@disasm_prefixes) {
+ my $len = length($pfx);
+ if (substr($fbs, 0, $len) eq $pfx) {
+ $prefix = $pfx;
+ $fbs = substr($fbs, $len, 2);
+ last;
+ }
+ }
+
+ if ($fbs ne '') {
+ return ($prefix.$fbs);
+ }
+
+ unshift(@codes, $c0);
+ } elsif ($c0 >= 010 && $c0 <= 013) {
+ return addprefix($prefix, $c1..($c1+7));
+ } elsif (($c0 & ~013) == 0144) {
+ return addprefix($prefix, $c1, $c1|2);
+ } elsif ($c0 == 0 || $c0 == 0340) {
+ return $prefix;
+ } elsif (($c0 & ~3) == 0260 || $c0 == 0270 ||
+ ($c0 & ~3) == 0240 || $c0 == 0250) {
+ my($c,$m,$wlp);
+ $m = shift(@codes);
+ $wlp = shift(@codes);
+ $c = ($m >> 6);
+ $m = $m & 31;
+ $prefix .= sprintf('%s%02X%01X', $vex_class[$c], $m, $wlp & 3);
+ if ($c0 < 0260) {
+ my $tuple = shift(@codes);
+ }
+ } elsif ($c0 >= 0172 && $c0 <= 173) {
+ shift(@codes); # Skip is4 control byte
+ } else {
+ # We really need to be able to distinguish "forbidden"
+ # and "ignorable" codes here
+ }
+ }
+ return ();
+}
+
+# EVEX tuple types offset is 0300. e.g. 0301 is for full vector(fv).
+sub tupletype($) {
+ my ($tuplestr) = @_;
+ my %tuple_codes = (
+ '' => 000,
+ 'fv' => 001,
+ 'hv' => 002,
+ 'fvm' => 003,
+ 't1s8' => 004,
+ 't1s16' => 005,
+ 't1s' => 006,
+ 't1f32' => 007,
+ 't1f64' => 010,
+ 't2' => 011,
+ 't4' => 012,
+ 't8' => 013,
+ 'hvm' => 014,
+ 'qvm' => 015,
+ 'ovm' => 016,
+ 'm128' => 017,
+ 'dup' => 020,
+ );
+
+ if (defined $tuple_codes{$tuplestr}) {
+ return 0300 + $tuple_codes{$tuplestr};
+ } else {
+ die "$fname:$line: undefined tuple type : $tuplestr\n";
+ }
+}
+
+#
+# This function takes a series of byte codes in a format which is more
+# typical of the Intel documentation, and encode it.
+#
+# The format looks like:
+#
+# [operands: opcodes]
+#
+# The operands word lists the order of the operands:
+#
+# r = register field in the modr/m
+# m = modr/m
+# v = VEX "v" field
+# i = immediate
+# s = register field of is4/imz2 field
+# - = implicit (unencoded) operand
+# x = indeX register of mib. 014..017 bytecodes are used.
+#
+# For an operand that should be filled into more than one field,
+# enter it as e.g. "r+v".
+#
+sub byte_code_compile($$) {
+ my($str, $relax) = @_;
+ my $opr;
+ my $opc;
+ my @codes = ();
+ my $litix = undef;
+ my %oppos = ();
+ my $i;
+ my ($op, $oq);
+ my $opex;
+
+ my %imm_codes = (
+ 'ib' => 020, # imm8
+ 'ib,u' => 024, # Unsigned imm8
+ 'iw' => 030, # imm16
+ 'ib,s' => 0274, # imm8 sign-extended to opsize or bits
+ 'iwd' => 034, # imm16 or imm32, depending on opsize
+ 'id' => 040, # imm32
+ 'id,s' => 0254, # imm32 sign-extended to 64 bits
+ 'iwdq' => 044, # imm16/32/64, depending on addrsize
+ 'rel8' => 050,
+ 'iq' => 054,
+ 'rel16' => 060,
+ 'rel' => 064, # 16 or 32 bit relative operand
+ 'rel32' => 070,
+ 'seg' => 074,
+ );
+ my %plain_codes = (
+ 'o16' => 0320, # 16-bit operand size
+ 'o32' => 0321, # 32-bit operand size
+ 'odf' => 0322, # Operand size is default
+ 'o64' => 0324, # 64-bit operand size requiring REX.W
+ 'o64nw' => 0323, # Implied 64-bit operand size (no REX.W)
+ 'a16' => 0310,
+ 'a32' => 0311,
+ 'adf' => 0312, # Address size is default
+ 'a64' => 0313,
+ '!osp' => 0364,
+ '!asp' => 0365,
+ 'f2i' => 0332, # F2 prefix, but 66 for operand size is OK
+ 'f3i' => 0333, # F3 prefix, but 66 for operand size is OK
+ 'mustrep' => 0336,
+ 'mustrepne' => 0337,
+ 'rex.l' => 0334,
+ 'norexb' => 0314,
+ 'norexx' => 0315,
+ 'norexr' => 0316,
+ 'norexw' => 0317,
+ 'repe' => 0335,
+ 'nohi' => 0325, # Use spl/bpl/sil/dil even without REX
+ 'nof3' => 0326, # No REP 0xF3 prefix permitted
+ 'norep' => 0331, # No REP prefix permitted
+ 'wait' => 0341, # Needs a wait prefix
+ 'resb' => 0340,
+ 'np' => 0360, # No prefix
+ 'jcc8' => 0370, # Match only if Jcc possible with single byte
+ 'jmp8' => 0371, # Match only if JMP possible with single byte
+ 'jlen' => 0373, # Length of jump
+ 'hlexr' => 0271,
+ 'hlenl' => 0272,
+ 'hle' => 0273,
+
+ # This instruction takes XMM VSIB
+ 'vsibx' => 0374,
+ 'vm32x' => 0374,
+ 'vm64x' => 0374,
+
+ # This instruction takes YMM VSIB
+ 'vsiby' => 0375,
+ 'vm32y' => 0375,
+ 'vm64y' => 0375,
+
+ # This instruction takes ZMM VSIB
+ 'vsibz' => 0376,
+ 'vm32z' => 0376,
+ 'vm64z' => 0376,
+ );
+
+ unless ($str =~ /^(([^\s:]*)\:*([^\s:]*)\:|)\s*(.*\S)\s*$/) {
+ die "$fname:$line: cannot parse: [$str]\n";
+ }
+ $opr = lc($2);
+ $tuple = lc($3); # Tuple type for AVX512
+ $opc = lc($4);
+
+ $op = 0;
+ for ($i = 0; $i < length($opr); $i++) {
+ my $c = substr($opr,$i,1);
+ if ($c eq '+') {
+ $op--;
+ } else {
+ if ($relax & 1) {
+ $op--;
+ }
+ $relax >>= 1;
+ $oppos{$c} = $op++;
+ }
+ }
+ $tup = tupletype($tuple);
+
+ my $last_imm = 'h';
+ my $prefix_ok = 1;
+ foreach $op (split(/\s*(?:\s|(?=[\/\\]))/, $opc)) {
+ my $pc = $plain_codes{$op};
+
+ if (defined $pc) {
+ # Plain code
+ push(@codes, $pc);
+ } elsif ($prefix_ok && $op =~ /^(66|f2|f3)$/) {
+ # 66/F2/F3 prefix used as an opcode extension
+ if ($op eq '66') {
+ push(@codes, 0361);
+ } elsif ($op eq 'f2') {
+ push(@codes, 0332);
+ } else {
+ push(@codes, 0333);
+ }
+ } elsif ($op =~ /^[0-9a-f]{2}$/) {
+ if (defined($litix) && $litix+$codes[$litix]+1 == scalar @codes &&
+ $codes[$litix] < 4) {
+ $codes[$litix]++;
+ push(@codes, hex $op);
+ } else {
+ $litix = scalar(@codes);
+ push(@codes, 01, hex $op);
+ }
+ $prefix_ok = 0;
+ } elsif ($op eq '/r') {
+ if (!defined($oppos{'r'}) || !defined($oppos{'m'})) {
+ die "$fname:$line: $op requires r and m operands\n";
+ }
+ $opex = (($oppos{'m'} & 4) ? 06 : 0) |
+ (($oppos{'r'} & 4) ? 05 : 0);
+ push(@codes, $opex) if ($opex);
+ # if mib is composed with two separate operands - ICC style
+ push(@codes, 014 + ($oppos{'x'} & 3)) if (defined($oppos{'x'}));
+ push(@codes, 0100 + (($oppos{'m'} & 3) << 3) + ($oppos{'r'} & 3));
+ $prefix_ok = 0;
+ } elsif ($op =~ m:^/([0-7])$:) {
+ if (!defined($oppos{'m'})) {
+ die "$fname:$line: $op requires an m operand\n";
+ }
+ push(@codes, 06) if ($oppos{'m'} & 4);
+ push(@codes, 0200 + (($oppos{'m'} & 3) << 3) + $1);
+ $prefix_ok = 0;
+ } elsif ($op =~ m:^/([0-3]?)r([0-7])$:) {
+ if (!defined($oppos{'r'})) {
+ die "$fname:$line: $op requires an r operand\n";
+ }
+ push(@codes, 05) if ($oppos{'r'} & 4);
+ push(@codes, 0171);
+ push(@codes, (($1+0) << 6) + (($oppos{'r'} & 3) << 3) + $2);
+ $prefix_ok = 0;
+ } elsif ($op =~ /^(vex|xop)(|\..*)$/) {
+ my $vexname = $1;
+ my $c = $vexmap{$vexname};
+ my ($m,$w,$l,$p) = (undef,2,undef,0);
+ my $has_nds = 0;
+ my @subops = split(/\./, $op);
+ shift @subops; # Drop prefix
+ foreach $oq (@subops) {
+ if ($oq eq '128' || $oq eq 'l0' || $oq eq 'lz') {
+ $l = 0;
+ } elsif ($oq eq '256' || $oq eq 'l1') {
+ $l = 1;
+ } elsif ($oq eq 'lig') {
+ $l = 2;
+ } elsif ($oq eq 'w0') {
+ $w = 0;
+ } elsif ($oq eq 'w1') {
+ $w = 1;
+ } elsif ($oq eq 'wig') {
+ $w = 2;
+ } elsif ($oq eq 'ww') {
+ $w = 3;
+ } elsif ($oq eq 'np' || $oq eq 'p0') {
+ $p = 0;
+ } elsif ($oq eq '66' || $oq eq 'p1') {
+ $p = 1;
+ } elsif ($oq eq 'f3' || $oq eq 'p2') {
+ $p = 2;
+ } elsif ($oq eq 'f2' || $oq eq 'p3') {
+ $p = 3;
+ } elsif ($oq eq '0f') {
+ $m = 1;
+ } elsif ($oq eq '0f38') {
+ $m = 2;
+ } elsif ($oq eq '0f3a') {
+ $m = 3;
+ } elsif ($oq =~ /^(m|map)([0-9]+)$/) {
+ $m = $2+0;
+ } elsif ($oq eq 'nds' || $oq eq 'ndd' || $oq eq 'dds') {
+ if (!defined($oppos{'v'})) {
+ die "$fname:$line: $vexname.$oq without 'v' operand\n";
+ }
+ $has_nds = 1;
+ } else {
+ die "$fname:$line: undefined \U$vexname\E subcode: $oq\n";
+ }
+ }
+ if (!defined($m) || !defined($w) || !defined($l) || !defined($p)) {
+ die "$fname:$line: missing fields in \U$vexname\E specification\n";
+ }
+ my $minmap = ($c == 1) ? 8 : 0; # 0-31 for VEX, 8-31 for XOP
+ if ($m < $minmap || $m > 31) {
+ die "$fname:$line: Only maps ${minmap}-31 are valid for \U${vexname}\n";
+ }
+ push(@codes, defined($oppos{'v'}) ? 0260+($oppos{'v'} & 3) : 0270,
+ ($c << 6)+$m, ($w << 4)+($l << 2)+$p);
+ $prefix_ok = 0;
+ } elsif ($op =~ /^(evex)(|\..*)$/) {
+ my $c = $vexmap{$1};
+ my ($m,$w,$l,$p) = (undef,2,undef,0);
+ my $has_nds = 0;
+ my @subops = split(/\./, $op);
+ shift @subops; # Drop prefix
+ foreach $oq (@subops) {
+ if ($oq eq '128' || $oq eq 'l0' || $oq eq 'lz' || $oq eq 'lig') {
+ $l = 0;
+ } elsif ($oq eq '256' || $oq eq 'l1') {
+ $l = 1;
+ } elsif ($oq eq '512' || $oq eq 'l2') {
+ $l = 2;
+ } elsif ($oq eq 'w0') {
+ $w = 0;
+ } elsif ($oq eq 'w1') {
+ $w = 1;
+ } elsif ($oq eq 'wig') {
+ $w = 2;
+ } elsif ($oq eq 'ww') {
+ $w = 3;
+ } elsif ($oq eq 'np' || $oq eq 'p0') {
+ $p = 0;
+ } elsif ($oq eq '66' || $oq eq 'p1') {
+ $p = 1;
+ } elsif ($oq eq 'f3' || $oq eq 'p2') {
+ $p = 2;
+ } elsif ($oq eq 'f2' || $oq eq 'p3') {
+ $p = 3;
+ } elsif ($oq eq '0f') {
+ $m = 1;
+ } elsif ($oq eq '0f38') {
+ $m = 2;
+ } elsif ($oq eq '0f3a') {
+ $m = 3;
+ } elsif ($oq eq 'map5') {
+ $m = 5;
+ } elsif ($oq eq 'map6') {
+ $m = 6;
+ } elsif ($oq =~ /^m([0-9]+)$/) {
+ $m = $1+0;
+ } elsif ($oq eq 'nds' || $oq eq 'ndd' || $oq eq 'dds') {
+ if (!defined($oppos{'v'})) {
+ die "$fname:$line: evex.$oq without 'v' operand\n";
+ }
+ $has_nds = 1;
+ } else {
+ die "$fname:$line: undefined EVEX subcode: $oq\n";
+ }
+ }
+ if (!defined($m) || !defined($w) || !defined($l) || !defined($p)) {
+ die "$fname:$line: missing fields in EVEX specification\n";
+ }
+ if ($m > 15) {
+ die "$fname:$line: Only maps 0-15 are valid for EVEX\n";
+ }
+ push(@codes, defined($oppos{'v'}) ? 0240+($oppos{'v'} & 3) : 0250,
+ ($c << 6)+$m, ($w << 4)+($l << 2)+$p, $tup);
+ $prefix_ok = 0;
+ } elsif (defined $imm_codes{$op}) {
+ if ($op eq 'seg') {
+ if ($last_imm lt 'i') {
+ die "$fname:$line: seg without an immediate operand\n";
+ }
+ } else {
+ $last_imm++;
+ if ($last_imm gt 'j') {
+ die "$fname:$line: too many immediate operands\n";
+ }
+ }
+ if (!defined($oppos{$last_imm})) {
+ die "$fname:$line: $op without '$last_imm' operand\n";
+ }
+ push(@codes, 05) if ($oppos{$last_imm} & 4);
+ push(@codes, $imm_codes{$op} + ($oppos{$last_imm} & 3));
+ $prefix_ok = 0;
+ } elsif ($op eq '/is4') {
+ if (!defined($oppos{'s'})) {
+ die "$fname:$line: $op without 's' operand\n";
+ }
+ if (defined($oppos{'i'})) {
+ push(@codes, 0172, ($oppos{'s'} << 3)+$oppos{'i'});
+ } else {
+ push(@codes, 05) if ($oppos{'s'} & 4);
+ push(@codes, 0174+($oppos{'s'} & 3));
+ }
+ $prefix_ok = 0;
+ } elsif ($op =~ /^\/is4\=([0-9]+)$/) {
+ my $imm = $1;
+ if (!defined($oppos{'s'})) {
+ die "$fname:$line: $op without 's' operand\n";
+ }
+ if ($imm < 0 || $imm > 15) {
+ die "$fname:$line: invalid imm4 value for $op: $imm\n";
+ }
+ push(@codes, 0173, ($oppos{'s'} << 4) + $imm);
+ $prefix_ok = 0;
+ } elsif ($op =~ /^([0-9a-f]{2})\+r$/) {
+ if (!defined($oppos{'r'})) {
+ die "$fname:$line: $op without 'r' operand\n";
+ }
+ push(@codes, 05) if ($oppos{'r'} & 4);
+ push(@codes, 010 + ($oppos{'r'} & 3), hex $1);
+ $prefix_ok = 0;
+ } elsif ($op =~ /^\\([0-7]+|x[0-9a-f]{2})$/) {
+ # Escape to enter literal bytecodes
+ push(@codes, oct $1);
+ } else {
+ die "$fname:$line: unknown operation: $op\n";
+ }
+ }
+
+ return @codes;
+}
diff --git a/vere/ext/nasm/x86/insnsa.c b/vere/ext/nasm/x86/insnsa.c
new file mode 100644
index 0000000..668ac07
--- /dev/null
+++ b/vere/ext/nasm/x86/insnsa.c
@@ -0,0 +1,19532 @@
+/* This file auto-generated from insns.dat by insns.pl - don't edit it */
+
+#include "nasm.h"
+#include "insns.h"
+
+static const struct itemplate instrux_DB[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DW[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DD[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DQ[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DT[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DO[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DY[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DZ[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RESB[] = {
+ {I_RESB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RESW[] = {
+ {I_RESW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RESD[] = {
+ {I_RESD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RESQ[] = {
+ {I_RESQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_REST[] = {
+ {I_REST, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RESO[] = {
+ {I_RESO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RESY[] = {
+ {I_RESY, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RESZ[] = {
+ {I_RESZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INCBIN[] = {
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AAA[] = {
+ {I_AAA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50187, 1},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AAD[] = {
+ {I_AAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49187, 1},
+ {I_AAD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49191, 2},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AAM[] = {
+ {I_AAM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49195, 1},
+ {I_AAM, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49199, 2},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AAS[] = {
+ {I_AAS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50190, 1},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADC[] = {
+ {I_ADC, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47247, 3},
+ {I_ADC, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47248, 0},
+ {I_ADC, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42741, 3},
+ {I_ADC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42742, 0},
+ {I_ADC, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42747, 4},
+ {I_ADC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42748, 5},
+ {I_ADC, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42753, 6},
+ {I_ADC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42754, 7},
+ {I_ADC, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+36381, 8},
+ {I_ADC, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+36381, 0},
+ {I_ADC, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47252, 8},
+ {I_ADC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47252, 0},
+ {I_ADC, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47257, 9},
+ {I_ADC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47257, 5},
+ {I_ADC, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47262, 10},
+ {I_ADC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47262, 7},
+ {I_ADC, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32864, 11},
+ {I_ADC, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32871, 12},
+ {I_ADC, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32878, 13},
+ {I_ADC, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49203, 8},
+ {I_ADC, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32865, 8},
+ {I_ADC, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47267, 8},
+ {I_ADC, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32872, 9},
+ {I_ADC, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47272, 9},
+ {I_ADC, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32879, 10},
+ {I_ADC, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47277, 10},
+ {I_ADC, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42759, 3},
+ {I_ADC, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32864, 3},
+ {I_ADC, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32885, 3},
+ {I_ADC, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32871, 4},
+ {I_ADC, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32892, 4},
+ {I_ADC, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32878, 6},
+ {I_ADC, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32899, 6},
+ {I_ADC, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42759, 3},
+ {I_ADC, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32864, 3},
+ {I_ADC, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32885, 3},
+ {I_ADC, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32871, 4},
+ {I_ADC, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32892, 4},
+ {I_ADC, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42765, 14},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADD[] = {
+ {I_ADD, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47282, 3},
+ {I_ADD, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47283, 0},
+ {I_ADD, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42771, 3},
+ {I_ADD, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42772, 0},
+ {I_ADD, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42777, 4},
+ {I_ADD, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42778, 5},
+ {I_ADD, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42783, 6},
+ {I_ADD, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42784, 7},
+ {I_ADD, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40154, 8},
+ {I_ADD, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40154, 0},
+ {I_ADD, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47287, 8},
+ {I_ADD, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47287, 0},
+ {I_ADD, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47292, 9},
+ {I_ADD, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47292, 5},
+ {I_ADD, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47297, 10},
+ {I_ADD, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47297, 7},
+ {I_ADD, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32906, 11},
+ {I_ADD, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32913, 12},
+ {I_ADD, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32920, 13},
+ {I_ADD, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49207, 8},
+ {I_ADD, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32907, 8},
+ {I_ADD, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47302, 8},
+ {I_ADD, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32914, 9},
+ {I_ADD, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47307, 9},
+ {I_ADD, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32921, 10},
+ {I_ADD, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47312, 10},
+ {I_ADD, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42789, 3},
+ {I_ADD, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32906, 3},
+ {I_ADD, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32927, 3},
+ {I_ADD, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32913, 4},
+ {I_ADD, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32934, 4},
+ {I_ADD, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32920, 6},
+ {I_ADD, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32941, 6},
+ {I_ADD, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42789, 3},
+ {I_ADD, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32906, 3},
+ {I_ADD, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32927, 3},
+ {I_ADD, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32913, 4},
+ {I_ADD, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32934, 4},
+ {I_ADD, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42795, 14},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AND[] = {
+ {I_AND, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47317, 3},
+ {I_AND, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47318, 0},
+ {I_AND, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42801, 3},
+ {I_AND, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42802, 0},
+ {I_AND, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42807, 4},
+ {I_AND, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42808, 5},
+ {I_AND, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42813, 6},
+ {I_AND, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42814, 7},
+ {I_AND, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40434, 8},
+ {I_AND, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40434, 0},
+ {I_AND, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47322, 8},
+ {I_AND, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47322, 0},
+ {I_AND, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47327, 9},
+ {I_AND, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47327, 5},
+ {I_AND, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47332, 10},
+ {I_AND, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47332, 7},
+ {I_AND, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32948, 11},
+ {I_AND, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32955, 12},
+ {I_AND, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32962, 13},
+ {I_AND, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49211, 8},
+ {I_AND, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32949, 8},
+ {I_AND, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47337, 8},
+ {I_AND, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32956, 9},
+ {I_AND, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47342, 9},
+ {I_AND, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32963, 10},
+ {I_AND, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47347, 10},
+ {I_AND, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42819, 3},
+ {I_AND, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32948, 3},
+ {I_AND, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32969, 3},
+ {I_AND, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32955, 4},
+ {I_AND, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32976, 4},
+ {I_AND, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+32962, 6},
+ {I_AND, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32983, 6},
+ {I_AND, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42819, 3},
+ {I_AND, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32948, 3},
+ {I_AND, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32969, 3},
+ {I_AND, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32955, 4},
+ {I_AND, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32976, 4},
+ {I_AND, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42825, 14},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ARPL[] = {
+ {I_ARPL, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29252, 15},
+ {I_ARPL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29252, 16},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BB0_RESET[] = {
+ {I_BB0_RESET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49215, 17},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BB1_RESET[] = {
+ {I_BB1_RESET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49219, 17},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BOUND[] = {
+ {I_BOUND, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47352, 18},
+ {I_BOUND, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47357, 19},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BSF[] = {
+ {I_BSF, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+32990, 9},
+ {I_BSF, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32990, 5},
+ {I_BSF, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+32997, 9},
+ {I_BSF, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32997, 5},
+ {I_BSF, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33004, 10},
+ {I_BSF, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33004, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BSR[] = {
+ {I_BSR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33011, 9},
+ {I_BSR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33011, 5},
+ {I_BSR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33018, 9},
+ {I_BSR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33018, 5},
+ {I_BSR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33025, 10},
+ {I_BSR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33025, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BSWAP[] = {
+ {I_BSWAP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42831, 20},
+ {I_BSWAP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42837, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BT[] = {
+ {I_BT, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42843, 9},
+ {I_BT, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42843, 5},
+ {I_BT, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42849, 9},
+ {I_BT, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42849, 5},
+ {I_BT, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42855, 10},
+ {I_BT, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42855, 7},
+ {I_BT, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33032, 5},
+ {I_BT, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33039, 5},
+ {I_BT, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33046, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BTC[] = {
+ {I_BTC, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33053, 4},
+ {I_BTC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33054, 5},
+ {I_BTC, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33060, 4},
+ {I_BTC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33061, 5},
+ {I_BTC, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33067, 6},
+ {I_BTC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33068, 7},
+ {I_BTC, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12304, 12},
+ {I_BTC, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12312, 12},
+ {I_BTC, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12320, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BTR[] = {
+ {I_BTR, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33074, 4},
+ {I_BTR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33075, 5},
+ {I_BTR, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33081, 4},
+ {I_BTR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33082, 5},
+ {I_BTR, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33088, 6},
+ {I_BTR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33089, 7},
+ {I_BTR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12328, 12},
+ {I_BTR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12336, 12},
+ {I_BTR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12344, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BTS[] = {
+ {I_BTS, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33095, 4},
+ {I_BTS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33096, 5},
+ {I_BTS, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33102, 4},
+ {I_BTS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33103, 5},
+ {I_BTS, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33109, 6},
+ {I_BTS, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33110, 7},
+ {I_BTS, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12352, 12},
+ {I_BTS, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12360, 12},
+ {I_BTS, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12368, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CALL[] = {
+ {I_CALL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47362, 21},
+ {I_CALL, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47362, 21},
+ {I_CALL, 1, {IMMEDIATE|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42861, 1},
+ {I_CALL, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47367, 22},
+ {I_CALL, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47367, 22},
+ {I_CALL, 1, {IMMEDIATE|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42867, 1},
+ {I_CALL, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47372, 23},
+ {I_CALL, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47372, 23},
+ {I_CALL, 1, {IMMEDIATE|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42873, 19},
+ {I_CALL, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47377, 24},
+ {I_CALL, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47377, 24},
+ {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42879, 1},
+ {I_CALL, 2, {IMMEDIATE|BITS16|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42885, 1},
+ {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42885, 1},
+ {I_CALL, 2, {IMMEDIATE|BITS32|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42891, 19},
+ {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42891, 19},
+ {I_CALL, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47382, 1},
+ {I_CALL, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47387, 7},
+ {I_CALL, 1, {MEMORY|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47392, 0},
+ {I_CALL, 1, {MEMORY|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47397, 5},
+ {I_CALL, 1, {MEMORY|BITS64|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47387, 7},
+ {I_CALL, 1, {MEMORY|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47402, 21},
+ {I_CALL, 1, {RM_GPR|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47407, 22},
+ {I_CALL, 1, {RM_GPR|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47412, 23},
+ {I_CALL, 1, {RM_GPR|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47417, 24},
+ {I_CALL, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47402, 21},
+ {I_CALL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47407, 22},
+ {I_CALL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47412, 23},
+ {I_CALL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47417, 24},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CBW[] = {
+ {I_CBW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49223, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CDQ[] = {
+ {I_CDQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49227, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CDQE[] = {
+ {I_CDQE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49231, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLC[] = {
+ {I_CLC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48819, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLD[] = {
+ {I_CLD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45984, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLI[] = {
+ {I_CLI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48134, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLTS[] = {
+ {I_CLTS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49235, 25},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMC[] = {
+ {I_CMC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50193, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMP[] = {
+ {I_CMP, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+49239, 8},
+ {I_CMP, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+49239, 0},
+ {I_CMP, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47422, 8},
+ {I_CMP, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47422, 0},
+ {I_CMP, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47427, 9},
+ {I_CMP, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47427, 5},
+ {I_CMP, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47432, 10},
+ {I_CMP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47432, 7},
+ {I_CMP, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40392, 8},
+ {I_CMP, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40392, 0},
+ {I_CMP, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47437, 8},
+ {I_CMP, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47437, 0},
+ {I_CMP, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47442, 9},
+ {I_CMP, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47442, 5},
+ {I_CMP, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47447, 10},
+ {I_CMP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47447, 7},
+ {I_CMP, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42897, 0},
+ {I_CMP, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42903, 5},
+ {I_CMP, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42909, 7},
+ {I_CMP, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49243, 8},
+ {I_CMP, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+42897, 8},
+ {I_CMP, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47452, 8},
+ {I_CMP, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+42903, 9},
+ {I_CMP, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47457, 9},
+ {I_CMP, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+42909, 10},
+ {I_CMP, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47462, 10},
+ {I_CMP, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47467, 8},
+ {I_CMP, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+42897, 8},
+ {I_CMP, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42915, 8},
+ {I_CMP, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+42903, 9},
+ {I_CMP, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42921, 9},
+ {I_CMP, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+42909, 10},
+ {I_CMP, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42927, 10},
+ {I_CMP, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47467, 8},
+ {I_CMP, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42897, 8},
+ {I_CMP, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42915, 8},
+ {I_CMP, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42903, 9},
+ {I_CMP, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42921, 9},
+ {I_CMP, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47472, 26},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPSB[] = {
+ {I_CMPSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49247, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPSD[] = {
+ {I_CMPSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47477, 5},
+ {I_CMPSD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+34292, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPSQ[] = {
+ {I_CMPSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47482, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPSW[] = {
+ {I_CMPSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47487, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPXCHG[] = {
+ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42933, 27},
+ {I_CMPXCHG, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42934, 28},
+ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33116, 27},
+ {I_CMPXCHG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33117, 28},
+ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33123, 27},
+ {I_CMPXCHG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33124, 28},
+ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33130, 6},
+ {I_CMPXCHG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33131, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPXCHG486[] = {
+ {I_CMPXCHG486, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47492, 29},
+ {I_CMPXCHG486, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47492, 30},
+ {I_CMPXCHG486, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42939, 29},
+ {I_CMPXCHG486, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42939, 30},
+ {I_CMPXCHG486, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42945, 29},
+ {I_CMPXCHG486, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42945, 30},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPXCHG8B[] = {
+ {I_CMPXCHG8B, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33137, 31},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPXCHG16B[] = {
+ {I_CMPXCHG16B, 1, {MEMORY|BITS128,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42951, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CPUID[] = {
+ {I_CPUID, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49251, 28},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CPU_READ[] = {
+ {I_CPU_READ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49255, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CPU_WRITE[] = {
+ {I_CPU_WRITE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49259, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CQO[] = {
+ {I_CQO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49263, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CWD[] = {
+ {I_CWD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49267, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CWDE[] = {
+ {I_CWDE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49271, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DAA[] = {
+ {I_DAA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50196, 1},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DAS[] = {
+ {I_DAS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50199, 1},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DEC[] = {
+ {I_DEC, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49275, 1},
+ {I_DEC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49279, 19},
+ {I_DEC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47497, 11},
+ {I_DEC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42957, 11},
+ {I_DEC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42963, 12},
+ {I_DEC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42969, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DIV[] = {
+ {I_DIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49283, 0},
+ {I_DIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47502, 0},
+ {I_DIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47507, 5},
+ {I_DIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47512, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DMINT[] = {
+ {I_DMINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49287, 33},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_EMMS[] = {
+ {I_EMMS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49291, 34},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENTER[] = {
+ {I_ENTER, 2, {IMMEDIATE,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47517, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_EQU[] = {
+ {I_EQU, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50228, 0},
+ {I_EQU, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50228, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_F2XM1[] = {
+ {I_F2XM1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49295, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FABS[] = {
+ {I_FABS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49299, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FADD[] = {
+ {I_FADD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49303, 36},
+ {I_FADD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49307, 36},
+ {I_FADD, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47522, 36},
+ {I_FADD, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47527, 36},
+ {I_FADD, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47522, 36},
+ {I_FADD, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47532, 36},
+ {I_FADD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49311, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FADDP[] = {
+ {I_FADDP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47537, 36},
+ {I_FADDP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47537, 36},
+ {I_FADDP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49311, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FBLD[] = {
+ {I_FBLD, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49315, 36},
+ {I_FBLD, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49315, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FBSTP[] = {
+ {I_FBSTP, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49319, 36},
+ {I_FBSTP, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49319, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCHS[] = {
+ {I_FCHS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49323, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCLEX[] = {
+ {I_FCLEX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47542, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVB[] = {
+ {I_FCMOVB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47547, 37},
+ {I_FCMOVB, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47552, 37},
+ {I_FCMOVB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49327, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVBE[] = {
+ {I_FCMOVBE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47557, 37},
+ {I_FCMOVBE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47562, 37},
+ {I_FCMOVBE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49331, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVE[] = {
+ {I_FCMOVE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47567, 37},
+ {I_FCMOVE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47572, 37},
+ {I_FCMOVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49335, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVNB[] = {
+ {I_FCMOVNB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47577, 37},
+ {I_FCMOVNB, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47582, 37},
+ {I_FCMOVNB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49339, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVNBE[] = {
+ {I_FCMOVNBE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47587, 37},
+ {I_FCMOVNBE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47592, 37},
+ {I_FCMOVNBE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49343, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVNE[] = {
+ {I_FCMOVNE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47597, 37},
+ {I_FCMOVNE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47602, 37},
+ {I_FCMOVNE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49347, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVNU[] = {
+ {I_FCMOVNU, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47607, 37},
+ {I_FCMOVNU, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47612, 37},
+ {I_FCMOVNU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49351, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCMOVU[] = {
+ {I_FCMOVU, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47617, 37},
+ {I_FCMOVU, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47622, 37},
+ {I_FCMOVU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49355, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCOM[] = {
+ {I_FCOM, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49359, 36},
+ {I_FCOM, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49363, 36},
+ {I_FCOM, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47627, 36},
+ {I_FCOM, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47632, 36},
+ {I_FCOM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49367, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCOMI[] = {
+ {I_FCOMI, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47637, 37},
+ {I_FCOMI, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47642, 37},
+ {I_FCOMI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49371, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCOMIP[] = {
+ {I_FCOMIP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47647, 37},
+ {I_FCOMIP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47652, 37},
+ {I_FCOMIP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49375, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCOMP[] = {
+ {I_FCOMP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49379, 36},
+ {I_FCOMP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49383, 36},
+ {I_FCOMP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47657, 36},
+ {I_FCOMP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47662, 36},
+ {I_FCOMP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49387, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCOMPP[] = {
+ {I_FCOMPP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49391, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FCOS[] = {
+ {I_FCOS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49395, 38},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FDECSTP[] = {
+ {I_FDECSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49399, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FDISI[] = {
+ {I_FDISI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47667, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FDIV[] = {
+ {I_FDIV, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49403, 36},
+ {I_FDIV, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49407, 36},
+ {I_FDIV, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47672, 36},
+ {I_FDIV, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47677, 36},
+ {I_FDIV, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47672, 36},
+ {I_FDIV, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47682, 36},
+ {I_FDIV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49411, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FDIVP[] = {
+ {I_FDIVP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47687, 36},
+ {I_FDIVP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47687, 36},
+ {I_FDIVP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49411, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FDIVR[] = {
+ {I_FDIVR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49415, 36},
+ {I_FDIVR, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49419, 36},
+ {I_FDIVR, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47692, 36},
+ {I_FDIVR, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47692, 36},
+ {I_FDIVR, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47697, 36},
+ {I_FDIVR, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47702, 36},
+ {I_FDIVR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49423, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FDIVRP[] = {
+ {I_FDIVRP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47707, 36},
+ {I_FDIVRP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47707, 36},
+ {I_FDIVRP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49423, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FEMMS[] = {
+ {I_FEMMS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49427, 39},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FENI[] = {
+ {I_FENI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47712, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FFREE[] = {
+ {I_FFREE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47717, 36},
+ {I_FFREE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49431, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FFREEP[] = {
+ {I_FFREEP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47722, 40},
+ {I_FFREEP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49435, 40},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FIADD[] = {
+ {I_FIADD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49439, 36},
+ {I_FIADD, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49443, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FICOM[] = {
+ {I_FICOM, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49447, 36},
+ {I_FICOM, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49451, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FICOMP[] = {
+ {I_FICOMP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49455, 36},
+ {I_FICOMP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49459, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FIDIV[] = {
+ {I_FIDIV, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49463, 36},
+ {I_FIDIV, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49467, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FIDIVR[] = {
+ {I_FIDIVR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49471, 36},
+ {I_FIDIVR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49475, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FILD[] = {
+ {I_FILD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49479, 36},
+ {I_FILD, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49483, 36},
+ {I_FILD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49487, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FIMUL[] = {
+ {I_FIMUL, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49491, 36},
+ {I_FIMUL, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49495, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FINCSTP[] = {
+ {I_FINCSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49499, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FINIT[] = {
+ {I_FINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47727, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FIST[] = {
+ {I_FIST, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49503, 36},
+ {I_FIST, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49507, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FISTP[] = {
+ {I_FISTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49511, 36},
+ {I_FISTP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49515, 36},
+ {I_FISTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49519, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FISTTP[] = {
+ {I_FISTTP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49523, 41},
+ {I_FISTTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49527, 41},
+ {I_FISTTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49531, 41},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FISUB[] = {
+ {I_FISUB, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49535, 36},
+ {I_FISUB, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49539, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FISUBR[] = {
+ {I_FISUBR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49543, 36},
+ {I_FISUBR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49547, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLD[] = {
+ {I_FLD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49551, 36},
+ {I_FLD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49555, 36},
+ {I_FLD, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49559, 36},
+ {I_FLD, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47732, 36},
+ {I_FLD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49563, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLD1[] = {
+ {I_FLD1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49567, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDCW[] = {
+ {I_FLDCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49571, 42},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDENV[] = {
+ {I_FLDENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49575, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDL2E[] = {
+ {I_FLDL2E, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49579, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDL2T[] = {
+ {I_FLDL2T, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49583, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDLG2[] = {
+ {I_FLDLG2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49587, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDLN2[] = {
+ {I_FLDLN2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49591, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDPI[] = {
+ {I_FLDPI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49595, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FLDZ[] = {
+ {I_FLDZ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49599, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FMUL[] = {
+ {I_FMUL, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49603, 36},
+ {I_FMUL, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49607, 36},
+ {I_FMUL, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47737, 36},
+ {I_FMUL, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47737, 36},
+ {I_FMUL, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47742, 36},
+ {I_FMUL, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47747, 36},
+ {I_FMUL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49611, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FMULP[] = {
+ {I_FMULP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47752, 36},
+ {I_FMULP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47752, 36},
+ {I_FMULP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49611, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNCLEX[] = {
+ {I_FNCLEX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47543, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNDISI[] = {
+ {I_FNDISI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47668, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNENI[] = {
+ {I_FNENI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47713, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNINIT[] = {
+ {I_FNINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47728, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNOP[] = {
+ {I_FNOP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49615, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNSAVE[] = {
+ {I_FNSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47758, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNSTCW[] = {
+ {I_FNSTCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47768, 42},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNSTENV[] = {
+ {I_FNSTENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47773, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FNSTSW[] = {
+ {I_FNSTSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47783, 42},
+ {I_FNSTSW, 1, {REG_AX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47788, 43},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FPATAN[] = {
+ {I_FPATAN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49619, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FPREM[] = {
+ {I_FPREM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49623, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FPREM1[] = {
+ {I_FPREM1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49627, 38},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FPTAN[] = {
+ {I_FPTAN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49631, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FRNDINT[] = {
+ {I_FRNDINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49635, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FRSTOR[] = {
+ {I_FRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49639, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSAVE[] = {
+ {I_FSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47757, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSCALE[] = {
+ {I_FSCALE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49643, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSETPM[] = {
+ {I_FSETPM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49647, 43},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSIN[] = {
+ {I_FSIN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49651, 38},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSINCOS[] = {
+ {I_FSINCOS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49655, 38},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSQRT[] = {
+ {I_FSQRT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49659, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FST[] = {
+ {I_FST, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49663, 36},
+ {I_FST, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49667, 36},
+ {I_FST, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47762, 36},
+ {I_FST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49671, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSTCW[] = {
+ {I_FSTCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47767, 42},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSTENV[] = {
+ {I_FSTENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47772, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSTP[] = {
+ {I_FSTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49675, 36},
+ {I_FSTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49679, 36},
+ {I_FSTP, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49683, 36},
+ {I_FSTP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47777, 36},
+ {I_FSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49687, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSTSW[] = {
+ {I_FSTSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47782, 42},
+ {I_FSTSW, 1, {REG_AX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47787, 43},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSUB[] = {
+ {I_FSUB, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49691, 36},
+ {I_FSUB, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49695, 36},
+ {I_FSUB, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47792, 36},
+ {I_FSUB, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47792, 36},
+ {I_FSUB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47797, 36},
+ {I_FSUB, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47802, 36},
+ {I_FSUB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49699, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSUBP[] = {
+ {I_FSUBP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47807, 36},
+ {I_FSUBP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47807, 36},
+ {I_FSUBP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49699, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSUBR[] = {
+ {I_FSUBR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49703, 36},
+ {I_FSUBR, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49707, 36},
+ {I_FSUBR, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47812, 36},
+ {I_FSUBR, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47812, 36},
+ {I_FSUBR, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47817, 36},
+ {I_FSUBR, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47822, 36},
+ {I_FSUBR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49711, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FSUBRP[] = {
+ {I_FSUBRP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47827, 36},
+ {I_FSUBRP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47827, 36},
+ {I_FSUBRP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49711, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FTST[] = {
+ {I_FTST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49715, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FUCOM[] = {
+ {I_FUCOM, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47832, 38},
+ {I_FUCOM, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47837, 38},
+ {I_FUCOM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49719, 38},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FUCOMI[] = {
+ {I_FUCOMI, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47842, 37},
+ {I_FUCOMI, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47847, 37},
+ {I_FUCOMI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49723, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FUCOMIP[] = {
+ {I_FUCOMIP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47852, 37},
+ {I_FUCOMIP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47857, 37},
+ {I_FUCOMIP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49727, 37},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FUCOMP[] = {
+ {I_FUCOMP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47862, 38},
+ {I_FUCOMP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47867, 38},
+ {I_FUCOMP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49731, 38},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FUCOMPP[] = {
+ {I_FUCOMPP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49735, 38},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FXAM[] = {
+ {I_FXAM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49739, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FXCH[] = {
+ {I_FXCH, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47872, 36},
+ {I_FXCH, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47872, 36},
+ {I_FXCH, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47877, 36},
+ {I_FXCH, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49743, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FXTRACT[] = {
+ {I_FXTRACT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49747, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FYL2X[] = {
+ {I_FYL2X, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49751, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FYL2XP1[] = {
+ {I_FYL2XP1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49755, 36},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HLT[] = {
+ {I_HLT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50202, 44},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IBTS[] = {
+ {I_IBTS, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42939, 45},
+ {I_IBTS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42939, 46},
+ {I_IBTS, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42945, 47},
+ {I_IBTS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42945, 46},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ICEBP[] = {
+ {I_ICEBP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50205, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IDIV[] = {
+ {I_IDIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49759, 0},
+ {I_IDIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47882, 0},
+ {I_IDIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47887, 5},
+ {I_IDIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47892, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IMUL[] = {
+ {I_IMUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49763, 0},
+ {I_IMUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47897, 0},
+ {I_IMUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47902, 5},
+ {I_IMUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47907, 7},
+ {I_IMUL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42975, 9},
+ {I_IMUL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42975, 5},
+ {I_IMUL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42981, 9},
+ {I_IMUL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42981, 5},
+ {I_IMUL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42987, 10},
+ {I_IMUL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42987, 7},
+ {I_IMUL, 3, {REG_GPR|BITS16,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+42993, 48},
+ {I_IMUL, 3, {REG_GPR|BITS16,MEMORY,SBYTEWORD,0,0}, NO_DECORATOR, nasm_bytecodes+42993, 49},
+ {I_IMUL, 3, {REG_GPR|BITS16,MEMORY,IMMEDIATE|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+42999, 49},
+ {I_IMUL, 3, {REG_GPR|BITS16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+42999, 49},
+ {I_IMUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+42993, 35},
+ {I_IMUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,SBYTEWORD,0,0}, NO_DECORATOR, nasm_bytecodes+42993, 49},
+ {I_IMUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+42999, 35},
+ {I_IMUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+42999, 49},
+ {I_IMUL, 3, {REG_GPR|BITS32,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43005, 50},
+ {I_IMUL, 3, {REG_GPR|BITS32,MEMORY,SBYTEDWORD,0,0}, NO_DECORATOR, nasm_bytecodes+43005, 9},
+ {I_IMUL, 3, {REG_GPR|BITS32,MEMORY,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43011, 9},
+ {I_IMUL, 3, {REG_GPR|BITS32,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+43011, 9},
+ {I_IMUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43005, 5},
+ {I_IMUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,SBYTEDWORD,0,0}, NO_DECORATOR, nasm_bytecodes+43005, 9},
+ {I_IMUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43011, 5},
+ {I_IMUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+43011, 9},
+ {I_IMUL, 3, {REG_GPR|BITS64,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43017, 51},
+ {I_IMUL, 3, {REG_GPR|BITS64,MEMORY,SBYTEDWORD,0,0}, NO_DECORATOR, nasm_bytecodes+43017, 10},
+ {I_IMUL, 3, {REG_GPR|BITS64,MEMORY,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43023, 51},
+ {I_IMUL, 3, {REG_GPR|BITS64,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+43029, 10},
+ {I_IMUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43017, 7},
+ {I_IMUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,SBYTEDWORD,0,0}, NO_DECORATOR, nasm_bytecodes+43017, 10},
+ {I_IMUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43023, 7},
+ {I_IMUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+43029, 10},
+ {I_IMUL, 2, {REG_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43035, 35},
+ {I_IMUL, 2, {REG_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+43035, 49},
+ {I_IMUL, 2, {REG_GPR|BITS16,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43041, 35},
+ {I_IMUL, 2, {REG_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43041, 49},
+ {I_IMUL, 2, {REG_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43047, 5},
+ {I_IMUL, 2, {REG_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+43047, 9},
+ {I_IMUL, 2, {REG_GPR|BITS32,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43053, 5},
+ {I_IMUL, 2, {REG_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43053, 9},
+ {I_IMUL, 2, {REG_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43059, 7},
+ {I_IMUL, 2, {REG_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+43059, 10},
+ {I_IMUL, 2, {REG_GPR|BITS64,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43065, 7},
+ {I_IMUL, 2, {REG_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43065, 10},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IN[] = {
+ {I_IN, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49767, 52},
+ {I_IN, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47912, 52},
+ {I_IN, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47917, 53},
+ {I_IN, 2, {REG_AL,REG_DX,0,0,0}, NO_DECORATOR, nasm_bytecodes+46092, 0},
+ {I_IN, 2, {REG_AX,REG_DX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49771, 0},
+ {I_IN, 2, {REG_EAX,REG_DX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49775, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INC[] = {
+ {I_INC, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49779, 1},
+ {I_INC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49783, 19},
+ {I_INC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47922, 11},
+ {I_INC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43071, 11},
+ {I_INC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43077, 12},
+ {I_INC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43083, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INSB[] = {
+ {I_INSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50208, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INSD[] = {
+ {I_INSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49787, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INSW[] = {
+ {I_INSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49791, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INT[] = {
+ {I_INT, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49795, 52},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INT01[] = {
+ {I_INT01, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50205, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INT1[] = {
+ {I_INT1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50205, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INT03[] = {
+ {I_INT03, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50211, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INT3[] = {
+ {I_INT3, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50211, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INTO[] = {
+ {I_INTO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50214, 1},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INVD[] = {
+ {I_INVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49799, 54},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INVPCID[] = {
+ {I_INVPCID, 2, {REG_GPR|BITS32,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+33144, 55},
+ {I_INVPCID, 2, {REG_GPR|BITS64,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+33144, 56},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INVLPG[] = {
+ {I_INVLPG, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47927, 54},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INVLPGA[] = {
+ {I_INVLPGA, 2, {REG_AX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43089, 57},
+ {I_INVLPGA, 2, {REG_EAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43095, 58},
+ {I_INVLPGA, 2, {REG_RAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33151, 59},
+ {I_INVLPGA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43096, 58},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IRET[] = {
+ {I_IRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49803, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IRETD[] = {
+ {I_IRETD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49807, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IRETQ[] = {
+ {I_IRETQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49811, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_IRETW[] = {
+ {I_IRETW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49815, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JCXZ[] = {
+ {I_JCXZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47932, 1},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JECXZ[] = {
+ {I_JECXZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47937, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JRCXZ[] = {
+ {I_JRCXZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43101, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JMP[] = {
+ {I_JMP, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47943, 0},
+ {I_JMP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47942, 0},
+ {I_JMP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47947, 21},
+ {I_JMP, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47947, 21},
+ {I_JMP, 1, {IMMEDIATE|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43107, 1},
+ {I_JMP, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47952, 22},
+ {I_JMP, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47952, 22},
+ {I_JMP, 1, {IMMEDIATE|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43113, 1},
+ {I_JMP, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47957, 23},
+ {I_JMP, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47957, 23},
+ {I_JMP, 1, {IMMEDIATE|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43119, 19},
+ {I_JMP, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47962, 24},
+ {I_JMP, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47962, 24},
+ {I_JMP, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43125, 1},
+ {I_JMP, 2, {IMMEDIATE|BITS16|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43131, 1},
+ {I_JMP, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43131, 1},
+ {I_JMP, 2, {IMMEDIATE|BITS32|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43137, 19},
+ {I_JMP, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43137, 19},
+ {I_JMP, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47967, 1},
+ {I_JMP, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47972, 7},
+ {I_JMP, 1, {MEMORY|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47977, 0},
+ {I_JMP, 1, {MEMORY|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47982, 5},
+ {I_JMP, 1, {MEMORY|BITS64|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47972, 7},
+ {I_JMP, 1, {MEMORY|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47987, 21},
+ {I_JMP, 1, {RM_GPR|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47992, 22},
+ {I_JMP, 1, {RM_GPR|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47997, 23},
+ {I_JMP, 1, {RM_GPR|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48002, 24},
+ {I_JMP, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47987, 21},
+ {I_JMP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47992, 22},
+ {I_JMP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47997, 23},
+ {I_JMP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48002, 24},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JMPE[] = {
+ {I_JMPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43143, 60},
+ {I_JMPE, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43149, 60},
+ {I_JMPE, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43155, 60},
+ {I_JMPE, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43161, 60},
+ {I_JMPE, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43167, 60},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LAHF[] = {
+ {I_LAHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50217, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LAR[] = {
+ {I_LAR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43173, 61},
+ {I_LAR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43173, 62},
+ {I_LAR, 2, {REG_GPR|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43173, 63},
+ {I_LAR, 2, {REG_GPR|BITS16,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33158, 64},
+ {I_LAR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43179, 65},
+ {I_LAR, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43179, 63},
+ {I_LAR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43179, 63},
+ {I_LAR, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33165, 64},
+ {I_LAR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 66},
+ {I_LAR, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 64},
+ {I_LAR, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 64},
+ {I_LAR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 64},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LDS[] = {
+ {I_LDS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48007, 1},
+ {I_LDS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48012, 19},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LEA[] = {
+ {I_LEA, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48017, 67},
+ {I_LEA, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48022, 68},
+ {I_LEA, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48027, 69},
+ {I_LEA, 2, {REG_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48017, 67},
+ {I_LEA, 2, {REG_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48022, 68},
+ {I_LEA, 2, {REG_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48027, 69},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LEAVE[] = {
+ {I_LEAVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48279, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LES[] = {
+ {I_LES, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48032, 1},
+ {I_LES, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48037, 19},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LFENCE[] = {
+ {I_LFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43191, 59},
+ {I_LFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43191, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LFS[] = {
+ {I_LFS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43197, 5},
+ {I_LFS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43203, 5},
+ {I_LFS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43209, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LGDT[] = {
+ {I_LGDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48042, 25},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LGS[] = {
+ {I_LGS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43215, 5},
+ {I_LGS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43221, 5},
+ {I_LGS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43227, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LIDT[] = {
+ {I_LIDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48047, 25},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LLDT[] = {
+ {I_LLDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48052, 70},
+ {I_LLDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48052, 70},
+ {I_LLDT, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48052, 70},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LMSW[] = {
+ {I_LMSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48057, 25},
+ {I_LMSW, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48057, 25},
+ {I_LMSW, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48057, 25},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LOADALL[] = {
+ {I_LOADALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49819, 46},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LOADALL286[] = {
+ {I_LOADALL286, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49823, 71},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LODSB[] = {
+ {I_LODSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50220, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LODSD[] = {
+ {I_LODSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49827, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LODSQ[] = {
+ {I_LODSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49831, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LODSW[] = {
+ {I_LODSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49835, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LOOP[] = {
+ {I_LOOP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48062, 0},
+ {I_LOOP, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48067, 1},
+ {I_LOOP, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48072, 5},
+ {I_LOOP, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48077, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LOOPE[] = {
+ {I_LOOPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48082, 0},
+ {I_LOOPE, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48087, 1},
+ {I_LOOPE, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48092, 5},
+ {I_LOOPE, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48097, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LOOPNE[] = {
+ {I_LOOPNE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48102, 0},
+ {I_LOOPNE, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48107, 1},
+ {I_LOOPNE, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48112, 5},
+ {I_LOOPNE, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48117, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LOOPNZ[] = {
+ {I_LOOPNZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48102, 0},
+ {I_LOOPNZ, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48107, 1},
+ {I_LOOPNZ, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48112, 5},
+ {I_LOOPNZ, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48117, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LOOPZ[] = {
+ {I_LOOPZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48082, 0},
+ {I_LOOPZ, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48087, 1},
+ {I_LOOPZ, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48092, 5},
+ {I_LOOPZ, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48097, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LSL[] = {
+ {I_LSL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43233, 61},
+ {I_LSL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43233, 62},
+ {I_LSL, 2, {REG_GPR|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43233, 63},
+ {I_LSL, 2, {REG_GPR|BITS16,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33172, 64},
+ {I_LSL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43239, 65},
+ {I_LSL, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43239, 63},
+ {I_LSL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43239, 63},
+ {I_LSL, 2, {REG_GPR|BITS32,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33179, 64},
+ {I_LSL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 66},
+ {I_LSL, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 64},
+ {I_LSL, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 64},
+ {I_LSL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 64},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LSS[] = {
+ {I_LSS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43251, 5},
+ {I_LSS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43257, 5},
+ {I_LSS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43263, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LTR[] = {
+ {I_LTR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48122, 70},
+ {I_LTR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48122, 70},
+ {I_LTR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48122, 70},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MFENCE[] = {
+ {I_MFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43269, 59},
+ {I_MFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43269, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MONITOR[] = {
+ {I_MONITOR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48127, 72},
+ {I_MONITOR, 3, {REG_EAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+48127, 73},
+ {I_MONITOR, 3, {REG_RAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+48127, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MONITORX[] = {
+ {I_MONITORX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48132, 74},
+ {I_MONITORX, 3, {REG_RAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+48132, 59},
+ {I_MONITORX, 3, {REG_EAX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+48132, 74},
+ {I_MONITORX, 3, {REG_AX,REG_ECX,REG_EDX,0,0}, NO_DECORATOR, nasm_bytecodes+48132, 74},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOV[] = {
+ {I_MOV, 2, {MEMORY,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48153, 75},
+ {I_MOV, 2, {REG_GPR|BITS16,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48137, 0},
+ {I_MOV, 2, {REG_GPR|BITS32,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48142, 5},
+ {I_MOV, 2, {REG_GPR|BITS64,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48147, 76},
+ {I_MOV, 2, {RM_GPR|BITS64,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48152, 7},
+ {I_MOV, 2, {REG_SREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48173, 75},
+ {I_MOV, 2, {REG_SREG,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48173, 77},
+ {I_MOV, 2, {REG_SREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48173, 78},
+ {I_MOV, 2, {REG_SREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48157, 76},
+ {I_MOV, 2, {REG_SREG,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48162, 0},
+ {I_MOV, 2, {REG_SREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48167, 5},
+ {I_MOV, 2, {REG_SREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48172, 7},
+ {I_MOV, 2, {REG_AL,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+49839, 8},
+ {I_MOV, 2, {REG_AX,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+48177, 8},
+ {I_MOV, 2, {REG_EAX,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+48182, 9},
+ {I_MOV, 2, {REG_RAX,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+48187, 10},
+ {I_MOV, 2, {MEM_OFFS,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49843, 79},
+ {I_MOV, 2, {MEM_OFFS,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48192, 79},
+ {I_MOV, 2, {MEM_OFFS,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48197, 80},
+ {I_MOV, 2, {MEM_OFFS,REG_RAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48202, 81},
+ {I_MOV, 2, {REG_GPR|BITS32,REG_CREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43275, 82},
+ {I_MOV, 2, {REG_GPR|BITS64,REG_CREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43281, 83},
+ {I_MOV, 2, {REG_CREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43287, 82},
+ {I_MOV, 2, {REG_CREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43293, 83},
+ {I_MOV, 2, {REG_GPR|BITS32,REG_DREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43300, 82},
+ {I_MOV, 2, {REG_GPR|BITS64,REG_DREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43299, 83},
+ {I_MOV, 2, {REG_DREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43306, 82},
+ {I_MOV, 2, {REG_DREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43305, 83},
+ {I_MOV, 2, {REG_GPR|BITS32,REG_TREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48207, 19},
+ {I_MOV, 2, {REG_TREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48212, 19},
+ {I_MOV, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48217, 8},
+ {I_MOV, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48218, 0},
+ {I_MOV, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43311, 8},
+ {I_MOV, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43312, 0},
+ {I_MOV, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43317, 9},
+ {I_MOV, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43318, 5},
+ {I_MOV, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43323, 10},
+ {I_MOV, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43324, 7},
+ {I_MOV, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+49847, 8},
+ {I_MOV, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+49847, 0},
+ {I_MOV, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48222, 8},
+ {I_MOV, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48222, 0},
+ {I_MOV, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48227, 9},
+ {I_MOV, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48227, 5},
+ {I_MOV, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48232, 10},
+ {I_MOV, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48232, 7},
+ {I_MOV, 2, {REG_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49851, 8},
+ {I_MOV, 2, {REG_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48237, 8},
+ {I_MOV, 2, {REG_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48242, 9},
+ {I_MOV, 2, {REG_GPR|BITS64,UDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+48247, 84},
+ {I_MOV, 2, {REG_GPR|BITS64,SDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33201, 84},
+ {I_MOV, 2, {REG_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48252, 10},
+ {I_MOV, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43329, 8},
+ {I_MOV, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33186, 8},
+ {I_MOV, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33193, 9},
+ {I_MOV, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33200, 10},
+ {I_MOV, 2, {RM_GPR|BITS64,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33200, 7},
+ {I_MOV, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43329, 8},
+ {I_MOV, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33186, 8},
+ {I_MOV, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33193, 9},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVD[] = {
+ {I_MOVD, 2, {MMXREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43335, 85},
+ {I_MOVD, 2, {RM_GPR|BITS32,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43341, 85},
+ {I_MOVD, 2, {MMXREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33207, 86},
+ {I_MOVD, 2, {RM_GPR|BITS64,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+33214, 86},
+ {I_MOVD, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34138, 148},
+ {I_MOVD, 2, {XMM_L16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34145, 148},
+ {I_MOVD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34145, 144},
+ {I_MOVD, 2, {RM_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34138, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVQ[] = {
+ {I_MOVQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43347, 87},
+ {I_MOVQ, 2, {RM_MMX,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43353, 87},
+ {I_MOVQ, 2, {MMXREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33207, 88},
+ {I_MOVQ, 2, {RM_GPR|BITS64,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+33214, 88},
+ {I_MOVQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44985, 144},
+ {I_MOVQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44991, 144},
+ {I_MOVQ, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44991, 149},
+ {I_MOVQ, 2, {XMM_L16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44985, 149},
+ {I_MOVQ, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34152, 150},
+ {I_MOVQ, 2, {RM_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34159, 150},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSB[] = {
+ {I_MOVSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12437, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSD[] = {
+ {I_MOVSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49855, 5},
+ {I_MOVSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45543, 144},
+ {I_MOVSD, 2, {RM_XMM_L16|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45549, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSQ[] = {
+ {I_MOVSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49859, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSW[] = {
+ {I_MOVSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49863, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSX[] = {
+ {I_MOVSX, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43359, 53},
+ {I_MOVSX, 2, {REG_GPR|BITS16,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43359, 5},
+ {I_MOVSX, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43365, 5},
+ {I_MOVSX, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43371, 5},
+ {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43377, 7},
+ {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43383, 7},
+ {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48257, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSXD[] = {
+ {I_MOVSXD, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48257, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVZX[] = {
+ {I_MOVZX, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43389, 53},
+ {I_MOVZX, 2, {REG_GPR|BITS16,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43389, 5},
+ {I_MOVZX, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43395, 5},
+ {I_MOVZX, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43401, 5},
+ {I_MOVZX, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43407, 7},
+ {I_MOVZX, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43413, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MUL[] = {
+ {I_MUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49867, 0},
+ {I_MUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48262, 0},
+ {I_MUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48267, 5},
+ {I_MUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48272, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MWAIT[] = {
+ {I_MWAIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48277, 72},
+ {I_MWAIT, 2, {REG_EAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48277, 72},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MWAITX[] = {
+ {I_MWAITX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48282, 74},
+ {I_MWAITX, 2, {REG_EAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48282, 74},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_NEG[] = {
+ {I_NEG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48287, 11},
+ {I_NEG, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43419, 11},
+ {I_NEG, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43425, 12},
+ {I_NEG, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43431, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_NOP[] = {
+ {I_NOP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48292, 0},
+ {I_NOP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43437, 89},
+ {I_NOP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43443, 89},
+ {I_NOP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43449, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_NOT[] = {
+ {I_NOT, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48297, 11},
+ {I_NOT, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43455, 11},
+ {I_NOT, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43461, 12},
+ {I_NOT, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43467, 13},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_OR[] = {
+ {I_OR, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48302, 3},
+ {I_OR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48303, 0},
+ {I_OR, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43473, 3},
+ {I_OR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43474, 0},
+ {I_OR, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43479, 4},
+ {I_OR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43480, 5},
+ {I_OR, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43485, 6},
+ {I_OR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43486, 7},
+ {I_OR, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40679, 8},
+ {I_OR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40679, 0},
+ {I_OR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48307, 8},
+ {I_OR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48307, 0},
+ {I_OR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48312, 9},
+ {I_OR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48312, 5},
+ {I_OR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48317, 10},
+ {I_OR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48317, 7},
+ {I_OR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33221, 11},
+ {I_OR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33228, 12},
+ {I_OR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33235, 13},
+ {I_OR, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49871, 8},
+ {I_OR, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33222, 8},
+ {I_OR, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48322, 8},
+ {I_OR, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33229, 9},
+ {I_OR, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48327, 9},
+ {I_OR, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33236, 10},
+ {I_OR, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48332, 10},
+ {I_OR, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43491, 3},
+ {I_OR, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33221, 3},
+ {I_OR, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33242, 3},
+ {I_OR, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33228, 4},
+ {I_OR, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33249, 4},
+ {I_OR, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33235, 6},
+ {I_OR, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33256, 6},
+ {I_OR, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43491, 3},
+ {I_OR, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33221, 3},
+ {I_OR, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33242, 3},
+ {I_OR, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33228, 4},
+ {I_OR, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33249, 4},
+ {I_OR, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43497, 14},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_OUT[] = {
+ {I_OUT, 2, {IMMEDIATE,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49875, 52},
+ {I_OUT, 2, {IMMEDIATE,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48337, 52},
+ {I_OUT, 2, {IMMEDIATE,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48342, 53},
+ {I_OUT, 2, {REG_DX,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+46074, 0},
+ {I_OUT, 2, {REG_DX,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49879, 0},
+ {I_OUT, 2, {REG_DX,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49883, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_OUTSB[] = {
+ {I_OUTSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50223, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_OUTSD[] = {
+ {I_OUTSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49887, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_OUTSW[] = {
+ {I_OUTSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49891, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PACKSSDW[] = {
+ {I_PACKSSDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33263, 87},
+ {I_PACKSSDW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45009, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PACKSSWB[] = {
+ {I_PACKSSWB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33270, 87},
+ {I_PACKSSWB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45003, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PACKUSWB[] = {
+ {I_PACKUSWB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33277, 87},
+ {I_PACKUSWB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45015, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDB[] = {
+ {I_PADDB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33284, 87},
+ {I_PADDB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45021, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDD[] = {
+ {I_PADDD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33291, 87},
+ {I_PADDD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45033, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDSB[] = {
+ {I_PADDSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33298, 87},
+ {I_PADDSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45051, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDSIW[] = {
+ {I_PADDSIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43503, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDSW[] = {
+ {I_PADDSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33305, 87},
+ {I_PADDSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45057, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDUSB[] = {
+ {I_PADDUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33312, 87},
+ {I_PADDUSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45063, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDUSW[] = {
+ {I_PADDUSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33319, 87},
+ {I_PADDUSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45069, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDW[] = {
+ {I_PADDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33326, 87},
+ {I_PADDW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45027, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PAND[] = {
+ {I_PAND, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33333, 87},
+ {I_PAND, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45075, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PANDN[] = {
+ {I_PANDN, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33340, 87},
+ {I_PANDN, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45081, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PAUSE[] = {
+ {I_PAUSE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49895, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PAVEB[] = {
+ {I_PAVEB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43509, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PAVGUSB[] = {
+ {I_PAVGUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12376, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPEQB[] = {
+ {I_PCMPEQB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33347, 87},
+ {I_PCMPEQB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45099, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPEQD[] = {
+ {I_PCMPEQD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33354, 87},
+ {I_PCMPEQD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45111, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPEQW[] = {
+ {I_PCMPEQW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33361, 87},
+ {I_PCMPEQW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45105, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPGTB[] = {
+ {I_PCMPGTB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33368, 87},
+ {I_PCMPGTB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45117, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPGTD[] = {
+ {I_PCMPGTD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33375, 87},
+ {I_PCMPGTD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45129, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPGTW[] = {
+ {I_PCMPGTW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33382, 87},
+ {I_PCMPGTW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45123, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PDISTIB[] = {
+ {I_PDISTIB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45376, 92},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PF2ID[] = {
+ {I_PF2ID, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12384, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFACC[] = {
+ {I_PFACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12392, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFADD[] = {
+ {I_PFADD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12400, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFCMPEQ[] = {
+ {I_PFCMPEQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12408, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFCMPGE[] = {
+ {I_PFCMPGE, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12416, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFCMPGT[] = {
+ {I_PFCMPGT, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12424, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFMAX[] = {
+ {I_PFMAX, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12432, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFMIN[] = {
+ {I_PFMIN, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12440, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFMUL[] = {
+ {I_PFMUL, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12448, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFRCP[] = {
+ {I_PFRCP, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12456, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFRCPIT1[] = {
+ {I_PFRCPIT1, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12464, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFRCPIT2[] = {
+ {I_PFRCPIT2, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12472, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFRSQIT1[] = {
+ {I_PFRSQIT1, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12480, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFRSQRT[] = {
+ {I_PFRSQRT, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12488, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFSUB[] = {
+ {I_PFSUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12496, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFSUBR[] = {
+ {I_PFSUBR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12504, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PI2FD[] = {
+ {I_PI2FD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12512, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMACHRIW[] = {
+ {I_PMACHRIW, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45472, 92},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMADDWD[] = {
+ {I_PMADDWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33389, 87},
+ {I_PMADDWD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45135, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMAGW[] = {
+ {I_PMAGW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43515, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULHRIW[] = {
+ {I_PMULHRIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43521, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULHRWA[] = {
+ {I_PMULHRWA, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12520, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULHRWC[] = {
+ {I_PMULHRWC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43527, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULHW[] = {
+ {I_PMULHW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33396, 87},
+ {I_PMULHW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45177, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULLW[] = {
+ {I_PMULLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33403, 87},
+ {I_PMULLW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45183, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMVGEZB[] = {
+ {I_PMVGEZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45604, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMVLZB[] = {
+ {I_PMVLZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45460, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMVNZB[] = {
+ {I_PMVNZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45442, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMVZB[] = {
+ {I_PMVZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45364, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POP[] = {
+ {I_POP, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49899, 0},
+ {I_POP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49903, 19},
+ {I_POP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49907, 7},
+ {I_POP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48347, 0},
+ {I_POP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48352, 19},
+ {I_POP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48357, 7},
+ {I_POP, 1, {REG_ES,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12813, 1},
+ {I_POP, 1, {REG_CS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7495, 93},
+ {I_POP, 1, {REG_SS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7621, 1},
+ {I_POP, 1, {REG_DS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7765, 1},
+ {I_POP, 1, {REG_FS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49911, 5},
+ {I_POP, 1, {REG_GS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49915, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPA[] = {
+ {I_POPA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49919, 18},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPAD[] = {
+ {I_POPAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49923, 19},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPAW[] = {
+ {I_POPAW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49927, 18},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPF[] = {
+ {I_POPF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49931, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPFD[] = {
+ {I_POPFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49935, 19},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPFQ[] = {
+ {I_POPFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49935, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPFW[] = {
+ {I_POPFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49939, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POR[] = {
+ {I_POR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33410, 87},
+ {I_POR, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45195, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCH[] = {
+ {I_PREFETCH, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48362, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHW[] = {
+ {I_PREFETCHW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48367, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSLLD[] = {
+ {I_PSLLD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33417, 87},
+ {I_PSLLD, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33424, 34},
+ {I_PSLLD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45213, 145},
+ {I_PSLLD, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34222, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSLLQ[] = {
+ {I_PSLLQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33431, 87},
+ {I_PSLLQ, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33438, 34},
+ {I_PSLLQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45219, 145},
+ {I_PSLLQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34229, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSLLW[] = {
+ {I_PSLLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33445, 87},
+ {I_PSLLW, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33452, 34},
+ {I_PSLLW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45207, 145},
+ {I_PSLLW, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34215, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSRAD[] = {
+ {I_PSRAD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33459, 87},
+ {I_PSRAD, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33466, 34},
+ {I_PSRAD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45231, 145},
+ {I_PSRAD, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34243, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSRAW[] = {
+ {I_PSRAW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33473, 87},
+ {I_PSRAW, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33480, 34},
+ {I_PSRAW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45225, 145},
+ {I_PSRAW, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34236, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSRLD[] = {
+ {I_PSRLD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33487, 87},
+ {I_PSRLD, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33494, 34},
+ {I_PSRLD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45243, 145},
+ {I_PSRLD, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34264, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSRLQ[] = {
+ {I_PSRLQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33501, 87},
+ {I_PSRLQ, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33508, 34},
+ {I_PSRLQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45249, 145},
+ {I_PSRLQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34271, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSRLW[] = {
+ {I_PSRLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33515, 87},
+ {I_PSRLW, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33522, 34},
+ {I_PSRLW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45237, 145},
+ {I_PSRLW, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34257, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBB[] = {
+ {I_PSUBB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33529, 87},
+ {I_PSUBB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45255, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBD[] = {
+ {I_PSUBD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33536, 87},
+ {I_PSUBD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45267, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBSB[] = {
+ {I_PSUBSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33543, 87},
+ {I_PSUBSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45279, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBSIW[] = {
+ {I_PSUBSIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43533, 90},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBSW[] = {
+ {I_PSUBSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33550, 87},
+ {I_PSUBSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45285, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBUSB[] = {
+ {I_PSUBUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33557, 87},
+ {I_PSUBUSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45291, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBUSW[] = {
+ {I_PSUBUSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33564, 87},
+ {I_PSUBUSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45297, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBW[] = {
+ {I_PSUBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33571, 87},
+ {I_PSUBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45261, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKHBW[] = {
+ {I_PUNPCKHBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33578, 87},
+ {I_PUNPCKHBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45303, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKHDQ[] = {
+ {I_PUNPCKHDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33585, 87},
+ {I_PUNPCKHDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45315, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKHWD[] = {
+ {I_PUNPCKHWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33592, 87},
+ {I_PUNPCKHWD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45309, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKLBW[] = {
+ {I_PUNPCKLBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33599, 87},
+ {I_PUNPCKLBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45327, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKLDQ[] = {
+ {I_PUNPCKLDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33606, 87},
+ {I_PUNPCKLDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45339, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKLWD[] = {
+ {I_PUNPCKLWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33613, 87},
+ {I_PUNPCKLWD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45333, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSH[] = {
+ {I_PUSH, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49943, 0},
+ {I_PUSH, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49947, 19},
+ {I_PUSH, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49951, 7},
+ {I_PUSH, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48372, 0},
+ {I_PUSH, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48377, 19},
+ {I_PUSH, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48382, 7},
+ {I_PUSH, 1, {REG_ES,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12781, 1},
+ {I_PUSH, 1, {REG_CS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7477, 1},
+ {I_PUSH, 1, {REG_SS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7603, 1},
+ {I_PUSH, 1, {REG_DS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7747, 1},
+ {I_PUSH, 1, {REG_FS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49955, 5},
+ {I_PUSH, 1, {REG_GS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49959, 5},
+ {I_PUSH, 1, {IMMEDIATE|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48408, 35},
+ {I_PUSH, 1, {SBYTEWORD|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48387, 94},
+ {I_PUSH, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48392, 94},
+ {I_PUSH, 1, {SBYTEDWORD|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48397, 95},
+ {I_PUSH, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48402, 95},
+ {I_PUSH, 1, {SBYTEDWORD|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48397, 96},
+ {I_PUSH, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48402, 96},
+ {I_PUSH, 1, {SBYTEDWORD|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48407, 97},
+ {I_PUSH, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48412, 97},
+ {I_PUSH, 1, {SBYTEDWORD|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48407, 97},
+ {I_PUSH, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48412, 97},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSHA[] = {
+ {I_PUSHA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49963, 18},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSHAD[] = {
+ {I_PUSHAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49967, 19},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSHAW[] = {
+ {I_PUSHAW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49971, 18},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSHF[] = {
+ {I_PUSHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49975, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSHFD[] = {
+ {I_PUSHFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49979, 19},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSHFQ[] = {
+ {I_PUSHFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49979, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUSHFW[] = {
+ {I_PUSHFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49983, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PXOR[] = {
+ {I_PXOR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33620, 87},
+ {I_PXOR, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45351, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RCL[] = {
+ {I_RCL, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+49987, 0},
+ {I_RCL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49991, 0},
+ {I_RCL, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48417, 35},
+ {I_RCL, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48422, 0},
+ {I_RCL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48427, 0},
+ {I_RCL, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43539, 35},
+ {I_RCL, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48432, 5},
+ {I_RCL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48437, 5},
+ {I_RCL, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43545, 5},
+ {I_RCL, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48442, 7},
+ {I_RCL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48447, 7},
+ {I_RCL, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43551, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RCR[] = {
+ {I_RCR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+49995, 0},
+ {I_RCR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49999, 0},
+ {I_RCR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48452, 35},
+ {I_RCR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48457, 0},
+ {I_RCR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48462, 0},
+ {I_RCR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43557, 35},
+ {I_RCR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48467, 5},
+ {I_RCR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48472, 5},
+ {I_RCR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43563, 5},
+ {I_RCR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48477, 7},
+ {I_RCR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48482, 7},
+ {I_RCR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43569, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDSHR[] = {
+ {I_RDSHR, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43575, 98},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDMSR[] = {
+ {I_RDMSR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50003, 99},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDPMC[] = {
+ {I_RDPMC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50007, 89},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDTSC[] = {
+ {I_RDTSC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50011, 28},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDTSCP[] = {
+ {I_RDTSCP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48487, 100},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RET[] = {
+ {I_RET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50032, 21},
+ {I_RET, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48513, 101},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETF[] = {
+ {I_RETF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50036, 0},
+ {I_RETF, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48518, 75},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETN[] = {
+ {I_RETN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50032, 21},
+ {I_RETN, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48513, 101},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETW[] = {
+ {I_RETW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50015, 21},
+ {I_RETW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48513, 101},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETFW[] = {
+ {I_RETFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50019, 0},
+ {I_RETFW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48492, 75},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETNW[] = {
+ {I_RETNW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50015, 21},
+ {I_RETNW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48497, 101},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETD[] = {
+ {I_RETD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50023, 22},
+ {I_RETD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48502, 102},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETFD[] = {
+ {I_RETFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50027, 0},
+ {I_RETFD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48507, 75},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETND[] = {
+ {I_RETND, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50023, 22},
+ {I_RETND, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48502, 102},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETQ[] = {
+ {I_RETQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50031, 24},
+ {I_RETQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48512, 103},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETFQ[] = {
+ {I_RETFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50035, 7},
+ {I_RETFQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48517, 104},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RETNQ[] = {
+ {I_RETNQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50031, 24},
+ {I_RETNQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48512, 103},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ROL[] = {
+ {I_ROL, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50039, 0},
+ {I_ROL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50043, 0},
+ {I_ROL, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48522, 35},
+ {I_ROL, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48527, 0},
+ {I_ROL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48532, 0},
+ {I_ROL, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43581, 35},
+ {I_ROL, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48537, 5},
+ {I_ROL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48542, 5},
+ {I_ROL, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43587, 5},
+ {I_ROL, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48547, 7},
+ {I_ROL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48552, 7},
+ {I_ROL, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43593, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ROR[] = {
+ {I_ROR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50047, 0},
+ {I_ROR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50051, 0},
+ {I_ROR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48557, 35},
+ {I_ROR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48562, 0},
+ {I_ROR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48567, 0},
+ {I_ROR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43599, 35},
+ {I_ROR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48572, 5},
+ {I_ROR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48577, 5},
+ {I_ROR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43605, 5},
+ {I_ROR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48582, 7},
+ {I_ROR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48587, 7},
+ {I_ROR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43611, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDM[] = {
+ {I_RDM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49215, 33},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RSDC[] = {
+ {I_RSDC, 2, {REG_SREG,MEMORY|BITS80,0,0,0}, NO_DECORATOR, nasm_bytecodes+45742, 105},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RSLDT[] = {
+ {I_RSLDT, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48592, 105},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RSM[] = {
+ {I_RSM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50055, 106},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RSTS[] = {
+ {I_RSTS, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48597, 105},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SAHF[] = {
+ {I_SAHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12405, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SAL[] = {
+ {I_SAL, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50059, 0},
+ {I_SAL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50063, 0},
+ {I_SAL, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48602, 35},
+ {I_SAL, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48607, 0},
+ {I_SAL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48612, 0},
+ {I_SAL, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43617, 35},
+ {I_SAL, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48617, 5},
+ {I_SAL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48622, 5},
+ {I_SAL, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43623, 5},
+ {I_SAL, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48627, 7},
+ {I_SAL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48632, 7},
+ {I_SAL, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43629, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SALC[] = {
+ {I_SALC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49174, 107},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SAR[] = {
+ {I_SAR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50067, 0},
+ {I_SAR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50071, 0},
+ {I_SAR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48637, 35},
+ {I_SAR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48642, 0},
+ {I_SAR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48647, 0},
+ {I_SAR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43635, 35},
+ {I_SAR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48652, 5},
+ {I_SAR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48657, 5},
+ {I_SAR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43641, 5},
+ {I_SAR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48662, 7},
+ {I_SAR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48667, 7},
+ {I_SAR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43647, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SBB[] = {
+ {I_SBB, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48672, 3},
+ {I_SBB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48673, 0},
+ {I_SBB, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43653, 3},
+ {I_SBB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43654, 0},
+ {I_SBB, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43659, 4},
+ {I_SBB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43660, 5},
+ {I_SBB, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43665, 6},
+ {I_SBB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43666, 7},
+ {I_SBB, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+35268, 8},
+ {I_SBB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+35268, 0},
+ {I_SBB, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48677, 8},
+ {I_SBB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48677, 0},
+ {I_SBB, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48682, 9},
+ {I_SBB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48682, 5},
+ {I_SBB, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48687, 10},
+ {I_SBB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48687, 7},
+ {I_SBB, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33627, 11},
+ {I_SBB, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33634, 12},
+ {I_SBB, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33641, 13},
+ {I_SBB, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50075, 8},
+ {I_SBB, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33628, 8},
+ {I_SBB, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48692, 8},
+ {I_SBB, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33635, 9},
+ {I_SBB, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48697, 9},
+ {I_SBB, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33642, 10},
+ {I_SBB, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48702, 10},
+ {I_SBB, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43671, 3},
+ {I_SBB, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33627, 3},
+ {I_SBB, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33648, 3},
+ {I_SBB, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33634, 4},
+ {I_SBB, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33655, 4},
+ {I_SBB, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33641, 6},
+ {I_SBB, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33662, 6},
+ {I_SBB, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43671, 3},
+ {I_SBB, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33627, 3},
+ {I_SBB, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33648, 3},
+ {I_SBB, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33634, 4},
+ {I_SBB, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33655, 4},
+ {I_SBB, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43677, 14},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SCASB[] = {
+ {I_SCASB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50079, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SCASD[] = {
+ {I_SCASD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48707, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SCASQ[] = {
+ {I_SCASQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48712, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SCASW[] = {
+ {I_SCASW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48717, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SFENCE[] = {
+ {I_SFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43683, 59},
+ {I_SFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43683, 139},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SGDT[] = {
+ {I_SGDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48722, 108},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHL[] = {
+ {I_SHL, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50059, 0},
+ {I_SHL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50063, 0},
+ {I_SHL, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48602, 35},
+ {I_SHL, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48607, 0},
+ {I_SHL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48612, 0},
+ {I_SHL, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43617, 35},
+ {I_SHL, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48617, 5},
+ {I_SHL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48622, 5},
+ {I_SHL, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43623, 5},
+ {I_SHL, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48627, 7},
+ {I_SHL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48632, 7},
+ {I_SHL, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43629, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHLD[] = {
+ {I_SHLD, 3, {MEMORY,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33669, 109},
+ {I_SHLD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33669, 109},
+ {I_SHLD, 3, {MEMORY,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33676, 109},
+ {I_SHLD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33676, 109},
+ {I_SHLD, 3, {MEMORY,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33683, 110},
+ {I_SHLD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33683, 110},
+ {I_SHLD, 3, {MEMORY,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43689, 9},
+ {I_SHLD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43689, 5},
+ {I_SHLD, 3, {MEMORY,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43695, 9},
+ {I_SHLD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43695, 5},
+ {I_SHLD, 3, {MEMORY,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43701, 10},
+ {I_SHLD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43701, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHR[] = {
+ {I_SHR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50083, 0},
+ {I_SHR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50087, 0},
+ {I_SHR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48727, 35},
+ {I_SHR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48732, 0},
+ {I_SHR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48737, 0},
+ {I_SHR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43707, 35},
+ {I_SHR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48742, 5},
+ {I_SHR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48747, 5},
+ {I_SHR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43713, 5},
+ {I_SHR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48752, 7},
+ {I_SHR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48757, 7},
+ {I_SHR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43719, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHRD[] = {
+ {I_SHRD, 3, {MEMORY,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33690, 109},
+ {I_SHRD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33690, 109},
+ {I_SHRD, 3, {MEMORY,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33697, 109},
+ {I_SHRD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33697, 109},
+ {I_SHRD, 3, {MEMORY,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33704, 110},
+ {I_SHRD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33704, 110},
+ {I_SHRD, 3, {MEMORY,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43725, 9},
+ {I_SHRD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43725, 5},
+ {I_SHRD, 3, {MEMORY,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43731, 9},
+ {I_SHRD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43731, 5},
+ {I_SHRD, 3, {MEMORY,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43737, 10},
+ {I_SHRD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43737, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SIDT[] = {
+ {I_SIDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48762, 108},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SLDT[] = {
+ {I_SLDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43762, 108},
+ {I_SLDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43762, 108},
+ {I_SLDT, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43743, 108},
+ {I_SLDT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43749, 5},
+ {I_SLDT, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43755, 7},
+ {I_SLDT, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43761, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SKINIT[] = {
+ {I_SKINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48767, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SMI[] = {
+ {I_SMI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50205, 111},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SMINT[] = {
+ {I_SMINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50091, 33},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SMINTOLD[] = {
+ {I_SMINTOLD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50095, 112},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SMSW[] = {
+ {I_SMSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43780, 108},
+ {I_SMSW, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43780, 108},
+ {I_SMSW, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43767, 108},
+ {I_SMSW, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43773, 5},
+ {I_SMSW, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43779, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STC[] = {
+ {I_STC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48489, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STD[] = {
+ {I_STD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50226, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STI[] = {
+ {I_STI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48284, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STOSB[] = {
+ {I_STOSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12509, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STOSD[] = {
+ {I_STOSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50099, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STOSQ[] = {
+ {I_STOSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50103, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STOSW[] = {
+ {I_STOSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50107, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STR[] = {
+ {I_STR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43798, 62},
+ {I_STR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43798, 62},
+ {I_STR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43785, 62},
+ {I_STR, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43791, 63},
+ {I_STR, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43797, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SUB[] = {
+ {I_SUB, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48772, 3},
+ {I_SUB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48773, 0},
+ {I_SUB, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43803, 3},
+ {I_SUB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43804, 0},
+ {I_SUB, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43809, 4},
+ {I_SUB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43810, 5},
+ {I_SUB, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43815, 6},
+ {I_SUB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43816, 7},
+ {I_SUB, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41036, 8},
+ {I_SUB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+41036, 0},
+ {I_SUB, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48777, 8},
+ {I_SUB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48777, 0},
+ {I_SUB, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48782, 9},
+ {I_SUB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48782, 5},
+ {I_SUB, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48787, 10},
+ {I_SUB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48787, 7},
+ {I_SUB, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33711, 11},
+ {I_SUB, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33718, 12},
+ {I_SUB, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33725, 13},
+ {I_SUB, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50111, 8},
+ {I_SUB, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33712, 8},
+ {I_SUB, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48792, 8},
+ {I_SUB, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33719, 9},
+ {I_SUB, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48797, 9},
+ {I_SUB, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33726, 10},
+ {I_SUB, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48802, 10},
+ {I_SUB, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43821, 3},
+ {I_SUB, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33711, 3},
+ {I_SUB, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33732, 3},
+ {I_SUB, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33718, 4},
+ {I_SUB, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33739, 4},
+ {I_SUB, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33725, 6},
+ {I_SUB, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33746, 6},
+ {I_SUB, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43821, 3},
+ {I_SUB, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33711, 3},
+ {I_SUB, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33732, 3},
+ {I_SUB, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33718, 4},
+ {I_SUB, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33739, 4},
+ {I_SUB, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43827, 14},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SVDC[] = {
+ {I_SVDC, 2, {MEMORY|BITS80,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34357, 105},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SVLDT[] = {
+ {I_SVLDT, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48807, 105},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SVTS[] = {
+ {I_SVTS, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48812, 105},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SWAPGS[] = {
+ {I_SWAPGS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48817, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SYSCALL[] = {
+ {I_SYSCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49823, 113},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SYSENTER[] = {
+ {I_SYSENTER, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50115, 89},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SYSEXIT[] = {
+ {I_SYSEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50119, 114},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SYSRET[] = {
+ {I_SYSRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49819, 115},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TEST[] = {
+ {I_TEST, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+50123, 8},
+ {I_TEST, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+50123, 0},
+ {I_TEST, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48822, 8},
+ {I_TEST, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48822, 0},
+ {I_TEST, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48827, 9},
+ {I_TEST, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48827, 5},
+ {I_TEST, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48832, 10},
+ {I_TEST, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48832, 7},
+ {I_TEST, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50127, 8},
+ {I_TEST, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48837, 8},
+ {I_TEST, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48842, 9},
+ {I_TEST, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48847, 10},
+ {I_TEST, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50131, 8},
+ {I_TEST, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48852, 8},
+ {I_TEST, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48857, 9},
+ {I_TEST, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48862, 10},
+ {I_TEST, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48867, 8},
+ {I_TEST, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43833, 8},
+ {I_TEST, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43839, 9},
+ {I_TEST, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43845, 10},
+ {I_TEST, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48867, 8},
+ {I_TEST, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43833, 8},
+ {I_TEST, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43839, 9},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UD0[] = {
+ {I_UD0, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50135, 116},
+ {I_UD0, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43851, 35},
+ {I_UD0, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43857, 35},
+ {I_UD0, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43863, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UD1[] = {
+ {I_UD1, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43869, 35},
+ {I_UD1, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43875, 35},
+ {I_UD1, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43881, 35},
+ {I_UD1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50139, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UD2B[] = {
+ {I_UD2B, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50139, 35},
+ {I_UD2B, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43869, 35},
+ {I_UD2B, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43875, 35},
+ {I_UD2B, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43881, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UD2[] = {
+ {I_UD2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50143, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UD2A[] = {
+ {I_UD2A, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50143, 35},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UMOV[] = {
+ {I_UMOV, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43887, 117},
+ {I_UMOV, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43887, 111},
+ {I_UMOV, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33753, 117},
+ {I_UMOV, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33753, 111},
+ {I_UMOV, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33760, 117},
+ {I_UMOV, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33760, 111},
+ {I_UMOV, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43893, 117},
+ {I_UMOV, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43893, 111},
+ {I_UMOV, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33767, 117},
+ {I_UMOV, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33767, 111},
+ {I_UMOV, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33774, 117},
+ {I_UMOV, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33774, 111},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VERR[] = {
+ {I_VERR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48872, 62},
+ {I_VERR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48872, 62},
+ {I_VERR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48872, 62},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VERW[] = {
+ {I_VERW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48877, 62},
+ {I_VERW, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48877, 62},
+ {I_VERW, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48877, 62},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FWAIT[] = {
+ {I_FWAIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49721, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WBINVD[] = {
+ {I_WBINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49183, 54},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRSHR[] = {
+ {I_WRSHR, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43899, 98},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRMSR[] = {
+ {I_WRMSR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50147, 99},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XADD[] = {
+ {I_XADD, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43905, 118},
+ {I_XADD, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43906, 20},
+ {I_XADD, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33781, 118},
+ {I_XADD, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33782, 20},
+ {I_XADD, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33788, 118},
+ {I_XADD, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33789, 20},
+ {I_XADD, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33795, 6},
+ {I_XADD, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33796, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XBTS[] = {
+ {I_XBTS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43911, 119},
+ {I_XBTS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43911, 111},
+ {I_XBTS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43917, 120},
+ {I_XBTS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43917, 111},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XCHG[] = {
+ {I_XCHG, 2, {REG_AX,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+50151, 0},
+ {I_XCHG, 2, {REG_EAX,REG32NA,0,0,0}, NO_DECORATOR, nasm_bytecodes+50155, 5},
+ {I_XCHG, 2, {REG_RAX,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+50159, 7},
+ {I_XCHG, 2, {REG_GPR|BITS16,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50163, 0},
+ {I_XCHG, 2, {REG32NA,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50167, 5},
+ {I_XCHG, 2, {REG_GPR|BITS64,REG_RAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50171, 7},
+ {I_XCHG, 2, {REG_EAX,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50175, 19},
+ {I_XCHG, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48882, 3},
+ {I_XCHG, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48883, 0},
+ {I_XCHG, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43923, 3},
+ {I_XCHG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43924, 0},
+ {I_XCHG, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43929, 4},
+ {I_XCHG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43930, 5},
+ {I_XCHG, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43935, 6},
+ {I_XCHG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43936, 7},
+ {I_XCHG, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48887, 3},
+ {I_XCHG, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48888, 0},
+ {I_XCHG, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43941, 3},
+ {I_XCHG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43942, 0},
+ {I_XCHG, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43947, 4},
+ {I_XCHG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43948, 5},
+ {I_XCHG, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43953, 6},
+ {I_XCHG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43954, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XLATB[] = {
+ {I_XLATB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46014, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XLAT[] = {
+ {I_XLAT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46014, 0},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XOR[] = {
+ {I_XOR, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48892, 3},
+ {I_XOR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48893, 0},
+ {I_XOR, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43959, 3},
+ {I_XOR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43960, 0},
+ {I_XOR, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43965, 4},
+ {I_XOR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43966, 5},
+ {I_XOR, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43971, 6},
+ {I_XOR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43972, 7},
+ {I_XOR, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40476, 8},
+ {I_XOR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40476, 0},
+ {I_XOR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48897, 8},
+ {I_XOR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48897, 0},
+ {I_XOR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48902, 9},
+ {I_XOR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48902, 5},
+ {I_XOR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48907, 10},
+ {I_XOR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48907, 7},
+ {I_XOR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33802, 11},
+ {I_XOR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33809, 12},
+ {I_XOR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33816, 13},
+ {I_XOR, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50179, 8},
+ {I_XOR, 2, {REG_AX,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33803, 8},
+ {I_XOR, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48912, 8},
+ {I_XOR, 2, {REG_EAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33810, 9},
+ {I_XOR, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48917, 9},
+ {I_XOR, 2, {REG_RAX,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33817, 10},
+ {I_XOR, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48922, 10},
+ {I_XOR, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43977, 3},
+ {I_XOR, 2, {RM_GPR|BITS16,SBYTEWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33802, 3},
+ {I_XOR, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33823, 3},
+ {I_XOR, 2, {RM_GPR|BITS32,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33809, 4},
+ {I_XOR, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33830, 4},
+ {I_XOR, 2, {RM_GPR|BITS64,SBYTEDWORD,0,0,0}, NO_DECORATOR, nasm_bytecodes+33816, 6},
+ {I_XOR, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33837, 6},
+ {I_XOR, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43977, 3},
+ {I_XOR, 2, {MEMORY,SBYTEWORD|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33802, 3},
+ {I_XOR, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33823, 3},
+ {I_XOR, 2, {MEMORY,SBYTEDWORD|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33809, 4},
+ {I_XOR, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33830, 4},
+ {I_XOR, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43983, 14},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVA[] = {
+ {I_CMOVA, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43989, 121},
+ {I_CMOVA, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43989, 89},
+ {I_CMOVA, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44085, 121},
+ {I_CMOVA, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44085, 89},
+ {I_CMOVA, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44181, 10},
+ {I_CMOVA, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44181, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVAE[] = {
+ {I_CMOVAE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 121},
+ {I_CMOVAE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 89},
+ {I_CMOVAE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 121},
+ {I_CMOVAE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 89},
+ {I_CMOVAE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 10},
+ {I_CMOVAE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVB[] = {
+ {I_CMOVB, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 121},
+ {I_CMOVB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 89},
+ {I_CMOVB, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 121},
+ {I_CMOVB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 89},
+ {I_CMOVB, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 10},
+ {I_CMOVB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVBE[] = {
+ {I_CMOVBE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44007, 121},
+ {I_CMOVBE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44007, 89},
+ {I_CMOVBE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44103, 121},
+ {I_CMOVBE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44103, 89},
+ {I_CMOVBE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44199, 10},
+ {I_CMOVBE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44199, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVC[] = {
+ {I_CMOVC, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 121},
+ {I_CMOVC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 89},
+ {I_CMOVC, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 121},
+ {I_CMOVC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 89},
+ {I_CMOVC, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 10},
+ {I_CMOVC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVE[] = {
+ {I_CMOVE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44013, 121},
+ {I_CMOVE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44013, 89},
+ {I_CMOVE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44109, 121},
+ {I_CMOVE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44109, 89},
+ {I_CMOVE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44205, 10},
+ {I_CMOVE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44205, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVG[] = {
+ {I_CMOVG, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44019, 121},
+ {I_CMOVG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44019, 89},
+ {I_CMOVG, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44115, 121},
+ {I_CMOVG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44115, 89},
+ {I_CMOVG, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44211, 10},
+ {I_CMOVG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44211, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVGE[] = {
+ {I_CMOVGE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44025, 121},
+ {I_CMOVGE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44025, 89},
+ {I_CMOVGE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44121, 121},
+ {I_CMOVGE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44121, 89},
+ {I_CMOVGE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44217, 10},
+ {I_CMOVGE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44217, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVL[] = {
+ {I_CMOVL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44031, 121},
+ {I_CMOVL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44031, 89},
+ {I_CMOVL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44127, 121},
+ {I_CMOVL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44127, 89},
+ {I_CMOVL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44223, 10},
+ {I_CMOVL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44223, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVLE[] = {
+ {I_CMOVLE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44037, 121},
+ {I_CMOVLE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44037, 89},
+ {I_CMOVLE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44133, 121},
+ {I_CMOVLE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44133, 89},
+ {I_CMOVLE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44229, 10},
+ {I_CMOVLE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44229, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNA[] = {
+ {I_CMOVNA, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44007, 121},
+ {I_CMOVNA, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44007, 89},
+ {I_CMOVNA, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44103, 121},
+ {I_CMOVNA, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44103, 89},
+ {I_CMOVNA, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44199, 10},
+ {I_CMOVNA, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44199, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNAE[] = {
+ {I_CMOVNAE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 121},
+ {I_CMOVNAE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 89},
+ {I_CMOVNAE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 121},
+ {I_CMOVNAE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 89},
+ {I_CMOVNAE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 10},
+ {I_CMOVNAE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNB[] = {
+ {I_CMOVNB, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 121},
+ {I_CMOVNB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 89},
+ {I_CMOVNB, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 121},
+ {I_CMOVNB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 89},
+ {I_CMOVNB, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 10},
+ {I_CMOVNB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNBE[] = {
+ {I_CMOVNBE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43989, 121},
+ {I_CMOVNBE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43989, 89},
+ {I_CMOVNBE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44085, 121},
+ {I_CMOVNBE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44085, 89},
+ {I_CMOVNBE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44181, 10},
+ {I_CMOVNBE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44181, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNC[] = {
+ {I_CMOVNC, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 121},
+ {I_CMOVNC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 89},
+ {I_CMOVNC, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 121},
+ {I_CMOVNC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 89},
+ {I_CMOVNC, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 10},
+ {I_CMOVNC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNE[] = {
+ {I_CMOVNE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44043, 121},
+ {I_CMOVNE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44043, 89},
+ {I_CMOVNE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44139, 121},
+ {I_CMOVNE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44139, 89},
+ {I_CMOVNE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44235, 10},
+ {I_CMOVNE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44235, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNG[] = {
+ {I_CMOVNG, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44037, 121},
+ {I_CMOVNG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44037, 89},
+ {I_CMOVNG, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44133, 121},
+ {I_CMOVNG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44133, 89},
+ {I_CMOVNG, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44229, 10},
+ {I_CMOVNG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44229, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNGE[] = {
+ {I_CMOVNGE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44031, 121},
+ {I_CMOVNGE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44031, 89},
+ {I_CMOVNGE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44127, 121},
+ {I_CMOVNGE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44127, 89},
+ {I_CMOVNGE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44223, 10},
+ {I_CMOVNGE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44223, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNL[] = {
+ {I_CMOVNL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44025, 121},
+ {I_CMOVNL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44025, 89},
+ {I_CMOVNL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44121, 121},
+ {I_CMOVNL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44121, 89},
+ {I_CMOVNL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44217, 10},
+ {I_CMOVNL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44217, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNLE[] = {
+ {I_CMOVNLE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44019, 121},
+ {I_CMOVNLE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44019, 89},
+ {I_CMOVNLE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44115, 121},
+ {I_CMOVNLE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44115, 89},
+ {I_CMOVNLE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44211, 10},
+ {I_CMOVNLE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44211, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNO[] = {
+ {I_CMOVNO, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44049, 121},
+ {I_CMOVNO, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44049, 89},
+ {I_CMOVNO, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44145, 121},
+ {I_CMOVNO, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44145, 89},
+ {I_CMOVNO, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44241, 10},
+ {I_CMOVNO, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44241, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNP[] = {
+ {I_CMOVNP, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44055, 121},
+ {I_CMOVNP, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44055, 89},
+ {I_CMOVNP, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44151, 121},
+ {I_CMOVNP, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44151, 89},
+ {I_CMOVNP, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44247, 10},
+ {I_CMOVNP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44247, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNS[] = {
+ {I_CMOVNS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44061, 121},
+ {I_CMOVNS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44061, 89},
+ {I_CMOVNS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44157, 121},
+ {I_CMOVNS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44157, 89},
+ {I_CMOVNS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44253, 10},
+ {I_CMOVNS, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44253, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVNZ[] = {
+ {I_CMOVNZ, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44043, 121},
+ {I_CMOVNZ, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44043, 89},
+ {I_CMOVNZ, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44139, 121},
+ {I_CMOVNZ, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44139, 89},
+ {I_CMOVNZ, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44235, 10},
+ {I_CMOVNZ, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44235, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVO[] = {
+ {I_CMOVO, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44067, 121},
+ {I_CMOVO, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44067, 89},
+ {I_CMOVO, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44163, 121},
+ {I_CMOVO, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44163, 89},
+ {I_CMOVO, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44259, 10},
+ {I_CMOVO, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44259, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVP[] = {
+ {I_CMOVP, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44073, 121},
+ {I_CMOVP, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44073, 89},
+ {I_CMOVP, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44169, 121},
+ {I_CMOVP, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44169, 89},
+ {I_CMOVP, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44265, 10},
+ {I_CMOVP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44265, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVPE[] = {
+ {I_CMOVPE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44073, 121},
+ {I_CMOVPE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44073, 89},
+ {I_CMOVPE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44169, 121},
+ {I_CMOVPE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44169, 89},
+ {I_CMOVPE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44265, 10},
+ {I_CMOVPE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44265, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVPO[] = {
+ {I_CMOVPO, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44055, 121},
+ {I_CMOVPO, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44055, 89},
+ {I_CMOVPO, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44151, 121},
+ {I_CMOVPO, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44151, 89},
+ {I_CMOVPO, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44247, 10},
+ {I_CMOVPO, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44247, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVS[] = {
+ {I_CMOVS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44079, 121},
+ {I_CMOVS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44079, 89},
+ {I_CMOVS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44175, 121},
+ {I_CMOVS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44175, 89},
+ {I_CMOVS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44271, 10},
+ {I_CMOVS, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44271, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMOVZ[] = {
+ {I_CMOVZ, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44013, 121},
+ {I_CMOVZ, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44013, 89},
+ {I_CMOVZ, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44109, 121},
+ {I_CMOVZ, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44109, 89},
+ {I_CMOVZ, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44205, 10},
+ {I_CMOVZ, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44205, 7},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JA[] = {
+ {I_JA, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44277, 122},
+ {I_JA, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44373, 23},
+ {I_JA, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44469, 23},
+ {I_JA, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44565, 24},
+ {I_JA, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48928, 21},
+ {I_JA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48927, 21},
+ {I_JA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44566, 122},
+ {I_JA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33844, 21},
+ {I_JA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48928, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JAE[] = {
+ {I_JAE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44283, 122},
+ {I_JAE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44379, 23},
+ {I_JAE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44475, 23},
+ {I_JAE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44571, 24},
+ {I_JAE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48933, 21},
+ {I_JAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48932, 21},
+ {I_JAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44572, 122},
+ {I_JAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33851, 21},
+ {I_JAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48933, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JB[] = {
+ {I_JB, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44289, 122},
+ {I_JB, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44385, 23},
+ {I_JB, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44481, 23},
+ {I_JB, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44577, 24},
+ {I_JB, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48938, 21},
+ {I_JB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48937, 21},
+ {I_JB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44578, 122},
+ {I_JB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33858, 21},
+ {I_JB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48938, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JBE[] = {
+ {I_JBE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44295, 122},
+ {I_JBE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44391, 23},
+ {I_JBE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44487, 23},
+ {I_JBE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44583, 24},
+ {I_JBE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48943, 21},
+ {I_JBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48942, 21},
+ {I_JBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44584, 122},
+ {I_JBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33865, 21},
+ {I_JBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48943, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JC[] = {
+ {I_JC, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44289, 122},
+ {I_JC, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44385, 23},
+ {I_JC, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44481, 23},
+ {I_JC, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44577, 24},
+ {I_JC, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48938, 21},
+ {I_JC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48937, 21},
+ {I_JC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44578, 122},
+ {I_JC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33858, 21},
+ {I_JC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48938, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JE[] = {
+ {I_JE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44301, 122},
+ {I_JE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44397, 23},
+ {I_JE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44493, 23},
+ {I_JE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44589, 24},
+ {I_JE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48948, 21},
+ {I_JE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48947, 21},
+ {I_JE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44590, 122},
+ {I_JE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33872, 21},
+ {I_JE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48948, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JG[] = {
+ {I_JG, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44307, 122},
+ {I_JG, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44403, 23},
+ {I_JG, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44499, 23},
+ {I_JG, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44595, 24},
+ {I_JG, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48953, 21},
+ {I_JG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48952, 21},
+ {I_JG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44596, 122},
+ {I_JG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33879, 21},
+ {I_JG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48953, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JGE[] = {
+ {I_JGE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44313, 122},
+ {I_JGE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44409, 23},
+ {I_JGE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44505, 23},
+ {I_JGE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44601, 24},
+ {I_JGE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48958, 21},
+ {I_JGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48957, 21},
+ {I_JGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44602, 122},
+ {I_JGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33886, 21},
+ {I_JGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48958, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JL[] = {
+ {I_JL, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44319, 122},
+ {I_JL, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44415, 23},
+ {I_JL, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44511, 23},
+ {I_JL, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44607, 24},
+ {I_JL, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48963, 21},
+ {I_JL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48962, 21},
+ {I_JL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44608, 122},
+ {I_JL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33893, 21},
+ {I_JL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48963, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JLE[] = {
+ {I_JLE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44325, 122},
+ {I_JLE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44421, 23},
+ {I_JLE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44517, 23},
+ {I_JLE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44613, 24},
+ {I_JLE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48968, 21},
+ {I_JLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48967, 21},
+ {I_JLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44614, 122},
+ {I_JLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33900, 21},
+ {I_JLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48968, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNA[] = {
+ {I_JNA, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44295, 122},
+ {I_JNA, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44391, 23},
+ {I_JNA, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44487, 23},
+ {I_JNA, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44583, 24},
+ {I_JNA, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48943, 21},
+ {I_JNA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48942, 21},
+ {I_JNA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44584, 122},
+ {I_JNA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33865, 21},
+ {I_JNA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48943, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNAE[] = {
+ {I_JNAE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44289, 122},
+ {I_JNAE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44385, 23},
+ {I_JNAE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44481, 23},
+ {I_JNAE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44577, 24},
+ {I_JNAE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48938, 21},
+ {I_JNAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48937, 21},
+ {I_JNAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44578, 122},
+ {I_JNAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33858, 21},
+ {I_JNAE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48938, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNB[] = {
+ {I_JNB, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44283, 122},
+ {I_JNB, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44379, 23},
+ {I_JNB, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44475, 23},
+ {I_JNB, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44571, 24},
+ {I_JNB, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48933, 21},
+ {I_JNB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48932, 21},
+ {I_JNB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44572, 122},
+ {I_JNB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33851, 21},
+ {I_JNB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48933, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNBE[] = {
+ {I_JNBE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44277, 122},
+ {I_JNBE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44373, 23},
+ {I_JNBE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44469, 23},
+ {I_JNBE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44565, 24},
+ {I_JNBE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48928, 21},
+ {I_JNBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48927, 21},
+ {I_JNBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44566, 122},
+ {I_JNBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33844, 21},
+ {I_JNBE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48928, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNC[] = {
+ {I_JNC, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44283, 122},
+ {I_JNC, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44379, 23},
+ {I_JNC, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44475, 23},
+ {I_JNC, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44571, 24},
+ {I_JNC, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48933, 21},
+ {I_JNC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48932, 21},
+ {I_JNC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44572, 122},
+ {I_JNC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33851, 21},
+ {I_JNC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48933, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNE[] = {
+ {I_JNE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44331, 122},
+ {I_JNE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44427, 23},
+ {I_JNE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44523, 23},
+ {I_JNE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44619, 24},
+ {I_JNE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48973, 21},
+ {I_JNE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48972, 21},
+ {I_JNE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44620, 122},
+ {I_JNE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33907, 21},
+ {I_JNE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48973, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNG[] = {
+ {I_JNG, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44325, 122},
+ {I_JNG, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44421, 23},
+ {I_JNG, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44517, 23},
+ {I_JNG, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44613, 24},
+ {I_JNG, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48968, 21},
+ {I_JNG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48967, 21},
+ {I_JNG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44614, 122},
+ {I_JNG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33900, 21},
+ {I_JNG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48968, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNGE[] = {
+ {I_JNGE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44319, 122},
+ {I_JNGE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44415, 23},
+ {I_JNGE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44511, 23},
+ {I_JNGE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44607, 24},
+ {I_JNGE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48963, 21},
+ {I_JNGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48962, 21},
+ {I_JNGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44608, 122},
+ {I_JNGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33893, 21},
+ {I_JNGE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48963, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNL[] = {
+ {I_JNL, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44313, 122},
+ {I_JNL, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44409, 23},
+ {I_JNL, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44505, 23},
+ {I_JNL, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44601, 24},
+ {I_JNL, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48958, 21},
+ {I_JNL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48957, 21},
+ {I_JNL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44602, 122},
+ {I_JNL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33886, 21},
+ {I_JNL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48958, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNLE[] = {
+ {I_JNLE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44307, 122},
+ {I_JNLE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44403, 23},
+ {I_JNLE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44499, 23},
+ {I_JNLE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44595, 24},
+ {I_JNLE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48953, 21},
+ {I_JNLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48952, 21},
+ {I_JNLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44596, 122},
+ {I_JNLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33879, 21},
+ {I_JNLE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48953, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNO[] = {
+ {I_JNO, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44337, 122},
+ {I_JNO, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44433, 23},
+ {I_JNO, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44529, 23},
+ {I_JNO, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44625, 24},
+ {I_JNO, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48978, 21},
+ {I_JNO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48977, 21},
+ {I_JNO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44626, 122},
+ {I_JNO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33914, 21},
+ {I_JNO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48978, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNP[] = {
+ {I_JNP, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44343, 122},
+ {I_JNP, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44439, 23},
+ {I_JNP, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44535, 23},
+ {I_JNP, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44631, 24},
+ {I_JNP, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48983, 21},
+ {I_JNP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48982, 21},
+ {I_JNP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44632, 122},
+ {I_JNP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33921, 21},
+ {I_JNP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48983, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNS[] = {
+ {I_JNS, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44349, 122},
+ {I_JNS, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44445, 23},
+ {I_JNS, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44541, 23},
+ {I_JNS, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44637, 24},
+ {I_JNS, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48988, 21},
+ {I_JNS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48987, 21},
+ {I_JNS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44638, 122},
+ {I_JNS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33928, 21},
+ {I_JNS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48988, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JNZ[] = {
+ {I_JNZ, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44331, 122},
+ {I_JNZ, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44427, 23},
+ {I_JNZ, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44523, 23},
+ {I_JNZ, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44619, 24},
+ {I_JNZ, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48973, 21},
+ {I_JNZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48972, 21},
+ {I_JNZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44620, 122},
+ {I_JNZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33907, 21},
+ {I_JNZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48973, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JO[] = {
+ {I_JO, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44355, 122},
+ {I_JO, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44451, 23},
+ {I_JO, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44547, 23},
+ {I_JO, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44643, 24},
+ {I_JO, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48993, 21},
+ {I_JO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48992, 21},
+ {I_JO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44644, 122},
+ {I_JO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33935, 21},
+ {I_JO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48993, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JP[] = {
+ {I_JP, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44361, 122},
+ {I_JP, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44457, 23},
+ {I_JP, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44553, 23},
+ {I_JP, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44649, 24},
+ {I_JP, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48998, 21},
+ {I_JP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48997, 21},
+ {I_JP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44650, 122},
+ {I_JP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33942, 21},
+ {I_JP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48998, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JPE[] = {
+ {I_JPE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44361, 122},
+ {I_JPE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44457, 23},
+ {I_JPE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44553, 23},
+ {I_JPE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44649, 24},
+ {I_JPE, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48998, 21},
+ {I_JPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48997, 21},
+ {I_JPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44650, 122},
+ {I_JPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33942, 21},
+ {I_JPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48998, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JPO[] = {
+ {I_JPO, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44343, 122},
+ {I_JPO, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44439, 23},
+ {I_JPO, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44535, 23},
+ {I_JPO, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44631, 24},
+ {I_JPO, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48983, 21},
+ {I_JPO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48982, 21},
+ {I_JPO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44632, 122},
+ {I_JPO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33921, 21},
+ {I_JPO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48983, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JS[] = {
+ {I_JS, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44367, 122},
+ {I_JS, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44463, 23},
+ {I_JS, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44559, 23},
+ {I_JS, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44655, 24},
+ {I_JS, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49003, 21},
+ {I_JS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49002, 21},
+ {I_JS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44656, 122},
+ {I_JS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33949, 21},
+ {I_JS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49003, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_JZ[] = {
+ {I_JZ, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44301, 122},
+ {I_JZ, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44397, 23},
+ {I_JZ, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44493, 23},
+ {I_JZ, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44589, 24},
+ {I_JZ, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48948, 21},
+ {I_JZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48947, 21},
+ {I_JZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44590, 122},
+ {I_JZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33872, 21},
+ {I_JZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48948, 21},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETA[] = {
+ {I_SETA, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49007, 53},
+ {I_SETA, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49007, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETAE[] = {
+ {I_SETAE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 53},
+ {I_SETAE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETB[] = {
+ {I_SETB, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 53},
+ {I_SETB, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETBE[] = {
+ {I_SETBE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49022, 53},
+ {I_SETBE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49022, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETC[] = {
+ {I_SETC, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 53},
+ {I_SETC, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETE[] = {
+ {I_SETE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49027, 53},
+ {I_SETE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49027, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETG[] = {
+ {I_SETG, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49032, 53},
+ {I_SETG, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49032, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETGE[] = {
+ {I_SETGE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49037, 53},
+ {I_SETGE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49037, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETL[] = {
+ {I_SETL, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49042, 53},
+ {I_SETL, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49042, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETLE[] = {
+ {I_SETLE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49047, 53},
+ {I_SETLE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49047, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNA[] = {
+ {I_SETNA, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49022, 53},
+ {I_SETNA, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49022, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNAE[] = {
+ {I_SETNAE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 53},
+ {I_SETNAE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNB[] = {
+ {I_SETNB, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 53},
+ {I_SETNB, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNBE[] = {
+ {I_SETNBE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49007, 53},
+ {I_SETNBE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49007, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNC[] = {
+ {I_SETNC, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 53},
+ {I_SETNC, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNE[] = {
+ {I_SETNE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49052, 53},
+ {I_SETNE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49052, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNG[] = {
+ {I_SETNG, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49047, 53},
+ {I_SETNG, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49047, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNGE[] = {
+ {I_SETNGE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49042, 53},
+ {I_SETNGE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49042, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNL[] = {
+ {I_SETNL, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49037, 53},
+ {I_SETNL, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49037, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNLE[] = {
+ {I_SETNLE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49032, 53},
+ {I_SETNLE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49032, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNO[] = {
+ {I_SETNO, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49057, 53},
+ {I_SETNO, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49057, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNP[] = {
+ {I_SETNP, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49062, 53},
+ {I_SETNP, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49062, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNS[] = {
+ {I_SETNS, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49067, 53},
+ {I_SETNS, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49067, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETNZ[] = {
+ {I_SETNZ, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49052, 53},
+ {I_SETNZ, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49052, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETO[] = {
+ {I_SETO, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49072, 53},
+ {I_SETO, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49072, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETP[] = {
+ {I_SETP, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49077, 53},
+ {I_SETP, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49077, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETPE[] = {
+ {I_SETPE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49077, 53},
+ {I_SETPE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49077, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETPO[] = {
+ {I_SETPO, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49062, 53},
+ {I_SETPO, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49062, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETS[] = {
+ {I_SETS, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49082, 53},
+ {I_SETS, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49082, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETZ[] = {
+ {I_SETZ, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49027, 53},
+ {I_SETZ, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49027, 5},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADDPS[] = {
+ {I_ADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44661, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADDSS[] = {
+ {I_ADDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44667, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ANDNPS[] = {
+ {I_ANDNPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44673, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ANDPS[] = {
+ {I_ANDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44679, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPEQPS[] = {
+ {I_CMPEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12528, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPEQSS[] = {
+ {I_CMPEQSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12536, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLEPS[] = {
+ {I_CMPLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12544, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLESS[] = {
+ {I_CMPLESS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12552, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLTPS[] = {
+ {I_CMPLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12560, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLTSS[] = {
+ {I_CMPLTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12568, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNEQPS[] = {
+ {I_CMPNEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12576, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNEQSS[] = {
+ {I_CMPNEQSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12584, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLEPS[] = {
+ {I_CMPNLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12592, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLESS[] = {
+ {I_CMPNLESS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12600, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLTPS[] = {
+ {I_CMPNLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12608, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLTSS[] = {
+ {I_CMPNLTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12616, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPORDPS[] = {
+ {I_CMPORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12624, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPORDSS[] = {
+ {I_CMPORDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12632, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPUNORDPS[] = {
+ {I_CMPUNORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12640, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPUNORDSS[] = {
+ {I_CMPUNORDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12648, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPPS[] = {
+ {I_CMPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+33956, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPSS[] = {
+ {I_CMPSS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+33963, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_COMISS[] = {
+ {I_COMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44685, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPI2PS[] = {
+ {I_CVTPI2PS, 2, {XMM_L16,RM_MMX|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44691, 124},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPS2PI[] = {
+ {I_CVTPS2PI, 2, {MMXREG,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44697, 124},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTSI2SS[] = {
+ {I_CVTSI2SS, 2, {XMM_L16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33971, 125},
+ {I_CVTSI2SS, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33971, 125},
+ {I_CVTSI2SS, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33970, 126},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTSS2SI[] = {
+ {I_CVTSS2SI, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33978, 125},
+ {I_CVTSS2SI, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33978, 125},
+ {I_CVTSS2SI, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33977, 127},
+ {I_CVTSS2SI, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33977, 127},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTTPS2PI[] = {
+ {I_CVTTPS2PI, 2, {MMXREG,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44703, 128},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTTSS2SI[] = {
+ {I_CVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33985, 125},
+ {I_CVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33984, 127},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DIVPS[] = {
+ {I_DIVPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44709, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DIVSS[] = {
+ {I_DIVSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44715, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LDMXCSR[] = {
+ {I_LDMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44721, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MAXPS[] = {
+ {I_MAXPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44727, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MAXSS[] = {
+ {I_MAXSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44733, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MINPS[] = {
+ {I_MINPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44739, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MINSS[] = {
+ {I_MINSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44745, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVAPS[] = {
+ {I_MOVAPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44751, 123},
+ {I_MOVAPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44757, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVHPS[] = {
+ {I_MOVHPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44763, 123},
+ {I_MOVHPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44769, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVLHPS[] = {
+ {I_MOVLHPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44763, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVLPS[] = {
+ {I_MOVLPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43893, 123},
+ {I_MOVLPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44775, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVHLPS[] = {
+ {I_MOVHLPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43893, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVMSKPS[] = {
+ {I_MOVMSKPS, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44781, 123},
+ {I_MOVMSKPS, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33991, 129},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTPS[] = {
+ {I_MOVNTPS, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44787, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSS[] = {
+ {I_MOVSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44793, 123},
+ {I_MOVSS, 2, {RM_XMM_L16|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44799, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVUPS[] = {
+ {I_MOVUPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44805, 123},
+ {I_MOVUPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44811, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MULPS[] = {
+ {I_MULPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44817, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MULSS[] = {
+ {I_MULSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44823, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ORPS[] = {
+ {I_ORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44829, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RCPPS[] = {
+ {I_RCPPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44835, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RCPSS[] = {
+ {I_RCPSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44841, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RSQRTPS[] = {
+ {I_RSQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44847, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RSQRTSS[] = {
+ {I_RSQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44853, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHUFPS[] = {
+ {I_SHUFPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+33998, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SQRTPS[] = {
+ {I_SQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44859, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SQRTSS[] = {
+ {I_SQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44865, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STMXCSR[] = {
+ {I_STMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44871, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SUBPS[] = {
+ {I_SUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44877, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SUBSS[] = {
+ {I_SUBSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44883, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UCOMISS[] = {
+ {I_UCOMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44889, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UNPCKHPS[] = {
+ {I_UNPCKHPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44895, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UNPCKLPS[] = {
+ {I_UNPCKLPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44901, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XORPS[] = {
+ {I_XORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44907, 123},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FXRSTOR[] = {
+ {I_FXRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34006, 130},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FXRSTOR64[] = {
+ {I_FXRSTOR64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34005, 131},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FXSAVE[] = {
+ {I_FXSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34013, 130},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_FXSAVE64[] = {
+ {I_FXSAVE64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34012, 131},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XGETBV[] = {
+ {I_XGETBV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49087, 132},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSETBV[] = {
+ {I_XSETBV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49092, 133},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVE[] = {
+ {I_XSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34020, 132},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVE64[] = {
+ {I_XSAVE64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34019, 134},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVEC[] = {
+ {I_XSAVEC, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34027, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVEC64[] = {
+ {I_XSAVEC64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34026, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVEOPT[] = {
+ {I_XSAVEOPT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34034, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVEOPT64[] = {
+ {I_XSAVEOPT64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34033, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVES[] = {
+ {I_XSAVES, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34041, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSAVES64[] = {
+ {I_XSAVES64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34040, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XRSTOR[] = {
+ {I_XRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34048, 132},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XRSTOR64[] = {
+ {I_XRSTOR64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34047, 134},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XRSTORS[] = {
+ {I_XRSTORS, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34055, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XRSTORS64[] = {
+ {I_XRSTORS64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34054, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHNTA[] = {
+ {I_PREFETCHNTA, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46126, 137},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHT0[] = {
+ {I_PREFETCHT0, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46144, 137},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHT1[] = {
+ {I_PREFETCHT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46162, 137},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHT2[] = {
+ {I_PREFETCHT2, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46180, 137},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHIT0[] = {
+ {I_PREFETCHIT0, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46252, 138},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHIT1[] = {
+ {I_PREFETCHIT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46234, 138},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MASKMOVQ[] = {
+ {I_MASKMOVQ, 2, {MMXREG,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44913, 140},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTQ[] = {
+ {I_MOVNTQ, 2, {MEMORY,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44919, 141},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PAVGB[] = {
+ {I_PAVGB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34061, 141},
+ {I_PAVGB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45087, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PAVGW[] = {
+ {I_PAVGW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34068, 141},
+ {I_PAVGW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45093, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PEXTRW[] = {
+ {I_PEXTRW, 3, {REG_GPR|BITS32,MMXREG,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34075, 142},
+ {I_PEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34166, 152},
+ {I_PEXTRW, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34166, 153},
+ {I_PEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4277, 173},
+ {I_PEXTRW, 3, {MEMORY|BITS16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4277, 173},
+ {I_PEXTRW, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4276, 174},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PINSRW[] = {
+ {I_PINSRW, 3, {MMXREG,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34082, 142},
+ {I_PINSRW, 3, {MMXREG,RM_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34082, 142},
+ {I_PINSRW, 3, {MMXREG,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34082, 142},
+ {I_PINSRW, 3, {XMM_L16,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 152},
+ {I_PINSRW, 3, {XMM_L16,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 152},
+ {I_PINSRW, 3, {XMM_L16,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 153},
+ {I_PINSRW, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 152},
+ {I_PINSRW, 3, {XMM_L16,MEMORY|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 152},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMAXSW[] = {
+ {I_PMAXSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34089, 141},
+ {I_PMAXSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45141, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMAXUB[] = {
+ {I_PMAXUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34096, 141},
+ {I_PMAXUB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45147, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMINSW[] = {
+ {I_PMINSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34103, 141},
+ {I_PMINSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45153, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMINUB[] = {
+ {I_PMINUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34110, 141},
+ {I_PMINUB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45159, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVMSKB[] = {
+ {I_PMOVMSKB, 2, {REG_GPR|BITS32,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44925, 140},
+ {I_PMOVMSKB, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45165, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULHUW[] = {
+ {I_PMULHUW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34117, 141},
+ {I_PMULHUW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45171, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSADBW[] = {
+ {I_PSADBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34124, 141},
+ {I_PSADBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45201, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSHUFW[] = {
+ {I_PSHUFW, 3, {MMXREG,RM_MMX,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12656, 143},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PF2IW[] = {
+ {I_PF2IW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12664, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFNACC[] = {
+ {I_PFNACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12672, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFPNACC[] = {
+ {I_PFPNACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12680, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PI2FW[] = {
+ {I_PI2FW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12688, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSWAPD[] = {
+ {I_PSWAPD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12696, 91},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MASKMOVDQU[] = {
+ {I_MASKMOVDQU, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44931, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLFLUSH[] = {
+ {I_CLFLUSH, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44937, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTDQ[] = {
+ {I_MOVNTDQ, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44943, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTI[] = {
+ {I_MOVNTI, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34132, 146},
+ {I_MOVNTI, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34131, 147},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTPD[] = {
+ {I_MOVNTPD, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44949, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVDQA[] = {
+ {I_MOVDQA, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44955, 145},
+ {I_MOVDQA, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44961, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVDQU[] = {
+ {I_MOVDQU, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44967, 145},
+ {I_MOVDQU, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44973, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVDQ2Q[] = {
+ {I_MOVDQ2Q, 2, {MMXREG,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44979, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVQ2DQ[] = {
+ {I_MOVQ2DQ, 2, {XMM_L16,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44997, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PADDQ[] = {
+ {I_PADDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+45039, 151},
+ {I_PADDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45045, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULUDQ[] = {
+ {I_PMULUDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34180, 145},
+ {I_PMULUDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45189, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSHUFD[] = {
+ {I_PSHUFD, 3, {XMM_L16,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34187, 152},
+ {I_PSHUFD, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34187, 154},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSHUFHW[] = {
+ {I_PSHUFHW, 3, {XMM_L16,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34194, 152},
+ {I_PSHUFHW, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34194, 154},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSHUFLW[] = {
+ {I_PSHUFLW, 3, {XMM_L16,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34201, 152},
+ {I_PSHUFLW, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34201, 154},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSLLDQ[] = {
+ {I_PSLLDQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34208, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSRLDQ[] = {
+ {I_PSRLDQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34250, 155},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSUBQ[] = {
+ {I_PSUBQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34278, 145},
+ {I_PSUBQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45273, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKHQDQ[] = {
+ {I_PUNPCKHQDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45321, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PUNPCKLQDQ[] = {
+ {I_PUNPCKLQDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45345, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADDPD[] = {
+ {I_ADDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45357, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADDSD[] = {
+ {I_ADDSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45363, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ANDNPD[] = {
+ {I_ANDNPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45369, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ANDPD[] = {
+ {I_ANDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45375, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPEQPD[] = {
+ {I_CMPEQPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12704, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPEQSD[] = {
+ {I_CMPEQSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12712, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLEPD[] = {
+ {I_CMPLEPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12720, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLESD[] = {
+ {I_CMPLESD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12728, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLTPD[] = {
+ {I_CMPLTPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12736, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLTSD[] = {
+ {I_CMPLTSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12744, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNEQPD[] = {
+ {I_CMPNEQPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12752, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNEQSD[] = {
+ {I_CMPNEQSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12760, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLEPD[] = {
+ {I_CMPNLEPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12768, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLESD[] = {
+ {I_CMPNLESD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12776, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLTPD[] = {
+ {I_CMPNLTPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12784, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLTSD[] = {
+ {I_CMPNLTSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12792, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPORDPD[] = {
+ {I_CMPORDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12800, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPORDSD[] = {
+ {I_CMPORDSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12808, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPUNORDPD[] = {
+ {I_CMPUNORDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12816, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPUNORDSD[] = {
+ {I_CMPUNORDSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12824, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPPD[] = {
+ {I_CMPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+34285, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_COMISD[] = {
+ {I_COMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45381, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTDQ2PD[] = {
+ {I_CVTDQ2PD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45387, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTDQ2PS[] = {
+ {I_CVTDQ2PS, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45393, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPD2DQ[] = {
+ {I_CVTPD2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45399, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPD2PI[] = {
+ {I_CVTPD2PI, 2, {MMXREG,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45405, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPD2PS[] = {
+ {I_CVTPD2PS, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45411, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPI2PD[] = {
+ {I_CVTPI2PD, 2, {XMM_L16,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+45417, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPS2DQ[] = {
+ {I_CVTPS2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45423, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTPS2PD[] = {
+ {I_CVTPS2PD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45429, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTSD2SI[] = {
+ {I_CVTSD2SI, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34299, 156},
+ {I_CVTSD2SI, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34299, 156},
+ {I_CVTSD2SI, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34306, 157},
+ {I_CVTSD2SI, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34306, 157},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTSD2SS[] = {
+ {I_CVTSD2SS, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45435, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTSI2SD[] = {
+ {I_CVTSI2SD, 2, {XMM_L16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34321, 158},
+ {I_CVTSI2SD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34313, 158},
+ {I_CVTSI2SD, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34320, 157},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTSS2SD[] = {
+ {I_CVTSS2SD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45441, 148},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTTPD2PI[] = {
+ {I_CVTTPD2PI, 2, {MMXREG,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45447, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTTPD2DQ[] = {
+ {I_CVTTPD2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45453, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTTPS2DQ[] = {
+ {I_CVTTPS2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45459, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CVTTSD2SI[] = {
+ {I_CVTTSD2SI, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34327, 156},
+ {I_CVTTSD2SI, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34327, 156},
+ {I_CVTTSD2SI, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34334, 157},
+ {I_CVTTSD2SI, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34334, 157},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DIVPD[] = {
+ {I_DIVPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45465, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DIVSD[] = {
+ {I_DIVSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45471, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MAXPD[] = {
+ {I_MAXPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45477, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MAXSD[] = {
+ {I_MAXSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45483, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MINPD[] = {
+ {I_MINPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45489, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MINSD[] = {
+ {I_MINSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45495, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVAPD[] = {
+ {I_MOVAPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45501, 144},
+ {I_MOVAPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45507, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVHPD[] = {
+ {I_MOVHPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45513, 144},
+ {I_MOVHPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45519, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVLPD[] = {
+ {I_MOVLPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45525, 144},
+ {I_MOVLPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45531, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVMSKPD[] = {
+ {I_MOVMSKPD, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45537, 144},
+ {I_MOVMSKPD, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34341, 150},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVUPD[] = {
+ {I_MOVUPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45555, 144},
+ {I_MOVUPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45561, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MULPD[] = {
+ {I_MULPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45567, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MULSD[] = {
+ {I_MULSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45573, 149},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ORPD[] = {
+ {I_ORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45579, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHUFPD[] = {
+ {I_SHUFPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+34348, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SQRTPD[] = {
+ {I_SQRTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45585, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SQRTSD[] = {
+ {I_SQRTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45591, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SUBPD[] = {
+ {I_SUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45597, 145},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SUBSD[] = {
+ {I_SUBSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45603, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UCOMISD[] = {
+ {I_UCOMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45609, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UNPCKHPD[] = {
+ {I_UNPCKHPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45615, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UNPCKLPD[] = {
+ {I_UNPCKLPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45621, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XORPD[] = {
+ {I_XORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45627, 144},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADDSUBPD[] = {
+ {I_ADDSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45633, 159},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADDSUBPS[] = {
+ {I_ADDSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45639, 159},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HADDPD[] = {
+ {I_HADDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45645, 159},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HADDPS[] = {
+ {I_HADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45651, 159},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HSUBPD[] = {
+ {I_HSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45657, 159},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HSUBPS[] = {
+ {I_HSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45663, 159},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LDDQU[] = {
+ {I_LDDQU, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45669, 159},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVDDUP[] = {
+ {I_MOVDDUP, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45675, 160},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSHDUP[] = {
+ {I_MOVSHDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45681, 161},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVSLDUP[] = {
+ {I_MOVSLDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45687, 161},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLGI[] = {
+ {I_CLGI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49097, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STGI[] = {
+ {I_STGI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49102, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMCALL[] = {
+ {I_VMCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45730, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMCLEAR[] = {
+ {I_VMCLEAR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45693, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMFUNC[] = {
+ {I_VMFUNC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49107, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMLAUNCH[] = {
+ {I_VMLAUNCH, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49112, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMLOAD[] = {
+ {I_VMLOAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49117, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMMCALL[] = {
+ {I_VMMCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49122, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMPTRLD[] = {
+ {I_VMPTRLD, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45699, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMPTRST[] = {
+ {I_VMPTRST, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45705, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMREAD[] = {
+ {I_VMREAD, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34356, 164},
+ {I_VMREAD, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34355, 165},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMRESUME[] = {
+ {I_VMRESUME, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49127, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMRUN[] = {
+ {I_VMRUN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49132, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMSAVE[] = {
+ {I_VMSAVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49137, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMWRITE[] = {
+ {I_VMWRITE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34363, 164},
+ {I_VMWRITE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34362, 165},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMXOFF[] = {
+ {I_VMXOFF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49142, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMXON[] = {
+ {I_VMXON, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42511, 163},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INVEPT[] = {
+ {I_INVEPT, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12833, 166},
+ {I_INVEPT, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12832, 167},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INVVPID[] = {
+ {I_INVVPID, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12841, 166},
+ {I_INVVPID, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12840, 167},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PVALIDATE[] = {
+ {I_PVALIDATE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45711, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RMPADJUST[] = {
+ {I_RMPADJUST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45717, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMGEXIT[] = {
+ {I_VMGEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45723, 162},
+ {I_VMGEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45729, 162},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PABSB[] = {
+ {I_PABSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34369, 168},
+ {I_PABSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34376, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PABSW[] = {
+ {I_PABSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34383, 168},
+ {I_PABSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34390, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PABSD[] = {
+ {I_PABSD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34397, 168},
+ {I_PABSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34404, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PALIGNR[] = {
+ {I_PALIGNR, 3, {MMXREG,RM_MMX,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12848, 168},
+ {I_PALIGNR, 3, {XMM_L16,RM_XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12856, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PHADDW[] = {
+ {I_PHADDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34411, 168},
+ {I_PHADDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34418, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PHADDD[] = {
+ {I_PHADDD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34425, 168},
+ {I_PHADDD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34432, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PHADDSW[] = {
+ {I_PHADDSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34439, 168},
+ {I_PHADDSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34446, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PHSUBW[] = {
+ {I_PHSUBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34453, 168},
+ {I_PHSUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34460, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PHSUBD[] = {
+ {I_PHSUBD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34467, 168},
+ {I_PHSUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34474, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PHSUBSW[] = {
+ {I_PHSUBSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34481, 168},
+ {I_PHSUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34488, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMADDUBSW[] = {
+ {I_PMADDUBSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34495, 168},
+ {I_PMADDUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34502, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULHRSW[] = {
+ {I_PMULHRSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34509, 168},
+ {I_PMULHRSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34516, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSHUFB[] = {
+ {I_PSHUFB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34523, 168},
+ {I_PSHUFB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34530, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSIGNB[] = {
+ {I_PSIGNB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34537, 168},
+ {I_PSIGNB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34544, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSIGNW[] = {
+ {I_PSIGNW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34551, 168},
+ {I_PSIGNW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34558, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PSIGND[] = {
+ {I_PSIGND, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34565, 168},
+ {I_PSIGND, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34572, 169},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_EXTRQ[] = {
+ {I_EXTRQ, 3, {XMM_L16,IMMEDIATE,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12864, 170},
+ {I_EXTRQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45735, 170},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INSERTQ[] = {
+ {I_INSERTQ, 4, {XMM_L16,XMM_L16,IMMEDIATE,IMMEDIATE,0}, NO_DECORATOR, nasm_bytecodes+12872, 170},
+ {I_INSERTQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45741, 170},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTSD[] = {
+ {I_MOVNTSD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45747, 171},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTSS[] = {
+ {I_MOVNTSS, 2, {MEMORY|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45753, 172},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LZCNT[] = {
+ {I_LZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34579, 113},
+ {I_LZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34586, 113},
+ {I_LZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34593, 59},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLENDPD[] = {
+ {I_BLENDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12880, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLENDPS[] = {
+ {I_BLENDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12888, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLENDVPD[] = {
+ {I_BLENDVPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+34600, 173},
+ {I_BLENDVPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34600, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLENDVPS[] = {
+ {I_BLENDVPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+34607, 173},
+ {I_BLENDVPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34607, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DPPD[] = {
+ {I_DPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12896, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_DPPS[] = {
+ {I_DPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12904, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_EXTRACTPS[] = {
+ {I_EXTRACTPS, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4241, 173},
+ {I_EXTRACTPS, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4240, 174},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INSERTPS[] = {
+ {I_INSERTPS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12912, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVNTDQA[] = {
+ {I_MOVNTDQA, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34614, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MPSADBW[] = {
+ {I_MPSADBW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12920, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PACKUSDW[] = {
+ {I_PACKUSDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34621, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PBLENDVB[] = {
+ {I_PBLENDVB, 3, {XMM_L16,RM_XMM_L16,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+34628, 173},
+ {I_PBLENDVB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34628, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PBLENDW[] = {
+ {I_PBLENDW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12928, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPEQQ[] = {
+ {I_PCMPEQQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34635, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PEXTRB[] = {
+ {I_PEXTRB, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4250, 173},
+ {I_PEXTRB, 3, {MEMORY|BITS8,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4250, 173},
+ {I_PEXTRB, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4249, 174},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PEXTRD[] = {
+ {I_PEXTRD, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4258, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PEXTRQ[] = {
+ {I_PEXTRQ, 3, {RM_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4267, 174},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PHMINPOSUW[] = {
+ {I_PHMINPOSUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34642, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PINSRB[] = {
+ {I_PINSRB, 3, {XMM_L16,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4286, 175},
+ {I_PINSRB, 3, {XMM_L16,RM_GPR|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4285, 175},
+ {I_PINSRB, 3, {XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4286, 175},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PINSRD[] = {
+ {I_PINSRD, 3, {XMM_L16,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4294, 175},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PINSRQ[] = {
+ {I_PINSRQ, 3, {XMM_L16,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4303, 176},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMAXSB[] = {
+ {I_PMAXSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34649, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMAXSD[] = {
+ {I_PMAXSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34656, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMAXUD[] = {
+ {I_PMAXUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34663, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMAXUW[] = {
+ {I_PMAXUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34670, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMINSB[] = {
+ {I_PMINSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34677, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMINSD[] = {
+ {I_PMINSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34684, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMINUD[] = {
+ {I_PMINUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34691, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMINUW[] = {
+ {I_PMINUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34698, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVSXBW[] = {
+ {I_PMOVSXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34705, 177},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVSXBD[] = {
+ {I_PMOVSXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34712, 178},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVSXBQ[] = {
+ {I_PMOVSXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34719, 179},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVSXWD[] = {
+ {I_PMOVSXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34726, 177},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVSXWQ[] = {
+ {I_PMOVSXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34733, 178},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVSXDQ[] = {
+ {I_PMOVSXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34740, 177},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVZXBW[] = {
+ {I_PMOVZXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34747, 177},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVZXBD[] = {
+ {I_PMOVZXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34754, 178},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVZXBQ[] = {
+ {I_PMOVZXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34761, 179},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVZXWD[] = {
+ {I_PMOVZXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34768, 177},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVZXWQ[] = {
+ {I_PMOVZXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34775, 178},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMOVZXDQ[] = {
+ {I_PMOVZXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34782, 177},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULDQ[] = {
+ {I_PMULDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34789, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PMULLD[] = {
+ {I_PMULLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34796, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PTEST[] = {
+ {I_PTEST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34803, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ROUNDPD[] = {
+ {I_ROUNDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12936, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ROUNDPS[] = {
+ {I_ROUNDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12944, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ROUNDSD[] = {
+ {I_ROUNDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12952, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ROUNDSS[] = {
+ {I_ROUNDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12960, 173},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CRC32[] = {
+ {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12985, 180},
+ {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12968, 180},
+ {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12976, 180},
+ {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12984, 181},
+ {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12992, 181},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPESTRI[] = {
+ {I_PCMPESTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13000, 180},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPESTRM[] = {
+ {I_PCMPESTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13008, 180},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPISTRI[] = {
+ {I_PCMPISTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13016, 180},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPISTRM[] = {
+ {I_PCMPISTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13024, 180},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCMPGTQ[] = {
+ {I_PCMPGTQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34810, 180},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_POPCNT[] = {
+ {I_POPCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34817, 182},
+ {I_POPCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34824, 183},
+ {I_POPCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34831, 184},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_GETSEC[] = {
+ {I_GETSEC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50183, 139},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFRCPV[] = {
+ {I_PFRCPV, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+13032, 185},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PFRSQRTV[] = {
+ {I_PFRSQRTV, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+13040, 185},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVBE[] = {
+ {I_MOVBE, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+13048, 186},
+ {I_MOVBE, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13056, 186},
+ {I_MOVBE, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13064, 186},
+ {I_MOVBE, 2, {MEMORY|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+13072, 186},
+ {I_MOVBE, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13080, 186},
+ {I_MOVBE, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13088, 186},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AESENC[] = {
+ {I_AESENC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34838, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AESENCLAST[] = {
+ {I_AESENCLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34845, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AESDEC[] = {
+ {I_AESDEC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34852, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AESDECLAST[] = {
+ {I_AESDECLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34859, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AESIMC[] = {
+ {I_AESIMC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34866, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AESKEYGENASSIST[] = {
+ {I_AESKEYGENASSIST, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13096, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VAESENC[] = {
+ {I_VAESENC, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34873, 188},
+ {I_VAESENC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34880, 188},
+ {I_VAESENC, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34936, 189},
+ {I_VAESENC, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34943, 189},
+ {I_VAESENC, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13112, 190},
+ {I_VAESENC, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13120, 190},
+ {I_VAESENC, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13128, 190},
+ {I_VAESENC, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13136, 190},
+ {I_VAESENC, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13240, 191},
+ {I_VAESENC, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13248, 191},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VAESENCLAST[] = {
+ {I_VAESENCLAST, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34887, 188},
+ {I_VAESENCLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34894, 188},
+ {I_VAESENCLAST, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34950, 189},
+ {I_VAESENCLAST, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34957, 189},
+ {I_VAESENCLAST, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13144, 190},
+ {I_VAESENCLAST, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13152, 190},
+ {I_VAESENCLAST, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13160, 190},
+ {I_VAESENCLAST, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13168, 190},
+ {I_VAESENCLAST, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13256, 191},
+ {I_VAESENCLAST, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13264, 191},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VAESDEC[] = {
+ {I_VAESDEC, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34901, 188},
+ {I_VAESDEC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34908, 188},
+ {I_VAESDEC, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34964, 189},
+ {I_VAESDEC, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34971, 189},
+ {I_VAESDEC, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13176, 190},
+ {I_VAESDEC, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13184, 190},
+ {I_VAESDEC, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13192, 190},
+ {I_VAESDEC, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13200, 190},
+ {I_VAESDEC, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13272, 191},
+ {I_VAESDEC, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13280, 191},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VAESDECLAST[] = {
+ {I_VAESDECLAST, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34915, 188},
+ {I_VAESDECLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34922, 188},
+ {I_VAESDECLAST, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34978, 189},
+ {I_VAESDECLAST, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34985, 189},
+ {I_VAESDECLAST, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13208, 190},
+ {I_VAESDECLAST, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13216, 190},
+ {I_VAESDECLAST, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13224, 190},
+ {I_VAESDECLAST, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13232, 190},
+ {I_VAESDECLAST, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13288, 191},
+ {I_VAESDECLAST, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13296, 191},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VAESIMC[] = {
+ {I_VAESIMC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34929, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VAESKEYGENASSIST[] = {
+ {I_VAESKEYGENASSIST, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13104, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDPD[] = {
+ {I_VADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34992, 188},
+ {I_VADDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34999, 188},
+ {I_VADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35006, 188},
+ {I_VADDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35013, 188},
+ {I_VADDPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16376, 240},
+ {I_VADDPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16384, 240},
+ {I_VADDPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16392, 240},
+ {I_VADDPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16400, 240},
+ {I_VADDPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+16408, 241},
+ {I_VADDPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+16416, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDPS[] = {
+ {I_VADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35020, 188},
+ {I_VADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35027, 188},
+ {I_VADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35034, 188},
+ {I_VADDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35041, 188},
+ {I_VADDPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16424, 240},
+ {I_VADDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16432, 240},
+ {I_VADDPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16440, 240},
+ {I_VADDPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16448, 240},
+ {I_VADDPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+16456, 241},
+ {I_VADDPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+16464, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDSD[] = {
+ {I_VADDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35048, 188},
+ {I_VADDSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35055, 188},
+ {I_VADDSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+16472, 241},
+ {I_VADDSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+16480, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDSS[] = {
+ {I_VADDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35062, 188},
+ {I_VADDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35069, 188},
+ {I_VADDSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+16488, 241},
+ {I_VADDSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+16496, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDSUBPD[] = {
+ {I_VADDSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35076, 188},
+ {I_VADDSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35083, 188},
+ {I_VADDSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35090, 188},
+ {I_VADDSUBPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35097, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDSUBPS[] = {
+ {I_VADDSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35104, 188},
+ {I_VADDSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35111, 188},
+ {I_VADDSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35118, 188},
+ {I_VADDSUBPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35125, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VANDPD[] = {
+ {I_VANDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35132, 188},
+ {I_VANDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35139, 188},
+ {I_VANDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35146, 188},
+ {I_VANDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35153, 188},
+ {I_VANDPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16600, 242},
+ {I_VANDPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16608, 242},
+ {I_VANDPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16616, 242},
+ {I_VANDPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16624, 242},
+ {I_VANDPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16632, 243},
+ {I_VANDPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16640, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VANDPS[] = {
+ {I_VANDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35160, 188},
+ {I_VANDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35167, 188},
+ {I_VANDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35174, 188},
+ {I_VANDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35181, 188},
+ {I_VANDPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16648, 242},
+ {I_VANDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16656, 242},
+ {I_VANDPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16664, 242},
+ {I_VANDPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16672, 242},
+ {I_VANDPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16680, 243},
+ {I_VANDPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16688, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VANDNPD[] = {
+ {I_VANDNPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35188, 188},
+ {I_VANDNPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35195, 188},
+ {I_VANDNPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35202, 188},
+ {I_VANDNPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35209, 188},
+ {I_VANDNPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16504, 242},
+ {I_VANDNPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16512, 242},
+ {I_VANDNPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16520, 242},
+ {I_VANDNPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16528, 242},
+ {I_VANDNPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16536, 243},
+ {I_VANDNPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16544, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VANDNPS[] = {
+ {I_VANDNPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35216, 188},
+ {I_VANDNPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35223, 188},
+ {I_VANDNPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35230, 188},
+ {I_VANDNPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35237, 188},
+ {I_VANDNPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16552, 242},
+ {I_VANDNPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16560, 242},
+ {I_VANDNPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16568, 242},
+ {I_VANDNPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16576, 242},
+ {I_VANDNPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16584, 243},
+ {I_VANDNPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16592, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBLENDPD[] = {
+ {I_VBLENDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13304, 188},
+ {I_VBLENDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13312, 188},
+ {I_VBLENDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13320, 188},
+ {I_VBLENDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13328, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBLENDPS[] = {
+ {I_VBLENDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13336, 188},
+ {I_VBLENDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13344, 188},
+ {I_VBLENDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13352, 188},
+ {I_VBLENDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13360, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBLENDVPD[] = {
+ {I_VBLENDVPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13368, 188},
+ {I_VBLENDVPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13376, 188},
+ {I_VBLENDVPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13384, 188},
+ {I_VBLENDVPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13392, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBLENDVPS[] = {
+ {I_VBLENDVPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13400, 188},
+ {I_VBLENDVPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13408, 188},
+ {I_VBLENDVPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13416, 188},
+ {I_VBLENDVPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13424, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTSS[] = {
+ {I_VBROADCASTSS, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35244, 188},
+ {I_VBROADCASTSS, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35251, 188},
+ {I_VBROADCASTSS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35244, 207},
+ {I_VBROADCASTSS, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35251, 207},
+ {I_VBROADCASTSS, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16912, 240},
+ {I_VBROADCASTSS, 2, {YMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16920, 240},
+ {I_VBROADCASTSS, 2, {ZMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16928, 241},
+ {I_VBROADCASTSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16936, 240},
+ {I_VBROADCASTSS, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16944, 240},
+ {I_VBROADCASTSS, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16952, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTSD[] = {
+ {I_VBROADCASTSD, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35258, 188},
+ {I_VBROADCASTSD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35258, 207},
+ {I_VBROADCASTSD, 2, {YMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16880, 240},
+ {I_VBROADCASTSD, 2, {ZMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16888, 241},
+ {I_VBROADCASTSD, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16896, 240},
+ {I_VBROADCASTSD, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16904, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTF128[] = {
+ {I_VBROADCASTF128, 2, {YMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35265, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OSPD[] = {
+ {I_VCMPEQ_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4312, 188},
+ {I_VCMPEQ_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4321, 188},
+ {I_VCMPEQ_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4330, 188},
+ {I_VCMPEQ_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4339, 188},
+ {I_VCMPEQ_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4312, 188},
+ {I_VCMPEQ_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4321, 188},
+ {I_VCMPEQ_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4330, 188},
+ {I_VCMPEQ_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4339, 188},
+ {I_VCMPEQ_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1520, 240},
+ {I_VCMPEQ_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1530, 240},
+ {I_VCMPEQ_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1540, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQPD[] = {
+ {I_VCMPEQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4348, 188},
+ {I_VCMPEQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4357, 188},
+ {I_VCMPEQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4366, 188},
+ {I_VCMPEQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4375, 188},
+ {I_VCMPEQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+240, 240},
+ {I_VCMPEQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+250, 240},
+ {I_VCMPEQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+260, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OSPD[] = {
+ {I_VCMPLT_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4384, 188},
+ {I_VCMPLT_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4393, 188},
+ {I_VCMPLT_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4402, 188},
+ {I_VCMPLT_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4411, 188},
+ {I_VCMPLT_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+320, 240},
+ {I_VCMPLT_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+330, 240},
+ {I_VCMPLT_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+340, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLTPD[] = {
+ {I_VCMPLTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4384, 188},
+ {I_VCMPLTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4393, 188},
+ {I_VCMPLTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4402, 188},
+ {I_VCMPLTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4411, 188},
+ {I_VCMPLTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+320, 240},
+ {I_VCMPLTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+330, 240},
+ {I_VCMPLTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+340, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OSPD[] = {
+ {I_VCMPLE_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4420, 188},
+ {I_VCMPLE_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4429, 188},
+ {I_VCMPLE_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4438, 188},
+ {I_VCMPLE_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4447, 188},
+ {I_VCMPLE_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+400, 240},
+ {I_VCMPLE_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+410, 240},
+ {I_VCMPLE_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+420, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLEPD[] = {
+ {I_VCMPLEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4420, 188},
+ {I_VCMPLEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4429, 188},
+ {I_VCMPLEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4438, 188},
+ {I_VCMPLEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4447, 188},
+ {I_VCMPLEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+400, 240},
+ {I_VCMPLEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+410, 240},
+ {I_VCMPLEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+420, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_QPD[] = {
+ {I_VCMPUNORD_QPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4456, 188},
+ {I_VCMPUNORD_QPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4465, 188},
+ {I_VCMPUNORD_QPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4474, 188},
+ {I_VCMPUNORD_QPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4483, 188},
+ {I_VCMPUNORD_QPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+480, 240},
+ {I_VCMPUNORD_QPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+490, 240},
+ {I_VCMPUNORD_QPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+500, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORDPD[] = {
+ {I_VCMPUNORDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4456, 188},
+ {I_VCMPUNORDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4465, 188},
+ {I_VCMPUNORDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4474, 188},
+ {I_VCMPUNORDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4483, 188},
+ {I_VCMPUNORDPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+480, 240},
+ {I_VCMPUNORDPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+490, 240},
+ {I_VCMPUNORDPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+500, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_UQPD[] = {
+ {I_VCMPNEQ_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4492, 188},
+ {I_VCMPNEQ_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4501, 188},
+ {I_VCMPNEQ_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4510, 188},
+ {I_VCMPNEQ_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4519, 188},
+ {I_VCMPNEQ_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+560, 240},
+ {I_VCMPNEQ_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+570, 240},
+ {I_VCMPNEQ_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+580, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQPD[] = {
+ {I_VCMPNEQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4492, 188},
+ {I_VCMPNEQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4501, 188},
+ {I_VCMPNEQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4510, 188},
+ {I_VCMPNEQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4519, 188},
+ {I_VCMPNEQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+560, 240},
+ {I_VCMPNEQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+570, 240},
+ {I_VCMPNEQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+580, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_USPD[] = {
+ {I_VCMPNLT_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4528, 188},
+ {I_VCMPNLT_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4537, 188},
+ {I_VCMPNLT_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4546, 188},
+ {I_VCMPNLT_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4555, 188},
+ {I_VCMPNLT_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+640, 240},
+ {I_VCMPNLT_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+650, 240},
+ {I_VCMPNLT_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+660, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLTPD[] = {
+ {I_VCMPNLTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4528, 188},
+ {I_VCMPNLTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4537, 188},
+ {I_VCMPNLTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4546, 188},
+ {I_VCMPNLTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4555, 188},
+ {I_VCMPNLTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+640, 240},
+ {I_VCMPNLTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+650, 240},
+ {I_VCMPNLTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+660, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_USPD[] = {
+ {I_VCMPNLE_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4564, 188},
+ {I_VCMPNLE_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4573, 188},
+ {I_VCMPNLE_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4582, 188},
+ {I_VCMPNLE_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4591, 188},
+ {I_VCMPNLE_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+720, 240},
+ {I_VCMPNLE_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+730, 240},
+ {I_VCMPNLE_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+740, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLEPD[] = {
+ {I_VCMPNLEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4564, 188},
+ {I_VCMPNLEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4573, 188},
+ {I_VCMPNLEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4582, 188},
+ {I_VCMPNLEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4591, 188},
+ {I_VCMPNLEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+720, 240},
+ {I_VCMPNLEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+730, 240},
+ {I_VCMPNLEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+740, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_QPD[] = {
+ {I_VCMPORD_QPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4600, 188},
+ {I_VCMPORD_QPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4609, 188},
+ {I_VCMPORD_QPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4618, 188},
+ {I_VCMPORD_QPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4627, 188},
+ {I_VCMPORD_QPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+800, 240},
+ {I_VCMPORD_QPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+810, 240},
+ {I_VCMPORD_QPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+820, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORDPD[] = {
+ {I_VCMPORDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4600, 188},
+ {I_VCMPORDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4609, 188},
+ {I_VCMPORDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4618, 188},
+ {I_VCMPORDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4627, 188},
+ {I_VCMPORDPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+800, 240},
+ {I_VCMPORDPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+810, 240},
+ {I_VCMPORDPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+820, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_UQPD[] = {
+ {I_VCMPEQ_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4636, 188},
+ {I_VCMPEQ_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4645, 188},
+ {I_VCMPEQ_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4654, 188},
+ {I_VCMPEQ_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4663, 188},
+ {I_VCMPEQ_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+880, 240},
+ {I_VCMPEQ_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+890, 240},
+ {I_VCMPEQ_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+900, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_USPD[] = {
+ {I_VCMPNGE_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4672, 188},
+ {I_VCMPNGE_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4681, 188},
+ {I_VCMPNGE_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4690, 188},
+ {I_VCMPNGE_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4699, 188},
+ {I_VCMPNGE_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+960, 240},
+ {I_VCMPNGE_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+970, 240},
+ {I_VCMPNGE_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+980, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGEPD[] = {
+ {I_VCMPNGEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4672, 188},
+ {I_VCMPNGEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4681, 188},
+ {I_VCMPNGEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4690, 188},
+ {I_VCMPNGEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4699, 188},
+ {I_VCMPNGEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+960, 240},
+ {I_VCMPNGEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+970, 240},
+ {I_VCMPNGEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+980, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_USPD[] = {
+ {I_VCMPNGT_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4708, 188},
+ {I_VCMPNGT_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4717, 188},
+ {I_VCMPNGT_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4726, 188},
+ {I_VCMPNGT_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4735, 188},
+ {I_VCMPNGT_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1040, 240},
+ {I_VCMPNGT_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1050, 240},
+ {I_VCMPNGT_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1060, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGTPD[] = {
+ {I_VCMPNGTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4708, 188},
+ {I_VCMPNGTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4717, 188},
+ {I_VCMPNGTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4726, 188},
+ {I_VCMPNGTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4735, 188},
+ {I_VCMPNGTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1040, 240},
+ {I_VCMPNGTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1050, 240},
+ {I_VCMPNGTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1060, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OQPD[] = {
+ {I_VCMPFALSE_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4744, 188},
+ {I_VCMPFALSE_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4753, 188},
+ {I_VCMPFALSE_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4762, 188},
+ {I_VCMPFALSE_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4771, 188},
+ {I_VCMPFALSE_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1120, 240},
+ {I_VCMPFALSE_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1130, 240},
+ {I_VCMPFALSE_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1140, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSEPD[] = {
+ {I_VCMPFALSEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4744, 188},
+ {I_VCMPFALSEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4753, 188},
+ {I_VCMPFALSEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4762, 188},
+ {I_VCMPFALSEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4771, 188},
+ {I_VCMPFALSEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1120, 240},
+ {I_VCMPFALSEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1130, 240},
+ {I_VCMPFALSEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1140, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OQPD[] = {
+ {I_VCMPNEQ_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4780, 188},
+ {I_VCMPNEQ_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4789, 188},
+ {I_VCMPNEQ_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4798, 188},
+ {I_VCMPNEQ_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4807, 188},
+ {I_VCMPNEQ_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1200, 240},
+ {I_VCMPNEQ_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1210, 240},
+ {I_VCMPNEQ_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1220, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OSPD[] = {
+ {I_VCMPGE_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4816, 188},
+ {I_VCMPGE_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4825, 188},
+ {I_VCMPGE_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4834, 188},
+ {I_VCMPGE_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4843, 188},
+ {I_VCMPGE_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1280, 240},
+ {I_VCMPGE_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1290, 240},
+ {I_VCMPGE_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1300, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGEPD[] = {
+ {I_VCMPGEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4816, 188},
+ {I_VCMPGEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4825, 188},
+ {I_VCMPGEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4834, 188},
+ {I_VCMPGEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4843, 188},
+ {I_VCMPGEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1280, 240},
+ {I_VCMPGEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1290, 240},
+ {I_VCMPGEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1300, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OSPD[] = {
+ {I_VCMPGT_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4852, 188},
+ {I_VCMPGT_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4861, 188},
+ {I_VCMPGT_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4870, 188},
+ {I_VCMPGT_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4879, 188},
+ {I_VCMPGT_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1360, 240},
+ {I_VCMPGT_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1370, 240},
+ {I_VCMPGT_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1380, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGTPD[] = {
+ {I_VCMPGTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4852, 188},
+ {I_VCMPGTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4861, 188},
+ {I_VCMPGTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4870, 188},
+ {I_VCMPGTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4879, 188},
+ {I_VCMPGTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1360, 240},
+ {I_VCMPGTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1370, 240},
+ {I_VCMPGTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1380, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_UQPD[] = {
+ {I_VCMPTRUE_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4888, 188},
+ {I_VCMPTRUE_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4897, 188},
+ {I_VCMPTRUE_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4906, 188},
+ {I_VCMPTRUE_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4915, 188},
+ {I_VCMPTRUE_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1440, 240},
+ {I_VCMPTRUE_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1450, 240},
+ {I_VCMPTRUE_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1460, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUEPD[] = {
+ {I_VCMPTRUEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4888, 188},
+ {I_VCMPTRUEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4897, 188},
+ {I_VCMPTRUEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4906, 188},
+ {I_VCMPTRUEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4915, 188},
+ {I_VCMPTRUEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1440, 240},
+ {I_VCMPTRUEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1450, 240},
+ {I_VCMPTRUEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1460, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OQPD[] = {
+ {I_VCMPLT_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4924, 188},
+ {I_VCMPLT_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4933, 188},
+ {I_VCMPLT_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4942, 188},
+ {I_VCMPLT_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4951, 188},
+ {I_VCMPLT_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1600, 240},
+ {I_VCMPLT_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1610, 240},
+ {I_VCMPLT_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1620, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OQPD[] = {
+ {I_VCMPLE_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4960, 188},
+ {I_VCMPLE_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4969, 188},
+ {I_VCMPLE_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4978, 188},
+ {I_VCMPLE_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4987, 188},
+ {I_VCMPLE_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1680, 240},
+ {I_VCMPLE_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1690, 240},
+ {I_VCMPLE_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1700, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_SPD[] = {
+ {I_VCMPUNORD_SPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4996, 188},
+ {I_VCMPUNORD_SPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5005, 188},
+ {I_VCMPUNORD_SPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5014, 188},
+ {I_VCMPUNORD_SPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5023, 188},
+ {I_VCMPUNORD_SPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1760, 240},
+ {I_VCMPUNORD_SPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1770, 240},
+ {I_VCMPUNORD_SPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1780, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_USPD[] = {
+ {I_VCMPNEQ_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5032, 188},
+ {I_VCMPNEQ_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5041, 188},
+ {I_VCMPNEQ_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5050, 188},
+ {I_VCMPNEQ_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5059, 188},
+ {I_VCMPNEQ_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1840, 240},
+ {I_VCMPNEQ_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1850, 240},
+ {I_VCMPNEQ_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1860, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_UQPD[] = {
+ {I_VCMPNLT_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5068, 188},
+ {I_VCMPNLT_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5077, 188},
+ {I_VCMPNLT_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5086, 188},
+ {I_VCMPNLT_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5095, 188},
+ {I_VCMPNLT_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1920, 240},
+ {I_VCMPNLT_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1930, 240},
+ {I_VCMPNLT_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1940, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_UQPD[] = {
+ {I_VCMPNLE_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5104, 188},
+ {I_VCMPNLE_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5113, 188},
+ {I_VCMPNLE_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5122, 188},
+ {I_VCMPNLE_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5131, 188},
+ {I_VCMPNLE_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2000, 240},
+ {I_VCMPNLE_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2010, 240},
+ {I_VCMPNLE_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2020, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_SPD[] = {
+ {I_VCMPORD_SPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5140, 188},
+ {I_VCMPORD_SPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5149, 188},
+ {I_VCMPORD_SPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5158, 188},
+ {I_VCMPORD_SPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5167, 188},
+ {I_VCMPORD_SPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2080, 240},
+ {I_VCMPORD_SPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2090, 240},
+ {I_VCMPORD_SPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2100, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_USPD[] = {
+ {I_VCMPEQ_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5176, 188},
+ {I_VCMPEQ_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5185, 188},
+ {I_VCMPEQ_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5194, 188},
+ {I_VCMPEQ_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5203, 188},
+ {I_VCMPEQ_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2160, 240},
+ {I_VCMPEQ_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2170, 240},
+ {I_VCMPEQ_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2180, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_UQPD[] = {
+ {I_VCMPNGE_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5212, 188},
+ {I_VCMPNGE_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5221, 188},
+ {I_VCMPNGE_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5230, 188},
+ {I_VCMPNGE_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5239, 188},
+ {I_VCMPNGE_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2240, 240},
+ {I_VCMPNGE_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2250, 240},
+ {I_VCMPNGE_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2260, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_UQPD[] = {
+ {I_VCMPNGT_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5248, 188},
+ {I_VCMPNGT_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5257, 188},
+ {I_VCMPNGT_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5266, 188},
+ {I_VCMPNGT_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5275, 188},
+ {I_VCMPNGT_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2320, 240},
+ {I_VCMPNGT_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2330, 240},
+ {I_VCMPNGT_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2340, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OSPD[] = {
+ {I_VCMPFALSE_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5284, 188},
+ {I_VCMPFALSE_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5293, 188},
+ {I_VCMPFALSE_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5302, 188},
+ {I_VCMPFALSE_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5311, 188},
+ {I_VCMPFALSE_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2400, 240},
+ {I_VCMPFALSE_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2410, 240},
+ {I_VCMPFALSE_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2420, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OSPD[] = {
+ {I_VCMPNEQ_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5320, 188},
+ {I_VCMPNEQ_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5329, 188},
+ {I_VCMPNEQ_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5338, 188},
+ {I_VCMPNEQ_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5347, 188},
+ {I_VCMPNEQ_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2480, 240},
+ {I_VCMPNEQ_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2490, 240},
+ {I_VCMPNEQ_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2500, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OQPD[] = {
+ {I_VCMPGE_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5356, 188},
+ {I_VCMPGE_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5365, 188},
+ {I_VCMPGE_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5374, 188},
+ {I_VCMPGE_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5383, 188},
+ {I_VCMPGE_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2560, 240},
+ {I_VCMPGE_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2570, 240},
+ {I_VCMPGE_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2580, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OQPD[] = {
+ {I_VCMPGT_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5392, 188},
+ {I_VCMPGT_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5401, 188},
+ {I_VCMPGT_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5410, 188},
+ {I_VCMPGT_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5419, 188},
+ {I_VCMPGT_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2640, 240},
+ {I_VCMPGT_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2650, 240},
+ {I_VCMPGT_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2660, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_USPD[] = {
+ {I_VCMPTRUE_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5428, 188},
+ {I_VCMPTRUE_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5437, 188},
+ {I_VCMPTRUE_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5446, 188},
+ {I_VCMPTRUE_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5455, 188},
+ {I_VCMPTRUE_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2720, 240},
+ {I_VCMPTRUE_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2730, 240},
+ {I_VCMPTRUE_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2740, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPPD[] = {
+ {I_VCMPPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13432, 188},
+ {I_VCMPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13440, 188},
+ {I_VCMPPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13448, 188},
+ {I_VCMPPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13456, 188},
+ {I_VCMPPD, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8110, 240},
+ {I_VCMPPD, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8119, 240},
+ {I_VCMPPD, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+8128, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OSPS[] = {
+ {I_VCMPEQ_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5464, 188},
+ {I_VCMPEQ_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5473, 188},
+ {I_VCMPEQ_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5482, 188},
+ {I_VCMPEQ_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5491, 188},
+ {I_VCMPEQ_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5464, 188},
+ {I_VCMPEQ_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5473, 188},
+ {I_VCMPEQ_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5482, 188},
+ {I_VCMPEQ_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5491, 188},
+ {I_VCMPEQ_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1550, 240},
+ {I_VCMPEQ_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1560, 240},
+ {I_VCMPEQ_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1570, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQPS[] = {
+ {I_VCMPEQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5500, 188},
+ {I_VCMPEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5509, 188},
+ {I_VCMPEQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5518, 188},
+ {I_VCMPEQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5527, 188},
+ {I_VCMPEQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+270, 240},
+ {I_VCMPEQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+280, 240},
+ {I_VCMPEQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+290, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OSPS[] = {
+ {I_VCMPLT_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5536, 188},
+ {I_VCMPLT_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5545, 188},
+ {I_VCMPLT_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5554, 188},
+ {I_VCMPLT_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5563, 188},
+ {I_VCMPLT_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+350, 240},
+ {I_VCMPLT_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+360, 240},
+ {I_VCMPLT_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+370, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLTPS[] = {
+ {I_VCMPLTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5536, 188},
+ {I_VCMPLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5545, 188},
+ {I_VCMPLTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5554, 188},
+ {I_VCMPLTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5563, 188},
+ {I_VCMPLTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+350, 240},
+ {I_VCMPLTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+360, 240},
+ {I_VCMPLTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+370, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OSPS[] = {
+ {I_VCMPLE_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5572, 188},
+ {I_VCMPLE_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5581, 188},
+ {I_VCMPLE_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5590, 188},
+ {I_VCMPLE_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5599, 188},
+ {I_VCMPLE_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+430, 240},
+ {I_VCMPLE_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+440, 240},
+ {I_VCMPLE_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+450, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLEPS[] = {
+ {I_VCMPLEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5572, 188},
+ {I_VCMPLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5581, 188},
+ {I_VCMPLEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5590, 188},
+ {I_VCMPLEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5599, 188},
+ {I_VCMPLEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+430, 240},
+ {I_VCMPLEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+440, 240},
+ {I_VCMPLEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+450, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_QPS[] = {
+ {I_VCMPUNORD_QPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5608, 188},
+ {I_VCMPUNORD_QPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5617, 188},
+ {I_VCMPUNORD_QPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5626, 188},
+ {I_VCMPUNORD_QPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5635, 188},
+ {I_VCMPUNORD_QPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+510, 240},
+ {I_VCMPUNORD_QPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+520, 240},
+ {I_VCMPUNORD_QPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+530, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORDPS[] = {
+ {I_VCMPUNORDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5608, 188},
+ {I_VCMPUNORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5617, 188},
+ {I_VCMPUNORDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5626, 188},
+ {I_VCMPUNORDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5635, 188},
+ {I_VCMPUNORDPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+510, 240},
+ {I_VCMPUNORDPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+520, 240},
+ {I_VCMPUNORDPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+530, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_UQPS[] = {
+ {I_VCMPNEQ_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5644, 188},
+ {I_VCMPNEQ_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5653, 188},
+ {I_VCMPNEQ_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5662, 188},
+ {I_VCMPNEQ_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5671, 188},
+ {I_VCMPNEQ_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+590, 240},
+ {I_VCMPNEQ_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+600, 240},
+ {I_VCMPNEQ_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+610, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQPS[] = {
+ {I_VCMPNEQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5644, 188},
+ {I_VCMPNEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5653, 188},
+ {I_VCMPNEQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5662, 188},
+ {I_VCMPNEQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5671, 188},
+ {I_VCMPNEQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+590, 240},
+ {I_VCMPNEQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+600, 240},
+ {I_VCMPNEQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+610, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_USPS[] = {
+ {I_VCMPNLT_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5680, 188},
+ {I_VCMPNLT_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5689, 188},
+ {I_VCMPNLT_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5698, 188},
+ {I_VCMPNLT_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5707, 188},
+ {I_VCMPNLT_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+670, 240},
+ {I_VCMPNLT_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+680, 240},
+ {I_VCMPNLT_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+690, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLTPS[] = {
+ {I_VCMPNLTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5680, 188},
+ {I_VCMPNLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5689, 188},
+ {I_VCMPNLTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5698, 188},
+ {I_VCMPNLTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5707, 188},
+ {I_VCMPNLTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+670, 240},
+ {I_VCMPNLTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+680, 240},
+ {I_VCMPNLTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+690, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_USPS[] = {
+ {I_VCMPNLE_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5716, 188},
+ {I_VCMPNLE_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5725, 188},
+ {I_VCMPNLE_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5734, 188},
+ {I_VCMPNLE_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5743, 188},
+ {I_VCMPNLE_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+750, 240},
+ {I_VCMPNLE_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+760, 240},
+ {I_VCMPNLE_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+770, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLEPS[] = {
+ {I_VCMPNLEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5716, 188},
+ {I_VCMPNLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5725, 188},
+ {I_VCMPNLEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5734, 188},
+ {I_VCMPNLEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5743, 188},
+ {I_VCMPNLEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+750, 240},
+ {I_VCMPNLEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+760, 240},
+ {I_VCMPNLEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+770, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_QPS[] = {
+ {I_VCMPORD_QPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5752, 188},
+ {I_VCMPORD_QPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5761, 188},
+ {I_VCMPORD_QPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5770, 188},
+ {I_VCMPORD_QPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5779, 188},
+ {I_VCMPORD_QPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+830, 240},
+ {I_VCMPORD_QPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+840, 240},
+ {I_VCMPORD_QPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+850, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORDPS[] = {
+ {I_VCMPORDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5752, 188},
+ {I_VCMPORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5761, 188},
+ {I_VCMPORDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5770, 188},
+ {I_VCMPORDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5779, 188},
+ {I_VCMPORDPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+830, 240},
+ {I_VCMPORDPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+840, 240},
+ {I_VCMPORDPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+850, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_UQPS[] = {
+ {I_VCMPEQ_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5788, 188},
+ {I_VCMPEQ_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5797, 188},
+ {I_VCMPEQ_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5806, 188},
+ {I_VCMPEQ_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5815, 188},
+ {I_VCMPEQ_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+910, 240},
+ {I_VCMPEQ_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+920, 240},
+ {I_VCMPEQ_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+930, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_USPS[] = {
+ {I_VCMPNGE_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5824, 188},
+ {I_VCMPNGE_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5833, 188},
+ {I_VCMPNGE_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5842, 188},
+ {I_VCMPNGE_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5851, 188},
+ {I_VCMPNGE_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+990, 240},
+ {I_VCMPNGE_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1000, 240},
+ {I_VCMPNGE_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1010, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGEPS[] = {
+ {I_VCMPNGEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5824, 188},
+ {I_VCMPNGEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5833, 188},
+ {I_VCMPNGEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5842, 188},
+ {I_VCMPNGEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5851, 188},
+ {I_VCMPNGEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+990, 240},
+ {I_VCMPNGEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1000, 240},
+ {I_VCMPNGEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1010, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_USPS[] = {
+ {I_VCMPNGT_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5860, 188},
+ {I_VCMPNGT_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5869, 188},
+ {I_VCMPNGT_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5878, 188},
+ {I_VCMPNGT_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5887, 188},
+ {I_VCMPNGT_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1070, 240},
+ {I_VCMPNGT_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1080, 240},
+ {I_VCMPNGT_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1090, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGTPS[] = {
+ {I_VCMPNGTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5860, 188},
+ {I_VCMPNGTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5869, 188},
+ {I_VCMPNGTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5878, 188},
+ {I_VCMPNGTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5887, 188},
+ {I_VCMPNGTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1070, 240},
+ {I_VCMPNGTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1080, 240},
+ {I_VCMPNGTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1090, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OQPS[] = {
+ {I_VCMPFALSE_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5896, 188},
+ {I_VCMPFALSE_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5905, 188},
+ {I_VCMPFALSE_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5914, 188},
+ {I_VCMPFALSE_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5923, 188},
+ {I_VCMPFALSE_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1150, 240},
+ {I_VCMPFALSE_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1160, 240},
+ {I_VCMPFALSE_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1170, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSEPS[] = {
+ {I_VCMPFALSEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5896, 188},
+ {I_VCMPFALSEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5905, 188},
+ {I_VCMPFALSEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5914, 188},
+ {I_VCMPFALSEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5923, 188},
+ {I_VCMPFALSEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1150, 240},
+ {I_VCMPFALSEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1160, 240},
+ {I_VCMPFALSEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1170, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OQPS[] = {
+ {I_VCMPNEQ_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5932, 188},
+ {I_VCMPNEQ_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5941, 188},
+ {I_VCMPNEQ_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5950, 188},
+ {I_VCMPNEQ_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5959, 188},
+ {I_VCMPNEQ_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1230, 240},
+ {I_VCMPNEQ_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1240, 240},
+ {I_VCMPNEQ_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1250, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OSPS[] = {
+ {I_VCMPGE_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5968, 188},
+ {I_VCMPGE_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5977, 188},
+ {I_VCMPGE_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5986, 188},
+ {I_VCMPGE_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5995, 188},
+ {I_VCMPGE_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1310, 240},
+ {I_VCMPGE_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1320, 240},
+ {I_VCMPGE_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1330, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGEPS[] = {
+ {I_VCMPGEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5968, 188},
+ {I_VCMPGEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5977, 188},
+ {I_VCMPGEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5986, 188},
+ {I_VCMPGEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5995, 188},
+ {I_VCMPGEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1310, 240},
+ {I_VCMPGEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1320, 240},
+ {I_VCMPGEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1330, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OSPS[] = {
+ {I_VCMPGT_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6004, 188},
+ {I_VCMPGT_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6013, 188},
+ {I_VCMPGT_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6022, 188},
+ {I_VCMPGT_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6031, 188},
+ {I_VCMPGT_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1390, 240},
+ {I_VCMPGT_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1400, 240},
+ {I_VCMPGT_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1410, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGTPS[] = {
+ {I_VCMPGTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6004, 188},
+ {I_VCMPGTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6013, 188},
+ {I_VCMPGTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6022, 188},
+ {I_VCMPGTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6031, 188},
+ {I_VCMPGTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1390, 240},
+ {I_VCMPGTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1400, 240},
+ {I_VCMPGTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1410, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_UQPS[] = {
+ {I_VCMPTRUE_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6040, 188},
+ {I_VCMPTRUE_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6049, 188},
+ {I_VCMPTRUE_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6058, 188},
+ {I_VCMPTRUE_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6067, 188},
+ {I_VCMPTRUE_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1470, 240},
+ {I_VCMPTRUE_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1480, 240},
+ {I_VCMPTRUE_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1490, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUEPS[] = {
+ {I_VCMPTRUEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6040, 188},
+ {I_VCMPTRUEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6049, 188},
+ {I_VCMPTRUEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6058, 188},
+ {I_VCMPTRUEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6067, 188},
+ {I_VCMPTRUEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1470, 240},
+ {I_VCMPTRUEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1480, 240},
+ {I_VCMPTRUEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1490, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OQPS[] = {
+ {I_VCMPLT_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6076, 188},
+ {I_VCMPLT_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6085, 188},
+ {I_VCMPLT_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6094, 188},
+ {I_VCMPLT_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6103, 188},
+ {I_VCMPLT_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1630, 240},
+ {I_VCMPLT_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1640, 240},
+ {I_VCMPLT_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1650, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OQPS[] = {
+ {I_VCMPLE_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6112, 188},
+ {I_VCMPLE_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6121, 188},
+ {I_VCMPLE_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6130, 188},
+ {I_VCMPLE_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6139, 188},
+ {I_VCMPLE_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1710, 240},
+ {I_VCMPLE_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1720, 240},
+ {I_VCMPLE_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1730, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_SPS[] = {
+ {I_VCMPUNORD_SPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6148, 188},
+ {I_VCMPUNORD_SPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6157, 188},
+ {I_VCMPUNORD_SPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6166, 188},
+ {I_VCMPUNORD_SPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6175, 188},
+ {I_VCMPUNORD_SPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1790, 240},
+ {I_VCMPUNORD_SPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1800, 240},
+ {I_VCMPUNORD_SPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1810, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_USPS[] = {
+ {I_VCMPNEQ_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6184, 188},
+ {I_VCMPNEQ_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6193, 188},
+ {I_VCMPNEQ_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6202, 188},
+ {I_VCMPNEQ_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6211, 188},
+ {I_VCMPNEQ_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1870, 240},
+ {I_VCMPNEQ_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1880, 240},
+ {I_VCMPNEQ_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1890, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_UQPS[] = {
+ {I_VCMPNLT_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6220, 188},
+ {I_VCMPNLT_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6229, 188},
+ {I_VCMPNLT_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6238, 188},
+ {I_VCMPNLT_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6247, 188},
+ {I_VCMPNLT_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1950, 240},
+ {I_VCMPNLT_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1960, 240},
+ {I_VCMPNLT_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1970, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_UQPS[] = {
+ {I_VCMPNLE_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6256, 188},
+ {I_VCMPNLE_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6265, 188},
+ {I_VCMPNLE_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6274, 188},
+ {I_VCMPNLE_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6283, 188},
+ {I_VCMPNLE_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2030, 240},
+ {I_VCMPNLE_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2040, 240},
+ {I_VCMPNLE_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2050, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_SPS[] = {
+ {I_VCMPORD_SPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6292, 188},
+ {I_VCMPORD_SPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6301, 188},
+ {I_VCMPORD_SPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6310, 188},
+ {I_VCMPORD_SPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6319, 188},
+ {I_VCMPORD_SPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2110, 240},
+ {I_VCMPORD_SPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2120, 240},
+ {I_VCMPORD_SPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2130, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_USPS[] = {
+ {I_VCMPEQ_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6328, 188},
+ {I_VCMPEQ_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6337, 188},
+ {I_VCMPEQ_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6346, 188},
+ {I_VCMPEQ_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6355, 188},
+ {I_VCMPEQ_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2190, 240},
+ {I_VCMPEQ_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2200, 240},
+ {I_VCMPEQ_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2210, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_UQPS[] = {
+ {I_VCMPNGE_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6364, 188},
+ {I_VCMPNGE_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6373, 188},
+ {I_VCMPNGE_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6382, 188},
+ {I_VCMPNGE_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6391, 188},
+ {I_VCMPNGE_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2270, 240},
+ {I_VCMPNGE_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2280, 240},
+ {I_VCMPNGE_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2290, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_UQPS[] = {
+ {I_VCMPNGT_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6400, 188},
+ {I_VCMPNGT_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6409, 188},
+ {I_VCMPNGT_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6418, 188},
+ {I_VCMPNGT_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6427, 188},
+ {I_VCMPNGT_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2350, 240},
+ {I_VCMPNGT_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2360, 240},
+ {I_VCMPNGT_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2370, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OSPS[] = {
+ {I_VCMPFALSE_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6436, 188},
+ {I_VCMPFALSE_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6445, 188},
+ {I_VCMPFALSE_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6454, 188},
+ {I_VCMPFALSE_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6463, 188},
+ {I_VCMPFALSE_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2430, 240},
+ {I_VCMPFALSE_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2440, 240},
+ {I_VCMPFALSE_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2450, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OSPS[] = {
+ {I_VCMPNEQ_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6472, 188},
+ {I_VCMPNEQ_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6481, 188},
+ {I_VCMPNEQ_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6490, 188},
+ {I_VCMPNEQ_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6499, 188},
+ {I_VCMPNEQ_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2510, 240},
+ {I_VCMPNEQ_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2520, 240},
+ {I_VCMPNEQ_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2530, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OQPS[] = {
+ {I_VCMPGE_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6508, 188},
+ {I_VCMPGE_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6517, 188},
+ {I_VCMPGE_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6526, 188},
+ {I_VCMPGE_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6535, 188},
+ {I_VCMPGE_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2590, 240},
+ {I_VCMPGE_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2600, 240},
+ {I_VCMPGE_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2610, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OQPS[] = {
+ {I_VCMPGT_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6544, 188},
+ {I_VCMPGT_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6553, 188},
+ {I_VCMPGT_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6562, 188},
+ {I_VCMPGT_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6571, 188},
+ {I_VCMPGT_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2670, 240},
+ {I_VCMPGT_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2680, 240},
+ {I_VCMPGT_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2690, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_USPS[] = {
+ {I_VCMPTRUE_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6580, 188},
+ {I_VCMPTRUE_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6589, 188},
+ {I_VCMPTRUE_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6598, 188},
+ {I_VCMPTRUE_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6607, 188},
+ {I_VCMPTRUE_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2750, 240},
+ {I_VCMPTRUE_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2760, 240},
+ {I_VCMPTRUE_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2770, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPPS[] = {
+ {I_VCMPPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13464, 188},
+ {I_VCMPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13472, 188},
+ {I_VCMPPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13480, 188},
+ {I_VCMPPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13488, 188},
+ {I_VCMPPS, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8137, 240},
+ {I_VCMPPS, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8146, 240},
+ {I_VCMPPS, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+8155, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OSSD[] = {
+ {I_VCMPEQ_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6616, 188},
+ {I_VCMPEQ_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6625, 188},
+ {I_VCMPEQ_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6616, 188},
+ {I_VCMPEQ_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6625, 188},
+ {I_VCMPEQ_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1580, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQSD[] = {
+ {I_VCMPEQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6634, 188},
+ {I_VCMPEQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6643, 188},
+ {I_VCMPEQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+300, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OSSD[] = {
+ {I_VCMPLT_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6652, 188},
+ {I_VCMPLT_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6661, 188},
+ {I_VCMPLT_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+380, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLTSD[] = {
+ {I_VCMPLTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6652, 188},
+ {I_VCMPLTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6661, 188},
+ {I_VCMPLTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+380, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OSSD[] = {
+ {I_VCMPLE_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6670, 188},
+ {I_VCMPLE_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6679, 188},
+ {I_VCMPLE_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+460, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLESD[] = {
+ {I_VCMPLESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6670, 188},
+ {I_VCMPLESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6679, 188},
+ {I_VCMPLESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+460, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_QSD[] = {
+ {I_VCMPUNORD_QSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6688, 188},
+ {I_VCMPUNORD_QSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6697, 188},
+ {I_VCMPUNORD_QSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+540, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORDSD[] = {
+ {I_VCMPUNORDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6688, 188},
+ {I_VCMPUNORDSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6697, 188},
+ {I_VCMPUNORDSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+540, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_UQSD[] = {
+ {I_VCMPNEQ_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6706, 188},
+ {I_VCMPNEQ_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6715, 188},
+ {I_VCMPNEQ_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+620, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQSD[] = {
+ {I_VCMPNEQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6706, 188},
+ {I_VCMPNEQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6715, 188},
+ {I_VCMPNEQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+620, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_USSD[] = {
+ {I_VCMPNLT_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6724, 188},
+ {I_VCMPNLT_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6733, 188},
+ {I_VCMPNLT_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+700, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLTSD[] = {
+ {I_VCMPNLTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6724, 188},
+ {I_VCMPNLTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6733, 188},
+ {I_VCMPNLTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+700, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_USSD[] = {
+ {I_VCMPNLE_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6742, 188},
+ {I_VCMPNLE_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6751, 188},
+ {I_VCMPNLE_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+780, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLESD[] = {
+ {I_VCMPNLESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6742, 188},
+ {I_VCMPNLESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6751, 188},
+ {I_VCMPNLESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+780, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_QSD[] = {
+ {I_VCMPORD_QSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6760, 188},
+ {I_VCMPORD_QSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6769, 188},
+ {I_VCMPORD_QSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+860, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORDSD[] = {
+ {I_VCMPORDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6760, 188},
+ {I_VCMPORDSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6769, 188},
+ {I_VCMPORDSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+860, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_UQSD[] = {
+ {I_VCMPEQ_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6778, 188},
+ {I_VCMPEQ_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6787, 188},
+ {I_VCMPEQ_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+940, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_USSD[] = {
+ {I_VCMPNGE_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6796, 188},
+ {I_VCMPNGE_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6805, 188},
+ {I_VCMPNGE_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1020, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGESD[] = {
+ {I_VCMPNGESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6796, 188},
+ {I_VCMPNGESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6805, 188},
+ {I_VCMPNGESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1020, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_USSD[] = {
+ {I_VCMPNGT_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6814, 188},
+ {I_VCMPNGT_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6823, 188},
+ {I_VCMPNGT_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1100, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGTSD[] = {
+ {I_VCMPNGTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6814, 188},
+ {I_VCMPNGTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6823, 188},
+ {I_VCMPNGTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1100, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OQSD[] = {
+ {I_VCMPFALSE_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6832, 188},
+ {I_VCMPFALSE_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6841, 188},
+ {I_VCMPFALSE_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1180, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSESD[] = {
+ {I_VCMPFALSESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6832, 188},
+ {I_VCMPFALSESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6841, 188},
+ {I_VCMPFALSESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1180, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OQSD[] = {
+ {I_VCMPNEQ_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6850, 188},
+ {I_VCMPNEQ_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6859, 188},
+ {I_VCMPNEQ_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1260, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OSSD[] = {
+ {I_VCMPGE_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6868, 188},
+ {I_VCMPGE_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6877, 188},
+ {I_VCMPGE_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1340, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGESD[] = {
+ {I_VCMPGESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6868, 188},
+ {I_VCMPGESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6877, 188},
+ {I_VCMPGESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1340, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OSSD[] = {
+ {I_VCMPGT_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6886, 188},
+ {I_VCMPGT_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6895, 188},
+ {I_VCMPGT_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1420, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGTSD[] = {
+ {I_VCMPGTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6886, 188},
+ {I_VCMPGTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6895, 188},
+ {I_VCMPGTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1420, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_UQSD[] = {
+ {I_VCMPTRUE_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6904, 188},
+ {I_VCMPTRUE_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6913, 188},
+ {I_VCMPTRUE_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1500, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUESD[] = {
+ {I_VCMPTRUESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6904, 188},
+ {I_VCMPTRUESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6913, 188},
+ {I_VCMPTRUESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1500, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OQSD[] = {
+ {I_VCMPLT_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6922, 188},
+ {I_VCMPLT_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6931, 188},
+ {I_VCMPLT_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1660, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OQSD[] = {
+ {I_VCMPLE_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6940, 188},
+ {I_VCMPLE_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6949, 188},
+ {I_VCMPLE_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1740, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_SSD[] = {
+ {I_VCMPUNORD_SSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6958, 188},
+ {I_VCMPUNORD_SSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6967, 188},
+ {I_VCMPUNORD_SSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1820, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_USSD[] = {
+ {I_VCMPNEQ_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6976, 188},
+ {I_VCMPNEQ_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6985, 188},
+ {I_VCMPNEQ_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1900, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_UQSD[] = {
+ {I_VCMPNLT_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6994, 188},
+ {I_VCMPNLT_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7003, 188},
+ {I_VCMPNLT_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1980, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_UQSD[] = {
+ {I_VCMPNLE_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7012, 188},
+ {I_VCMPNLE_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7021, 188},
+ {I_VCMPNLE_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2060, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_SSD[] = {
+ {I_VCMPORD_SSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7030, 188},
+ {I_VCMPORD_SSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7039, 188},
+ {I_VCMPORD_SSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2140, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_USSD[] = {
+ {I_VCMPEQ_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7048, 188},
+ {I_VCMPEQ_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7057, 188},
+ {I_VCMPEQ_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2220, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_UQSD[] = {
+ {I_VCMPNGE_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7066, 188},
+ {I_VCMPNGE_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7075, 188},
+ {I_VCMPNGE_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2300, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_UQSD[] = {
+ {I_VCMPNGT_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7084, 188},
+ {I_VCMPNGT_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7093, 188},
+ {I_VCMPNGT_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2380, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OSSD[] = {
+ {I_VCMPFALSE_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7102, 188},
+ {I_VCMPFALSE_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7111, 188},
+ {I_VCMPFALSE_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2460, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OSSD[] = {
+ {I_VCMPNEQ_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7120, 188},
+ {I_VCMPNEQ_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7129, 188},
+ {I_VCMPNEQ_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2540, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OQSD[] = {
+ {I_VCMPGE_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7138, 188},
+ {I_VCMPGE_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7147, 188},
+ {I_VCMPGE_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2620, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OQSD[] = {
+ {I_VCMPGT_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7156, 188},
+ {I_VCMPGT_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7165, 188},
+ {I_VCMPGT_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2700, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_USSD[] = {
+ {I_VCMPTRUE_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7174, 188},
+ {I_VCMPTRUE_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7183, 188},
+ {I_VCMPTRUE_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2780, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPSD[] = {
+ {I_VCMPSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13496, 188},
+ {I_VCMPSD, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13504, 188},
+ {I_VCMPSD, 4, {KREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+8164, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OSSS[] = {
+ {I_VCMPEQ_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7192, 188},
+ {I_VCMPEQ_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7201, 188},
+ {I_VCMPEQ_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7192, 188},
+ {I_VCMPEQ_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7201, 188},
+ {I_VCMPEQ_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1590, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQSS[] = {
+ {I_VCMPEQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7210, 188},
+ {I_VCMPEQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7219, 188},
+ {I_VCMPEQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+310, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OSSS[] = {
+ {I_VCMPLT_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7228, 188},
+ {I_VCMPLT_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7237, 188},
+ {I_VCMPLT_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+390, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLTSS[] = {
+ {I_VCMPLTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7228, 188},
+ {I_VCMPLTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7237, 188},
+ {I_VCMPLTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+390, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OSSS[] = {
+ {I_VCMPLE_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7246, 188},
+ {I_VCMPLE_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7255, 188},
+ {I_VCMPLE_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+470, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLESS[] = {
+ {I_VCMPLESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7246, 188},
+ {I_VCMPLESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7255, 188},
+ {I_VCMPLESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+470, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_QSS[] = {
+ {I_VCMPUNORD_QSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7264, 188},
+ {I_VCMPUNORD_QSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7273, 188},
+ {I_VCMPUNORD_QSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+550, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORDSS[] = {
+ {I_VCMPUNORDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7264, 188},
+ {I_VCMPUNORDSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7273, 188},
+ {I_VCMPUNORDSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+550, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_UQSS[] = {
+ {I_VCMPNEQ_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7282, 188},
+ {I_VCMPNEQ_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7291, 188},
+ {I_VCMPNEQ_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+630, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQSS[] = {
+ {I_VCMPNEQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7282, 188},
+ {I_VCMPNEQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7291, 188},
+ {I_VCMPNEQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+630, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_USSS[] = {
+ {I_VCMPNLT_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7300, 188},
+ {I_VCMPNLT_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7309, 188},
+ {I_VCMPNLT_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+710, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLTSS[] = {
+ {I_VCMPNLTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7300, 188},
+ {I_VCMPNLTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7309, 188},
+ {I_VCMPNLTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+710, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_USSS[] = {
+ {I_VCMPNLE_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7318, 188},
+ {I_VCMPNLE_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7327, 188},
+ {I_VCMPNLE_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+790, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLESS[] = {
+ {I_VCMPNLESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7318, 188},
+ {I_VCMPNLESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7327, 188},
+ {I_VCMPNLESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+790, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_QSS[] = {
+ {I_VCMPORD_QSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7336, 188},
+ {I_VCMPORD_QSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7345, 188},
+ {I_VCMPORD_QSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+870, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORDSS[] = {
+ {I_VCMPORDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7336, 188},
+ {I_VCMPORDSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7345, 188},
+ {I_VCMPORDSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+870, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_UQSS[] = {
+ {I_VCMPEQ_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7354, 188},
+ {I_VCMPEQ_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7363, 188},
+ {I_VCMPEQ_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+950, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_USSS[] = {
+ {I_VCMPNGE_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7372, 188},
+ {I_VCMPNGE_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7381, 188},
+ {I_VCMPNGE_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1030, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGESS[] = {
+ {I_VCMPNGESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7372, 188},
+ {I_VCMPNGESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7381, 188},
+ {I_VCMPNGESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1030, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_USSS[] = {
+ {I_VCMPNGT_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7390, 188},
+ {I_VCMPNGT_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7399, 188},
+ {I_VCMPNGT_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1110, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGTSS[] = {
+ {I_VCMPNGTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7390, 188},
+ {I_VCMPNGTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7399, 188},
+ {I_VCMPNGTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1110, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OQSS[] = {
+ {I_VCMPFALSE_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7408, 188},
+ {I_VCMPFALSE_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7417, 188},
+ {I_VCMPFALSE_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1190, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSESS[] = {
+ {I_VCMPFALSESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7408, 188},
+ {I_VCMPFALSESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7417, 188},
+ {I_VCMPFALSESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1190, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OQSS[] = {
+ {I_VCMPNEQ_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7426, 188},
+ {I_VCMPNEQ_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7435, 188},
+ {I_VCMPNEQ_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1270, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OSSS[] = {
+ {I_VCMPGE_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7444, 188},
+ {I_VCMPGE_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7453, 188},
+ {I_VCMPGE_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1350, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGESS[] = {
+ {I_VCMPGESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7444, 188},
+ {I_VCMPGESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7453, 188},
+ {I_VCMPGESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1350, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OSSS[] = {
+ {I_VCMPGT_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7462, 188},
+ {I_VCMPGT_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7471, 188},
+ {I_VCMPGT_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1430, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGTSS[] = {
+ {I_VCMPGTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7462, 188},
+ {I_VCMPGTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7471, 188},
+ {I_VCMPGTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1430, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_UQSS[] = {
+ {I_VCMPTRUE_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7480, 188},
+ {I_VCMPTRUE_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7489, 188},
+ {I_VCMPTRUE_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1510, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUESS[] = {
+ {I_VCMPTRUESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7480, 188},
+ {I_VCMPTRUESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7489, 188},
+ {I_VCMPTRUESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1510, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLT_OQSS[] = {
+ {I_VCMPLT_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7498, 188},
+ {I_VCMPLT_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7507, 188},
+ {I_VCMPLT_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1670, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPLE_OQSS[] = {
+ {I_VCMPLE_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7516, 188},
+ {I_VCMPLE_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7525, 188},
+ {I_VCMPLE_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1750, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPUNORD_SSS[] = {
+ {I_VCMPUNORD_SSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7534, 188},
+ {I_VCMPUNORD_SSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7543, 188},
+ {I_VCMPUNORD_SSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1830, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_USSS[] = {
+ {I_VCMPNEQ_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7552, 188},
+ {I_VCMPNEQ_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7561, 188},
+ {I_VCMPNEQ_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1910, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLT_UQSS[] = {
+ {I_VCMPNLT_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7570, 188},
+ {I_VCMPNLT_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7579, 188},
+ {I_VCMPNLT_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1990, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNLE_UQSS[] = {
+ {I_VCMPNLE_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7588, 188},
+ {I_VCMPNLE_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7597, 188},
+ {I_VCMPNLE_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2070, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPORD_SSS[] = {
+ {I_VCMPORD_SSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7606, 188},
+ {I_VCMPORD_SSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7615, 188},
+ {I_VCMPORD_SSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2150, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_USSS[] = {
+ {I_VCMPEQ_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7624, 188},
+ {I_VCMPEQ_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7633, 188},
+ {I_VCMPEQ_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2230, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGE_UQSS[] = {
+ {I_VCMPNGE_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7642, 188},
+ {I_VCMPNGE_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7651, 188},
+ {I_VCMPNGE_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2310, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNGT_UQSS[] = {
+ {I_VCMPNGT_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7660, 188},
+ {I_VCMPNGT_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7669, 188},
+ {I_VCMPNGT_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2390, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPFALSE_OSSS[] = {
+ {I_VCMPFALSE_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7678, 188},
+ {I_VCMPFALSE_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7687, 188},
+ {I_VCMPFALSE_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2470, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPNEQ_OSSS[] = {
+ {I_VCMPNEQ_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7696, 188},
+ {I_VCMPNEQ_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7705, 188},
+ {I_VCMPNEQ_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2550, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGE_OQSS[] = {
+ {I_VCMPGE_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7714, 188},
+ {I_VCMPGE_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7723, 188},
+ {I_VCMPGE_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2630, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPGT_OQSS[] = {
+ {I_VCMPGT_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7732, 188},
+ {I_VCMPGT_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7741, 188},
+ {I_VCMPGT_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2710, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPTRUE_USSS[] = {
+ {I_VCMPTRUE_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7750, 188},
+ {I_VCMPTRUE_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7759, 188},
+ {I_VCMPTRUE_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2790, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPSS[] = {
+ {I_VCMPSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13512, 188},
+ {I_VCMPSS, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13520, 188},
+ {I_VCMPSS, 4, {KREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+8173, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCOMISD[] = {
+ {I_VCOMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35272, 188},
+ {I_VCOMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+16960, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCOMISS[] = {
+ {I_VCOMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35279, 188},
+ {I_VCOMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+16968, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTDQ2PD[] = {
+ {I_VCVTDQ2PD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35286, 188},
+ {I_VCVTDQ2PD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35293, 188},
+ {I_VCVTDQ2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17072, 240},
+ {I_VCVTDQ2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17080, 240},
+ {I_VCVTDQ2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17088, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTDQ2PS[] = {
+ {I_VCVTDQ2PS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35300, 188},
+ {I_VCVTDQ2PS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35307, 188},
+ {I_VCVTDQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17096, 240},
+ {I_VCVTDQ2PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17104, 240},
+ {I_VCVTDQ2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17112, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPD2DQ[] = {
+ {I_VCVTPD2DQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35314, 188},
+ {I_VCVTPD2DQ, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35314, 192},
+ {I_VCVTPD2DQ, 2, {XMM_L16,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35321, 188},
+ {I_VCVTPD2DQ, 2, {XMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35321, 193},
+ {I_VCVTPD2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17120, 240},
+ {I_VCVTPD2DQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17128, 240},
+ {I_VCVTPD2DQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17136, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPD2PS[] = {
+ {I_VCVTPD2PS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35328, 188},
+ {I_VCVTPD2PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35328, 192},
+ {I_VCVTPD2PS, 2, {XMM_L16,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35335, 188},
+ {I_VCVTPD2PS, 2, {XMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35335, 193},
+ {I_VCVTPD2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17144, 240},
+ {I_VCVTPD2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17152, 240},
+ {I_VCVTPD2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17160, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPS2DQ[] = {
+ {I_VCVTPS2DQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35342, 188},
+ {I_VCVTPS2DQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35349, 188},
+ {I_VCVTPS2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17264, 240},
+ {I_VCVTPS2DQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17272, 240},
+ {I_VCVTPS2DQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17280, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPS2PD[] = {
+ {I_VCVTPS2PD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35356, 188},
+ {I_VCVTPS2PD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35363, 188},
+ {I_VCVTPS2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17288, 240},
+ {I_VCVTPS2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17296, 240},
+ {I_VCVTPS2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17304, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSD2SI[] = {
+ {I_VCVTSD2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35370, 188},
+ {I_VCVTSD2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35377, 194},
+ {I_VCVTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17432, 241},
+ {I_VCVTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17440, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSD2SS[] = {
+ {I_VCVTSD2SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35384, 188},
+ {I_VCVTSD2SS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35391, 188},
+ {I_VCVTSD2SS, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+17448, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSI2SD[] = {
+ {I_VCVTSI2SD, 3, {XMM_L16,XMM_L16,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35398, 195},
+ {I_VCVTSI2SD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35405, 195},
+ {I_VCVTSI2SD, 3, {XMM_L16,XMM_L16,MEMORY|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35398, 195},
+ {I_VCVTSI2SD, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35405, 195},
+ {I_VCVTSI2SD, 3, {XMM_L16,XMM_L16,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35412, 196},
+ {I_VCVTSI2SD, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35419, 196},
+ {I_VCVTSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17472, 241},
+ {I_VCVTSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17480, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSI2SS[] = {
+ {I_VCVTSI2SS, 3, {XMM_L16,XMM_L16,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35426, 195},
+ {I_VCVTSI2SS, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35433, 195},
+ {I_VCVTSI2SS, 3, {XMM_L16,XMM_L16,MEMORY|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35426, 195},
+ {I_VCVTSI2SS, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35433, 195},
+ {I_VCVTSI2SS, 3, {XMM_L16,XMM_L16,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35440, 196},
+ {I_VCVTSI2SS, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35447, 196},
+ {I_VCVTSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17488, 241},
+ {I_VCVTSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17496, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSS2SD[] = {
+ {I_VCVTSS2SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35454, 188},
+ {I_VCVTSS2SD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35461, 188},
+ {I_VCVTSS2SD, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+17504, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSS2SI[] = {
+ {I_VCVTSS2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35468, 188},
+ {I_VCVTSS2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35475, 194},
+ {I_VCVTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17512, 241},
+ {I_VCVTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17520, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPD2DQ[] = {
+ {I_VCVTTPD2DQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35482, 188},
+ {I_VCVTTPD2DQ, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35482, 192},
+ {I_VCVTTPD2DQ, 2, {XMM_L16,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35489, 188},
+ {I_VCVTTPD2DQ, 2, {XMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35489, 193},
+ {I_VCVTTPD2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17544, 240},
+ {I_VCVTTPD2DQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17552, 240},
+ {I_VCVTTPD2DQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17560, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPS2DQ[] = {
+ {I_VCVTTPS2DQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35496, 188},
+ {I_VCVTTPS2DQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35503, 188},
+ {I_VCVTTPS2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17640, 240},
+ {I_VCVTTPS2DQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17648, 240},
+ {I_VCVTTPS2DQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17656, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTSD2SI[] = {
+ {I_VCVTTSD2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35510, 188},
+ {I_VCVTTSD2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35517, 194},
+ {I_VCVTTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17736, 241},
+ {I_VCVTTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17744, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTSS2SI[] = {
+ {I_VCVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35524, 188},
+ {I_VCVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35531, 194},
+ {I_VCVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17768, 241},
+ {I_VCVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17776, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDIVPD[] = {
+ {I_VDIVPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35538, 188},
+ {I_VDIVPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35545, 188},
+ {I_VDIVPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35552, 188},
+ {I_VDIVPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35559, 188},
+ {I_VDIVPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+17928, 240},
+ {I_VDIVPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17936, 240},
+ {I_VDIVPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+17944, 240},
+ {I_VDIVPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17952, 240},
+ {I_VDIVPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+17960, 241},
+ {I_VDIVPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17968, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDIVPS[] = {
+ {I_VDIVPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35566, 188},
+ {I_VDIVPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35573, 188},
+ {I_VDIVPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35580, 188},
+ {I_VDIVPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35587, 188},
+ {I_VDIVPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+17976, 240},
+ {I_VDIVPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17984, 240},
+ {I_VDIVPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+17992, 240},
+ {I_VDIVPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+18000, 240},
+ {I_VDIVPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18008, 241},
+ {I_VDIVPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+18016, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDIVSD[] = {
+ {I_VDIVSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35594, 188},
+ {I_VDIVSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35601, 188},
+ {I_VDIVSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18024, 241},
+ {I_VDIVSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+18032, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDIVSS[] = {
+ {I_VDIVSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35608, 188},
+ {I_VDIVSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35615, 188},
+ {I_VDIVSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18040, 241},
+ {I_VDIVSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+18048, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDPPD[] = {
+ {I_VDPPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13528, 188},
+ {I_VDPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13536, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDPPS[] = {
+ {I_VDPPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13544, 188},
+ {I_VDPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13552, 188},
+ {I_VDPPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13560, 188},
+ {I_VDPPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13568, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTF128[] = {
+ {I_VEXTRACTF128, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13576, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTPS[] = {
+ {I_VEXTRACTPS, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13584, 188},
+ {I_VEXTRACTPS, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+8479, 241},
+ {I_VEXTRACTPS, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+8479, 241},
+ {I_VEXTRACTPS, 3, {MEMORY|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+8479, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VHADDPD[] = {
+ {I_VHADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35622, 188},
+ {I_VHADDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35629, 188},
+ {I_VHADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35636, 188},
+ {I_VHADDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35643, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VHADDPS[] = {
+ {I_VHADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35650, 188},
+ {I_VHADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35657, 188},
+ {I_VHADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35664, 188},
+ {I_VHADDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35671, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VHSUBPD[] = {
+ {I_VHSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35678, 188},
+ {I_VHSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35685, 188},
+ {I_VHSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35692, 188},
+ {I_VHSUBPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35699, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VHSUBPS[] = {
+ {I_VHSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35706, 188},
+ {I_VHSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35713, 188},
+ {I_VHSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35720, 188},
+ {I_VHSUBPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35727, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTF128[] = {
+ {I_VINSERTF128, 4, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13592, 188},
+ {I_VINSERTF128, 3, {YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13600, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTPS[] = {
+ {I_VINSERTPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13608, 188},
+ {I_VINSERTPS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13616, 188},
+ {I_VINSERTPS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9172, 241},
+ {I_VINSERTPS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9181, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VLDDQU[] = {
+ {I_VLDDQU, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35734, 188},
+ {I_VLDDQU, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35741, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VLDQQU[] = {
+ {I_VLDQQU, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35741, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VLDMXCSR[] = {
+ {I_VLDMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+35748, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMASKMOVDQU[] = {
+ {I_VMASKMOVDQU, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35755, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMASKMOVPS[] = {
+ {I_VMASKMOVPS, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35762, 188},
+ {I_VMASKMOVPS, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35769, 188},
+ {I_VMASKMOVPS, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35776, 192},
+ {I_VMASKMOVPS, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35783, 193},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMASKMOVPD[] = {
+ {I_VMASKMOVPD, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35790, 188},
+ {I_VMASKMOVPD, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35797, 188},
+ {I_VMASKMOVPD, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35804, 188},
+ {I_VMASKMOVPD, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35811, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMAXPD[] = {
+ {I_VMAXPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35818, 188},
+ {I_VMAXPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35825, 188},
+ {I_VMAXPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35832, 188},
+ {I_VMAXPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35839, 188},
+ {I_VMAXPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19240, 240},
+ {I_VMAXPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19248, 240},
+ {I_VMAXPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19256, 240},
+ {I_VMAXPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19264, 240},
+ {I_VMAXPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+19272, 241},
+ {I_VMAXPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+19280, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMAXPS[] = {
+ {I_VMAXPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35846, 188},
+ {I_VMAXPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35853, 188},
+ {I_VMAXPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35860, 188},
+ {I_VMAXPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35867, 188},
+ {I_VMAXPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19288, 240},
+ {I_VMAXPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19296, 240},
+ {I_VMAXPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19304, 240},
+ {I_VMAXPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19312, 240},
+ {I_VMAXPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+19320, 241},
+ {I_VMAXPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+19328, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMAXSD[] = {
+ {I_VMAXSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35874, 188},
+ {I_VMAXSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35881, 188},
+ {I_VMAXSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19336, 241},
+ {I_VMAXSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19344, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMAXSS[] = {
+ {I_VMAXSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35888, 188},
+ {I_VMAXSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35895, 188},
+ {I_VMAXSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19352, 241},
+ {I_VMAXSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19360, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMINPD[] = {
+ {I_VMINPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35902, 188},
+ {I_VMINPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35909, 188},
+ {I_VMINPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35916, 188},
+ {I_VMINPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35923, 188},
+ {I_VMINPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19368, 240},
+ {I_VMINPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19376, 240},
+ {I_VMINPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19384, 240},
+ {I_VMINPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19392, 240},
+ {I_VMINPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+19400, 241},
+ {I_VMINPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+19408, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMINPS[] = {
+ {I_VMINPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35930, 188},
+ {I_VMINPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35937, 188},
+ {I_VMINPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35944, 188},
+ {I_VMINPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35951, 188},
+ {I_VMINPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19416, 240},
+ {I_VMINPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19424, 240},
+ {I_VMINPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19432, 240},
+ {I_VMINPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19440, 240},
+ {I_VMINPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+19448, 241},
+ {I_VMINPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+19456, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMINSD[] = {
+ {I_VMINSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35958, 188},
+ {I_VMINSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35965, 188},
+ {I_VMINSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19464, 241},
+ {I_VMINSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19472, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMINSS[] = {
+ {I_VMINSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35972, 188},
+ {I_VMINSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35979, 188},
+ {I_VMINSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19480, 241},
+ {I_VMINSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19488, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVAPD[] = {
+ {I_VMOVAPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35986, 188},
+ {I_VMOVAPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35993, 188},
+ {I_VMOVAPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36000, 188},
+ {I_VMOVAPD, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36007, 188},
+ {I_VMOVAPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19496, 240},
+ {I_VMOVAPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19504, 240},
+ {I_VMOVAPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19512, 241},
+ {I_VMOVAPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19520, 240},
+ {I_VMOVAPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19528, 240},
+ {I_VMOVAPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19536, 241},
+ {I_VMOVAPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19544, 240},
+ {I_VMOVAPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19552, 240},
+ {I_VMOVAPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19560, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVAPS[] = {
+ {I_VMOVAPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36014, 188},
+ {I_VMOVAPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36021, 188},
+ {I_VMOVAPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36028, 188},
+ {I_VMOVAPS, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36035, 188},
+ {I_VMOVAPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19568, 240},
+ {I_VMOVAPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19576, 240},
+ {I_VMOVAPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19584, 241},
+ {I_VMOVAPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19592, 240},
+ {I_VMOVAPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19600, 240},
+ {I_VMOVAPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19608, 241},
+ {I_VMOVAPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19616, 240},
+ {I_VMOVAPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19624, 240},
+ {I_VMOVAPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19632, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVD[] = {
+ {I_VMOVD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+36042, 188},
+ {I_VMOVD, 2, {RM_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36049, 188},
+ {I_VMOVD, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+19640, 241},
+ {I_VMOVD, 2, {RM_GPR|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+19648, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVQ[] = {
+ {I_VMOVQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36056, 197},
+ {I_VMOVQ, 2, {RM_XMM_L16|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36063, 197},
+ {I_VMOVQ, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36070, 196},
+ {I_VMOVQ, 2, {RM_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36077, 196},
+ {I_VMOVQ, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20192, 241},
+ {I_VMOVQ, 2, {RM_GPR|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20200, 241},
+ {I_VMOVQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20208, 241},
+ {I_VMOVQ, 2, {RM_XMM|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20216, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDDUP[] = {
+ {I_VMOVDDUP, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36084, 188},
+ {I_VMOVDDUP, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36091, 188},
+ {I_VMOVDDUP, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19656, 240},
+ {I_VMOVDDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19664, 240},
+ {I_VMOVDDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19672, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQA[] = {
+ {I_VMOVDQA, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36098, 188},
+ {I_VMOVDQA, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36105, 188},
+ {I_VMOVDQA, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36112, 188},
+ {I_VMOVDQA, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36119, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVQQA[] = {
+ {I_VMOVQQA, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36112, 188},
+ {I_VMOVQQA, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36119, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQU[] = {
+ {I_VMOVDQU, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36126, 188},
+ {I_VMOVDQU, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36133, 188},
+ {I_VMOVDQU, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36140, 188},
+ {I_VMOVDQU, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36147, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVQQU[] = {
+ {I_VMOVQQU, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36140, 188},
+ {I_VMOVQQU, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36147, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVHLPS[] = {
+ {I_VMOVHLPS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36154, 188},
+ {I_VMOVHLPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36161, 188},
+ {I_VMOVHLPS, 3, {XMMREG,XMMREG,XMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+19968, 241},
+ {I_VMOVHLPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+19976, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVHPD[] = {
+ {I_VMOVHPD, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36168, 188},
+ {I_VMOVHPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36175, 188},
+ {I_VMOVHPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36182, 188},
+ {I_VMOVHPD, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+19984, 241},
+ {I_VMOVHPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+19992, 241},
+ {I_VMOVHPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20000, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVHPS[] = {
+ {I_VMOVHPS, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36189, 188},
+ {I_VMOVHPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36196, 188},
+ {I_VMOVHPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36203, 188},
+ {I_VMOVHPS, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+20008, 241},
+ {I_VMOVHPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20016, 241},
+ {I_VMOVHPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20024, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVLHPS[] = {
+ {I_VMOVLHPS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36189, 188},
+ {I_VMOVLHPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36196, 188},
+ {I_VMOVLHPS, 3, {XMMREG,XMMREG,XMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+20032, 241},
+ {I_VMOVLHPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20040, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVLPD[] = {
+ {I_VMOVLPD, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36210, 188},
+ {I_VMOVLPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36217, 188},
+ {I_VMOVLPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36224, 188},
+ {I_VMOVLPD, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+20048, 241},
+ {I_VMOVLPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20056, 241},
+ {I_VMOVLPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20064, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVLPS[] = {
+ {I_VMOVLPS, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36154, 188},
+ {I_VMOVLPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36161, 188},
+ {I_VMOVLPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36231, 188},
+ {I_VMOVLPS, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+20072, 241},
+ {I_VMOVLPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20080, 241},
+ {I_VMOVLPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20088, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVMSKPD[] = {
+ {I_VMOVMSKPD, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36238, 194},
+ {I_VMOVMSKPD, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36238, 188},
+ {I_VMOVMSKPD, 2, {REG_GPR|BITS64,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36245, 194},
+ {I_VMOVMSKPD, 2, {REG_GPR|BITS32,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36245, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVMSKPS[] = {
+ {I_VMOVMSKPS, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36252, 194},
+ {I_VMOVMSKPS, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36252, 188},
+ {I_VMOVMSKPS, 2, {REG_GPR|BITS64,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36259, 194},
+ {I_VMOVMSKPS, 2, {REG_GPR|BITS32,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36259, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVNTDQ[] = {
+ {I_VMOVNTDQ, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36266, 188},
+ {I_VMOVNTDQ, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36273, 188},
+ {I_VMOVNTDQ, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20096, 240},
+ {I_VMOVNTDQ, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20104, 240},
+ {I_VMOVNTDQ, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20112, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVNTQQ[] = {
+ {I_VMOVNTQQ, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36273, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVNTDQA[] = {
+ {I_VMOVNTDQA, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36280, 188},
+ {I_VMOVNTDQA, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41033, 207},
+ {I_VMOVNTDQA, 2, {XMMREG,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+20120, 240},
+ {I_VMOVNTDQA, 2, {YMMREG,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+20128, 240},
+ {I_VMOVNTDQA, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+20136, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVNTPD[] = {
+ {I_VMOVNTPD, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36287, 188},
+ {I_VMOVNTPD, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36294, 188},
+ {I_VMOVNTPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20144, 240},
+ {I_VMOVNTPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20152, 240},
+ {I_VMOVNTPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20160, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVNTPS[] = {
+ {I_VMOVNTPS, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36301, 188},
+ {I_VMOVNTPS, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36308, 188},
+ {I_VMOVNTPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20168, 240},
+ {I_VMOVNTPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20176, 240},
+ {I_VMOVNTPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20184, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVSD[] = {
+ {I_VMOVSD, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36315, 188},
+ {I_VMOVSD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36322, 188},
+ {I_VMOVSD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36329, 188},
+ {I_VMOVSD, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36336, 188},
+ {I_VMOVSD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36343, 188},
+ {I_VMOVSD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36350, 188},
+ {I_VMOVSD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20224, 241},
+ {I_VMOVSD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20232, 241},
+ {I_VMOVSD, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20240, 241},
+ {I_VMOVSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20248, 241},
+ {I_VMOVSD, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20256, 241},
+ {I_VMOVSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20264, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVSHDUP[] = {
+ {I_VMOVSHDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36357, 188},
+ {I_VMOVSHDUP, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36364, 188},
+ {I_VMOVSHDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20272, 240},
+ {I_VMOVSHDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20280, 240},
+ {I_VMOVSHDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20288, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVSLDUP[] = {
+ {I_VMOVSLDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36371, 188},
+ {I_VMOVSLDUP, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36378, 188},
+ {I_VMOVSLDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20296, 240},
+ {I_VMOVSLDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20304, 240},
+ {I_VMOVSLDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20312, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVSS[] = {
+ {I_VMOVSS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36385, 188},
+ {I_VMOVSS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36392, 188},
+ {I_VMOVSS, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+36399, 188},
+ {I_VMOVSS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36406, 188},
+ {I_VMOVSS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36413, 188},
+ {I_VMOVSS, 2, {MEMORY|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36420, 188},
+ {I_VMOVSS, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20320, 241},
+ {I_VMOVSS, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20328, 241},
+ {I_VMOVSS, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20336, 241},
+ {I_VMOVSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20344, 241},
+ {I_VMOVSS, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20352, 241},
+ {I_VMOVSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20360, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVUPD[] = {
+ {I_VMOVUPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36427, 188},
+ {I_VMOVUPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36434, 188},
+ {I_VMOVUPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36441, 188},
+ {I_VMOVUPD, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36448, 188},
+ {I_VMOVUPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20368, 240},
+ {I_VMOVUPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20376, 240},
+ {I_VMOVUPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20384, 241},
+ {I_VMOVUPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20392, 240},
+ {I_VMOVUPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20400, 240},
+ {I_VMOVUPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20408, 241},
+ {I_VMOVUPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20416, 240},
+ {I_VMOVUPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20424, 240},
+ {I_VMOVUPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20432, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVUPS[] = {
+ {I_VMOVUPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36455, 188},
+ {I_VMOVUPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36462, 188},
+ {I_VMOVUPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36469, 188},
+ {I_VMOVUPS, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36476, 188},
+ {I_VMOVUPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20440, 240},
+ {I_VMOVUPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20448, 240},
+ {I_VMOVUPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20456, 241},
+ {I_VMOVUPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20464, 240},
+ {I_VMOVUPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20472, 240},
+ {I_VMOVUPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20480, 241},
+ {I_VMOVUPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20488, 240},
+ {I_VMOVUPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20496, 240},
+ {I_VMOVUPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20504, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMPSADBW[] = {
+ {I_VMPSADBW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13624, 188},
+ {I_VMPSADBW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13632, 188},
+ {I_VMPSADBW, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15808, 207},
+ {I_VMPSADBW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15816, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMULPD[] = {
+ {I_VMULPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36483, 188},
+ {I_VMULPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36490, 188},
+ {I_VMULPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36497, 188},
+ {I_VMULPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36504, 188},
+ {I_VMULPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20512, 240},
+ {I_VMULPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20520, 240},
+ {I_VMULPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20528, 240},
+ {I_VMULPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20536, 240},
+ {I_VMULPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+20544, 241},
+ {I_VMULPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+20552, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMULPS[] = {
+ {I_VMULPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36511, 188},
+ {I_VMULPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36518, 188},
+ {I_VMULPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36525, 188},
+ {I_VMULPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36532, 188},
+ {I_VMULPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20560, 240},
+ {I_VMULPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20568, 240},
+ {I_VMULPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20576, 240},
+ {I_VMULPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20584, 240},
+ {I_VMULPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+20592, 241},
+ {I_VMULPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+20600, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMULSD[] = {
+ {I_VMULSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36539, 188},
+ {I_VMULSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36546, 188},
+ {I_VMULSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+20608, 241},
+ {I_VMULSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+20616, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMULSS[] = {
+ {I_VMULSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+36553, 188},
+ {I_VMULSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+36560, 188},
+ {I_VMULSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+20624, 241},
+ {I_VMULSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+20632, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VORPD[] = {
+ {I_VORPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36567, 188},
+ {I_VORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36574, 188},
+ {I_VORPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36581, 188},
+ {I_VORPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36588, 188},
+ {I_VORPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20640, 242},
+ {I_VORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20648, 242},
+ {I_VORPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20656, 242},
+ {I_VORPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20664, 242},
+ {I_VORPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20672, 243},
+ {I_VORPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20680, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VORPS[] = {
+ {I_VORPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36595, 188},
+ {I_VORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36602, 188},
+ {I_VORPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36609, 188},
+ {I_VORPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36616, 188},
+ {I_VORPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20688, 242},
+ {I_VORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20696, 242},
+ {I_VORPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20704, 242},
+ {I_VORPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20712, 242},
+ {I_VORPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20720, 243},
+ {I_VORPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20728, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPABSB[] = {
+ {I_VPABSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36623, 188},
+ {I_VPABSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39773, 207},
+ {I_VPABSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20736, 244},
+ {I_VPABSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20744, 244},
+ {I_VPABSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20752, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPABSW[] = {
+ {I_VPABSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36630, 188},
+ {I_VPABSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39780, 207},
+ {I_VPABSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20808, 244},
+ {I_VPABSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20816, 244},
+ {I_VPABSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20824, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPABSD[] = {
+ {I_VPABSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36637, 188},
+ {I_VPABSD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39787, 207},
+ {I_VPABSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20760, 240},
+ {I_VPABSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20768, 240},
+ {I_VPABSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20776, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPACKSSWB[] = {
+ {I_VPACKSSWB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36644, 188},
+ {I_VPACKSSWB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36651, 188},
+ {I_VPACKSSWB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39794, 207},
+ {I_VPACKSSWB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39801, 207},
+ {I_VPACKSSWB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20880, 244},
+ {I_VPACKSSWB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20888, 244},
+ {I_VPACKSSWB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20896, 244},
+ {I_VPACKSSWB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20904, 244},
+ {I_VPACKSSWB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20912, 245},
+ {I_VPACKSSWB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20920, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPACKSSDW[] = {
+ {I_VPACKSSDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36658, 188},
+ {I_VPACKSSDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36665, 188},
+ {I_VPACKSSDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39808, 207},
+ {I_VPACKSSDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39815, 207},
+ {I_VPACKSSDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20832, 244},
+ {I_VPACKSSDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20840, 244},
+ {I_VPACKSSDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20848, 244},
+ {I_VPACKSSDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20856, 244},
+ {I_VPACKSSDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20864, 245},
+ {I_VPACKSSDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20872, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPACKUSWB[] = {
+ {I_VPACKUSWB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36672, 188},
+ {I_VPACKUSWB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36679, 188},
+ {I_VPACKUSWB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39836, 207},
+ {I_VPACKUSWB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39843, 207},
+ {I_VPACKUSWB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20976, 244},
+ {I_VPACKUSWB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20984, 244},
+ {I_VPACKUSWB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20992, 244},
+ {I_VPACKUSWB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21000, 244},
+ {I_VPACKUSWB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21008, 245},
+ {I_VPACKUSWB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21016, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPACKUSDW[] = {
+ {I_VPACKUSDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36686, 188},
+ {I_VPACKUSDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36693, 188},
+ {I_VPACKUSDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39822, 207},
+ {I_VPACKUSDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39829, 207},
+ {I_VPACKUSDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20928, 244},
+ {I_VPACKUSDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20936, 244},
+ {I_VPACKUSDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20944, 244},
+ {I_VPACKUSDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20952, 244},
+ {I_VPACKUSDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20960, 245},
+ {I_VPACKUSDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20968, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDB[] = {
+ {I_VPADDB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36700, 188},
+ {I_VPADDB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36707, 188},
+ {I_VPADDB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39850, 207},
+ {I_VPADDB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39857, 207},
+ {I_VPADDB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21024, 244},
+ {I_VPADDB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21032, 244},
+ {I_VPADDB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21040, 244},
+ {I_VPADDB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21048, 244},
+ {I_VPADDB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21056, 245},
+ {I_VPADDB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21064, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDW[] = {
+ {I_VPADDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36714, 188},
+ {I_VPADDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36721, 188},
+ {I_VPADDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39864, 207},
+ {I_VPADDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39871, 207},
+ {I_VPADDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21360, 244},
+ {I_VPADDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21368, 244},
+ {I_VPADDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21376, 244},
+ {I_VPADDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21384, 244},
+ {I_VPADDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21392, 245},
+ {I_VPADDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21400, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDD[] = {
+ {I_VPADDD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36728, 188},
+ {I_VPADDD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36735, 188},
+ {I_VPADDD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39878, 207},
+ {I_VPADDD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39885, 207},
+ {I_VPADDD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21072, 240},
+ {I_VPADDD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21080, 240},
+ {I_VPADDD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21088, 240},
+ {I_VPADDD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21096, 240},
+ {I_VPADDD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21104, 241},
+ {I_VPADDD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21112, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDQ[] = {
+ {I_VPADDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36742, 188},
+ {I_VPADDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36749, 188},
+ {I_VPADDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39892, 207},
+ {I_VPADDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39899, 207},
+ {I_VPADDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21120, 240},
+ {I_VPADDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21128, 240},
+ {I_VPADDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21136, 240},
+ {I_VPADDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21144, 240},
+ {I_VPADDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21152, 241},
+ {I_VPADDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21160, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDSB[] = {
+ {I_VPADDSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36756, 188},
+ {I_VPADDSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36763, 188},
+ {I_VPADDSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39906, 207},
+ {I_VPADDSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39913, 207},
+ {I_VPADDSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21168, 244},
+ {I_VPADDSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21176, 244},
+ {I_VPADDSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21184, 244},
+ {I_VPADDSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21192, 244},
+ {I_VPADDSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21200, 245},
+ {I_VPADDSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21208, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDSW[] = {
+ {I_VPADDSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36770, 188},
+ {I_VPADDSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36777, 188},
+ {I_VPADDSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39920, 207},
+ {I_VPADDSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39927, 207},
+ {I_VPADDSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21216, 244},
+ {I_VPADDSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21224, 244},
+ {I_VPADDSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21232, 244},
+ {I_VPADDSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21240, 244},
+ {I_VPADDSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21248, 245},
+ {I_VPADDSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21256, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDUSB[] = {
+ {I_VPADDUSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36784, 188},
+ {I_VPADDUSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36791, 188},
+ {I_VPADDUSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39934, 207},
+ {I_VPADDUSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39941, 207},
+ {I_VPADDUSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21264, 244},
+ {I_VPADDUSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21272, 244},
+ {I_VPADDUSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21280, 244},
+ {I_VPADDUSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21288, 244},
+ {I_VPADDUSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21296, 245},
+ {I_VPADDUSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21304, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPADDUSW[] = {
+ {I_VPADDUSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36798, 188},
+ {I_VPADDUSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36805, 188},
+ {I_VPADDUSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39948, 207},
+ {I_VPADDUSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39955, 207},
+ {I_VPADDUSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21312, 244},
+ {I_VPADDUSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21320, 244},
+ {I_VPADDUSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21328, 244},
+ {I_VPADDUSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21336, 244},
+ {I_VPADDUSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21344, 245},
+ {I_VPADDUSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21352, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPALIGNR[] = {
+ {I_VPALIGNR, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13640, 188},
+ {I_VPALIGNR, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13648, 188},
+ {I_VPALIGNR, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15824, 207},
+ {I_VPALIGNR, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15832, 207},
+ {I_VPALIGNR, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9190, 244},
+ {I_VPALIGNR, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9199, 244},
+ {I_VPALIGNR, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9208, 244},
+ {I_VPALIGNR, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9217, 244},
+ {I_VPALIGNR, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9226, 245},
+ {I_VPALIGNR, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9235, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPAND[] = {
+ {I_VPAND, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36812, 188},
+ {I_VPAND, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36819, 188},
+ {I_VPAND, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39962, 207},
+ {I_VPAND, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39969, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPANDN[] = {
+ {I_VPANDN, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36826, 188},
+ {I_VPANDN, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36833, 188},
+ {I_VPANDN, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39976, 207},
+ {I_VPANDN, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39983, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPAVGB[] = {
+ {I_VPAVGB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36840, 188},
+ {I_VPAVGB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36847, 188},
+ {I_VPAVGB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39990, 207},
+ {I_VPAVGB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39997, 207},
+ {I_VPAVGB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21600, 244},
+ {I_VPAVGB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21608, 244},
+ {I_VPAVGB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21616, 244},
+ {I_VPAVGB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21624, 244},
+ {I_VPAVGB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21632, 245},
+ {I_VPAVGB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21640, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPAVGW[] = {
+ {I_VPAVGW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36854, 188},
+ {I_VPAVGW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36861, 188},
+ {I_VPAVGW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40004, 207},
+ {I_VPAVGW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40011, 207},
+ {I_VPAVGW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21648, 244},
+ {I_VPAVGW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21656, 244},
+ {I_VPAVGW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21664, 244},
+ {I_VPAVGW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21672, 244},
+ {I_VPAVGW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21680, 245},
+ {I_VPAVGW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21688, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBLENDVB[] = {
+ {I_VPBLENDVB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13656, 188},
+ {I_VPBLENDVB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13664, 188},
+ {I_VPBLENDVB, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15840, 207},
+ {I_VPBLENDVB, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15848, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBLENDW[] = {
+ {I_VPBLENDW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13672, 188},
+ {I_VPBLENDW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13680, 188},
+ {I_VPBLENDW, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15856, 207},
+ {I_VPBLENDW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15864, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPESTRI[] = {
+ {I_VPCMPESTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13688, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPESTRM[] = {
+ {I_VPCMPESTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13696, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPISTRI[] = {
+ {I_VPCMPISTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13704, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPISTRM[] = {
+ {I_VPCMPISTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13712, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQB[] = {
+ {I_VPCMPEQB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36868, 188},
+ {I_VPCMPEQB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36875, 188},
+ {I_VPCMPEQB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40018, 207},
+ {I_VPCMPEQB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40025, 207},
+ {I_VPCMPEQB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22080, 244},
+ {I_VPCMPEQB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22088, 244},
+ {I_VPCMPEQB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22096, 245},
+ {I_VPCMPEQB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2800, 244},
+ {I_VPCMPEQB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2810, 244},
+ {I_VPCMPEQB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2820, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQW[] = {
+ {I_VPCMPEQW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36882, 188},
+ {I_VPCMPEQW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36889, 188},
+ {I_VPCMPEQW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40032, 207},
+ {I_VPCMPEQW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40039, 207},
+ {I_VPCMPEQW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22152, 244},
+ {I_VPCMPEQW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22160, 244},
+ {I_VPCMPEQW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22168, 245},
+ {I_VPCMPEQW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3010, 244},
+ {I_VPCMPEQW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3020, 244},
+ {I_VPCMPEQW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3030, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQD[] = {
+ {I_VPCMPEQD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36896, 188},
+ {I_VPCMPEQD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36903, 188},
+ {I_VPCMPEQD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40046, 207},
+ {I_VPCMPEQD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40053, 207},
+ {I_VPCMPEQD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22104, 240},
+ {I_VPCMPEQD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22112, 240},
+ {I_VPCMPEQD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22120, 241},
+ {I_VPCMPEQD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2830, 240},
+ {I_VPCMPEQD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2840, 240},
+ {I_VPCMPEQD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2850, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQQ[] = {
+ {I_VPCMPEQQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36910, 188},
+ {I_VPCMPEQQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36917, 188},
+ {I_VPCMPEQQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40060, 207},
+ {I_VPCMPEQQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40067, 207},
+ {I_VPCMPEQQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22128, 240},
+ {I_VPCMPEQQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22136, 240},
+ {I_VPCMPEQQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22144, 241},
+ {I_VPCMPEQQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2860, 240},
+ {I_VPCMPEQQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2870, 240},
+ {I_VPCMPEQQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2880, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTB[] = {
+ {I_VPCMPGTB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36924, 188},
+ {I_VPCMPGTB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36931, 188},
+ {I_VPCMPGTB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40074, 207},
+ {I_VPCMPGTB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40081, 207},
+ {I_VPCMPGTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22176, 244},
+ {I_VPCMPGTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22184, 244},
+ {I_VPCMPGTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22192, 245},
+ {I_VPCMPGTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3280, 244},
+ {I_VPCMPGTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3290, 244},
+ {I_VPCMPGTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3300, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTW[] = {
+ {I_VPCMPGTW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36938, 188},
+ {I_VPCMPGTW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36945, 188},
+ {I_VPCMPGTW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40088, 207},
+ {I_VPCMPGTW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40095, 207},
+ {I_VPCMPGTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22248, 244},
+ {I_VPCMPGTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22256, 244},
+ {I_VPCMPGTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22264, 245},
+ {I_VPCMPGTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3490, 244},
+ {I_VPCMPGTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3500, 244},
+ {I_VPCMPGTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3510, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTD[] = {
+ {I_VPCMPGTD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36952, 188},
+ {I_VPCMPGTD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36959, 188},
+ {I_VPCMPGTD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40102, 207},
+ {I_VPCMPGTD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40109, 207},
+ {I_VPCMPGTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22200, 240},
+ {I_VPCMPGTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22208, 240},
+ {I_VPCMPGTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22216, 241},
+ {I_VPCMPGTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3310, 240},
+ {I_VPCMPGTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3320, 240},
+ {I_VPCMPGTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3330, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTQ[] = {
+ {I_VPCMPGTQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36966, 188},
+ {I_VPCMPGTQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36973, 188},
+ {I_VPCMPGTQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40116, 207},
+ {I_VPCMPGTQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40123, 207},
+ {I_VPCMPGTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22224, 240},
+ {I_VPCMPGTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22232, 240},
+ {I_VPCMPGTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22240, 241},
+ {I_VPCMPGTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3340, 240},
+ {I_VPCMPGTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3350, 240},
+ {I_VPCMPGTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3360, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMILPD[] = {
+ {I_VPERMILPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36980, 188},
+ {I_VPERMILPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36987, 188},
+ {I_VPERMILPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36994, 188},
+ {I_VPERMILPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37001, 188},
+ {I_VPERMILPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13720, 188},
+ {I_VPERMILPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13728, 188},
+ {I_VPERMILPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9460, 240},
+ {I_VPERMILPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9469, 240},
+ {I_VPERMILPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9478, 241},
+ {I_VPERMILPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22640, 240},
+ {I_VPERMILPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22648, 240},
+ {I_VPERMILPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22656, 240},
+ {I_VPERMILPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22664, 240},
+ {I_VPERMILPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22672, 241},
+ {I_VPERMILPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22680, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMILPS[] = {
+ {I_VPERMILPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37008, 188},
+ {I_VPERMILPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37015, 188},
+ {I_VPERMILPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+37022, 188},
+ {I_VPERMILPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37029, 188},
+ {I_VPERMILPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13736, 188},
+ {I_VPERMILPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13744, 188},
+ {I_VPERMILPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9487, 240},
+ {I_VPERMILPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9496, 240},
+ {I_VPERMILPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9505, 241},
+ {I_VPERMILPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22688, 240},
+ {I_VPERMILPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22696, 240},
+ {I_VPERMILPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22704, 240},
+ {I_VPERMILPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22712, 240},
+ {I_VPERMILPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22720, 241},
+ {I_VPERMILPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22728, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERM2F128[] = {
+ {I_VPERM2F128, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13752, 188},
+ {I_VPERM2F128, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13760, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXTRB[] = {
+ {I_VPEXTRB, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13768, 194},
+ {I_VPEXTRB, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13768, 188},
+ {I_VPEXTRB, 3, {MEMORY|BITS8,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13768, 188},
+ {I_VPEXTRB, 3, {REG_GPR|BITS8,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ {I_VPEXTRB, 3, {REG_GPR|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ {I_VPEXTRB, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ {I_VPEXTRB, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ {I_VPEXTRB, 3, {MEMORY|BITS8,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXTRW[] = {
+ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13776, 194},
+ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13776, 188},
+ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13784, 194},
+ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13784, 188},
+ {I_VPEXTRW, 3, {MEMORY|BITS16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13784, 188},
+ {I_VPEXTRW, 3, {REG_GPR|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ {I_VPEXTRW, 3, {MEMORY|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ {I_VPEXTRW, 3, {REG_GPR|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9586, 245},
+ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9586, 245},
+ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9586, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXTRD[] = {
+ {I_VPEXTRD, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13792, 194},
+ {I_VPEXTRD, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13792, 188},
+ {I_VPEXTRD, 3, {RM_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9559, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXTRQ[] = {
+ {I_VPEXTRQ, 3, {RM_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13800, 194},
+ {I_VPEXTRQ, 3, {RM_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9568, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDW[] = {
+ {I_VPHADDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37036, 188},
+ {I_VPHADDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37043, 188},
+ {I_VPHADDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40130, 207},
+ {I_VPHADDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40137, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDD[] = {
+ {I_VPHADDD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37050, 188},
+ {I_VPHADDD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37057, 188},
+ {I_VPHADDD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40144, 207},
+ {I_VPHADDD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40151, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDSW[] = {
+ {I_VPHADDSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37064, 188},
+ {I_VPHADDSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37071, 188},
+ {I_VPHADDSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40158, 207},
+ {I_VPHADDSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40165, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHMINPOSUW[] = {
+ {I_VPHMINPOSUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37078, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHSUBW[] = {
+ {I_VPHSUBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37085, 188},
+ {I_VPHSUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37092, 188},
+ {I_VPHSUBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40172, 207},
+ {I_VPHSUBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40179, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHSUBD[] = {
+ {I_VPHSUBD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37099, 188},
+ {I_VPHSUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37106, 188},
+ {I_VPHSUBD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40186, 207},
+ {I_VPHSUBD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40193, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHSUBSW[] = {
+ {I_VPHSUBSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37113, 188},
+ {I_VPHSUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37120, 188},
+ {I_VPHSUBSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40200, 207},
+ {I_VPHSUBSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40207, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPINSRB[] = {
+ {I_VPINSRB, 4, {XMM_L16,XMM_L16,MEMORY|BITS8,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13808, 188},
+ {I_VPINSRB, 3, {XMM_L16,MEMORY|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13816, 188},
+ {I_VPINSRB, 4, {XMM_L16,XMM_L16,RM_GPR|BITS8,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13808, 188},
+ {I_VPINSRB, 3, {XMM_L16,RM_GPR|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13816, 188},
+ {I_VPINSRB, 4, {XMM_L16,XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13808, 188},
+ {I_VPINSRB, 3, {XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13816, 188},
+ {I_VPINSRB, 4, {XMMREG,XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9703, 245},
+ {I_VPINSRB, 3, {XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9712, 245},
+ {I_VPINSRB, 4, {XMMREG,XMMREG,MEMORY|BITS8,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9703, 245},
+ {I_VPINSRB, 3, {XMMREG,MEMORY|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9712, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPINSRW[] = {
+ {I_VPINSRW, 4, {XMM_L16,XMM_L16,MEMORY|BITS16,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13824, 188},
+ {I_VPINSRW, 3, {XMM_L16,MEMORY|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13832, 188},
+ {I_VPINSRW, 4, {XMM_L16,XMM_L16,RM_GPR|BITS16,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13824, 188},
+ {I_VPINSRW, 3, {XMM_L16,RM_GPR|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13832, 188},
+ {I_VPINSRW, 4, {XMM_L16,XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13824, 188},
+ {I_VPINSRW, 3, {XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13832, 188},
+ {I_VPINSRW, 4, {XMMREG,XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9757, 245},
+ {I_VPINSRW, 3, {XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9766, 245},
+ {I_VPINSRW, 4, {XMMREG,XMMREG,MEMORY|BITS16,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9757, 245},
+ {I_VPINSRW, 3, {XMMREG,MEMORY|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9766, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPINSRD[] = {
+ {I_VPINSRD, 4, {XMM_L16,XMM_L16,MEMORY|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13840, 188},
+ {I_VPINSRD, 3, {XMM_L16,MEMORY|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13848, 188},
+ {I_VPINSRD, 4, {XMM_L16,XMM_L16,RM_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13840, 188},
+ {I_VPINSRD, 3, {XMM_L16,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13848, 188},
+ {I_VPINSRD, 4, {XMMREG,XMMREG,RM_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9721, 243},
+ {I_VPINSRD, 3, {XMMREG,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9730, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPINSRQ[] = {
+ {I_VPINSRQ, 4, {XMM_L16,XMM_L16,MEMORY|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13856, 194},
+ {I_VPINSRQ, 3, {XMM_L16,MEMORY|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13864, 194},
+ {I_VPINSRQ, 4, {XMM_L16,XMM_L16,RM_GPR|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13856, 194},
+ {I_VPINSRQ, 3, {XMM_L16,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13864, 194},
+ {I_VPINSRQ, 4, {XMMREG,XMMREG,RM_GPR|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9739, 243},
+ {I_VPINSRQ, 3, {XMMREG,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9748, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADDWD[] = {
+ {I_VPMADDWD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37127, 188},
+ {I_VPMADDWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37134, 188},
+ {I_VPMADDWD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40228, 207},
+ {I_VPMADDWD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40235, 207},
+ {I_VPMADDWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23216, 244},
+ {I_VPMADDWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23224, 244},
+ {I_VPMADDWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23232, 244},
+ {I_VPMADDWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23240, 244},
+ {I_VPMADDWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23248, 245},
+ {I_VPMADDWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23256, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADDUBSW[] = {
+ {I_VPMADDUBSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37141, 188},
+ {I_VPMADDUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37148, 188},
+ {I_VPMADDUBSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40214, 207},
+ {I_VPMADDUBSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40221, 207},
+ {I_VPMADDUBSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23168, 244},
+ {I_VPMADDUBSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23176, 244},
+ {I_VPMADDUBSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23184, 244},
+ {I_VPMADDUBSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23192, 244},
+ {I_VPMADDUBSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23200, 245},
+ {I_VPMADDUBSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23208, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXSB[] = {
+ {I_VPMAXSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37155, 188},
+ {I_VPMAXSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37162, 188},
+ {I_VPMAXSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40242, 207},
+ {I_VPMAXSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40249, 207},
+ {I_VPMAXSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23264, 244},
+ {I_VPMAXSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23272, 244},
+ {I_VPMAXSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23280, 244},
+ {I_VPMAXSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23288, 244},
+ {I_VPMAXSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23296, 245},
+ {I_VPMAXSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23304, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXSW[] = {
+ {I_VPMAXSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37169, 188},
+ {I_VPMAXSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37176, 188},
+ {I_VPMAXSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40256, 207},
+ {I_VPMAXSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40263, 207},
+ {I_VPMAXSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23408, 244},
+ {I_VPMAXSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23416, 244},
+ {I_VPMAXSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23424, 244},
+ {I_VPMAXSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23432, 244},
+ {I_VPMAXSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23440, 245},
+ {I_VPMAXSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23448, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXSD[] = {
+ {I_VPMAXSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37183, 188},
+ {I_VPMAXSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37190, 188},
+ {I_VPMAXSD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40270, 207},
+ {I_VPMAXSD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40277, 207},
+ {I_VPMAXSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23312, 240},
+ {I_VPMAXSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23320, 240},
+ {I_VPMAXSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23328, 240},
+ {I_VPMAXSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23336, 240},
+ {I_VPMAXSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23344, 241},
+ {I_VPMAXSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23352, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXUB[] = {
+ {I_VPMAXUB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37197, 188},
+ {I_VPMAXUB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37204, 188},
+ {I_VPMAXUB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40284, 207},
+ {I_VPMAXUB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40291, 207},
+ {I_VPMAXUB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23456, 244},
+ {I_VPMAXUB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23464, 244},
+ {I_VPMAXUB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23472, 244},
+ {I_VPMAXUB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23480, 244},
+ {I_VPMAXUB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23488, 245},
+ {I_VPMAXUB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23496, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXUW[] = {
+ {I_VPMAXUW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37211, 188},
+ {I_VPMAXUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37218, 188},
+ {I_VPMAXUW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40298, 207},
+ {I_VPMAXUW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40305, 207},
+ {I_VPMAXUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23600, 244},
+ {I_VPMAXUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23608, 244},
+ {I_VPMAXUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23616, 244},
+ {I_VPMAXUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23624, 244},
+ {I_VPMAXUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23632, 245},
+ {I_VPMAXUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23640, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXUD[] = {
+ {I_VPMAXUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37225, 188},
+ {I_VPMAXUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37232, 188},
+ {I_VPMAXUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40312, 207},
+ {I_VPMAXUD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40319, 207},
+ {I_VPMAXUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23504, 240},
+ {I_VPMAXUD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23512, 240},
+ {I_VPMAXUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23520, 240},
+ {I_VPMAXUD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23528, 240},
+ {I_VPMAXUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23536, 241},
+ {I_VPMAXUD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23544, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINSB[] = {
+ {I_VPMINSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37239, 188},
+ {I_VPMINSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37246, 188},
+ {I_VPMINSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40326, 207},
+ {I_VPMINSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40333, 207},
+ {I_VPMINSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23648, 244},
+ {I_VPMINSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23656, 244},
+ {I_VPMINSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23664, 244},
+ {I_VPMINSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23672, 244},
+ {I_VPMINSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23680, 245},
+ {I_VPMINSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23688, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINSW[] = {
+ {I_VPMINSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37253, 188},
+ {I_VPMINSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37260, 188},
+ {I_VPMINSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40340, 207},
+ {I_VPMINSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40347, 207},
+ {I_VPMINSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23792, 244},
+ {I_VPMINSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23800, 244},
+ {I_VPMINSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23808, 244},
+ {I_VPMINSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23816, 244},
+ {I_VPMINSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23824, 245},
+ {I_VPMINSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23832, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINSD[] = {
+ {I_VPMINSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37267, 188},
+ {I_VPMINSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37274, 188},
+ {I_VPMINSD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40354, 207},
+ {I_VPMINSD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40361, 207},
+ {I_VPMINSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23696, 240},
+ {I_VPMINSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23704, 240},
+ {I_VPMINSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23712, 240},
+ {I_VPMINSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23720, 240},
+ {I_VPMINSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23728, 241},
+ {I_VPMINSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23736, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINUB[] = {
+ {I_VPMINUB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37281, 188},
+ {I_VPMINUB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37288, 188},
+ {I_VPMINUB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40368, 207},
+ {I_VPMINUB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40375, 207},
+ {I_VPMINUB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23840, 244},
+ {I_VPMINUB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23848, 244},
+ {I_VPMINUB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23856, 244},
+ {I_VPMINUB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23864, 244},
+ {I_VPMINUB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23872, 245},
+ {I_VPMINUB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23880, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINUW[] = {
+ {I_VPMINUW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37295, 188},
+ {I_VPMINUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37302, 188},
+ {I_VPMINUW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40382, 207},
+ {I_VPMINUW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40389, 207},
+ {I_VPMINUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23984, 244},
+ {I_VPMINUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23992, 244},
+ {I_VPMINUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24000, 244},
+ {I_VPMINUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24008, 244},
+ {I_VPMINUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24016, 245},
+ {I_VPMINUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24024, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINUD[] = {
+ {I_VPMINUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37309, 188},
+ {I_VPMINUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37316, 188},
+ {I_VPMINUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40396, 207},
+ {I_VPMINUD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40403, 207},
+ {I_VPMINUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23888, 240},
+ {I_VPMINUD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23896, 240},
+ {I_VPMINUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23904, 240},
+ {I_VPMINUD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23912, 240},
+ {I_VPMINUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23920, 241},
+ {I_VPMINUD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23928, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVMSKB[] = {
+ {I_VPMOVMSKB, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37323, 194},
+ {I_VPMOVMSKB, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37323, 188},
+ {I_VPMOVMSKB, 2, {REG_GPR|BITS32,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40410, 207},
+ {I_VPMOVMSKB, 2, {REG_GPR|BITS64,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40410, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSXBW[] = {
+ {I_VPMOVSXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37330, 188},
+ {I_VPMOVSXBW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40417, 207},
+ {I_VPMOVSXBW, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24776, 244},
+ {I_VPMOVSXBW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24784, 244},
+ {I_VPMOVSXBW, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24792, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSXBD[] = {
+ {I_VPMOVSXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37337, 188},
+ {I_VPMOVSXBD, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40424, 207},
+ {I_VPMOVSXBD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40424, 207},
+ {I_VPMOVSXBD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24728, 240},
+ {I_VPMOVSXBD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24736, 240},
+ {I_VPMOVSXBD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24744, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSXBQ[] = {
+ {I_VPMOVSXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37344, 188},
+ {I_VPMOVSXBQ, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+40431, 207},
+ {I_VPMOVSXBQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40431, 207},
+ {I_VPMOVSXBQ, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24752, 240},
+ {I_VPMOVSXBQ, 2, {YMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24760, 240},
+ {I_VPMOVSXBQ, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24768, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSXWD[] = {
+ {I_VPMOVSXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37351, 188},
+ {I_VPMOVSXWD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40438, 207},
+ {I_VPMOVSXWD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24824, 240},
+ {I_VPMOVSXWD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24832, 240},
+ {I_VPMOVSXWD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24840, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSXWQ[] = {
+ {I_VPMOVSXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37358, 188},
+ {I_VPMOVSXWQ, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40445, 207},
+ {I_VPMOVSXWQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40445, 207},
+ {I_VPMOVSXWQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24848, 240},
+ {I_VPMOVSXWQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24856, 240},
+ {I_VPMOVSXWQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24864, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSXDQ[] = {
+ {I_VPMOVSXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37365, 188},
+ {I_VPMOVSXDQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40452, 207},
+ {I_VPMOVSXDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24800, 240},
+ {I_VPMOVSXDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24808, 240},
+ {I_VPMOVSXDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24816, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVZXBW[] = {
+ {I_VPMOVZXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37372, 188},
+ {I_VPMOVZXBW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40459, 207},
+ {I_VPMOVZXBW, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25280, 244},
+ {I_VPMOVZXBW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25288, 244},
+ {I_VPMOVZXBW, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25296, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVZXBD[] = {
+ {I_VPMOVZXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37379, 188},
+ {I_VPMOVZXBD, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40466, 207},
+ {I_VPMOVZXBD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40466, 207},
+ {I_VPMOVZXBD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25232, 240},
+ {I_VPMOVZXBD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25240, 240},
+ {I_VPMOVZXBD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25248, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVZXBQ[] = {
+ {I_VPMOVZXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37386, 188},
+ {I_VPMOVZXBQ, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+40473, 207},
+ {I_VPMOVZXBQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40473, 207},
+ {I_VPMOVZXBQ, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25256, 240},
+ {I_VPMOVZXBQ, 2, {YMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25264, 240},
+ {I_VPMOVZXBQ, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25272, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVZXWD[] = {
+ {I_VPMOVZXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37393, 188},
+ {I_VPMOVZXWD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40480, 207},
+ {I_VPMOVZXWD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25328, 240},
+ {I_VPMOVZXWD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25336, 240},
+ {I_VPMOVZXWD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25344, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVZXWQ[] = {
+ {I_VPMOVZXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37400, 188},
+ {I_VPMOVZXWQ, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40487, 207},
+ {I_VPMOVZXWQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40487, 207},
+ {I_VPMOVZXWQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25352, 240},
+ {I_VPMOVZXWQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25360, 240},
+ {I_VPMOVZXWQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25368, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVZXDQ[] = {
+ {I_VPMOVZXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37407, 188},
+ {I_VPMOVZXDQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40494, 207},
+ {I_VPMOVZXDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25304, 240},
+ {I_VPMOVZXDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25312, 240},
+ {I_VPMOVZXDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25320, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULHUW[] = {
+ {I_VPMULHUW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37414, 188},
+ {I_VPMULHUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37421, 188},
+ {I_VPMULHUW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40529, 207},
+ {I_VPMULHUW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40536, 207},
+ {I_VPMULHUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25472, 244},
+ {I_VPMULHUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25480, 244},
+ {I_VPMULHUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25488, 244},
+ {I_VPMULHUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25496, 244},
+ {I_VPMULHUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25504, 245},
+ {I_VPMULHUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25512, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULHRSW[] = {
+ {I_VPMULHRSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37428, 188},
+ {I_VPMULHRSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37435, 188},
+ {I_VPMULHRSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40515, 207},
+ {I_VPMULHRSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40522, 207},
+ {I_VPMULHRSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25424, 244},
+ {I_VPMULHRSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25432, 244},
+ {I_VPMULHRSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25440, 244},
+ {I_VPMULHRSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25448, 244},
+ {I_VPMULHRSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25456, 245},
+ {I_VPMULHRSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25464, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULHW[] = {
+ {I_VPMULHW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37442, 188},
+ {I_VPMULHW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37449, 188},
+ {I_VPMULHW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40543, 207},
+ {I_VPMULHW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40550, 207},
+ {I_VPMULHW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25520, 244},
+ {I_VPMULHW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25528, 244},
+ {I_VPMULHW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25536, 244},
+ {I_VPMULHW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25544, 244},
+ {I_VPMULHW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25552, 245},
+ {I_VPMULHW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25560, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULLW[] = {
+ {I_VPMULLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37456, 188},
+ {I_VPMULLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37463, 188},
+ {I_VPMULLW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40557, 207},
+ {I_VPMULLW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40564, 207},
+ {I_VPMULLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25664, 244},
+ {I_VPMULLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25672, 244},
+ {I_VPMULLW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25680, 244},
+ {I_VPMULLW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25688, 244},
+ {I_VPMULLW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25696, 245},
+ {I_VPMULLW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25704, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULLD[] = {
+ {I_VPMULLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37470, 188},
+ {I_VPMULLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37477, 188},
+ {I_VPMULLD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40571, 207},
+ {I_VPMULLD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40578, 207},
+ {I_VPMULLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25568, 240},
+ {I_VPMULLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25576, 240},
+ {I_VPMULLD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25584, 240},
+ {I_VPMULLD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25592, 240},
+ {I_VPMULLD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25600, 241},
+ {I_VPMULLD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25608, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULUDQ[] = {
+ {I_VPMULUDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37484, 188},
+ {I_VPMULUDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37491, 188},
+ {I_VPMULUDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40585, 207},
+ {I_VPMULUDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40592, 207},
+ {I_VPMULUDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25760, 240},
+ {I_VPMULUDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25768, 240},
+ {I_VPMULUDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25776, 240},
+ {I_VPMULUDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25784, 240},
+ {I_VPMULUDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25792, 241},
+ {I_VPMULUDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25800, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULDQ[] = {
+ {I_VPMULDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37498, 188},
+ {I_VPMULDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37505, 188},
+ {I_VPMULDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40501, 207},
+ {I_VPMULDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40508, 207},
+ {I_VPMULDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25376, 240},
+ {I_VPMULDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25384, 240},
+ {I_VPMULDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25392, 240},
+ {I_VPMULDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25400, 240},
+ {I_VPMULDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25408, 241},
+ {I_VPMULDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25416, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPOR[] = {
+ {I_VPOR, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37512, 188},
+ {I_VPOR, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37519, 188},
+ {I_VPOR, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40599, 207},
+ {I_VPOR, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40606, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSADBW[] = {
+ {I_VPSADBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37526, 188},
+ {I_VPSADBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37533, 188},
+ {I_VPSADBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40613, 207},
+ {I_VPSADBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40620, 207},
+ {I_VPSADBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+26096, 244},
+ {I_VPSADBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+26104, 244},
+ {I_VPSADBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+26112, 244},
+ {I_VPSADBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+26120, 244},
+ {I_VPSADBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+26128, 245},
+ {I_VPSADBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+26136, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHUFB[] = {
+ {I_VPSHUFB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37540, 188},
+ {I_VPSHUFB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37547, 188},
+ {I_VPSHUFB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40627, 207},
+ {I_VPSHUFB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40634, 207},
+ {I_VPSHUFB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26144, 244},
+ {I_VPSHUFB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26152, 244},
+ {I_VPSHUFB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26160, 244},
+ {I_VPSHUFB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26168, 244},
+ {I_VPSHUFB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26176, 245},
+ {I_VPSHUFB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26184, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHUFD[] = {
+ {I_VPSHUFD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13872, 188},
+ {I_VPSHUFD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15872, 207},
+ {I_VPSHUFD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10099, 240},
+ {I_VPSHUFD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10108, 240},
+ {I_VPSHUFD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10117, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHUFHW[] = {
+ {I_VPSHUFHW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13880, 188},
+ {I_VPSHUFHW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15880, 207},
+ {I_VPSHUFHW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10126, 244},
+ {I_VPSHUFHW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10135, 244},
+ {I_VPSHUFHW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10144, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHUFLW[] = {
+ {I_VPSHUFLW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13888, 188},
+ {I_VPSHUFLW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15888, 207},
+ {I_VPSHUFLW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10153, 244},
+ {I_VPSHUFLW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10162, 244},
+ {I_VPSHUFLW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10171, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSIGNB[] = {
+ {I_VPSIGNB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37554, 188},
+ {I_VPSIGNB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37561, 188},
+ {I_VPSIGNB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40641, 207},
+ {I_VPSIGNB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40648, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSIGNW[] = {
+ {I_VPSIGNW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37568, 188},
+ {I_VPSIGNW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37575, 188},
+ {I_VPSIGNW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40655, 207},
+ {I_VPSIGNW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40662, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSIGND[] = {
+ {I_VPSIGND, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37582, 188},
+ {I_VPSIGND, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37589, 188},
+ {I_VPSIGND, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40669, 207},
+ {I_VPSIGND, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40676, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSLLDQ[] = {
+ {I_VPSLLDQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13896, 188},
+ {I_VPSLLDQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13904, 188},
+ {I_VPSLLDQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15896, 207},
+ {I_VPSLLDQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15904, 207},
+ {I_VPSLLDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10234, 244},
+ {I_VPSLLDQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10243, 244},
+ {I_VPSLLDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10252, 244},
+ {I_VPSLLDQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10261, 244},
+ {I_VPSLLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10270, 245},
+ {I_VPSLLDQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10279, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRLDQ[] = {
+ {I_VPSRLDQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13912, 188},
+ {I_VPSRLDQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13920, 188},
+ {I_VPSRLDQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15992, 207},
+ {I_VPSRLDQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16000, 207},
+ {I_VPSRLDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10612, 244},
+ {I_VPSRLDQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10621, 244},
+ {I_VPSRLDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10630, 244},
+ {I_VPSRLDQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10639, 244},
+ {I_VPSRLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10648, 245},
+ {I_VPSRLDQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10657, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSLLW[] = {
+ {I_VPSLLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37596, 188},
+ {I_VPSLLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37603, 188},
+ {I_VPSLLW, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13928, 188},
+ {I_VPSLLW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13936, 188},
+ {I_VPSLLW, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40683, 207},
+ {I_VPSLLW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40690, 207},
+ {I_VPSLLW, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15912, 207},
+ {I_VPSLLW, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15920, 207},
+ {I_VPSLLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26432, 244},
+ {I_VPSLLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26440, 244},
+ {I_VPSLLW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26448, 244},
+ {I_VPSLLW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26456, 244},
+ {I_VPSLLW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26464, 245},
+ {I_VPSLLW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26472, 245},
+ {I_VPSLLW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10342, 244},
+ {I_VPSLLW, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10351, 244},
+ {I_VPSLLW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10360, 244},
+ {I_VPSLLW, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10369, 244},
+ {I_VPSLLW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10378, 245},
+ {I_VPSLLW, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10387, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSLLD[] = {
+ {I_VPSLLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37610, 188},
+ {I_VPSLLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37617, 188},
+ {I_VPSLLD, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13944, 188},
+ {I_VPSLLD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13952, 188},
+ {I_VPSLLD, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40697, 207},
+ {I_VPSLLD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40704, 207},
+ {I_VPSLLD, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15928, 207},
+ {I_VPSLLD, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15936, 207},
+ {I_VPSLLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26192, 240},
+ {I_VPSLLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26200, 240},
+ {I_VPSLLD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26208, 240},
+ {I_VPSLLD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26216, 240},
+ {I_VPSLLD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26224, 241},
+ {I_VPSLLD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26232, 241},
+ {I_VPSLLD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10180, 240},
+ {I_VPSLLD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10189, 240},
+ {I_VPSLLD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10198, 240},
+ {I_VPSLLD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10207, 240},
+ {I_VPSLLD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10216, 241},
+ {I_VPSLLD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10225, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSLLQ[] = {
+ {I_VPSLLQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37624, 188},
+ {I_VPSLLQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37631, 188},
+ {I_VPSLLQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13960, 188},
+ {I_VPSLLQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13968, 188},
+ {I_VPSLLQ, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40711, 207},
+ {I_VPSLLQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40718, 207},
+ {I_VPSLLQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15944, 207},
+ {I_VPSLLQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15952, 207},
+ {I_VPSLLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26240, 240},
+ {I_VPSLLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26248, 240},
+ {I_VPSLLQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26256, 240},
+ {I_VPSLLQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26264, 240},
+ {I_VPSLLQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26272, 241},
+ {I_VPSLLQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26280, 241},
+ {I_VPSLLQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10288, 240},
+ {I_VPSLLQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10297, 240},
+ {I_VPSLLQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10306, 240},
+ {I_VPSLLQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10315, 240},
+ {I_VPSLLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10324, 241},
+ {I_VPSLLQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10333, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRAW[] = {
+ {I_VPSRAW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37638, 188},
+ {I_VPSRAW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37645, 188},
+ {I_VPSRAW, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13976, 188},
+ {I_VPSRAW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13984, 188},
+ {I_VPSRAW, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40725, 207},
+ {I_VPSRAW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40732, 207},
+ {I_VPSRAW, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15960, 207},
+ {I_VPSRAW, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15968, 207},
+ {I_VPSRAW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26720, 244},
+ {I_VPSRAW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26728, 244},
+ {I_VPSRAW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26736, 244},
+ {I_VPSRAW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26744, 244},
+ {I_VPSRAW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26752, 245},
+ {I_VPSRAW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26760, 245},
+ {I_VPSRAW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10504, 244},
+ {I_VPSRAW, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10513, 244},
+ {I_VPSRAW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10522, 244},
+ {I_VPSRAW, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10531, 244},
+ {I_VPSRAW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10540, 245},
+ {I_VPSRAW, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10549, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRAD[] = {
+ {I_VPSRAD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37652, 188},
+ {I_VPSRAD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37659, 188},
+ {I_VPSRAD, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13992, 188},
+ {I_VPSRAD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14000, 188},
+ {I_VPSRAD, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40739, 207},
+ {I_VPSRAD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40746, 207},
+ {I_VPSRAD, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15976, 207},
+ {I_VPSRAD, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15984, 207},
+ {I_VPSRAD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26480, 240},
+ {I_VPSRAD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26488, 240},
+ {I_VPSRAD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26496, 240},
+ {I_VPSRAD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26504, 240},
+ {I_VPSRAD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26512, 241},
+ {I_VPSRAD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26520, 241},
+ {I_VPSRAD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10396, 240},
+ {I_VPSRAD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10405, 240},
+ {I_VPSRAD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10414, 240},
+ {I_VPSRAD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10423, 240},
+ {I_VPSRAD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10432, 241},
+ {I_VPSRAD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10441, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRLW[] = {
+ {I_VPSRLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37666, 188},
+ {I_VPSRLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37673, 188},
+ {I_VPSRLW, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14008, 188},
+ {I_VPSRLW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14016, 188},
+ {I_VPSRLW, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40753, 207},
+ {I_VPSRLW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40760, 207},
+ {I_VPSRLW, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16008, 207},
+ {I_VPSRLW, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16016, 207},
+ {I_VPSRLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27008, 244},
+ {I_VPSRLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27016, 244},
+ {I_VPSRLW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27024, 244},
+ {I_VPSRLW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27032, 244},
+ {I_VPSRLW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27040, 245},
+ {I_VPSRLW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27048, 245},
+ {I_VPSRLW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10720, 244},
+ {I_VPSRLW, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10729, 244},
+ {I_VPSRLW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10738, 244},
+ {I_VPSRLW, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10747, 244},
+ {I_VPSRLW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10756, 245},
+ {I_VPSRLW, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10765, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRLD[] = {
+ {I_VPSRLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37680, 188},
+ {I_VPSRLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37687, 188},
+ {I_VPSRLD, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14024, 188},
+ {I_VPSRLD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14032, 188},
+ {I_VPSRLD, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40767, 207},
+ {I_VPSRLD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40774, 207},
+ {I_VPSRLD, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16024, 207},
+ {I_VPSRLD, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16032, 207},
+ {I_VPSRLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26768, 240},
+ {I_VPSRLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26776, 240},
+ {I_VPSRLD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26784, 240},
+ {I_VPSRLD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26792, 240},
+ {I_VPSRLD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26800, 241},
+ {I_VPSRLD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26808, 241},
+ {I_VPSRLD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10558, 240},
+ {I_VPSRLD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10567, 240},
+ {I_VPSRLD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10576, 240},
+ {I_VPSRLD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10585, 240},
+ {I_VPSRLD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10594, 241},
+ {I_VPSRLD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10603, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRLQ[] = {
+ {I_VPSRLQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37694, 188},
+ {I_VPSRLQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37701, 188},
+ {I_VPSRLQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14040, 188},
+ {I_VPSRLQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14048, 188},
+ {I_VPSRLQ, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40781, 207},
+ {I_VPSRLQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40788, 207},
+ {I_VPSRLQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16040, 207},
+ {I_VPSRLQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16048, 207},
+ {I_VPSRLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26816, 240},
+ {I_VPSRLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26824, 240},
+ {I_VPSRLQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26832, 240},
+ {I_VPSRLQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26840, 240},
+ {I_VPSRLQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26848, 241},
+ {I_VPSRLQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26856, 241},
+ {I_VPSRLQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10666, 240},
+ {I_VPSRLQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10675, 240},
+ {I_VPSRLQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10684, 240},
+ {I_VPSRLQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10693, 240},
+ {I_VPSRLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10702, 241},
+ {I_VPSRLQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10711, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTEST[] = {
+ {I_VPTEST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37708, 188},
+ {I_VPTEST, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37715, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBB[] = {
+ {I_VPSUBB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37722, 188},
+ {I_VPSUBB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37729, 188},
+ {I_VPSUBB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40795, 207},
+ {I_VPSUBB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40802, 207},
+ {I_VPSUBB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27056, 244},
+ {I_VPSUBB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27064, 244},
+ {I_VPSUBB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27072, 244},
+ {I_VPSUBB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27080, 244},
+ {I_VPSUBB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27088, 245},
+ {I_VPSUBB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27096, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBW[] = {
+ {I_VPSUBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37736, 188},
+ {I_VPSUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37743, 188},
+ {I_VPSUBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40809, 207},
+ {I_VPSUBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40816, 207},
+ {I_VPSUBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27392, 244},
+ {I_VPSUBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27400, 244},
+ {I_VPSUBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27408, 244},
+ {I_VPSUBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27416, 244},
+ {I_VPSUBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27424, 245},
+ {I_VPSUBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27432, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBD[] = {
+ {I_VPSUBD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37750, 188},
+ {I_VPSUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37757, 188},
+ {I_VPSUBD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40823, 207},
+ {I_VPSUBD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40830, 207},
+ {I_VPSUBD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27104, 240},
+ {I_VPSUBD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27112, 240},
+ {I_VPSUBD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27120, 240},
+ {I_VPSUBD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27128, 240},
+ {I_VPSUBD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27136, 241},
+ {I_VPSUBD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27144, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBQ[] = {
+ {I_VPSUBQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37764, 188},
+ {I_VPSUBQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37771, 188},
+ {I_VPSUBQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40837, 207},
+ {I_VPSUBQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40844, 207},
+ {I_VPSUBQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27152, 240},
+ {I_VPSUBQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27160, 240},
+ {I_VPSUBQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27168, 240},
+ {I_VPSUBQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27176, 240},
+ {I_VPSUBQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27184, 241},
+ {I_VPSUBQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27192, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBSB[] = {
+ {I_VPSUBSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37778, 188},
+ {I_VPSUBSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37785, 188},
+ {I_VPSUBSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40851, 207},
+ {I_VPSUBSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40858, 207},
+ {I_VPSUBSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27200, 244},
+ {I_VPSUBSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27208, 244},
+ {I_VPSUBSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27216, 244},
+ {I_VPSUBSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27224, 244},
+ {I_VPSUBSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27232, 245},
+ {I_VPSUBSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27240, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBSW[] = {
+ {I_VPSUBSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37792, 188},
+ {I_VPSUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37799, 188},
+ {I_VPSUBSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40865, 207},
+ {I_VPSUBSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40872, 207},
+ {I_VPSUBSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27248, 244},
+ {I_VPSUBSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27256, 244},
+ {I_VPSUBSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27264, 244},
+ {I_VPSUBSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27272, 244},
+ {I_VPSUBSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27280, 245},
+ {I_VPSUBSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27288, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBUSB[] = {
+ {I_VPSUBUSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37806, 188},
+ {I_VPSUBUSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37813, 188},
+ {I_VPSUBUSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40879, 207},
+ {I_VPSUBUSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40886, 207},
+ {I_VPSUBUSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27296, 244},
+ {I_VPSUBUSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27304, 244},
+ {I_VPSUBUSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27312, 244},
+ {I_VPSUBUSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27320, 244},
+ {I_VPSUBUSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27328, 245},
+ {I_VPSUBUSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27336, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSUBUSW[] = {
+ {I_VPSUBUSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37820, 188},
+ {I_VPSUBUSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37827, 188},
+ {I_VPSUBUSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40893, 207},
+ {I_VPSUBUSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40900, 207},
+ {I_VPSUBUSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27344, 244},
+ {I_VPSUBUSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27352, 244},
+ {I_VPSUBUSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27360, 244},
+ {I_VPSUBUSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27368, 244},
+ {I_VPSUBUSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27376, 245},
+ {I_VPSUBUSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27384, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKHBW[] = {
+ {I_VPUNPCKHBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37834, 188},
+ {I_VPUNPCKHBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37841, 188},
+ {I_VPUNPCKHBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40907, 207},
+ {I_VPUNPCKHBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40914, 207},
+ {I_VPUNPCKHBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27632, 244},
+ {I_VPUNPCKHBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27640, 244},
+ {I_VPUNPCKHBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27648, 244},
+ {I_VPUNPCKHBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27656, 244},
+ {I_VPUNPCKHBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27664, 245},
+ {I_VPUNPCKHBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27672, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKHWD[] = {
+ {I_VPUNPCKHWD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37848, 188},
+ {I_VPUNPCKHWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37855, 188},
+ {I_VPUNPCKHWD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40921, 207},
+ {I_VPUNPCKHWD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40928, 207},
+ {I_VPUNPCKHWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27776, 244},
+ {I_VPUNPCKHWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27784, 244},
+ {I_VPUNPCKHWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27792, 244},
+ {I_VPUNPCKHWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27800, 244},
+ {I_VPUNPCKHWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27808, 245},
+ {I_VPUNPCKHWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27816, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKHDQ[] = {
+ {I_VPUNPCKHDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37862, 188},
+ {I_VPUNPCKHDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37869, 188},
+ {I_VPUNPCKHDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40935, 207},
+ {I_VPUNPCKHDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40942, 207},
+ {I_VPUNPCKHDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27680, 240},
+ {I_VPUNPCKHDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27688, 240},
+ {I_VPUNPCKHDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27696, 240},
+ {I_VPUNPCKHDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27704, 240},
+ {I_VPUNPCKHDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27712, 241},
+ {I_VPUNPCKHDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27720, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKHQDQ[] = {
+ {I_VPUNPCKHQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37876, 188},
+ {I_VPUNPCKHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37883, 188},
+ {I_VPUNPCKHQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40949, 207},
+ {I_VPUNPCKHQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40956, 207},
+ {I_VPUNPCKHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27728, 240},
+ {I_VPUNPCKHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27736, 240},
+ {I_VPUNPCKHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27744, 240},
+ {I_VPUNPCKHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27752, 240},
+ {I_VPUNPCKHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27760, 241},
+ {I_VPUNPCKHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27768, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKLBW[] = {
+ {I_VPUNPCKLBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37890, 188},
+ {I_VPUNPCKLBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37897, 188},
+ {I_VPUNPCKLBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40963, 207},
+ {I_VPUNPCKLBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40970, 207},
+ {I_VPUNPCKLBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27824, 244},
+ {I_VPUNPCKLBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27832, 244},
+ {I_VPUNPCKLBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27840, 244},
+ {I_VPUNPCKLBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27848, 244},
+ {I_VPUNPCKLBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27856, 245},
+ {I_VPUNPCKLBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27864, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKLWD[] = {
+ {I_VPUNPCKLWD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37904, 188},
+ {I_VPUNPCKLWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37911, 188},
+ {I_VPUNPCKLWD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40977, 207},
+ {I_VPUNPCKLWD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40984, 207},
+ {I_VPUNPCKLWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27968, 244},
+ {I_VPUNPCKLWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27976, 244},
+ {I_VPUNPCKLWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27984, 244},
+ {I_VPUNPCKLWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27992, 244},
+ {I_VPUNPCKLWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28000, 245},
+ {I_VPUNPCKLWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28008, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKLDQ[] = {
+ {I_VPUNPCKLDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37918, 188},
+ {I_VPUNPCKLDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37925, 188},
+ {I_VPUNPCKLDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40991, 207},
+ {I_VPUNPCKLDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40998, 207},
+ {I_VPUNPCKLDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27872, 240},
+ {I_VPUNPCKLDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27880, 240},
+ {I_VPUNPCKLDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27888, 240},
+ {I_VPUNPCKLDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27896, 240},
+ {I_VPUNPCKLDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27904, 241},
+ {I_VPUNPCKLDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27912, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPUNPCKLQDQ[] = {
+ {I_VPUNPCKLQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37932, 188},
+ {I_VPUNPCKLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37939, 188},
+ {I_VPUNPCKLQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41005, 207},
+ {I_VPUNPCKLQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41012, 207},
+ {I_VPUNPCKLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27920, 240},
+ {I_VPUNPCKLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27928, 240},
+ {I_VPUNPCKLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27936, 240},
+ {I_VPUNPCKLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27944, 240},
+ {I_VPUNPCKLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27952, 241},
+ {I_VPUNPCKLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27960, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPXOR[] = {
+ {I_VPXOR, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37946, 188},
+ {I_VPXOR, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37953, 188},
+ {I_VPXOR, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41019, 207},
+ {I_VPXOR, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41026, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCPPS[] = {
+ {I_VRCPPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37960, 188},
+ {I_VRCPPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37967, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCPSS[] = {
+ {I_VRCPSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+37974, 188},
+ {I_VRCPSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37981, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRTPS[] = {
+ {I_VRSQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37988, 188},
+ {I_VRSQRTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37995, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRTSS[] = {
+ {I_VRSQRTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38002, 188},
+ {I_VRSQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38009, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VROUNDPD[] = {
+ {I_VROUNDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14056, 188},
+ {I_VROUNDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14064, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VROUNDPS[] = {
+ {I_VROUNDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14072, 188},
+ {I_VROUNDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14080, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VROUNDSD[] = {
+ {I_VROUNDSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14088, 188},
+ {I_VROUNDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14096, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VROUNDSS[] = {
+ {I_VROUNDSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14104, 188},
+ {I_VROUNDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14112, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSHUFPD[] = {
+ {I_VSHUFPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14120, 188},
+ {I_VSHUFPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14128, 188},
+ {I_VSHUFPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14136, 188},
+ {I_VSHUFPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14144, 188},
+ {I_VSHUFPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11476, 240},
+ {I_VSHUFPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11485, 240},
+ {I_VSHUFPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11494, 240},
+ {I_VSHUFPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11503, 240},
+ {I_VSHUFPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11512, 241},
+ {I_VSHUFPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11521, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSHUFPS[] = {
+ {I_VSHUFPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14152, 188},
+ {I_VSHUFPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14160, 188},
+ {I_VSHUFPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14168, 188},
+ {I_VSHUFPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14176, 188},
+ {I_VSHUFPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11530, 240},
+ {I_VSHUFPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11539, 240},
+ {I_VSHUFPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11548, 240},
+ {I_VSHUFPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11557, 240},
+ {I_VSHUFPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11566, 241},
+ {I_VSHUFPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11575, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSQRTPD[] = {
+ {I_VSQRTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38016, 188},
+ {I_VSQRTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38023, 188},
+ {I_VSQRTPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28496, 240},
+ {I_VSQRTPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28504, 240},
+ {I_VSQRTPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+28512, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSQRTPS[] = {
+ {I_VSQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38030, 188},
+ {I_VSQRTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38037, 188},
+ {I_VSQRTPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28520, 240},
+ {I_VSQRTPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28528, 240},
+ {I_VSQRTPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+28536, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSQRTSD[] = {
+ {I_VSQRTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38044, 188},
+ {I_VSQRTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+38051, 188},
+ {I_VSQRTSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28544, 241},
+ {I_VSQRTSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28552, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSQRTSS[] = {
+ {I_VSQRTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38058, 188},
+ {I_VSQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38065, 188},
+ {I_VSQRTSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28560, 241},
+ {I_VSQRTSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28568, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSTMXCSR[] = {
+ {I_VSTMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+38072, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSUBPD[] = {
+ {I_VSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38079, 188},
+ {I_VSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38086, 188},
+ {I_VSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38093, 188},
+ {I_VSUBPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38100, 188},
+ {I_VSUBPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28576, 240},
+ {I_VSUBPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28584, 240},
+ {I_VSUBPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28592, 240},
+ {I_VSUBPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28600, 240},
+ {I_VSUBPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+28608, 241},
+ {I_VSUBPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+28616, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSUBPS[] = {
+ {I_VSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38107, 188},
+ {I_VSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38114, 188},
+ {I_VSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38121, 188},
+ {I_VSUBPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38128, 188},
+ {I_VSUBPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28624, 240},
+ {I_VSUBPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28632, 240},
+ {I_VSUBPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28640, 240},
+ {I_VSUBPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28648, 240},
+ {I_VSUBPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+28656, 241},
+ {I_VSUBPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+28664, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSUBSD[] = {
+ {I_VSUBSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38135, 188},
+ {I_VSUBSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+38142, 188},
+ {I_VSUBSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28672, 241},
+ {I_VSUBSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28680, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSUBSS[] = {
+ {I_VSUBSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38149, 188},
+ {I_VSUBSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38156, 188},
+ {I_VSUBSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28688, 241},
+ {I_VSUBSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28696, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VTESTPS[] = {
+ {I_VTESTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38163, 188},
+ {I_VTESTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38170, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VTESTPD[] = {
+ {I_VTESTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38177, 188},
+ {I_VTESTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38184, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VUCOMISD[] = {
+ {I_VUCOMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+38191, 188},
+ {I_VUCOMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+28704, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VUCOMISS[] = {
+ {I_VUCOMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38198, 188},
+ {I_VUCOMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+28712, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VUNPCKHPD[] = {
+ {I_VUNPCKHPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38205, 188},
+ {I_VUNPCKHPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38212, 188},
+ {I_VUNPCKHPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38219, 188},
+ {I_VUNPCKHPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38226, 188},
+ {I_VUNPCKHPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28720, 240},
+ {I_VUNPCKHPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28728, 240},
+ {I_VUNPCKHPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28736, 240},
+ {I_VUNPCKHPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28744, 240},
+ {I_VUNPCKHPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28752, 241},
+ {I_VUNPCKHPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28760, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VUNPCKHPS[] = {
+ {I_VUNPCKHPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38233, 188},
+ {I_VUNPCKHPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38240, 188},
+ {I_VUNPCKHPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38247, 188},
+ {I_VUNPCKHPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38254, 188},
+ {I_VUNPCKHPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28768, 240},
+ {I_VUNPCKHPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28776, 240},
+ {I_VUNPCKHPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28784, 240},
+ {I_VUNPCKHPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28792, 240},
+ {I_VUNPCKHPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28800, 241},
+ {I_VUNPCKHPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28808, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VUNPCKLPD[] = {
+ {I_VUNPCKLPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38261, 188},
+ {I_VUNPCKLPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38268, 188},
+ {I_VUNPCKLPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38275, 188},
+ {I_VUNPCKLPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38282, 188},
+ {I_VUNPCKLPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28816, 240},
+ {I_VUNPCKLPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28824, 240},
+ {I_VUNPCKLPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28832, 240},
+ {I_VUNPCKLPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28840, 240},
+ {I_VUNPCKLPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28848, 241},
+ {I_VUNPCKLPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28856, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VUNPCKLPS[] = {
+ {I_VUNPCKLPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38289, 188},
+ {I_VUNPCKLPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38296, 188},
+ {I_VUNPCKLPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38303, 188},
+ {I_VUNPCKLPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38310, 188},
+ {I_VUNPCKLPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28864, 240},
+ {I_VUNPCKLPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28872, 240},
+ {I_VUNPCKLPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28880, 240},
+ {I_VUNPCKLPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28888, 240},
+ {I_VUNPCKLPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28896, 241},
+ {I_VUNPCKLPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28904, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VXORPD[] = {
+ {I_VXORPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38317, 188},
+ {I_VXORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38324, 188},
+ {I_VXORPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38331, 188},
+ {I_VXORPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38338, 188},
+ {I_VXORPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28912, 242},
+ {I_VXORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28920, 242},
+ {I_VXORPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28928, 242},
+ {I_VXORPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28936, 242},
+ {I_VXORPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28944, 243},
+ {I_VXORPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28952, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VXORPS[] = {
+ {I_VXORPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38345, 188},
+ {I_VXORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38352, 188},
+ {I_VXORPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38359, 188},
+ {I_VXORPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38366, 188},
+ {I_VXORPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28960, 242},
+ {I_VXORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28968, 242},
+ {I_VXORPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28976, 242},
+ {I_VXORPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28984, 242},
+ {I_VXORPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28992, 243},
+ {I_VXORPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29000, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VZEROALL[] = {
+ {I_VZEROALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45759, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VZEROUPPER[] = {
+ {I_VZEROUPPER, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45765, 188},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCLMULLQLQDQ[] = {
+ {I_PCLMULLQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7768, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCLMULHQLQDQ[] = {
+ {I_PCLMULHQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7777, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCLMULLQHQDQ[] = {
+ {I_PCLMULLQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7786, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCLMULHQHQDQ[] = {
+ {I_PCLMULHQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7795, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCLMULQDQ[] = {
+ {I_PCLMULQDQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14184, 187},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCLMULLQLQDQ[] = {
+ {I_VPCLMULLQLQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7804, 188},
+ {I_VPCLMULLQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7813, 188},
+ {I_VPCLMULLQLQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7876, 198},
+ {I_VPCLMULLQLQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7885, 198},
+ {I_VPCLMULLQLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+0, 199},
+ {I_VPCLMULLQLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+10, 199},
+ {I_VPCLMULLQLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+80, 199},
+ {I_VPCLMULLQLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+90, 199},
+ {I_VPCLMULLQLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+160, 200},
+ {I_VPCLMULLQLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+170, 200},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCLMULHQLQDQ[] = {
+ {I_VPCLMULHQLQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7822, 188},
+ {I_VPCLMULHQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7831, 188},
+ {I_VPCLMULHQLQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7894, 198},
+ {I_VPCLMULHQLQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7903, 198},
+ {I_VPCLMULHQLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+20, 199},
+ {I_VPCLMULHQLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+30, 199},
+ {I_VPCLMULHQLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+100, 199},
+ {I_VPCLMULHQLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+110, 199},
+ {I_VPCLMULHQLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+180, 200},
+ {I_VPCLMULHQLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+190, 200},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCLMULLQHQDQ[] = {
+ {I_VPCLMULLQHQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7840, 188},
+ {I_VPCLMULLQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7849, 188},
+ {I_VPCLMULLQHQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7912, 198},
+ {I_VPCLMULLQHQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7921, 198},
+ {I_VPCLMULLQHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40, 199},
+ {I_VPCLMULLQHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+50, 199},
+ {I_VPCLMULLQHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+120, 199},
+ {I_VPCLMULLQHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+130, 199},
+ {I_VPCLMULLQHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+200, 200},
+ {I_VPCLMULLQHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+210, 200},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCLMULHQHQDQ[] = {
+ {I_VPCLMULHQHQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7858, 188},
+ {I_VPCLMULHQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7867, 188},
+ {I_VPCLMULHQHQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7930, 198},
+ {I_VPCLMULHQHQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7939, 198},
+ {I_VPCLMULHQHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+60, 199},
+ {I_VPCLMULHQHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+70, 199},
+ {I_VPCLMULHQHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+140, 199},
+ {I_VPCLMULHQHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+150, 199},
+ {I_VPCLMULHQHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+220, 200},
+ {I_VPCLMULHQHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+230, 200},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCLMULQDQ[] = {
+ {I_VPCLMULQDQ, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14192, 188},
+ {I_VPCLMULQDQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14200, 188},
+ {I_VPCLMULQDQ, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14208, 198},
+ {I_VPCLMULQDQ, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14216, 198},
+ {I_VPCLMULQDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+7948, 199},
+ {I_VPCLMULQDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+7957, 199},
+ {I_VPCLMULQDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+7966, 199},
+ {I_VPCLMULQDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+7975, 199},
+ {I_VPCLMULQDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+7984, 200},
+ {I_VPCLMULQDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+7993, 200},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD132PS[] = {
+ {I_VFMADD132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38373, 201},
+ {I_VFMADD132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38380, 201},
+ {I_VFMADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18144, 240},
+ {I_VFMADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18152, 240},
+ {I_VFMADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18160, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD132PD[] = {
+ {I_VFMADD132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38387, 201},
+ {I_VFMADD132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38394, 201},
+ {I_VFMADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18120, 240},
+ {I_VFMADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18128, 240},
+ {I_VFMADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18136, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD312PS[] = {
+ {I_VFMADD312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38373, 201},
+ {I_VFMADD312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38380, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD312PD[] = {
+ {I_VFMADD312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38387, 201},
+ {I_VFMADD312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38394, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD213PS[] = {
+ {I_VFMADD213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38401, 201},
+ {I_VFMADD213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38408, 201},
+ {I_VFMADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18208, 240},
+ {I_VFMADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18216, 240},
+ {I_VFMADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18224, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD213PD[] = {
+ {I_VFMADD213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38415, 201},
+ {I_VFMADD213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38422, 201},
+ {I_VFMADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18184, 240},
+ {I_VFMADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18192, 240},
+ {I_VFMADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18200, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD123PS[] = {
+ {I_VFMADD123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38401, 201},
+ {I_VFMADD123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38408, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD123PD[] = {
+ {I_VFMADD123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38415, 201},
+ {I_VFMADD123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38422, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD231PS[] = {
+ {I_VFMADD231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38429, 201},
+ {I_VFMADD231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38436, 201},
+ {I_VFMADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18272, 240},
+ {I_VFMADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18280, 240},
+ {I_VFMADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18288, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD231PD[] = {
+ {I_VFMADD231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38443, 201},
+ {I_VFMADD231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38450, 201},
+ {I_VFMADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18248, 240},
+ {I_VFMADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18256, 240},
+ {I_VFMADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18264, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD321PS[] = {
+ {I_VFMADD321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38429, 201},
+ {I_VFMADD321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38436, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD321PD[] = {
+ {I_VFMADD321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38443, 201},
+ {I_VFMADD321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38450, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB132PS[] = {
+ {I_VFMADDSUB132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38457, 201},
+ {I_VFMADDSUB132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38464, 201},
+ {I_VFMADDSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18336, 240},
+ {I_VFMADDSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18344, 240},
+ {I_VFMADDSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18352, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB132PD[] = {
+ {I_VFMADDSUB132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38471, 201},
+ {I_VFMADDSUB132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38478, 201},
+ {I_VFMADDSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18312, 240},
+ {I_VFMADDSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18320, 240},
+ {I_VFMADDSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18328, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB312PS[] = {
+ {I_VFMADDSUB312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38457, 201},
+ {I_VFMADDSUB312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38464, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB312PD[] = {
+ {I_VFMADDSUB312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38471, 201},
+ {I_VFMADDSUB312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38478, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB213PS[] = {
+ {I_VFMADDSUB213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38485, 201},
+ {I_VFMADDSUB213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38492, 201},
+ {I_VFMADDSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18384, 240},
+ {I_VFMADDSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18392, 240},
+ {I_VFMADDSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18400, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB213PD[] = {
+ {I_VFMADDSUB213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38499, 201},
+ {I_VFMADDSUB213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38506, 201},
+ {I_VFMADDSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18360, 240},
+ {I_VFMADDSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18368, 240},
+ {I_VFMADDSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18376, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB123PS[] = {
+ {I_VFMADDSUB123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38485, 201},
+ {I_VFMADDSUB123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38492, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB123PD[] = {
+ {I_VFMADDSUB123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38499, 201},
+ {I_VFMADDSUB123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38506, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB231PS[] = {
+ {I_VFMADDSUB231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38513, 201},
+ {I_VFMADDSUB231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38520, 201},
+ {I_VFMADDSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18432, 240},
+ {I_VFMADDSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18440, 240},
+ {I_VFMADDSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18448, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB231PD[] = {
+ {I_VFMADDSUB231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38527, 201},
+ {I_VFMADDSUB231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38534, 201},
+ {I_VFMADDSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18408, 240},
+ {I_VFMADDSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18416, 240},
+ {I_VFMADDSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18424, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB321PS[] = {
+ {I_VFMADDSUB321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38513, 201},
+ {I_VFMADDSUB321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38520, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB321PD[] = {
+ {I_VFMADDSUB321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38527, 201},
+ {I_VFMADDSUB321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38534, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB132PS[] = {
+ {I_VFMSUB132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38541, 201},
+ {I_VFMSUB132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38548, 201},
+ {I_VFMSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18480, 240},
+ {I_VFMSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18488, 240},
+ {I_VFMSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18496, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB132PD[] = {
+ {I_VFMSUB132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38555, 201},
+ {I_VFMSUB132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38562, 201},
+ {I_VFMSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18456, 240},
+ {I_VFMSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18464, 240},
+ {I_VFMSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18472, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB312PS[] = {
+ {I_VFMSUB312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38541, 201},
+ {I_VFMSUB312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38548, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB312PD[] = {
+ {I_VFMSUB312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38555, 201},
+ {I_VFMSUB312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38562, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB213PS[] = {
+ {I_VFMSUB213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38569, 201},
+ {I_VFMSUB213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38576, 201},
+ {I_VFMSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18544, 240},
+ {I_VFMSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18552, 240},
+ {I_VFMSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18560, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB213PD[] = {
+ {I_VFMSUB213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38583, 201},
+ {I_VFMSUB213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38590, 201},
+ {I_VFMSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18520, 240},
+ {I_VFMSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18528, 240},
+ {I_VFMSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18536, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB123PS[] = {
+ {I_VFMSUB123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38569, 201},
+ {I_VFMSUB123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38576, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB123PD[] = {
+ {I_VFMSUB123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38583, 201},
+ {I_VFMSUB123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38590, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB231PS[] = {
+ {I_VFMSUB231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38597, 201},
+ {I_VFMSUB231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38604, 201},
+ {I_VFMSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18608, 240},
+ {I_VFMSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18616, 240},
+ {I_VFMSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18624, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB231PD[] = {
+ {I_VFMSUB231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38611, 201},
+ {I_VFMSUB231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38618, 201},
+ {I_VFMSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18584, 240},
+ {I_VFMSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18592, 240},
+ {I_VFMSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18600, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB321PS[] = {
+ {I_VFMSUB321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38597, 201},
+ {I_VFMSUB321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38604, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB321PD[] = {
+ {I_VFMSUB321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38611, 201},
+ {I_VFMSUB321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38618, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD132PS[] = {
+ {I_VFMSUBADD132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38625, 201},
+ {I_VFMSUBADD132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38632, 201},
+ {I_VFMSUBADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18672, 240},
+ {I_VFMSUBADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18680, 240},
+ {I_VFMSUBADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18688, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD132PD[] = {
+ {I_VFMSUBADD132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38639, 201},
+ {I_VFMSUBADD132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38646, 201},
+ {I_VFMSUBADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18648, 240},
+ {I_VFMSUBADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18656, 240},
+ {I_VFMSUBADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18664, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD312PS[] = {
+ {I_VFMSUBADD312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38625, 201},
+ {I_VFMSUBADD312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38632, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD312PD[] = {
+ {I_VFMSUBADD312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38639, 201},
+ {I_VFMSUBADD312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38646, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD213PS[] = {
+ {I_VFMSUBADD213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38653, 201},
+ {I_VFMSUBADD213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38660, 201},
+ {I_VFMSUBADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18720, 240},
+ {I_VFMSUBADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18728, 240},
+ {I_VFMSUBADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18736, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD213PD[] = {
+ {I_VFMSUBADD213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38667, 201},
+ {I_VFMSUBADD213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38674, 201},
+ {I_VFMSUBADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18696, 240},
+ {I_VFMSUBADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18704, 240},
+ {I_VFMSUBADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18712, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD123PS[] = {
+ {I_VFMSUBADD123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38653, 201},
+ {I_VFMSUBADD123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38660, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD123PD[] = {
+ {I_VFMSUBADD123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38667, 201},
+ {I_VFMSUBADD123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38674, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD231PS[] = {
+ {I_VFMSUBADD231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38681, 201},
+ {I_VFMSUBADD231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38688, 201},
+ {I_VFMSUBADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18768, 240},
+ {I_VFMSUBADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18776, 240},
+ {I_VFMSUBADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18784, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD231PD[] = {
+ {I_VFMSUBADD231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38695, 201},
+ {I_VFMSUBADD231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38702, 201},
+ {I_VFMSUBADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18744, 240},
+ {I_VFMSUBADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18752, 240},
+ {I_VFMSUBADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18760, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD321PS[] = {
+ {I_VFMSUBADD321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38681, 201},
+ {I_VFMSUBADD321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38688, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD321PD[] = {
+ {I_VFMSUBADD321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38695, 201},
+ {I_VFMSUBADD321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38702, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD132PS[] = {
+ {I_VFNMADD132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38709, 201},
+ {I_VFNMADD132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38716, 201},
+ {I_VFNMADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18816, 240},
+ {I_VFNMADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18824, 240},
+ {I_VFNMADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18832, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD132PD[] = {
+ {I_VFNMADD132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38723, 201},
+ {I_VFNMADD132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38730, 201},
+ {I_VFNMADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18792, 240},
+ {I_VFNMADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18800, 240},
+ {I_VFNMADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18808, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD312PS[] = {
+ {I_VFNMADD312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38709, 201},
+ {I_VFNMADD312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38716, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD312PD[] = {
+ {I_VFNMADD312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38723, 201},
+ {I_VFNMADD312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38730, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD213PS[] = {
+ {I_VFNMADD213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38737, 201},
+ {I_VFNMADD213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38744, 201},
+ {I_VFNMADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18880, 240},
+ {I_VFNMADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18888, 240},
+ {I_VFNMADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18896, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD213PD[] = {
+ {I_VFNMADD213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38751, 201},
+ {I_VFNMADD213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38758, 201},
+ {I_VFNMADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18856, 240},
+ {I_VFNMADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18864, 240},
+ {I_VFNMADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18872, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD123PS[] = {
+ {I_VFNMADD123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38737, 201},
+ {I_VFNMADD123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38744, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD123PD[] = {
+ {I_VFNMADD123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38751, 201},
+ {I_VFNMADD123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38758, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD231PS[] = {
+ {I_VFNMADD231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38765, 201},
+ {I_VFNMADD231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38772, 201},
+ {I_VFNMADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18944, 240},
+ {I_VFNMADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18952, 240},
+ {I_VFNMADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18960, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD231PD[] = {
+ {I_VFNMADD231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38779, 201},
+ {I_VFNMADD231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38786, 201},
+ {I_VFNMADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18920, 240},
+ {I_VFNMADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18928, 240},
+ {I_VFNMADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18936, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD321PS[] = {
+ {I_VFNMADD321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38765, 201},
+ {I_VFNMADD321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38772, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD321PD[] = {
+ {I_VFNMADD321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38779, 201},
+ {I_VFNMADD321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38786, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB132PS[] = {
+ {I_VFNMSUB132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38793, 201},
+ {I_VFNMSUB132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38800, 201},
+ {I_VFNMSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19008, 240},
+ {I_VFNMSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19016, 240},
+ {I_VFNMSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+19024, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB132PD[] = {
+ {I_VFNMSUB132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38807, 201},
+ {I_VFNMSUB132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38814, 201},
+ {I_VFNMSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18984, 240},
+ {I_VFNMSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18992, 240},
+ {I_VFNMSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+19000, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB312PS[] = {
+ {I_VFNMSUB312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38793, 201},
+ {I_VFNMSUB312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38800, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB312PD[] = {
+ {I_VFNMSUB312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38807, 201},
+ {I_VFNMSUB312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38814, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB213PS[] = {
+ {I_VFNMSUB213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38821, 201},
+ {I_VFNMSUB213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38828, 201},
+ {I_VFNMSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19072, 240},
+ {I_VFNMSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19080, 240},
+ {I_VFNMSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+19088, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB213PD[] = {
+ {I_VFNMSUB213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38835, 201},
+ {I_VFNMSUB213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38842, 201},
+ {I_VFNMSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19048, 240},
+ {I_VFNMSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19056, 240},
+ {I_VFNMSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+19064, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB123PS[] = {
+ {I_VFNMSUB123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38821, 201},
+ {I_VFNMSUB123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38828, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB123PD[] = {
+ {I_VFNMSUB123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38835, 201},
+ {I_VFNMSUB123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38842, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB231PS[] = {
+ {I_VFNMSUB231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38849, 201},
+ {I_VFNMSUB231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38856, 201},
+ {I_VFNMSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19136, 240},
+ {I_VFNMSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19144, 240},
+ {I_VFNMSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+19152, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB231PD[] = {
+ {I_VFNMSUB231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38863, 201},
+ {I_VFNMSUB231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38870, 201},
+ {I_VFNMSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19112, 240},
+ {I_VFNMSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19120, 240},
+ {I_VFNMSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+19128, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB321PS[] = {
+ {I_VFNMSUB321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38849, 201},
+ {I_VFNMSUB321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38856, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB321PD[] = {
+ {I_VFNMSUB321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38863, 201},
+ {I_VFNMSUB321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38870, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD132SS[] = {
+ {I_VFMADD132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38877, 201},
+ {I_VFMADD132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18176, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD132SD[] = {
+ {I_VFMADD132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38884, 201},
+ {I_VFMADD132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18168, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD312SS[] = {
+ {I_VFMADD312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38877, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD312SD[] = {
+ {I_VFMADD312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38884, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD213SS[] = {
+ {I_VFMADD213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38891, 201},
+ {I_VFMADD213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18240, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD213SD[] = {
+ {I_VFMADD213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38898, 201},
+ {I_VFMADD213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18232, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD123SS[] = {
+ {I_VFMADD123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38891, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD123SD[] = {
+ {I_VFMADD123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38898, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD231SS[] = {
+ {I_VFMADD231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38905, 201},
+ {I_VFMADD231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18304, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD231SD[] = {
+ {I_VFMADD231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38912, 201},
+ {I_VFMADD231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18296, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD321SS[] = {
+ {I_VFMADD321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38905, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD321SD[] = {
+ {I_VFMADD321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38912, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB132SS[] = {
+ {I_VFMSUB132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38919, 201},
+ {I_VFMSUB132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18512, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB132SD[] = {
+ {I_VFMSUB132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38926, 201},
+ {I_VFMSUB132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18504, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB312SS[] = {
+ {I_VFMSUB312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38919, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB312SD[] = {
+ {I_VFMSUB312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38926, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB213SS[] = {
+ {I_VFMSUB213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38933, 201},
+ {I_VFMSUB213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18576, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB213SD[] = {
+ {I_VFMSUB213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38940, 201},
+ {I_VFMSUB213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18568, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB123SS[] = {
+ {I_VFMSUB123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38933, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB123SD[] = {
+ {I_VFMSUB123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38940, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB231SS[] = {
+ {I_VFMSUB231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38947, 201},
+ {I_VFMSUB231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18640, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB231SD[] = {
+ {I_VFMSUB231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38954, 201},
+ {I_VFMSUB231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18632, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB321SS[] = {
+ {I_VFMSUB321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38947, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB321SD[] = {
+ {I_VFMSUB321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38954, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD132SS[] = {
+ {I_VFNMADD132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38961, 201},
+ {I_VFNMADD132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18848, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD132SD[] = {
+ {I_VFNMADD132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38968, 201},
+ {I_VFNMADD132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18840, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD312SS[] = {
+ {I_VFNMADD312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38961, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD312SD[] = {
+ {I_VFNMADD312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38968, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD213SS[] = {
+ {I_VFNMADD213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38975, 201},
+ {I_VFNMADD213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18912, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD213SD[] = {
+ {I_VFNMADD213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38982, 201},
+ {I_VFNMADD213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18904, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD123SS[] = {
+ {I_VFNMADD123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38975, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD123SD[] = {
+ {I_VFNMADD123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38982, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD231SS[] = {
+ {I_VFNMADD231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38989, 201},
+ {I_VFNMADD231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18976, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD231SD[] = {
+ {I_VFNMADD231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38996, 201},
+ {I_VFNMADD231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18968, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD321SS[] = {
+ {I_VFNMADD321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38989, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADD321SD[] = {
+ {I_VFNMADD321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38996, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB132SS[] = {
+ {I_VFNMSUB132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39003, 201},
+ {I_VFNMSUB132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19040, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB132SD[] = {
+ {I_VFNMSUB132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39010, 201},
+ {I_VFNMSUB132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19032, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB312SS[] = {
+ {I_VFNMSUB312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39003, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB312SD[] = {
+ {I_VFNMSUB312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39010, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB213SS[] = {
+ {I_VFNMSUB213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39017, 201},
+ {I_VFNMSUB213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19104, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB213SD[] = {
+ {I_VFNMSUB213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39024, 201},
+ {I_VFNMSUB213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19096, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB123SS[] = {
+ {I_VFNMSUB123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39017, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB123SD[] = {
+ {I_VFNMSUB123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39024, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB231SS[] = {
+ {I_VFNMSUB231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39031, 201},
+ {I_VFNMSUB231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19168, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB231SD[] = {
+ {I_VFNMSUB231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39038, 201},
+ {I_VFNMSUB231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19160, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB321SS[] = {
+ {I_VFNMSUB321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39031, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUB321SD[] = {
+ {I_VFNMSUB321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39038, 201},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDFSBASE[] = {
+ {I_RDFSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39045, 136},
+ {I_RDFSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39052, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDGSBASE[] = {
+ {I_RDGSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39059, 136},
+ {I_RDGSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39066, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDRAND[] = {
+ {I_RDRAND, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45771, 135},
+ {I_RDRAND, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45777, 135},
+ {I_RDRAND, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45783, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRFSBASE[] = {
+ {I_WRFSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39073, 136},
+ {I_WRFSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39080, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRGSBASE[] = {
+ {I_WRGSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39087, 136},
+ {I_WRGSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39094, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2PS[] = {
+ {I_VCVTPH2PS, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39101, 202},
+ {I_VCVTPH2PS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+39108, 202},
+ {I_VCVTPH2PS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17240, 240},
+ {I_VCVTPH2PS, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17248, 240},
+ {I_VCVTPH2PS, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+17256, 241},
+ {I_VCVTPH2PS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+39108, 297},
+ {I_VCVTPH2PS, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39101, 297},
+ {I_VCVTPH2PS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17240, 240},
+ {I_VCVTPH2PS, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17248, 240},
+ {I_VCVTPH2PS, 2, {ZMM_L16,RM_YMM_L16|BITS256,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+17256, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPS2PH[] = {
+ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14224, 202},
+ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14232, 202},
+ {I_VCVTPS2PH, 3, {XMMREG,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8182, 240},
+ {I_VCVTPS2PH, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8191, 240},
+ {I_VCVTPS2PH, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ {I_VCVTPS2PH, 3, {MEMORY|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8182, 240},
+ {I_VCVTPS2PH, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8191, 240},
+ {I_VCVTPS2PH, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14232, 298},
+ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14224, 298},
+ {I_VCVTPS2PH, 3, {XMMREG,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8182, 240},
+ {I_VCVTPS2PH, 3, {MEMORY|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8182, 240},
+ {I_VCVTPS2PH, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8191, 240},
+ {I_VCVTPS2PH, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8191, 240},
+ {I_VCVTPS2PH, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ {I_VCVTPS2PH, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ {I_VCVTPS2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30504, 295},
+ {I_VCVTPS2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30512, 295},
+ {I_VCVTPS2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+30520, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADCX[] = {
+ {I_ADCX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+14240, 135},
+ {I_ADCX, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+14248, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ADOX[] = {
+ {I_ADOX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+14256, 135},
+ {I_ADOX, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+14264, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDSEED[] = {
+ {I_RDSEED, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45789, 135},
+ {I_RDSEED, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45795, 135},
+ {I_RDSEED, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45801, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLAC[] = {
+ {I_CLAC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49147, 203},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STAC[] = {
+ {I_STAC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49152, 203},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSTORE[] = {
+ {I_XSTORE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49157, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XCRYPTECB[] = {
+ {I_XCRYPTECB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45807, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XCRYPTCBC[] = {
+ {I_XCRYPTCBC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45813, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XCRYPTCTR[] = {
+ {I_XCRYPTCTR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45819, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XCRYPTCFB[] = {
+ {I_XCRYPTCFB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45825, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XCRYPTOFB[] = {
+ {I_XCRYPTOFB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45831, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MONTMUL[] = {
+ {I_MONTMUL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45837, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSHA1[] = {
+ {I_XSHA1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45843, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSHA256[] = {
+ {I_XSHA256, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45849, 32},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LLWPCB[] = {
+ {I_LLWPCB, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39115, 204},
+ {I_LLWPCB, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39122, 205},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SLWPCB[] = {
+ {I_SLWPCB, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39129, 204},
+ {I_SLWPCB, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39136, 205},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LWPVAL[] = {
+ {I_LWPVAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14272, 204},
+ {I_LWPVAL, 3, {REG_GPR|BITS64,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14280, 205},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LWPINS[] = {
+ {I_LWPINS, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14288, 204},
+ {I_LWPINS, 3, {REG_GPR|BITS64,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14296, 205},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDPD[] = {
+ {I_VFMADDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14304, 206},
+ {I_VFMADDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14312, 206},
+ {I_VFMADDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14320, 206},
+ {I_VFMADDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14328, 206},
+ {I_VFMADDPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14336, 206},
+ {I_VFMADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14344, 206},
+ {I_VFMADDPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14352, 206},
+ {I_VFMADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14360, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDPS[] = {
+ {I_VFMADDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14368, 206},
+ {I_VFMADDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14376, 206},
+ {I_VFMADDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14384, 206},
+ {I_VFMADDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14392, 206},
+ {I_VFMADDPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14400, 206},
+ {I_VFMADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14408, 206},
+ {I_VFMADDPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14416, 206},
+ {I_VFMADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14424, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSD[] = {
+ {I_VFMADDSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14432, 206},
+ {I_VFMADDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14440, 206},
+ {I_VFMADDSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+14448, 206},
+ {I_VFMADDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14456, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSS[] = {
+ {I_VFMADDSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14464, 206},
+ {I_VFMADDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14472, 206},
+ {I_VFMADDSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+14480, 206},
+ {I_VFMADDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14488, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUBPD[] = {
+ {I_VFMADDSUBPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14496, 206},
+ {I_VFMADDSUBPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14504, 206},
+ {I_VFMADDSUBPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14512, 206},
+ {I_VFMADDSUBPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14520, 206},
+ {I_VFMADDSUBPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14528, 206},
+ {I_VFMADDSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14536, 206},
+ {I_VFMADDSUBPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14544, 206},
+ {I_VFMADDSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14552, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUBPS[] = {
+ {I_VFMADDSUBPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14560, 206},
+ {I_VFMADDSUBPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14568, 206},
+ {I_VFMADDSUBPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14576, 206},
+ {I_VFMADDSUBPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14584, 206},
+ {I_VFMADDSUBPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14592, 206},
+ {I_VFMADDSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14600, 206},
+ {I_VFMADDSUBPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14608, 206},
+ {I_VFMADDSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14616, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADDPD[] = {
+ {I_VFMSUBADDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14624, 206},
+ {I_VFMSUBADDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14632, 206},
+ {I_VFMSUBADDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14640, 206},
+ {I_VFMSUBADDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14648, 206},
+ {I_VFMSUBADDPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14656, 206},
+ {I_VFMSUBADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14664, 206},
+ {I_VFMSUBADDPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14672, 206},
+ {I_VFMSUBADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14680, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADDPS[] = {
+ {I_VFMSUBADDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14688, 206},
+ {I_VFMSUBADDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14696, 206},
+ {I_VFMSUBADDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14704, 206},
+ {I_VFMSUBADDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14712, 206},
+ {I_VFMSUBADDPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14720, 206},
+ {I_VFMSUBADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14728, 206},
+ {I_VFMSUBADDPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14736, 206},
+ {I_VFMSUBADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14744, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBPD[] = {
+ {I_VFMSUBPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14752, 206},
+ {I_VFMSUBPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14760, 206},
+ {I_VFMSUBPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14768, 206},
+ {I_VFMSUBPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14776, 206},
+ {I_VFMSUBPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14784, 206},
+ {I_VFMSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14792, 206},
+ {I_VFMSUBPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14800, 206},
+ {I_VFMSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14808, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBPS[] = {
+ {I_VFMSUBPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14816, 206},
+ {I_VFMSUBPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14824, 206},
+ {I_VFMSUBPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14832, 206},
+ {I_VFMSUBPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14840, 206},
+ {I_VFMSUBPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14848, 206},
+ {I_VFMSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14856, 206},
+ {I_VFMSUBPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14864, 206},
+ {I_VFMSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14872, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBSD[] = {
+ {I_VFMSUBSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14880, 206},
+ {I_VFMSUBSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14888, 206},
+ {I_VFMSUBSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+14896, 206},
+ {I_VFMSUBSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14904, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBSS[] = {
+ {I_VFMSUBSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14912, 206},
+ {I_VFMSUBSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14920, 206},
+ {I_VFMSUBSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+14928, 206},
+ {I_VFMSUBSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14936, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADDPD[] = {
+ {I_VFNMADDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14944, 206},
+ {I_VFNMADDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14952, 206},
+ {I_VFNMADDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14960, 206},
+ {I_VFNMADDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14968, 206},
+ {I_VFNMADDPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14976, 206},
+ {I_VFNMADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14984, 206},
+ {I_VFNMADDPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14992, 206},
+ {I_VFNMADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15000, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADDPS[] = {
+ {I_VFNMADDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15008, 206},
+ {I_VFNMADDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15016, 206},
+ {I_VFNMADDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15024, 206},
+ {I_VFNMADDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15032, 206},
+ {I_VFNMADDPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15040, 206},
+ {I_VFNMADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15048, 206},
+ {I_VFNMADDPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15056, 206},
+ {I_VFNMADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15064, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADDSD[] = {
+ {I_VFNMADDSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15072, 206},
+ {I_VFNMADDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15080, 206},
+ {I_VFNMADDSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+15088, 206},
+ {I_VFNMADDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15096, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMADDSS[] = {
+ {I_VFNMADDSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15104, 206},
+ {I_VFNMADDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15112, 206},
+ {I_VFNMADDSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+15120, 206},
+ {I_VFNMADDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15128, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUBPD[] = {
+ {I_VFNMSUBPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15136, 206},
+ {I_VFNMSUBPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15144, 206},
+ {I_VFNMSUBPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15152, 206},
+ {I_VFNMSUBPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15160, 206},
+ {I_VFNMSUBPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15168, 206},
+ {I_VFNMSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15176, 206},
+ {I_VFNMSUBPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15184, 206},
+ {I_VFNMSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15192, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUBPS[] = {
+ {I_VFNMSUBPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15200, 206},
+ {I_VFNMSUBPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15208, 206},
+ {I_VFNMSUBPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15216, 206},
+ {I_VFNMSUBPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15224, 206},
+ {I_VFNMSUBPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15232, 206},
+ {I_VFNMSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15240, 206},
+ {I_VFNMSUBPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15248, 206},
+ {I_VFNMSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15256, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUBSD[] = {
+ {I_VFNMSUBSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15264, 206},
+ {I_VFNMSUBSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15272, 206},
+ {I_VFNMSUBSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+15280, 206},
+ {I_VFNMSUBSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15288, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFNMSUBSS[] = {
+ {I_VFNMSUBSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15296, 206},
+ {I_VFNMSUBSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15304, 206},
+ {I_VFNMSUBSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+15312, 206},
+ {I_VFNMSUBSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15320, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFRCZPD[] = {
+ {I_VFRCZPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39143, 206},
+ {I_VFRCZPD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39150, 206},
+ {I_VFRCZPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39157, 206},
+ {I_VFRCZPD, 1, {YMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39164, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFRCZPS[] = {
+ {I_VFRCZPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39171, 206},
+ {I_VFRCZPS, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39178, 206},
+ {I_VFRCZPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39185, 206},
+ {I_VFRCZPS, 1, {YMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39192, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFRCZSD[] = {
+ {I_VFRCZSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+39199, 206},
+ {I_VFRCZSD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39206, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFRCZSS[] = {
+ {I_VFRCZSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+39213, 206},
+ {I_VFRCZSS, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39220, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMOV[] = {
+ {I_VPCMOV, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15328, 206},
+ {I_VPCMOV, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15336, 206},
+ {I_VPCMOV, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15344, 206},
+ {I_VPCMOV, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15352, 206},
+ {I_VPCMOV, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15360, 206},
+ {I_VPCMOV, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15368, 206},
+ {I_VPCMOV, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15376, 206},
+ {I_VPCMOV, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15384, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMB[] = {
+ {I_VPCOMB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15392, 206},
+ {I_VPCOMB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15400, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMD[] = {
+ {I_VPCOMD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15408, 206},
+ {I_VPCOMD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15416, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMQ[] = {
+ {I_VPCOMQ, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15424, 206},
+ {I_VPCOMQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15432, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMUB[] = {
+ {I_VPCOMUB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15440, 206},
+ {I_VPCOMUB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15448, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMUD[] = {
+ {I_VPCOMUD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15456, 206},
+ {I_VPCOMUD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15464, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMUQ[] = {
+ {I_VPCOMUQ, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15472, 206},
+ {I_VPCOMUQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15480, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMUW[] = {
+ {I_VPCOMUW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15488, 206},
+ {I_VPCOMUW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15496, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMW[] = {
+ {I_VPCOMW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15504, 206},
+ {I_VPCOMW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15512, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDBD[] = {
+ {I_VPHADDBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39227, 206},
+ {I_VPHADDBD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39234, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDBQ[] = {
+ {I_VPHADDBQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39241, 206},
+ {I_VPHADDBQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39248, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDBW[] = {
+ {I_VPHADDBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39255, 206},
+ {I_VPHADDBW, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39262, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDDQ[] = {
+ {I_VPHADDDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39269, 206},
+ {I_VPHADDDQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39276, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDUBD[] = {
+ {I_VPHADDUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39283, 206},
+ {I_VPHADDUBD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39290, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDUBQ[] = {
+ {I_VPHADDUBQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39297, 206},
+ {I_VPHADDUBQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39304, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDUBW[] = {
+ {I_VPHADDUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39311, 206},
+ {I_VPHADDUBW, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39318, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDUDQ[] = {
+ {I_VPHADDUDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39325, 206},
+ {I_VPHADDUDQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39332, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDUWD[] = {
+ {I_VPHADDUWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39339, 206},
+ {I_VPHADDUWD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39346, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDUWQ[] = {
+ {I_VPHADDUWQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39353, 206},
+ {I_VPHADDUWQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39360, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDWD[] = {
+ {I_VPHADDWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39367, 206},
+ {I_VPHADDWD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39374, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHADDWQ[] = {
+ {I_VPHADDWQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39381, 206},
+ {I_VPHADDWQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39388, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHSUBBW[] = {
+ {I_VPHSUBBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39395, 206},
+ {I_VPHSUBBW, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39402, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHSUBDQ[] = {
+ {I_VPHSUBDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39409, 206},
+ {I_VPHSUBDQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39416, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPHSUBWD[] = {
+ {I_VPHSUBWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39423, 206},
+ {I_VPHSUBWD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39430, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSDD[] = {
+ {I_VPMACSDD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15520, 206},
+ {I_VPMACSDD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15528, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSDQH[] = {
+ {I_VPMACSDQH, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15536, 206},
+ {I_VPMACSDQH, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15544, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSDQL[] = {
+ {I_VPMACSDQL, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15552, 206},
+ {I_VPMACSDQL, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15560, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSSDD[] = {
+ {I_VPMACSSDD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15568, 206},
+ {I_VPMACSSDD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15576, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSSDQH[] = {
+ {I_VPMACSSDQH, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15584, 206},
+ {I_VPMACSSDQH, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15592, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSSDQL[] = {
+ {I_VPMACSSDQL, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15600, 206},
+ {I_VPMACSSDQL, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15608, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSSWD[] = {
+ {I_VPMACSSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15616, 206},
+ {I_VPMACSSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15624, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSSWW[] = {
+ {I_VPMACSSWW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15632, 206},
+ {I_VPMACSSWW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15640, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSWD[] = {
+ {I_VPMACSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15648, 206},
+ {I_VPMACSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15656, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMACSWW[] = {
+ {I_VPMACSWW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15664, 206},
+ {I_VPMACSWW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15672, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADCSSWD[] = {
+ {I_VPMADCSSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15680, 206},
+ {I_VPMADCSSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15688, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADCSWD[] = {
+ {I_VPMADCSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15696, 206},
+ {I_VPMADCSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15704, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPPERM[] = {
+ {I_VPPERM, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15712, 206},
+ {I_VPPERM, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15720, 206},
+ {I_VPPERM, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15728, 206},
+ {I_VPPERM, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15736, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROTB[] = {
+ {I_VPROTB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39437, 206},
+ {I_VPROTB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39444, 206},
+ {I_VPROTB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39451, 206},
+ {I_VPROTB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39458, 206},
+ {I_VPROTB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15744, 206},
+ {I_VPROTB, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15752, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROTD[] = {
+ {I_VPROTD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39465, 206},
+ {I_VPROTD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39472, 206},
+ {I_VPROTD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39479, 206},
+ {I_VPROTD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39486, 206},
+ {I_VPROTD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15760, 206},
+ {I_VPROTD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15768, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROTQ[] = {
+ {I_VPROTQ, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39493, 206},
+ {I_VPROTQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39500, 206},
+ {I_VPROTQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39507, 206},
+ {I_VPROTQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39514, 206},
+ {I_VPROTQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15776, 206},
+ {I_VPROTQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15784, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROTW[] = {
+ {I_VPROTW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39521, 206},
+ {I_VPROTW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39528, 206},
+ {I_VPROTW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39535, 206},
+ {I_VPROTW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39542, 206},
+ {I_VPROTW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15792, 206},
+ {I_VPROTW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15800, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHAB[] = {
+ {I_VPSHAB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39549, 206},
+ {I_VPSHAB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39556, 206},
+ {I_VPSHAB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39563, 206},
+ {I_VPSHAB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39570, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHAD[] = {
+ {I_VPSHAD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39577, 206},
+ {I_VPSHAD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39584, 206},
+ {I_VPSHAD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39591, 206},
+ {I_VPSHAD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39598, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHAQ[] = {
+ {I_VPSHAQ, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39605, 206},
+ {I_VPSHAQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39612, 206},
+ {I_VPSHAQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39619, 206},
+ {I_VPSHAQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39626, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHAW[] = {
+ {I_VPSHAW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39633, 206},
+ {I_VPSHAW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39640, 206},
+ {I_VPSHAW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39647, 206},
+ {I_VPSHAW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39654, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLB[] = {
+ {I_VPSHLB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39661, 206},
+ {I_VPSHLB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39668, 206},
+ {I_VPSHLB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39675, 206},
+ {I_VPSHLB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39682, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLD[] = {
+ {I_VPSHLD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39689, 206},
+ {I_VPSHLD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39696, 206},
+ {I_VPSHLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39703, 206},
+ {I_VPSHLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39710, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLQ[] = {
+ {I_VPSHLQ, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39717, 206},
+ {I_VPSHLQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39724, 206},
+ {I_VPSHLQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39731, 206},
+ {I_VPSHLQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39738, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLW[] = {
+ {I_VPSHLW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39745, 206},
+ {I_VPSHLW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39752, 206},
+ {I_VPSHLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39759, 206},
+ {I_VPSHLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39766, 206},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTI128[] = {
+ {I_VBROADCASTI128, 2, {YMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41040, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBLENDD[] = {
+ {I_VPBLENDD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16056, 207},
+ {I_VPBLENDD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16064, 207},
+ {I_VPBLENDD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16072, 207},
+ {I_VPBLENDD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16080, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBROADCASTB[] = {
+ {I_VPBROADCASTB, 2, {XMM_L16,MEMORY|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+41047, 207},
+ {I_VPBROADCASTB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41047, 207},
+ {I_VPBROADCASTB, 2, {YMM_L16,MEMORY|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+41054, 207},
+ {I_VPBROADCASTB, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41054, 207},
+ {I_VPBROADCASTB, 2, {XMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21792, 244},
+ {I_VPBROADCASTB, 2, {YMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21800, 244},
+ {I_VPBROADCASTB, 2, {ZMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21808, 245},
+ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBROADCASTW[] = {
+ {I_VPBROADCASTW, 2, {XMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41061, 207},
+ {I_VPBROADCASTW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41061, 207},
+ {I_VPBROADCASTW, 2, {YMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41068, 207},
+ {I_VPBROADCASTW, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41068, 207},
+ {I_VPBROADCASTW, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22032, 244},
+ {I_VPBROADCASTW, 2, {YMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22040, 244},
+ {I_VPBROADCASTW, 2, {ZMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22048, 245},
+ {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22056, 244},
+ {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22056, 244},
+ {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22056, 244},
+ {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22064, 244},
+ {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22064, 244},
+ {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22064, 244},
+ {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22072, 245},
+ {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22072, 245},
+ {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22072, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBROADCASTD[] = {
+ {I_VPBROADCASTD, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41075, 207},
+ {I_VPBROADCASTD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41075, 207},
+ {I_VPBROADCASTD, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41082, 207},
+ {I_VPBROADCASTD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41082, 207},
+ {I_VPBROADCASTD, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21840, 240},
+ {I_VPBROADCASTD, 2, {YMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21848, 240},
+ {I_VPBROADCASTD, 2, {ZMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21856, 241},
+ {I_VPBROADCASTD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21864, 240},
+ {I_VPBROADCASTD, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21872, 240},
+ {I_VPBROADCASTD, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21880, 241},
+ {I_VPBROADCASTD, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21888, 240},
+ {I_VPBROADCASTD, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21896, 240},
+ {I_VPBROADCASTD, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21904, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBROADCASTQ[] = {
+ {I_VPBROADCASTQ, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41089, 207},
+ {I_VPBROADCASTQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41089, 207},
+ {I_VPBROADCASTQ, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41096, 207},
+ {I_VPBROADCASTQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41096, 207},
+ {I_VPBROADCASTQ, 2, {XMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21960, 240},
+ {I_VPBROADCASTQ, 2, {YMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21968, 240},
+ {I_VPBROADCASTQ, 2, {ZMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21976, 241},
+ {I_VPBROADCASTQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21984, 240},
+ {I_VPBROADCASTQ, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21992, 240},
+ {I_VPBROADCASTQ, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22000, 241},
+ {I_VPBROADCASTQ, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22008, 240},
+ {I_VPBROADCASTQ, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22016, 240},
+ {I_VPBROADCASTQ, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22024, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMD[] = {
+ {I_VPERMD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41103, 207},
+ {I_VPERMD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41110, 207},
+ {I_VPERMD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22464, 240},
+ {I_VPERMD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22472, 240},
+ {I_VPERMD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22480, 241},
+ {I_VPERMD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22488, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMPD[] = {
+ {I_VPERMPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16088, 207},
+ {I_VPERMPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9514, 240},
+ {I_VPERMPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9523, 241},
+ {I_VPERMPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22736, 240},
+ {I_VPERMPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22744, 240},
+ {I_VPERMPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22752, 241},
+ {I_VPERMPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22760, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMPS[] = {
+ {I_VPERMPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41117, 207},
+ {I_VPERMPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41124, 207},
+ {I_VPERMPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22768, 240},
+ {I_VPERMPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22776, 240},
+ {I_VPERMPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22784, 241},
+ {I_VPERMPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22792, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMQ[] = {
+ {I_VPERMQ, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16096, 207},
+ {I_VPERMQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9532, 240},
+ {I_VPERMQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9541, 241},
+ {I_VPERMQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22800, 240},
+ {I_VPERMQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22808, 240},
+ {I_VPERMQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22816, 241},
+ {I_VPERMQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22824, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERM2I128[] = {
+ {I_VPERM2I128, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16104, 207},
+ {I_VPERM2I128, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16112, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTI128[] = {
+ {I_VEXTRACTI128, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16120, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTI128[] = {
+ {I_VINSERTI128, 4, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16128, 207},
+ {I_VINSERTI128, 3, {YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16136, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMASKMOVD[] = {
+ {I_VPMASKMOVD, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41131, 207},
+ {I_VPMASKMOVD, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41138, 207},
+ {I_VPMASKMOVD, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41145, 207},
+ {I_VPMASKMOVD, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41152, 207},
+ {I_VPMASKMOVD, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41187, 207},
+ {I_VPMASKMOVD, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41194, 207},
+ {I_VPMASKMOVD, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41201, 207},
+ {I_VPMASKMOVD, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41208, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMASKMOVQ[] = {
+ {I_VPMASKMOVQ, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41159, 207},
+ {I_VPMASKMOVQ, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41166, 207},
+ {I_VPMASKMOVQ, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41173, 207},
+ {I_VPMASKMOVQ, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41180, 207},
+ {I_VPMASKMOVQ, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41215, 207},
+ {I_VPMASKMOVQ, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41222, 207},
+ {I_VPMASKMOVQ, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41229, 207},
+ {I_VPMASKMOVQ, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41236, 207},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSLLVD[] = {
+ {I_VPSLLVD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41243, 207},
+ {I_VPSLLVD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41250, 207},
+ {I_VPSLLVD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41271, 207},
+ {I_VPSLLVD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41278, 207},
+ {I_VPSLLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26288, 240},
+ {I_VPSLLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26296, 240},
+ {I_VPSLLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26304, 240},
+ {I_VPSLLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26312, 240},
+ {I_VPSLLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26320, 241},
+ {I_VPSLLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26328, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSLLVQ[] = {
+ {I_VPSLLVQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41257, 207},
+ {I_VPSLLVQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41264, 207},
+ {I_VPSLLVQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41285, 207},
+ {I_VPSLLVQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41292, 207},
+ {I_VPSLLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26336, 240},
+ {I_VPSLLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26344, 240},
+ {I_VPSLLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26352, 240},
+ {I_VPSLLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26360, 240},
+ {I_VPSLLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26368, 241},
+ {I_VPSLLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26376, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRAVD[] = {
+ {I_VPSRAVD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41299, 207},
+ {I_VPSRAVD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41306, 207},
+ {I_VPSRAVD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41313, 207},
+ {I_VPSRAVD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41320, 207},
+ {I_VPSRAVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26576, 240},
+ {I_VPSRAVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26584, 240},
+ {I_VPSRAVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26592, 240},
+ {I_VPSRAVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26600, 240},
+ {I_VPSRAVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26608, 241},
+ {I_VPSRAVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26616, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRLVD[] = {
+ {I_VPSRLVD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41327, 207},
+ {I_VPSRLVD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41334, 207},
+ {I_VPSRLVD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41355, 207},
+ {I_VPSRLVD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41362, 207},
+ {I_VPSRLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26864, 240},
+ {I_VPSRLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26872, 240},
+ {I_VPSRLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26880, 240},
+ {I_VPSRLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26888, 240},
+ {I_VPSRLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26896, 241},
+ {I_VPSRLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26904, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRLVQ[] = {
+ {I_VPSRLVQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41341, 207},
+ {I_VPSRLVQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41348, 207},
+ {I_VPSRLVQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41369, 207},
+ {I_VPSRLVQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41376, 207},
+ {I_VPSRLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26912, 240},
+ {I_VPSRLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26920, 240},
+ {I_VPSRLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26928, 240},
+ {I_VPSRLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26936, 240},
+ {I_VPSRLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26944, 241},
+ {I_VPSRLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26952, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERDPD[] = {
+ {I_VGATHERDPD, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16144, 207},
+ {I_VGATHERDPD, 3, {YMM_L16,XMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16160, 207},
+ {I_VGATHERDPD, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8704, 240},
+ {I_VGATHERDPD, 2, {YMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8713, 240},
+ {I_VGATHERDPD, 2, {ZMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8722, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERQPD[] = {
+ {I_VGATHERQPD, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16152, 207},
+ {I_VGATHERQPD, 3, {YMM_L16,YMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16168, 207},
+ {I_VGATHERQPD, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8830, 240},
+ {I_VGATHERQPD, 2, {YMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8839, 240},
+ {I_VGATHERQPD, 2, {ZMMREG,ZMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8848, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERDPS[] = {
+ {I_VGATHERDPS, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16176, 207},
+ {I_VGATHERDPS, 3, {YMM_L16,YMEM|BITS32,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16192, 207},
+ {I_VGATHERDPS, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8731, 240},
+ {I_VGATHERDPS, 2, {YMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8740, 240},
+ {I_VGATHERDPS, 2, {ZMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8749, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERQPS[] = {
+ {I_VGATHERQPS, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16184, 207},
+ {I_VGATHERQPS, 3, {XMM_L16,YMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16200, 207},
+ {I_VGATHERQPS, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8857, 240},
+ {I_VGATHERQPS, 2, {XMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8866, 240},
+ {I_VGATHERQPS, 2, {YMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8875, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPGATHERDD[] = {
+ {I_VPGATHERDD, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16208, 207},
+ {I_VPGATHERDD, 3, {YMM_L16,YMEM|BITS32,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16224, 207},
+ {I_VPGATHERDD, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9595, 240},
+ {I_VPGATHERDD, 2, {YMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9604, 240},
+ {I_VPGATHERDD, 2, {ZMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9613, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPGATHERQD[] = {
+ {I_VPGATHERQD, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16216, 207},
+ {I_VPGATHERQD, 3, {XMM_L16,YMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16232, 207},
+ {I_VPGATHERQD, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9649, 240},
+ {I_VPGATHERQD, 2, {XMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9658, 240},
+ {I_VPGATHERQD, 2, {YMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9667, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPGATHERDQ[] = {
+ {I_VPGATHERDQ, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16240, 207},
+ {I_VPGATHERDQ, 3, {YMM_L16,XMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16256, 207},
+ {I_VPGATHERDQ, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9622, 240},
+ {I_VPGATHERDQ, 2, {YMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9631, 240},
+ {I_VPGATHERDQ, 2, {ZMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9640, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPGATHERQQ[] = {
+ {I_VPGATHERQQ, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16248, 207},
+ {I_VPGATHERQQ, 3, {YMM_L16,YMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16264, 207},
+ {I_VPGATHERQQ, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9676, 240},
+ {I_VPGATHERQQ, 2, {YMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9685, 240},
+ {I_VPGATHERQQ, 2, {ZMMREG,ZMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9694, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XABORT[] = {
+ {I_XABORT, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49162, 208},
+ {I_XABORT, 1, {IMMEDIATE|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49162, 208},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XBEGIN[] = {
+ {I_XBEGIN, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45855, 208},
+ {I_XBEGIN, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45855, 208},
+ {I_XBEGIN, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45861, 209},
+ {I_XBEGIN, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45861, 209},
+ {I_XBEGIN, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45867, 209},
+ {I_XBEGIN, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45867, 209},
+ {I_XBEGIN, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45873, 210},
+ {I_XBEGIN, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45873, 210},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XEND[] = {
+ {I_XEND, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49167, 208},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XTEST[] = {
+ {I_XTEST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49172, 211},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ANDN[] = {
+ {I_ANDN, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41383, 212},
+ {I_ANDN, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41390, 213},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BEXTR[] = {
+ {I_BEXTR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41397, 212},
+ {I_BEXTR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41404, 213},
+ {I_BEXTR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16272, 214},
+ {I_BEXTR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16280, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLCI[] = {
+ {I_BLCI, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41411, 214},
+ {I_BLCI, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41418, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLCIC[] = {
+ {I_BLCIC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41425, 214},
+ {I_BLCIC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41432, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLSI[] = {
+ {I_BLSI, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41439, 212},
+ {I_BLSI, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41446, 213},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLSIC[] = {
+ {I_BLSIC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41453, 214},
+ {I_BLSIC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41460, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLCFILL[] = {
+ {I_BLCFILL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41467, 214},
+ {I_BLCFILL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41474, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLSFILL[] = {
+ {I_BLSFILL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41481, 214},
+ {I_BLSFILL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41488, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLCMSK[] = {
+ {I_BLCMSK, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41495, 214},
+ {I_BLCMSK, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41502, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLSMSK[] = {
+ {I_BLSMSK, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41509, 212},
+ {I_BLSMSK, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41516, 213},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLSR[] = {
+ {I_BLSR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41523, 212},
+ {I_BLSR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41530, 213},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BLCS[] = {
+ {I_BLCS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41537, 214},
+ {I_BLCS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41544, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BZHI[] = {
+ {I_BZHI, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41551, 216},
+ {I_BZHI, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41558, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MULX[] = {
+ {I_MULX, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41565, 216},
+ {I_MULX, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41572, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PDEP[] = {
+ {I_PDEP, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41579, 216},
+ {I_PDEP, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41586, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PEXT[] = {
+ {I_PEXT, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41593, 216},
+ {I_PEXT, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41600, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RORX[] = {
+ {I_RORX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16288, 216},
+ {I_RORX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16296, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SARX[] = {
+ {I_SARX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41607, 216},
+ {I_SARX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41614, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHLX[] = {
+ {I_SHLX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41621, 216},
+ {I_SHLX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41628, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHRX[] = {
+ {I_SHRX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41635, 216},
+ {I_SHRX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41642, 217},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TZCNT[] = {
+ {I_TZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41649, 218},
+ {I_TZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41656, 218},
+ {I_TZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41663, 219},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TZMSK[] = {
+ {I_TZMSK, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41670, 214},
+ {I_TZMSK, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41677, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_T1MSKC[] = {
+ {I_T1MSKC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41684, 214},
+ {I_T1MSKC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41691, 215},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PREFETCHWT1[] = {
+ {I_PREFETCHWT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49177, 220},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BNDMK[] = {
+ {I_BNDMK, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45879, 221},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BNDCL[] = {
+ {I_BNDCL, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41699, 222},
+ {I_BNDCL, 2, {BNDREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41699, 223},
+ {I_BNDCL, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41698, 224},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BNDCU[] = {
+ {I_BNDCU, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41706, 222},
+ {I_BNDCU, 2, {BNDREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41706, 223},
+ {I_BNDCU, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41705, 224},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BNDCN[] = {
+ {I_BNDCN, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41713, 222},
+ {I_BNDCN, 2, {BNDREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41713, 223},
+ {I_BNDCN, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41712, 224},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BNDMOV[] = {
+ {I_BNDMOV, 2, {BNDREG,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45885, 222},
+ {I_BNDMOV, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45885, 222},
+ {I_BNDMOV, 2, {BNDREG,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45891, 222},
+ {I_BNDMOV, 2, {MEMORY,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45891, 222},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BNDLDX[] = {
+ {I_BNDLDX, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45886, 221},
+ {I_BNDLDX, 3, {BNDREG,MEMORY,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+45897, 225},
+ {I_BNDLDX, 3, {BNDREG,MEMORY,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+45897, 226},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_BNDSTX[] = {
+ {I_BNDSTX, 2, {MEMORY,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45892, 221},
+ {I_BNDSTX, 3, {MEMORY,REG_GPR|BITS32,BNDREG,0,0}, NO_DECORATOR, nasm_bytecodes+45903, 225},
+ {I_BNDSTX, 3, {MEMORY,REG_GPR|BITS64,BNDREG,0,0}, NO_DECORATOR, nasm_bytecodes+45903, 226},
+ {I_BNDSTX, 3, {MEMORY,BNDREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+45909, 225},
+ {I_BNDSTX, 3, {MEMORY,BNDREG,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+45909, 226},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHA1MSG1[] = {
+ {I_SHA1MSG1, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45915, 227},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHA1MSG2[] = {
+ {I_SHA1MSG2, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45921, 227},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHA1NEXTE[] = {
+ {I_SHA1NEXTE, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45927, 227},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHA1RNDS4[] = {
+ {I_SHA1RNDS4, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+41719, 227},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHA256MSG1[] = {
+ {I_SHA256MSG1, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45933, 227},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHA256MSG2[] = {
+ {I_SHA256MSG2, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45939, 227},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SHA256RNDS2[] = {
+ {I_SHA256RNDS2, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+45945, 227},
+ {I_SHA256RNDS2, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45945, 227},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBCSTNEBF16PS[] = {
+ {I_VBCSTNEBF16PS, 2, {XMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41726, 228},
+ {I_VBCSTNEBF16PS, 2, {YMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41733, 228},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBCSTNESH2PS[] = {
+ {I_VBCSTNESH2PS, 2, {XMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41740, 228},
+ {I_VBCSTNESH2PS, 2, {YMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41747, 228},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTNEEBF162PS[] = {
+ {I_VCVTNEEBF162PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41754, 229},
+ {I_VCVTNEEBF162PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41761, 230},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTNEEPH2PS[] = {
+ {I_VCVTNEEPH2PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41768, 229},
+ {I_VCVTNEEPH2PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41775, 230},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTNEOBF162PS[] = {
+ {I_VCVTNEOBF162PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41782, 229},
+ {I_VCVTNEOBF162PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41789, 230},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTNEOPH2PS[] = {
+ {I_VCVTNEOPH2PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41796, 229},
+ {I_VCVTNEOPH2PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41803, 230},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTNEPS2BF16[] = {
+ {I_VCVTNEPS2BF16, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41810, 229},
+ {I_VCVTNEPS2BF16, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41817, 230},
+ {I_VCVTNEPS2BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30064, 289},
+ {I_VCVTNEPS2BF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30072, 289},
+ {I_VCVTNEPS2BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30080, 289},
+ {I_VCVTNEPS2BF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30088, 289},
+ {I_VCVTNEPS2BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30096, 289},
+ {I_VCVTNEPS2BF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30104, 289},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBSSD[] = {
+ {I_VPDPBSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41824, 231},
+ {I_VPDPBSSD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41831, 232},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBSSDS[] = {
+ {I_VPDPBSSDS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41838, 231},
+ {I_VPDPBSSDS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41845, 232},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBSUD[] = {
+ {I_VPDPBSUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41852, 231},
+ {I_VPDPBSUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41859, 232},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBSUDS[] = {
+ {I_VPDPBSUDS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41866, 231},
+ {I_VPDPBSUDS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41873, 232},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBUUD[] = {
+ {I_VPDPBUUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41880, 231},
+ {I_VPDPBUUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41887, 232},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBUUDS[] = {
+ {I_VPDPBUUDS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41894, 231},
+ {I_VPDPBUUDS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41901, 232},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD52HUQ[] = {
+ {I_VPMADD52HUQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41908, 233},
+ {I_VPMADD52HUQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41915, 234},
+ {I_VPMADD52HUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23120, 252},
+ {I_VPMADD52HUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23128, 252},
+ {I_VPMADD52HUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23136, 253},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD52LUQ[] = {
+ {I_VPMADD52LUQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41922, 233},
+ {I_VPMADD52LUQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41929, 234},
+ {I_VPMADD52LUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23144, 252},
+ {I_VPMADD52LUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23152, 252},
+ {I_VPMADD52LUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23160, 253},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KADDB[] = {
+ {I_KADDB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41936, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KADDD[] = {
+ {I_KADDD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41943, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KADDQ[] = {
+ {I_KADDQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41950, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KADDW[] = {
+ {I_KADDW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41957, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDB[] = {
+ {I_KANDB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41964, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDD[] = {
+ {I_KANDD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41971, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDNB[] = {
+ {I_KANDNB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41978, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDND[] = {
+ {I_KANDND, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41985, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDNQ[] = {
+ {I_KANDNQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41992, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDNW[] = {
+ {I_KANDNW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41999, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDQ[] = {
+ {I_KANDQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42006, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDW[] = {
+ {I_KANDW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42013, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KMOVB[] = {
+ {I_KMOVB, 2, {KREG,RM_K|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42020, 235},
+ {I_KMOVB, 2, {MEMORY|BITS8,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42027, 235},
+ {I_KMOVB, 2, {KREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42034, 235},
+ {I_KMOVB, 2, {KREG,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16304, 235},
+ {I_KMOVB, 2, {REG_GPR|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42041, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KMOVD[] = {
+ {I_KMOVD, 2, {KREG,RM_K|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42048, 235},
+ {I_KMOVD, 2, {MEMORY|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42055, 235},
+ {I_KMOVD, 2, {KREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42062, 235},
+ {I_KMOVD, 2, {REG_GPR|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42069, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KMOVQ[] = {
+ {I_KMOVQ, 2, {KREG,RM_K|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42076, 235},
+ {I_KMOVQ, 2, {MEMORY|BITS64,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42083, 235},
+ {I_KMOVQ, 2, {KREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42090, 235},
+ {I_KMOVQ, 2, {REG_GPR|BITS64,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42097, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KMOVW[] = {
+ {I_KMOVW, 2, {KREG,RM_K|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42104, 235},
+ {I_KMOVW, 2, {MEMORY|BITS16,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42111, 235},
+ {I_KMOVW, 2, {KREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42118, 235},
+ {I_KMOVW, 2, {KREG,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42118, 235},
+ {I_KMOVW, 2, {REG_GPR|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42125, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KNOTB[] = {
+ {I_KNOTB, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42132, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KNOTD[] = {
+ {I_KNOTD, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42139, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KNOTQ[] = {
+ {I_KNOTQ, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42146, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KNOTW[] = {
+ {I_KNOTW, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42153, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORB[] = {
+ {I_KORB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42160, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORD[] = {
+ {I_KORD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42167, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORQ[] = {
+ {I_KORQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42174, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORW[] = {
+ {I_KORW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42181, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORTESTB[] = {
+ {I_KORTESTB, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42188, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORTESTD[] = {
+ {I_KORTESTD, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42195, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORTESTQ[] = {
+ {I_KORTESTQ, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42202, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORTESTW[] = {
+ {I_KORTESTW, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42209, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTLB[] = {
+ {I_KSHIFTLB, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16312, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTLD[] = {
+ {I_KSHIFTLD, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16320, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTLQ[] = {
+ {I_KSHIFTLQ, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16328, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTLW[] = {
+ {I_KSHIFTLW, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16336, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTRB[] = {
+ {I_KSHIFTRB, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16344, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTRD[] = {
+ {I_KSHIFTRD, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16352, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTRQ[] = {
+ {I_KSHIFTRQ, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16360, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTRW[] = {
+ {I_KSHIFTRW, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16368, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KTESTB[] = {
+ {I_KTESTB, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42216, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KTESTD[] = {
+ {I_KTESTD, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42223, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KTESTQ[] = {
+ {I_KTESTQ, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42230, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KTESTW[] = {
+ {I_KTESTW, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42237, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KUNPCKBW[] = {
+ {I_KUNPCKBW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42244, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KUNPCKDQ[] = {
+ {I_KUNPCKDQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42251, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KUNPCKWD[] = {
+ {I_KUNPCKWD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42258, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXNORB[] = {
+ {I_KXNORB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42265, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXNORD[] = {
+ {I_KXNORD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42272, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXNORQ[] = {
+ {I_KXNORQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42279, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXNORW[] = {
+ {I_KXNORW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42286, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXORB[] = {
+ {I_KXORB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42293, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXORD[] = {
+ {I_KXORD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42300, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXORQ[] = {
+ {I_KXORQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42307, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXORW[] = {
+ {I_KXORW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42314, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KADD[] = {
+ {I_KADD, 3, {KREG|BITS8,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41936, 236},
+ {I_KADD, 3, {KREG|BITS32,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41943, 236},
+ {I_KADD, 3, {KREG|BITS64,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41950, 236},
+ {I_KADD, 3, {KREG|BITS16,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41957, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KAND[] = {
+ {I_KAND, 3, {KREG|BITS8,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41964, 236},
+ {I_KAND, 3, {KREG|BITS32,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41971, 236},
+ {I_KAND, 3, {KREG|BITS64,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42006, 236},
+ {I_KAND, 3, {KREG|BITS16,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42013, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KANDN[] = {
+ {I_KANDN, 3, {KREG|BITS64,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41978, 236},
+ {I_KANDN, 3, {KREG|BITS16,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41985, 236},
+ {I_KANDN, 3, {KREG|BITS8,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41992, 236},
+ {I_KANDN, 3, {KREG|BITS32,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41999, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KMOV[] = {
+ {I_KMOV, 2, {KREG|BITS8,RM_K|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42020, 236},
+ {I_KMOV, 2, {MEMORY|BITS8,KREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42027, 237},
+ {I_KMOV, 2, {KREG|BITS8,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42034, 238},
+ {I_KMOV, 2, {KREG|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42034, 236},
+ {I_KMOV, 2, {REG_GPR|BITS32,KREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42041, 238},
+ {I_KMOV, 2, {KREG|BITS32,RM_K|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42048, 236},
+ {I_KMOV, 2, {MEMORY|BITS32,KREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42055, 236},
+ {I_KMOV, 2, {KREG|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42062, 236},
+ {I_KMOV, 2, {REG_GPR|BITS32,KREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42069, 236},
+ {I_KMOV, 2, {KREG|BITS64,RM_K|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42076, 236},
+ {I_KMOV, 2, {MEMORY|BITS64,KREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42083, 236},
+ {I_KMOV, 2, {KREG|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42090, 236},
+ {I_KMOV, 2, {REG_GPR|BITS64,KREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42097, 236},
+ {I_KMOV, 2, {KREG|BITS16,RM_K|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42104, 236},
+ {I_KMOV, 2, {MEMORY|BITS16,KREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42111, 236},
+ {I_KMOV, 2, {KREG|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42118, 238},
+ {I_KMOV, 2, {REG_GPR|BITS32,KREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42125, 238},
+ {I_KMOV, 2, {KREG|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42118, 238},
+ {I_KMOV, 2, {KREG|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42118, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KNOT[] = {
+ {I_KNOT, 2, {KREG|BITS8,KREG|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42132, 236},
+ {I_KNOT, 2, {KREG|BITS32,KREG|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42139, 236},
+ {I_KNOT, 2, {KREG|BITS64,KREG|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42146, 236},
+ {I_KNOT, 2, {KREG|BITS16,KREG|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42153, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KOR[] = {
+ {I_KOR, 3, {KREG|BITS8,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42160, 236},
+ {I_KOR, 3, {KREG|BITS32,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42167, 236},
+ {I_KOR, 3, {KREG|BITS64,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42174, 236},
+ {I_KOR, 3, {KREG|BITS16,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42181, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KORTEST[] = {
+ {I_KORTEST, 2, {KREG|BITS8,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42188, 236},
+ {I_KORTEST, 2, {KREG|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42195, 236},
+ {I_KORTEST, 2, {KREG|BITS64,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42202, 236},
+ {I_KORTEST, 2, {KREG|BITS16,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42209, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTL[] = {
+ {I_KSHIFTL, 3, {KREG|BITS8,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16312, 239},
+ {I_KSHIFTL, 3, {KREG|BITS32,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16320, 239},
+ {I_KSHIFTL, 3, {KREG|BITS64,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16328, 239},
+ {I_KSHIFTL, 3, {KREG|BITS16,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16336, 239},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KSHIFTR[] = {
+ {I_KSHIFTR, 3, {KREG|BITS8,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16344, 239},
+ {I_KSHIFTR, 3, {KREG|BITS32,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16352, 239},
+ {I_KSHIFTR, 3, {KREG|BITS64,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16360, 239},
+ {I_KSHIFTR, 3, {KREG|BITS16,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16368, 239},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KTEST[] = {
+ {I_KTEST, 2, {KREG|BITS8,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42216, 236},
+ {I_KTEST, 2, {KREG|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42223, 236},
+ {I_KTEST, 2, {KREG|BITS64,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42230, 236},
+ {I_KTEST, 2, {KREG|BITS16,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42237, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KUNPCK[] = {
+ {I_KUNPCK, 3, {KREG|BITS16,KREG|BITS8,KREG|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+42244, 235},
+ {I_KUNPCK, 3, {KREG|BITS64,KREG|BITS32,KREG|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42251, 235},
+ {I_KUNPCK, 3, {KREG|BITS32,KREG|BITS16,KREG|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+42258, 235},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXNOR[] = {
+ {I_KXNOR, 3, {KREG|BITS8,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42265, 236},
+ {I_KXNOR, 3, {KREG|BITS32,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42272, 236},
+ {I_KXNOR, 3, {KREG|BITS64,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42279, 236},
+ {I_KXNOR, 3, {KREG|BITS16,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42286, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_KXOR[] = {
+ {I_KXOR, 3, {KREG|BITS8,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42293, 236},
+ {I_KXOR, 3, {KREG|BITS32,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42300, 236},
+ {I_KXOR, 3, {KREG|BITS64,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42307, 236},
+ {I_KXOR, 3, {KREG|BITS16,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42314, 236},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VALIGND[] = {
+ {I_VALIGND, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8002, 240},
+ {I_VALIGND, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8011, 240},
+ {I_VALIGND, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8020, 240},
+ {I_VALIGND, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8029, 240},
+ {I_VALIGND, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8038, 241},
+ {I_VALIGND, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8047, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VALIGNQ[] = {
+ {I_VALIGNQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8056, 240},
+ {I_VALIGNQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8065, 240},
+ {I_VALIGNQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8074, 240},
+ {I_VALIGNQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8083, 240},
+ {I_VALIGNQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8092, 241},
+ {I_VALIGNQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8101, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBLENDMPD[] = {
+ {I_VBLENDMPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16696, 240},
+ {I_VBLENDMPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16704, 240},
+ {I_VBLENDMPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16712, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBLENDMPS[] = {
+ {I_VBLENDMPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16720, 240},
+ {I_VBLENDMPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16728, 240},
+ {I_VBLENDMPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16736, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTF32X2[] = {
+ {I_VBROADCASTF32X2, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16744, 242},
+ {I_VBROADCASTF32X2, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16752, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTF32X4[] = {
+ {I_VBROADCASTF32X4, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16760, 240},
+ {I_VBROADCASTF32X4, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16768, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTF32X8[] = {
+ {I_VBROADCASTF32X8, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16776, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTF64X2[] = {
+ {I_VBROADCASTF64X2, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16784, 242},
+ {I_VBROADCASTF64X2, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16792, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTF64X4[] = {
+ {I_VBROADCASTF64X4, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16800, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTI32X2[] = {
+ {I_VBROADCASTI32X2, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16808, 242},
+ {I_VBROADCASTI32X2, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16816, 242},
+ {I_VBROADCASTI32X2, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16824, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTI32X4[] = {
+ {I_VBROADCASTI32X4, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16832, 240},
+ {I_VBROADCASTI32X4, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16840, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTI32X8[] = {
+ {I_VBROADCASTI32X8, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16848, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTI64X2[] = {
+ {I_VBROADCASTI64X2, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16856, 242},
+ {I_VBROADCASTI64X2, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16864, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VBROADCASTI64X4[] = {
+ {I_VBROADCASTI64X4, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16872, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OQPD[] = {
+ {I_VCMPEQ_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+240, 240},
+ {I_VCMPEQ_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+250, 240},
+ {I_VCMPEQ_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+260, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OQPS[] = {
+ {I_VCMPEQ_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+270, 240},
+ {I_VCMPEQ_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+280, 240},
+ {I_VCMPEQ_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+290, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OQSD[] = {
+ {I_VCMPEQ_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+300, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPEQ_OQSS[] = {
+ {I_VCMPEQ_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+310, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCOMPRESSPD[] = {
+ {I_VCOMPRESSPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+16976, 240},
+ {I_VCOMPRESSPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+16984, 240},
+ {I_VCOMPRESSPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+16992, 241},
+ {I_VCOMPRESSPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17000, 240},
+ {I_VCOMPRESSPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17008, 240},
+ {I_VCOMPRESSPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17016, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCOMPRESSPS[] = {
+ {I_VCOMPRESSPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+17024, 240},
+ {I_VCOMPRESSPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+17032, 240},
+ {I_VCOMPRESSPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+17040, 241},
+ {I_VCOMPRESSPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17048, 240},
+ {I_VCOMPRESSPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17056, 240},
+ {I_VCOMPRESSPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17064, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPD2QQ[] = {
+ {I_VCVTPD2QQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17168, 242},
+ {I_VCVTPD2QQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17176, 242},
+ {I_VCVTPD2QQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17184, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPD2UDQ[] = {
+ {I_VCVTPD2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17192, 240},
+ {I_VCVTPD2UDQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17200, 240},
+ {I_VCVTPD2UDQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17208, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPD2UQQ[] = {
+ {I_VCVTPD2UQQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17216, 242},
+ {I_VCVTPD2UQQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17224, 242},
+ {I_VCVTPD2UQQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17232, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPS2QQ[] = {
+ {I_VCVTPS2QQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17312, 242},
+ {I_VCVTPS2QQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17320, 242},
+ {I_VCVTPS2QQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17328, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPS2UDQ[] = {
+ {I_VCVTPS2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17336, 240},
+ {I_VCVTPS2UDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17344, 240},
+ {I_VCVTPS2UDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17352, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPS2UQQ[] = {
+ {I_VCVTPS2UQQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17360, 242},
+ {I_VCVTPS2UQQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17368, 242},
+ {I_VCVTPS2UQQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17376, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTQQ2PD[] = {
+ {I_VCVTQQ2PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17384, 242},
+ {I_VCVTQQ2PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17392, 242},
+ {I_VCVTQQ2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17400, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTQQ2PS[] = {
+ {I_VCVTQQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17408, 242},
+ {I_VCVTQQ2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17416, 242},
+ {I_VCVTQQ2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17424, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSD2USI[] = {
+ {I_VCVTSD2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17456, 241},
+ {I_VCVTSD2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17464, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSS2USI[] = {
+ {I_VCVTSS2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17528, 241},
+ {I_VCVTSS2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17536, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPD2QQ[] = {
+ {I_VCVTTPD2QQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17568, 242},
+ {I_VCVTTPD2QQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17576, 242},
+ {I_VCVTTPD2QQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17584, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPD2UDQ[] = {
+ {I_VCVTTPD2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17592, 240},
+ {I_VCVTTPD2UDQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17600, 240},
+ {I_VCVTTPD2UDQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17608, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPD2UQQ[] = {
+ {I_VCVTTPD2UQQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17616, 242},
+ {I_VCVTTPD2UQQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17624, 242},
+ {I_VCVTTPD2UQQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17632, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPS2QQ[] = {
+ {I_VCVTTPS2QQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17664, 242},
+ {I_VCVTTPS2QQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17672, 242},
+ {I_VCVTTPS2QQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17680, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPS2UDQ[] = {
+ {I_VCVTTPS2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17688, 240},
+ {I_VCVTTPS2UDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17696, 240},
+ {I_VCVTTPS2UDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17704, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPS2UQQ[] = {
+ {I_VCVTTPS2UQQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17712, 242},
+ {I_VCVTTPS2UQQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17720, 242},
+ {I_VCVTTPS2UQQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17728, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTSD2USI[] = {
+ {I_VCVTTSD2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17752, 241},
+ {I_VCVTTSD2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17760, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTSS2USI[] = {
+ {I_VCVTTSS2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17784, 241},
+ {I_VCVTTSS2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17792, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUDQ2PD[] = {
+ {I_VCVTUDQ2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17800, 240},
+ {I_VCVTUDQ2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17808, 240},
+ {I_VCVTUDQ2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17816, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUDQ2PS[] = {
+ {I_VCVTUDQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17824, 240},
+ {I_VCVTUDQ2PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17832, 240},
+ {I_VCVTUDQ2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17840, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUQQ2PD[] = {
+ {I_VCVTUQQ2PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17848, 242},
+ {I_VCVTUQQ2PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17856, 242},
+ {I_VCVTUQQ2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17864, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUQQ2PS[] = {
+ {I_VCVTUQQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17872, 242},
+ {I_VCVTUQQ2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17880, 242},
+ {I_VCVTUQQ2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17888, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUSI2SD[] = {
+ {I_VCVTUSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17896, 241},
+ {I_VCVTUSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17904, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUSI2SS[] = {
+ {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17912, 241},
+ {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17920, 241},
+ {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,ER,0,0}, nasm_bytecodes+30912, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDBPSADBW[] = {
+ {I_VDBPSADBW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8209, 244},
+ {I_VDBPSADBW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8218, 244},
+ {I_VDBPSADBW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8227, 244},
+ {I_VDBPSADBW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8236, 244},
+ {I_VDBPSADBW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8245, 245},
+ {I_VDBPSADBW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8254, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXP2PD[] = {
+ {I_VEXP2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+18056, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXP2PS[] = {
+ {I_VEXP2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+18064, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXPANDPD[] = {
+ {I_VEXPANDPD, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18072, 240},
+ {I_VEXPANDPD, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18080, 240},
+ {I_VEXPANDPD, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18088, 241},
+ {I_VEXPANDPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18072, 240},
+ {I_VEXPANDPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18080, 240},
+ {I_VEXPANDPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18088, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXPANDPS[] = {
+ {I_VEXPANDPS, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18096, 240},
+ {I_VEXPANDPS, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18104, 240},
+ {I_VEXPANDPS, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18112, 241},
+ {I_VEXPANDPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18096, 240},
+ {I_VEXPANDPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18104, 240},
+ {I_VEXPANDPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18112, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTF32X4[] = {
+ {I_VEXTRACTF32X4, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8263, 240},
+ {I_VEXTRACTF32X4, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8272, 241},
+ {I_VEXTRACTF32X4, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8281, 240},
+ {I_VEXTRACTF32X4, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8290, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTF32X8[] = {
+ {I_VEXTRACTF32X8, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8299, 243},
+ {I_VEXTRACTF32X8, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8308, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTF64X2[] = {
+ {I_VEXTRACTF64X2, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8317, 242},
+ {I_VEXTRACTF64X2, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8326, 243},
+ {I_VEXTRACTF64X2, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8335, 242},
+ {I_VEXTRACTF64X2, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8344, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTF64X4[] = {
+ {I_VEXTRACTF64X4, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8353, 241},
+ {I_VEXTRACTF64X4, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8362, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTI32X4[] = {
+ {I_VEXTRACTI32X4, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8371, 240},
+ {I_VEXTRACTI32X4, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8380, 241},
+ {I_VEXTRACTI32X4, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8389, 240},
+ {I_VEXTRACTI32X4, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8398, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTI32X8[] = {
+ {I_VEXTRACTI32X8, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8407, 243},
+ {I_VEXTRACTI32X8, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8416, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTI64X2[] = {
+ {I_VEXTRACTI64X2, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8425, 242},
+ {I_VEXTRACTI64X2, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8434, 243},
+ {I_VEXTRACTI64X2, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8443, 242},
+ {I_VEXTRACTI64X2, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8452, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VEXTRACTI64X4[] = {
+ {I_VEXTRACTI64X4, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8461, 241},
+ {I_VEXTRACTI64X4, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8470, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFIXUPIMMPD[] = {
+ {I_VFIXUPIMMPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8488, 240},
+ {I_VFIXUPIMMPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8497, 240},
+ {I_VFIXUPIMMPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8506, 240},
+ {I_VFIXUPIMMPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8515, 240},
+ {I_VFIXUPIMMPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+8524, 241},
+ {I_VFIXUPIMMPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+8533, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFIXUPIMMPS[] = {
+ {I_VFIXUPIMMPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8542, 240},
+ {I_VFIXUPIMMPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8551, 240},
+ {I_VFIXUPIMMPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8560, 240},
+ {I_VFIXUPIMMPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8569, 240},
+ {I_VFIXUPIMMPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+8578, 241},
+ {I_VFIXUPIMMPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+8587, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFIXUPIMMSD[] = {
+ {I_VFIXUPIMMSD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8596, 241},
+ {I_VFIXUPIMMSD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8605, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFIXUPIMMSS[] = {
+ {I_VFIXUPIMMSS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8614, 241},
+ {I_VFIXUPIMMSS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8623, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFPCLASSPD[] = {
+ {I_VFPCLASSPD, 3, {KREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+8632, 242},
+ {I_VFPCLASSPD, 3, {KREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+8641, 242},
+ {I_VFPCLASSPD, 3, {KREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+8650, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFPCLASSPS[] = {
+ {I_VFPCLASSPS, 3, {KREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+8659, 242},
+ {I_VFPCLASSPS, 3, {KREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+8668, 242},
+ {I_VFPCLASSPS, 3, {KREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+8677, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFPCLASSSD[] = {
+ {I_VFPCLASSSD, 3, {KREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8686, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFPCLASSSS[] = {
+ {I_VFPCLASSSS, 3, {KREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8695, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF0DPD[] = {
+ {I_VGATHERPF0DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8758, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF0DPS[] = {
+ {I_VGATHERPF0DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8767, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF0QPD[] = {
+ {I_VGATHERPF0QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8776, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF0QPS[] = {
+ {I_VGATHERPF0QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8785, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF1DPD[] = {
+ {I_VGATHERPF1DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8794, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF1DPS[] = {
+ {I_VGATHERPF1DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8803, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF1QPD[] = {
+ {I_VGATHERPF1QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8812, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGATHERPF1QPS[] = {
+ {I_VGATHERPF1QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8821, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETEXPPD[] = {
+ {I_VGETEXPPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19176, 240},
+ {I_VGETEXPPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19184, 240},
+ {I_VGETEXPPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+19192, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETEXPPS[] = {
+ {I_VGETEXPPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19200, 240},
+ {I_VGETEXPPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19208, 240},
+ {I_VGETEXPPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+19216, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETEXPSD[] = {
+ {I_VGETEXPSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19224, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETEXPSS[] = {
+ {I_VGETEXPSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19232, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMANTPD[] = {
+ {I_VGETMANTPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8884, 240},
+ {I_VGETMANTPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8893, 240},
+ {I_VGETMANTPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+8902, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMANTPS[] = {
+ {I_VGETMANTPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8911, 240},
+ {I_VGETMANTPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8920, 240},
+ {I_VGETMANTPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+8929, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMANTSD[] = {
+ {I_VGETMANTSD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8938, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMANTSS[] = {
+ {I_VGETMANTSS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8947, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTF32X4[] = {
+ {I_VINSERTF32X4, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8956, 240},
+ {I_VINSERTF32X4, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8965, 240},
+ {I_VINSERTF32X4, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8974, 241},
+ {I_VINSERTF32X4, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8983, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTF32X8[] = {
+ {I_VINSERTF32X8, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8992, 243},
+ {I_VINSERTF32X8, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9001, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTF64X2[] = {
+ {I_VINSERTF64X2, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9010, 242},
+ {I_VINSERTF64X2, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9019, 242},
+ {I_VINSERTF64X2, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9028, 243},
+ {I_VINSERTF64X2, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9037, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTF64X4[] = {
+ {I_VINSERTF64X4, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9046, 241},
+ {I_VINSERTF64X4, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9055, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTI32X4[] = {
+ {I_VINSERTI32X4, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9064, 240},
+ {I_VINSERTI32X4, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9073, 240},
+ {I_VINSERTI32X4, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9082, 241},
+ {I_VINSERTI32X4, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9091, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTI32X8[] = {
+ {I_VINSERTI32X8, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9100, 243},
+ {I_VINSERTI32X8, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9109, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTI64X2[] = {
+ {I_VINSERTI64X2, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9118, 242},
+ {I_VINSERTI64X2, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9127, 242},
+ {I_VINSERTI64X2, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9136, 243},
+ {I_VINSERTI64X2, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9145, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VINSERTI64X4[] = {
+ {I_VINSERTI64X4, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9154, 241},
+ {I_VINSERTI64X4, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9163, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQA32[] = {
+ {I_VMOVDQA32, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19680, 240},
+ {I_VMOVDQA32, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19688, 240},
+ {I_VMOVDQA32, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19696, 241},
+ {I_VMOVDQA32, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19704, 240},
+ {I_VMOVDQA32, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19712, 240},
+ {I_VMOVDQA32, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19720, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQA64[] = {
+ {I_VMOVDQA64, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19728, 240},
+ {I_VMOVDQA64, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19736, 240},
+ {I_VMOVDQA64, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19744, 241},
+ {I_VMOVDQA64, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19752, 240},
+ {I_VMOVDQA64, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19760, 240},
+ {I_VMOVDQA64, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19768, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQU16[] = {
+ {I_VMOVDQU16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19776, 244},
+ {I_VMOVDQU16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19784, 244},
+ {I_VMOVDQU16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19792, 245},
+ {I_VMOVDQU16, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19800, 244},
+ {I_VMOVDQU16, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19808, 244},
+ {I_VMOVDQU16, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19816, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQU32[] = {
+ {I_VMOVDQU32, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19824, 240},
+ {I_VMOVDQU32, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19832, 240},
+ {I_VMOVDQU32, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19840, 241},
+ {I_VMOVDQU32, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19848, 240},
+ {I_VMOVDQU32, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19856, 240},
+ {I_VMOVDQU32, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19864, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQU64[] = {
+ {I_VMOVDQU64, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19872, 240},
+ {I_VMOVDQU64, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19880, 240},
+ {I_VMOVDQU64, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19888, 241},
+ {I_VMOVDQU64, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19896, 240},
+ {I_VMOVDQU64, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19904, 240},
+ {I_VMOVDQU64, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19912, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVDQU8[] = {
+ {I_VMOVDQU8, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19920, 244},
+ {I_VMOVDQU8, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19928, 244},
+ {I_VMOVDQU8, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19936, 245},
+ {I_VMOVDQU8, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19944, 244},
+ {I_VMOVDQU8, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19952, 244},
+ {I_VMOVDQU8, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19960, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPABSQ[] = {
+ {I_VPABSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20784, 240},
+ {I_VPABSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20792, 240},
+ {I_VPABSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20800, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPANDD[] = {
+ {I_VPANDD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21408, 240},
+ {I_VPANDD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21416, 240},
+ {I_VPANDD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21424, 240},
+ {I_VPANDD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21432, 240},
+ {I_VPANDD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21440, 241},
+ {I_VPANDD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21448, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPANDND[] = {
+ {I_VPANDND, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21456, 240},
+ {I_VPANDND, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21464, 240},
+ {I_VPANDND, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21472, 240},
+ {I_VPANDND, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21480, 240},
+ {I_VPANDND, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21488, 241},
+ {I_VPANDND, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21496, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPANDNQ[] = {
+ {I_VPANDNQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21504, 240},
+ {I_VPANDNQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21512, 240},
+ {I_VPANDNQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21520, 240},
+ {I_VPANDNQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21528, 240},
+ {I_VPANDNQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21536, 241},
+ {I_VPANDNQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21544, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPANDQ[] = {
+ {I_VPANDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21552, 240},
+ {I_VPANDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21560, 240},
+ {I_VPANDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21568, 240},
+ {I_VPANDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21576, 240},
+ {I_VPANDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21584, 241},
+ {I_VPANDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21592, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBLENDMB[] = {
+ {I_VPBLENDMB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21696, 244},
+ {I_VPBLENDMB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21704, 244},
+ {I_VPBLENDMB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21712, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBLENDMD[] = {
+ {I_VPBLENDMD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21720, 240},
+ {I_VPBLENDMD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21728, 240},
+ {I_VPBLENDMD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21736, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBLENDMQ[] = {
+ {I_VPBLENDMQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21744, 240},
+ {I_VPBLENDMQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21752, 240},
+ {I_VPBLENDMQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21760, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBLENDMW[] = {
+ {I_VPBLENDMW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21768, 244},
+ {I_VPBLENDMW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21776, 244},
+ {I_VPBLENDMW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21784, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBROADCASTMB2Q[] = {
+ {I_VPBROADCASTMB2Q, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21912, 248},
+ {I_VPBROADCASTMB2Q, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21920, 248},
+ {I_VPBROADCASTMB2Q, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21928, 249},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPBROADCASTMW2D[] = {
+ {I_VPBROADCASTMW2D, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21936, 248},
+ {I_VPBROADCASTMW2D, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21944, 248},
+ {I_VPBROADCASTMW2D, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21952, 249},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQUB[] = {
+ {I_VPCMPEQUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2890, 244},
+ {I_VPCMPEQUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2900, 244},
+ {I_VPCMPEQUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2910, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQUD[] = {
+ {I_VPCMPEQUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2920, 240},
+ {I_VPCMPEQUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2930, 240},
+ {I_VPCMPEQUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2940, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQUQ[] = {
+ {I_VPCMPEQUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2950, 240},
+ {I_VPCMPEQUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2960, 240},
+ {I_VPCMPEQUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2970, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPEQUW[] = {
+ {I_VPCMPEQUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2980, 244},
+ {I_VPCMPEQUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2990, 244},
+ {I_VPCMPEQUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3000, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGEB[] = {
+ {I_VPCMPGEB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3040, 244},
+ {I_VPCMPGEB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3050, 244},
+ {I_VPCMPGEB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3060, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGED[] = {
+ {I_VPCMPGED, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3070, 240},
+ {I_VPCMPGED, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3080, 240},
+ {I_VPCMPGED, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3090, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGEQ[] = {
+ {I_VPCMPGEQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3100, 240},
+ {I_VPCMPGEQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3110, 240},
+ {I_VPCMPGEQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3120, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGEUB[] = {
+ {I_VPCMPGEUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3130, 244},
+ {I_VPCMPGEUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3140, 244},
+ {I_VPCMPGEUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3150, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGEUD[] = {
+ {I_VPCMPGEUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3160, 240},
+ {I_VPCMPGEUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3170, 240},
+ {I_VPCMPGEUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3180, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGEUQ[] = {
+ {I_VPCMPGEUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3190, 240},
+ {I_VPCMPGEUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3200, 240},
+ {I_VPCMPGEUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3210, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGEUW[] = {
+ {I_VPCMPGEUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3220, 244},
+ {I_VPCMPGEUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3230, 244},
+ {I_VPCMPGEUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3240, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGEW[] = {
+ {I_VPCMPGEW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3250, 244},
+ {I_VPCMPGEW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3260, 244},
+ {I_VPCMPGEW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3270, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTUB[] = {
+ {I_VPCMPGTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3370, 244},
+ {I_VPCMPGTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3380, 244},
+ {I_VPCMPGTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3390, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTUD[] = {
+ {I_VPCMPGTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3400, 240},
+ {I_VPCMPGTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3410, 240},
+ {I_VPCMPGTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3420, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTUQ[] = {
+ {I_VPCMPGTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3430, 240},
+ {I_VPCMPGTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3440, 240},
+ {I_VPCMPGTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3450, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPGTUW[] = {
+ {I_VPCMPGTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3460, 244},
+ {I_VPCMPGTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3470, 244},
+ {I_VPCMPGTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3480, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLEB[] = {
+ {I_VPCMPLEB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3520, 244},
+ {I_VPCMPLEB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3530, 244},
+ {I_VPCMPLEB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3540, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLED[] = {
+ {I_VPCMPLED, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3550, 240},
+ {I_VPCMPLED, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3560, 240},
+ {I_VPCMPLED, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3570, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLEQ[] = {
+ {I_VPCMPLEQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3580, 240},
+ {I_VPCMPLEQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3590, 240},
+ {I_VPCMPLEQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3600, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLEUB[] = {
+ {I_VPCMPLEUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3610, 244},
+ {I_VPCMPLEUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3620, 244},
+ {I_VPCMPLEUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3630, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLEUD[] = {
+ {I_VPCMPLEUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3640, 240},
+ {I_VPCMPLEUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3650, 240},
+ {I_VPCMPLEUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3660, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLEUQ[] = {
+ {I_VPCMPLEUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3670, 240},
+ {I_VPCMPLEUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3680, 240},
+ {I_VPCMPLEUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3690, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLEUW[] = {
+ {I_VPCMPLEUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3700, 244},
+ {I_VPCMPLEUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3710, 244},
+ {I_VPCMPLEUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3720, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLEW[] = {
+ {I_VPCMPLEW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3730, 244},
+ {I_VPCMPLEW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3740, 244},
+ {I_VPCMPLEW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3750, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTB[] = {
+ {I_VPCMPLTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3760, 244},
+ {I_VPCMPLTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3770, 244},
+ {I_VPCMPLTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3780, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTD[] = {
+ {I_VPCMPLTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3790, 240},
+ {I_VPCMPLTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3800, 240},
+ {I_VPCMPLTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3810, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTQ[] = {
+ {I_VPCMPLTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3820, 240},
+ {I_VPCMPLTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3830, 240},
+ {I_VPCMPLTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3840, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTUB[] = {
+ {I_VPCMPLTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3850, 244},
+ {I_VPCMPLTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3860, 244},
+ {I_VPCMPLTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3870, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTUD[] = {
+ {I_VPCMPLTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3880, 240},
+ {I_VPCMPLTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3890, 240},
+ {I_VPCMPLTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3900, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTUQ[] = {
+ {I_VPCMPLTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3910, 240},
+ {I_VPCMPLTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3920, 240},
+ {I_VPCMPLTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3930, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTUW[] = {
+ {I_VPCMPLTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3940, 244},
+ {I_VPCMPLTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3950, 244},
+ {I_VPCMPLTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3960, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPLTW[] = {
+ {I_VPCMPLTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3970, 244},
+ {I_VPCMPLTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3980, 244},
+ {I_VPCMPLTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3990, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQB[] = {
+ {I_VPCMPNEQB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4000, 244},
+ {I_VPCMPNEQB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4010, 244},
+ {I_VPCMPNEQB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4020, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQD[] = {
+ {I_VPCMPNEQD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4030, 240},
+ {I_VPCMPNEQD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4040, 240},
+ {I_VPCMPNEQD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4050, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQQ[] = {
+ {I_VPCMPNEQQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4060, 240},
+ {I_VPCMPNEQQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4070, 240},
+ {I_VPCMPNEQQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4080, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQUB[] = {
+ {I_VPCMPNEQUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4090, 244},
+ {I_VPCMPNEQUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4100, 244},
+ {I_VPCMPNEQUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4110, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQUD[] = {
+ {I_VPCMPNEQUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4120, 240},
+ {I_VPCMPNEQUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4130, 240},
+ {I_VPCMPNEQUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4140, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQUQ[] = {
+ {I_VPCMPNEQUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4150, 240},
+ {I_VPCMPNEQUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4160, 240},
+ {I_VPCMPNEQUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4170, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQUW[] = {
+ {I_VPCMPNEQUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4180, 244},
+ {I_VPCMPNEQUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4190, 244},
+ {I_VPCMPNEQUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4200, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNEQW[] = {
+ {I_VPCMPNEQW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4210, 244},
+ {I_VPCMPNEQW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4220, 244},
+ {I_VPCMPNEQW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4230, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTB[] = {
+ {I_VPCMPNGTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3520, 244},
+ {I_VPCMPNGTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3530, 244},
+ {I_VPCMPNGTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3540, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTD[] = {
+ {I_VPCMPNGTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3550, 240},
+ {I_VPCMPNGTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3560, 240},
+ {I_VPCMPNGTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3570, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTQ[] = {
+ {I_VPCMPNGTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3580, 240},
+ {I_VPCMPNGTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3590, 240},
+ {I_VPCMPNGTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3600, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTUB[] = {
+ {I_VPCMPNGTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3610, 244},
+ {I_VPCMPNGTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3620, 244},
+ {I_VPCMPNGTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3630, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTUD[] = {
+ {I_VPCMPNGTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3640, 240},
+ {I_VPCMPNGTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3650, 240},
+ {I_VPCMPNGTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3660, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTUQ[] = {
+ {I_VPCMPNGTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3670, 240},
+ {I_VPCMPNGTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3680, 240},
+ {I_VPCMPNGTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3690, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTUW[] = {
+ {I_VPCMPNGTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3700, 244},
+ {I_VPCMPNGTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3710, 244},
+ {I_VPCMPNGTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3720, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNGTW[] = {
+ {I_VPCMPNGTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3730, 244},
+ {I_VPCMPNGTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3740, 244},
+ {I_VPCMPNGTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3750, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLEB[] = {
+ {I_VPCMPNLEB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3280, 244},
+ {I_VPCMPNLEB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3290, 244},
+ {I_VPCMPNLEB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3300, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLED[] = {
+ {I_VPCMPNLED, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3310, 240},
+ {I_VPCMPNLED, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3320, 240},
+ {I_VPCMPNLED, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3330, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLEQ[] = {
+ {I_VPCMPNLEQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3340, 240},
+ {I_VPCMPNLEQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3350, 240},
+ {I_VPCMPNLEQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3360, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLEUB[] = {
+ {I_VPCMPNLEUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3370, 244},
+ {I_VPCMPNLEUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3380, 244},
+ {I_VPCMPNLEUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3390, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLEUD[] = {
+ {I_VPCMPNLEUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3400, 240},
+ {I_VPCMPNLEUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3410, 240},
+ {I_VPCMPNLEUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3420, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLEUQ[] = {
+ {I_VPCMPNLEUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3430, 240},
+ {I_VPCMPNLEUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3440, 240},
+ {I_VPCMPNLEUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3450, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLEUW[] = {
+ {I_VPCMPNLEUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3460, 244},
+ {I_VPCMPNLEUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3470, 244},
+ {I_VPCMPNLEUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3480, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLEW[] = {
+ {I_VPCMPNLEW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3490, 244},
+ {I_VPCMPNLEW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3500, 244},
+ {I_VPCMPNLEW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3510, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTB[] = {
+ {I_VPCMPNLTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3040, 244},
+ {I_VPCMPNLTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3050, 244},
+ {I_VPCMPNLTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3060, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTD[] = {
+ {I_VPCMPNLTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3070, 240},
+ {I_VPCMPNLTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3080, 240},
+ {I_VPCMPNLTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3090, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTQ[] = {
+ {I_VPCMPNLTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3100, 240},
+ {I_VPCMPNLTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3110, 240},
+ {I_VPCMPNLTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3120, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTUB[] = {
+ {I_VPCMPNLTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3130, 244},
+ {I_VPCMPNLTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3140, 244},
+ {I_VPCMPNLTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3150, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTUD[] = {
+ {I_VPCMPNLTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3160, 240},
+ {I_VPCMPNLTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3170, 240},
+ {I_VPCMPNLTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3180, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTUQ[] = {
+ {I_VPCMPNLTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3190, 240},
+ {I_VPCMPNLTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3200, 240},
+ {I_VPCMPNLTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3210, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTUW[] = {
+ {I_VPCMPNLTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3220, 244},
+ {I_VPCMPNLTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3230, 244},
+ {I_VPCMPNLTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3240, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPNLTW[] = {
+ {I_VPCMPNLTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3250, 244},
+ {I_VPCMPNLTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3260, 244},
+ {I_VPCMPNLTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3270, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPB[] = {
+ {I_VPCMPB, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9244, 244},
+ {I_VPCMPB, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9253, 244},
+ {I_VPCMPB, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9262, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPD[] = {
+ {I_VPCMPD, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9271, 240},
+ {I_VPCMPD, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9280, 240},
+ {I_VPCMPD, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9289, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPQ[] = {
+ {I_VPCMPQ, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9298, 240},
+ {I_VPCMPQ, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9307, 240},
+ {I_VPCMPQ, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9316, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPUB[] = {
+ {I_VPCMPUB, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9325, 244},
+ {I_VPCMPUB, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9334, 244},
+ {I_VPCMPUB, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9343, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPUD[] = {
+ {I_VPCMPUD, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9352, 240},
+ {I_VPCMPUD, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9361, 240},
+ {I_VPCMPUD, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9370, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPUQ[] = {
+ {I_VPCMPUQ, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9379, 240},
+ {I_VPCMPUQ, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9388, 240},
+ {I_VPCMPUQ, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9397, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPUW[] = {
+ {I_VPCMPUW, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9406, 244},
+ {I_VPCMPUW, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9415, 244},
+ {I_VPCMPUW, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9424, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCMPW[] = {
+ {I_VPCMPW, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9433, 244},
+ {I_VPCMPW, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9442, 244},
+ {I_VPCMPW, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9451, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMPRESSD[] = {
+ {I_VPCOMPRESSD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22272, 240},
+ {I_VPCOMPRESSD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22280, 240},
+ {I_VPCOMPRESSD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22288, 241},
+ {I_VPCOMPRESSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22296, 240},
+ {I_VPCOMPRESSD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22304, 240},
+ {I_VPCOMPRESSD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22312, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMPRESSQ[] = {
+ {I_VPCOMPRESSQ, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22320, 240},
+ {I_VPCOMPRESSQ, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22328, 240},
+ {I_VPCOMPRESSQ, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22336, 241},
+ {I_VPCOMPRESSQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22344, 240},
+ {I_VPCOMPRESSQ, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22352, 240},
+ {I_VPCOMPRESSQ, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22360, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCONFLICTD[] = {
+ {I_VPCONFLICTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22368, 248},
+ {I_VPCONFLICTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22376, 248},
+ {I_VPCONFLICTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22384, 249},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCONFLICTQ[] = {
+ {I_VPCONFLICTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22392, 248},
+ {I_VPCONFLICTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22400, 248},
+ {I_VPCONFLICTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22408, 249},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMB[] = {
+ {I_VPERMB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22416, 250},
+ {I_VPERMB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22424, 250},
+ {I_VPERMB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22432, 250},
+ {I_VPERMB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22440, 250},
+ {I_VPERMB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22448, 251},
+ {I_VPERMB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22456, 251},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMI2B[] = {
+ {I_VPERMI2B, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22496, 250},
+ {I_VPERMI2B, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22504, 250},
+ {I_VPERMI2B, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22512, 251},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMI2D[] = {
+ {I_VPERMI2D, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22520, 240},
+ {I_VPERMI2D, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22528, 240},
+ {I_VPERMI2D, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22536, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMI2PD[] = {
+ {I_VPERMI2PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22544, 240},
+ {I_VPERMI2PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22552, 240},
+ {I_VPERMI2PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22560, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMI2PS[] = {
+ {I_VPERMI2PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22568, 240},
+ {I_VPERMI2PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22576, 240},
+ {I_VPERMI2PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22584, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMI2Q[] = {
+ {I_VPERMI2Q, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22592, 240},
+ {I_VPERMI2Q, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22600, 240},
+ {I_VPERMI2Q, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22608, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMI2W[] = {
+ {I_VPERMI2W, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22616, 244},
+ {I_VPERMI2W, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22624, 244},
+ {I_VPERMI2W, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22632, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMT2B[] = {
+ {I_VPERMT2B, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22832, 250},
+ {I_VPERMT2B, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22840, 250},
+ {I_VPERMT2B, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22848, 251},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMT2D[] = {
+ {I_VPERMT2D, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22856, 240},
+ {I_VPERMT2D, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22864, 240},
+ {I_VPERMT2D, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22872, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMT2PD[] = {
+ {I_VPERMT2PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22880, 240},
+ {I_VPERMT2PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22888, 240},
+ {I_VPERMT2PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22896, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMT2PS[] = {
+ {I_VPERMT2PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22904, 240},
+ {I_VPERMT2PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22912, 240},
+ {I_VPERMT2PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22920, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMT2Q[] = {
+ {I_VPERMT2Q, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22928, 240},
+ {I_VPERMT2Q, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22936, 240},
+ {I_VPERMT2Q, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22944, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMT2W[] = {
+ {I_VPERMT2W, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22952, 244},
+ {I_VPERMT2W, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22960, 244},
+ {I_VPERMT2W, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22968, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPERMW[] = {
+ {I_VPERMW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22976, 244},
+ {I_VPERMW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22984, 244},
+ {I_VPERMW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22992, 244},
+ {I_VPERMW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23000, 244},
+ {I_VPERMW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23008, 245},
+ {I_VPERMW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23016, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXPANDD[] = {
+ {I_VPEXPANDD, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23024, 240},
+ {I_VPEXPANDD, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23032, 240},
+ {I_VPEXPANDD, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23040, 241},
+ {I_VPEXPANDD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23024, 240},
+ {I_VPEXPANDD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23032, 240},
+ {I_VPEXPANDD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23040, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXPANDQ[] = {
+ {I_VPEXPANDQ, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23048, 240},
+ {I_VPEXPANDQ, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23056, 240},
+ {I_VPEXPANDQ, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23064, 241},
+ {I_VPEXPANDQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23048, 240},
+ {I_VPEXPANDQ, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23056, 240},
+ {I_VPEXPANDQ, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23064, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPLZCNTD[] = {
+ {I_VPLZCNTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23072, 248},
+ {I_VPLZCNTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23080, 248},
+ {I_VPLZCNTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23088, 249},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPLZCNTQ[] = {
+ {I_VPLZCNTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23096, 248},
+ {I_VPLZCNTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23104, 248},
+ {I_VPLZCNTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23112, 249},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXSQ[] = {
+ {I_VPMAXSQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23360, 240},
+ {I_VPMAXSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23368, 240},
+ {I_VPMAXSQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23376, 240},
+ {I_VPMAXSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23384, 240},
+ {I_VPMAXSQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23392, 241},
+ {I_VPMAXSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23400, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMAXUQ[] = {
+ {I_VPMAXUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23552, 240},
+ {I_VPMAXUQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23560, 240},
+ {I_VPMAXUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23568, 240},
+ {I_VPMAXUQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23576, 240},
+ {I_VPMAXUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23584, 241},
+ {I_VPMAXUQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23592, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINSQ[] = {
+ {I_VPMINSQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23744, 240},
+ {I_VPMINSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23752, 240},
+ {I_VPMINSQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23760, 240},
+ {I_VPMINSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23768, 240},
+ {I_VPMINSQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23776, 241},
+ {I_VPMINSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23784, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMINUQ[] = {
+ {I_VPMINUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23936, 240},
+ {I_VPMINUQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23944, 240},
+ {I_VPMINUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23952, 240},
+ {I_VPMINUQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23960, 240},
+ {I_VPMINUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23968, 241},
+ {I_VPMINUQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23976, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVB2M[] = {
+ {I_VPMOVB2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24032, 244},
+ {I_VPMOVB2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24040, 244},
+ {I_VPMOVB2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24048, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVD2M[] = {
+ {I_VPMOVD2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24056, 242},
+ {I_VPMOVD2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24064, 242},
+ {I_VPMOVD2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24072, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVDB[] = {
+ {I_VPMOVDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24080, 240},
+ {I_VPMOVDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24088, 240},
+ {I_VPMOVDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24096, 241},
+ {I_VPMOVDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24104, 240},
+ {I_VPMOVDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24112, 240},
+ {I_VPMOVDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24120, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVDW[] = {
+ {I_VPMOVDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24128, 240},
+ {I_VPMOVDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24136, 240},
+ {I_VPMOVDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24144, 241},
+ {I_VPMOVDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24152, 240},
+ {I_VPMOVDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24160, 240},
+ {I_VPMOVDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24168, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVM2B[] = {
+ {I_VPMOVM2B, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24176, 244},
+ {I_VPMOVM2B, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24184, 244},
+ {I_VPMOVM2B, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVM2D[] = {
+ {I_VPMOVM2D, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24200, 242},
+ {I_VPMOVM2D, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24208, 242},
+ {I_VPMOVM2D, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24216, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVM2Q[] = {
+ {I_VPMOVM2Q, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24224, 242},
+ {I_VPMOVM2Q, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24232, 242},
+ {I_VPMOVM2Q, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24240, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVM2W[] = {
+ {I_VPMOVM2W, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24248, 244},
+ {I_VPMOVM2W, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24256, 244},
+ {I_VPMOVM2W, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24264, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVQ2M[] = {
+ {I_VPMOVQ2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24272, 242},
+ {I_VPMOVQ2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24280, 242},
+ {I_VPMOVQ2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24288, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVQB[] = {
+ {I_VPMOVQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24296, 240},
+ {I_VPMOVQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24304, 240},
+ {I_VPMOVQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24312, 241},
+ {I_VPMOVQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24320, 240},
+ {I_VPMOVQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24328, 240},
+ {I_VPMOVQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24336, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVQD[] = {
+ {I_VPMOVQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24344, 240},
+ {I_VPMOVQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24352, 240},
+ {I_VPMOVQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24360, 241},
+ {I_VPMOVQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24368, 240},
+ {I_VPMOVQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24376, 240},
+ {I_VPMOVQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24384, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVQW[] = {
+ {I_VPMOVQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24392, 240},
+ {I_VPMOVQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24400, 240},
+ {I_VPMOVQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24408, 241},
+ {I_VPMOVQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24416, 240},
+ {I_VPMOVQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24424, 240},
+ {I_VPMOVQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24432, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSDB[] = {
+ {I_VPMOVSDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24440, 240},
+ {I_VPMOVSDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24448, 240},
+ {I_VPMOVSDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24456, 241},
+ {I_VPMOVSDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24464, 240},
+ {I_VPMOVSDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24472, 240},
+ {I_VPMOVSDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24480, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSDW[] = {
+ {I_VPMOVSDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24488, 240},
+ {I_VPMOVSDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24496, 240},
+ {I_VPMOVSDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24504, 241},
+ {I_VPMOVSDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24512, 240},
+ {I_VPMOVSDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24520, 240},
+ {I_VPMOVSDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24528, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSQB[] = {
+ {I_VPMOVSQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24536, 240},
+ {I_VPMOVSQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24544, 240},
+ {I_VPMOVSQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24552, 241},
+ {I_VPMOVSQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24560, 240},
+ {I_VPMOVSQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24568, 240},
+ {I_VPMOVSQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24576, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSQD[] = {
+ {I_VPMOVSQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24584, 240},
+ {I_VPMOVSQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24592, 240},
+ {I_VPMOVSQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24600, 241},
+ {I_VPMOVSQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24608, 240},
+ {I_VPMOVSQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24616, 240},
+ {I_VPMOVSQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24624, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSQW[] = {
+ {I_VPMOVSQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24632, 240},
+ {I_VPMOVSQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24640, 240},
+ {I_VPMOVSQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24648, 241},
+ {I_VPMOVSQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24656, 240},
+ {I_VPMOVSQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24664, 240},
+ {I_VPMOVSQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24672, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVSWB[] = {
+ {I_VPMOVSWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24680, 244},
+ {I_VPMOVSWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24688, 244},
+ {I_VPMOVSWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24696, 245},
+ {I_VPMOVSWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24704, 244},
+ {I_VPMOVSWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24712, 244},
+ {I_VPMOVSWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24720, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVUSDB[] = {
+ {I_VPMOVUSDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24872, 240},
+ {I_VPMOVUSDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24880, 240},
+ {I_VPMOVUSDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24888, 241},
+ {I_VPMOVUSDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24896, 240},
+ {I_VPMOVUSDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24904, 240},
+ {I_VPMOVUSDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24912, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVUSDW[] = {
+ {I_VPMOVUSDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24920, 240},
+ {I_VPMOVUSDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24928, 240},
+ {I_VPMOVUSDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24936, 241},
+ {I_VPMOVUSDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24944, 240},
+ {I_VPMOVUSDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24952, 240},
+ {I_VPMOVUSDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24960, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVUSQB[] = {
+ {I_VPMOVUSQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24968, 240},
+ {I_VPMOVUSQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24976, 240},
+ {I_VPMOVUSQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24984, 241},
+ {I_VPMOVUSQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24992, 240},
+ {I_VPMOVUSQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25000, 240},
+ {I_VPMOVUSQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25008, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVUSQD[] = {
+ {I_VPMOVUSQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25016, 240},
+ {I_VPMOVUSQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25024, 240},
+ {I_VPMOVUSQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25032, 241},
+ {I_VPMOVUSQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25040, 240},
+ {I_VPMOVUSQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25048, 240},
+ {I_VPMOVUSQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25056, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVUSQW[] = {
+ {I_VPMOVUSQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25064, 240},
+ {I_VPMOVUSQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25072, 240},
+ {I_VPMOVUSQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25080, 241},
+ {I_VPMOVUSQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25088, 240},
+ {I_VPMOVUSQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25096, 240},
+ {I_VPMOVUSQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25104, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVUSWB[] = {
+ {I_VPMOVUSWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25112, 244},
+ {I_VPMOVUSWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25120, 244},
+ {I_VPMOVUSWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25128, 245},
+ {I_VPMOVUSWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25136, 244},
+ {I_VPMOVUSWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25144, 244},
+ {I_VPMOVUSWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25152, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVW2M[] = {
+ {I_VPMOVW2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+25160, 244},
+ {I_VPMOVW2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+25168, 244},
+ {I_VPMOVW2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+25176, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMOVWB[] = {
+ {I_VPMOVWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25184, 244},
+ {I_VPMOVWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25192, 244},
+ {I_VPMOVWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25200, 245},
+ {I_VPMOVWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25208, 244},
+ {I_VPMOVWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25216, 244},
+ {I_VPMOVWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25224, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULLQ[] = {
+ {I_VPMULLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25616, 242},
+ {I_VPMULLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25624, 242},
+ {I_VPMULLQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25632, 242},
+ {I_VPMULLQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25640, 242},
+ {I_VPMULLQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25648, 243},
+ {I_VPMULLQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25656, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMULTISHIFTQB[] = {
+ {I_VPMULTISHIFTQB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25712, 250},
+ {I_VPMULTISHIFTQB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25720, 250},
+ {I_VPMULTISHIFTQB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25728, 250},
+ {I_VPMULTISHIFTQB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25736, 250},
+ {I_VPMULTISHIFTQB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25744, 251},
+ {I_VPMULTISHIFTQB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25752, 251},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPORD[] = {
+ {I_VPORD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25808, 240},
+ {I_VPORD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25816, 240},
+ {I_VPORD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25824, 240},
+ {I_VPORD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25832, 240},
+ {I_VPORD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25840, 241},
+ {I_VPORD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25848, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPORQ[] = {
+ {I_VPORQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25856, 240},
+ {I_VPORQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25864, 240},
+ {I_VPORQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25872, 240},
+ {I_VPORQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25880, 240},
+ {I_VPORQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25888, 241},
+ {I_VPORQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25896, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROLD[] = {
+ {I_VPROLD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9775, 240},
+ {I_VPROLD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9784, 240},
+ {I_VPROLD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9793, 240},
+ {I_VPROLD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9802, 240},
+ {I_VPROLD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9811, 241},
+ {I_VPROLD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9820, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROLQ[] = {
+ {I_VPROLQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9829, 240},
+ {I_VPROLQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9838, 240},
+ {I_VPROLQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9847, 240},
+ {I_VPROLQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9856, 240},
+ {I_VPROLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9865, 241},
+ {I_VPROLQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9874, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROLVD[] = {
+ {I_VPROLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25904, 240},
+ {I_VPROLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25912, 240},
+ {I_VPROLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25920, 240},
+ {I_VPROLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25928, 240},
+ {I_VPROLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25936, 241},
+ {I_VPROLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25944, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPROLVQ[] = {
+ {I_VPROLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25952, 240},
+ {I_VPROLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25960, 240},
+ {I_VPROLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25968, 240},
+ {I_VPROLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25976, 240},
+ {I_VPROLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25984, 241},
+ {I_VPROLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25992, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPRORD[] = {
+ {I_VPRORD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9883, 240},
+ {I_VPRORD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9892, 240},
+ {I_VPRORD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9901, 240},
+ {I_VPRORD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9910, 240},
+ {I_VPRORD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9919, 241},
+ {I_VPRORD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9928, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPRORQ[] = {
+ {I_VPRORQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9937, 240},
+ {I_VPRORQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9946, 240},
+ {I_VPRORQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9955, 240},
+ {I_VPRORQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9964, 240},
+ {I_VPRORQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9973, 241},
+ {I_VPRORQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9982, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPRORVD[] = {
+ {I_VPRORVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26000, 240},
+ {I_VPRORVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26008, 240},
+ {I_VPRORVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26016, 240},
+ {I_VPRORVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26024, 240},
+ {I_VPRORVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26032, 241},
+ {I_VPRORVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26040, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPRORVQ[] = {
+ {I_VPRORVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26048, 240},
+ {I_VPRORVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26056, 240},
+ {I_VPRORVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26064, 240},
+ {I_VPRORVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26072, 240},
+ {I_VPRORVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26080, 241},
+ {I_VPRORVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26088, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSCATTERDD[] = {
+ {I_VPSCATTERDD, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9991, 240},
+ {I_VPSCATTERDD, 2, {YMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10000, 240},
+ {I_VPSCATTERDD, 2, {ZMEM|BITS32,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10009, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSCATTERDQ[] = {
+ {I_VPSCATTERDQ, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10018, 240},
+ {I_VPSCATTERDQ, 2, {XMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10027, 240},
+ {I_VPSCATTERDQ, 2, {YMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10036, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSCATTERQD[] = {
+ {I_VPSCATTERQD, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10045, 240},
+ {I_VPSCATTERQD, 2, {YMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10054, 240},
+ {I_VPSCATTERQD, 2, {ZMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10063, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSCATTERQQ[] = {
+ {I_VPSCATTERQQ, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10072, 240},
+ {I_VPSCATTERQQ, 2, {YMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10081, 240},
+ {I_VPSCATTERQQ, 2, {ZMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10090, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSLLVW[] = {
+ {I_VPSLLVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26384, 244},
+ {I_VPSLLVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26392, 244},
+ {I_VPSLLVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26400, 244},
+ {I_VPSLLVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26408, 244},
+ {I_VPSLLVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26416, 245},
+ {I_VPSLLVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26424, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRAQ[] = {
+ {I_VPSRAQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26528, 240},
+ {I_VPSRAQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26536, 240},
+ {I_VPSRAQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26544, 240},
+ {I_VPSRAQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26552, 240},
+ {I_VPSRAQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26560, 241},
+ {I_VPSRAQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26568, 241},
+ {I_VPSRAQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10450, 240},
+ {I_VPSRAQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10459, 240},
+ {I_VPSRAQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10468, 240},
+ {I_VPSRAQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10477, 240},
+ {I_VPSRAQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10486, 241},
+ {I_VPSRAQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10495, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRAVQ[] = {
+ {I_VPSRAVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26624, 240},
+ {I_VPSRAVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26632, 240},
+ {I_VPSRAVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26640, 240},
+ {I_VPSRAVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26648, 240},
+ {I_VPSRAVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26656, 241},
+ {I_VPSRAVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26664, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRAVW[] = {
+ {I_VPSRAVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26672, 244},
+ {I_VPSRAVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26680, 244},
+ {I_VPSRAVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26688, 244},
+ {I_VPSRAVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26696, 244},
+ {I_VPSRAVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26704, 245},
+ {I_VPSRAVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26712, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSRLVW[] = {
+ {I_VPSRLVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26960, 244},
+ {I_VPSRLVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26968, 244},
+ {I_VPSRLVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26976, 244},
+ {I_VPSRLVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26984, 244},
+ {I_VPSRLVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26992, 245},
+ {I_VPSRLVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27000, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTERNLOGD[] = {
+ {I_VPTERNLOGD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10774, 240},
+ {I_VPTERNLOGD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10783, 240},
+ {I_VPTERNLOGD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10792, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTERNLOGQ[] = {
+ {I_VPTERNLOGQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10801, 240},
+ {I_VPTERNLOGQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10810, 240},
+ {I_VPTERNLOGQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10819, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTMB[] = {
+ {I_VPTESTMB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27440, 244},
+ {I_VPTESTMB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27448, 244},
+ {I_VPTESTMB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27456, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTMD[] = {
+ {I_VPTESTMD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27464, 240},
+ {I_VPTESTMD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27472, 240},
+ {I_VPTESTMD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27480, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTMQ[] = {
+ {I_VPTESTMQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27488, 240},
+ {I_VPTESTMQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27496, 240},
+ {I_VPTESTMQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27504, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTMW[] = {
+ {I_VPTESTMW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27512, 244},
+ {I_VPTESTMW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27520, 244},
+ {I_VPTESTMW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27528, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTNMB[] = {
+ {I_VPTESTNMB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27536, 244},
+ {I_VPTESTNMB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27544, 244},
+ {I_VPTESTNMB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27552, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTNMD[] = {
+ {I_VPTESTNMD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27560, 240},
+ {I_VPTESTNMD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27568, 240},
+ {I_VPTESTNMD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27576, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTNMQ[] = {
+ {I_VPTESTNMQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27584, 240},
+ {I_VPTESTNMQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27592, 240},
+ {I_VPTESTNMQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27600, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPTESTNMW[] = {
+ {I_VPTESTNMW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27608, 244},
+ {I_VPTESTNMW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27616, 244},
+ {I_VPTESTNMW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27624, 245},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPXORD[] = {
+ {I_VPXORD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28016, 240},
+ {I_VPXORD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28024, 240},
+ {I_VPXORD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28032, 240},
+ {I_VPXORD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28040, 240},
+ {I_VPXORD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28048, 241},
+ {I_VPXORD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28056, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPXORQ[] = {
+ {I_VPXORQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28064, 240},
+ {I_VPXORQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28072, 240},
+ {I_VPXORQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28080, 240},
+ {I_VPXORQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28088, 240},
+ {I_VPXORQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28096, 241},
+ {I_VPXORQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28104, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRANGEPD[] = {
+ {I_VRANGEPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10828, 242},
+ {I_VRANGEPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10837, 242},
+ {I_VRANGEPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10846, 242},
+ {I_VRANGEPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10855, 242},
+ {I_VRANGEPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+10864, 243},
+ {I_VRANGEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+10873, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRANGEPS[] = {
+ {I_VRANGEPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10882, 242},
+ {I_VRANGEPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10891, 242},
+ {I_VRANGEPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10900, 242},
+ {I_VRANGEPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10909, 242},
+ {I_VRANGEPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+10918, 243},
+ {I_VRANGEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+10927, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRANGESD[] = {
+ {I_VRANGESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+10936, 243},
+ {I_VRANGESD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+10945, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRANGESS[] = {
+ {I_VRANGESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+10954, 243},
+ {I_VRANGESS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+10963, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP14PD[] = {
+ {I_VRCP14PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28112, 240},
+ {I_VRCP14PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28120, 240},
+ {I_VRCP14PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28128, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP14PS[] = {
+ {I_VRCP14PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28136, 240},
+ {I_VRCP14PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28144, 240},
+ {I_VRCP14PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28152, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP14SD[] = {
+ {I_VRCP14SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28160, 241},
+ {I_VRCP14SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28168, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP14SS[] = {
+ {I_VRCP14SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28176, 241},
+ {I_VRCP14SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28184, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP28PD[] = {
+ {I_VRCP28PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+28192, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP28PS[] = {
+ {I_VRCP28PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+28200, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP28SD[] = {
+ {I_VRCP28SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28208, 246},
+ {I_VRCP28SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28216, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCP28SS[] = {
+ {I_VRCP28SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28224, 246},
+ {I_VRCP28SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28232, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VREDUCEPD[] = {
+ {I_VREDUCEPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10972, 242},
+ {I_VREDUCEPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10981, 242},
+ {I_VREDUCEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+10990, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VREDUCEPS[] = {
+ {I_VREDUCEPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10999, 242},
+ {I_VREDUCEPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11008, 242},
+ {I_VREDUCEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+11017, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VREDUCESD[] = {
+ {I_VREDUCESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11026, 243},
+ {I_VREDUCESD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11035, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VREDUCESS[] = {
+ {I_VREDUCESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11044, 243},
+ {I_VREDUCESS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11053, 243},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRNDSCALEPD[] = {
+ {I_VRNDSCALEPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11062, 240},
+ {I_VRNDSCALEPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11071, 240},
+ {I_VRNDSCALEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+11080, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRNDSCALEPS[] = {
+ {I_VRNDSCALEPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11089, 240},
+ {I_VRNDSCALEPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11098, 240},
+ {I_VRNDSCALEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+11107, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRNDSCALESD[] = {
+ {I_VRNDSCALESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11116, 241},
+ {I_VRNDSCALESD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11125, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRNDSCALESS[] = {
+ {I_VRNDSCALESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11134, 241},
+ {I_VRNDSCALESS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11143, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT14PD[] = {
+ {I_VRSQRT14PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28240, 240},
+ {I_VRSQRT14PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28248, 240},
+ {I_VRSQRT14PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28256, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT14PS[] = {
+ {I_VRSQRT14PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28264, 240},
+ {I_VRSQRT14PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28272, 240},
+ {I_VRSQRT14PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28280, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT14SD[] = {
+ {I_VRSQRT14SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28288, 241},
+ {I_VRSQRT14SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28296, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT14SS[] = {
+ {I_VRSQRT14SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28304, 241},
+ {I_VRSQRT14SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28312, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT28PD[] = {
+ {I_VRSQRT28PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+28320, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT28PS[] = {
+ {I_VRSQRT28PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+28328, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT28SD[] = {
+ {I_VRSQRT28SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28336, 246},
+ {I_VRSQRT28SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28344, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRT28SS[] = {
+ {I_VRSQRT28SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28352, 246},
+ {I_VRSQRT28SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28360, 246},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCALEFPD[] = {
+ {I_VSCALEFPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28368, 240},
+ {I_VSCALEFPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28376, 240},
+ {I_VSCALEFPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28384, 240},
+ {I_VSCALEFPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28392, 240},
+ {I_VSCALEFPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+28400, 241},
+ {I_VSCALEFPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+28408, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCALEFPS[] = {
+ {I_VSCALEFPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28416, 240},
+ {I_VSCALEFPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28424, 240},
+ {I_VSCALEFPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28432, 240},
+ {I_VSCALEFPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28440, 240},
+ {I_VSCALEFPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+28448, 241},
+ {I_VSCALEFPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+28456, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCALEFSD[] = {
+ {I_VSCALEFSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28464, 241},
+ {I_VSCALEFSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28472, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCALEFSS[] = {
+ {I_VSCALEFSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28480, 241},
+ {I_VSCALEFSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28488, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERDPD[] = {
+ {I_VSCATTERDPD, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11152, 240},
+ {I_VSCATTERDPD, 2, {XMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11161, 240},
+ {I_VSCATTERDPD, 2, {YMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11170, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERDPS[] = {
+ {I_VSCATTERDPS, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11179, 240},
+ {I_VSCATTERDPS, 2, {YMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11188, 240},
+ {I_VSCATTERDPS, 2, {ZMEM|BITS32,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11197, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF0DPD[] = {
+ {I_VSCATTERPF0DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11206, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF0DPS[] = {
+ {I_VSCATTERPF0DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11215, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF0QPD[] = {
+ {I_VSCATTERPF0QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11224, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF0QPS[] = {
+ {I_VSCATTERPF0QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11233, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF1DPD[] = {
+ {I_VSCATTERPF1DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11242, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF1DPS[] = {
+ {I_VSCATTERPF1DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11251, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF1QPD[] = {
+ {I_VSCATTERPF1QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11260, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERPF1QPS[] = {
+ {I_VSCATTERPF1QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11269, 247},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERQPD[] = {
+ {I_VSCATTERQPD, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11278, 240},
+ {I_VSCATTERQPD, 2, {YMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11287, 240},
+ {I_VSCATTERQPD, 2, {ZMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11296, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCATTERQPS[] = {
+ {I_VSCATTERQPS, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11305, 240},
+ {I_VSCATTERQPS, 2, {YMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11314, 240},
+ {I_VSCATTERQPS, 2, {ZMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11323, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSHUFF32X4[] = {
+ {I_VSHUFF32X4, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11332, 240},
+ {I_VSHUFF32X4, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11341, 240},
+ {I_VSHUFF32X4, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11350, 241},
+ {I_VSHUFF32X4, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11359, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSHUFF64X2[] = {
+ {I_VSHUFF64X2, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11368, 240},
+ {I_VSHUFF64X2, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11377, 240},
+ {I_VSHUFF64X2, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11386, 241},
+ {I_VSHUFF64X2, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11395, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSHUFI32X4[] = {
+ {I_VSHUFI32X4, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11404, 240},
+ {I_VSHUFI32X4, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11413, 240},
+ {I_VSHUFI32X4, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11422, 241},
+ {I_VSHUFI32X4, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11431, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSHUFI64X2[] = {
+ {I_VSHUFI64X2, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11440, 240},
+ {I_VSHUFI64X2, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11449, 240},
+ {I_VSHUFI64X2, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11458, 241},
+ {I_VSHUFI64X2, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11467, 241},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDPKRU[] = {
+ {I_RDPKRU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46072, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRPKRU[] = {
+ {I_WRPKRU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46078, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDPID[] = {
+ {I_RDPID, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42322, 254},
+ {I_RDPID, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42321, 136},
+ {I_RDPID, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42322, 255},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLFLUSHOPT[] = {
+ {I_CLFLUSHOPT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45951, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLWB[] = {
+ {I_CLWB, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45957, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCOMMIT[] = {
+ {I_PCOMMIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45963, 256},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLZERO[] = {
+ {I_CLZERO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45982, 257},
+ {I_CLZERO, 1, {REG_AX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45969, 258},
+ {I_CLZERO, 1, {REG_EAX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45975, 257},
+ {I_CLZERO, 1, {REG_RAX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45981, 259},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PTWRITE[] = {
+ {I_PTWRITE, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34020, 135},
+ {I_PTWRITE, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34019, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLDEMOTE[] = {
+ {I_CLDEMOTE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45987, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVDIRI[] = {
+ {I_MOVDIRI, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42328, 260},
+ {I_MOVDIRI, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42335, 261},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_MOVDIR64B[] = {
+ {I_MOVDIR64B, 2, {REG_GPR|BITS16,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29008, 254},
+ {I_MOVDIR64B, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29016, 135},
+ {I_MOVDIR64B, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+11584, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_PCONFIG[] = {
+ {I_PCONFIG, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45993, 135},
+ {I_PCONFIG, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45993, 285},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TPAUSE[] = {
+ {I_TPAUSE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45957, 135},
+ {I_TPAUSE, 3, {REG_GPR|BITS32,REG_EDX,REG_EAX,0,0}, NO_DECORATOR, nasm_bytecodes+45957, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UMONITOR[] = {
+ {I_UMONITOR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42342, 254},
+ {I_UMONITOR, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42349, 135},
+ {I_UMONITOR, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+29024, 136},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UMWAIT[] = {
+ {I_UMWAIT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45999, 135},
+ {I_UMWAIT, 3, {REG_GPR|BITS32,REG_EDX,REG_EAX,0,0}, NO_DECORATOR, nasm_bytecodes+45999, 135},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WBNOINVD[] = {
+ {I_WBNOINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49182, 135},
+ {I_WBNOINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49182, 287},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_GF2P8AFFINEINVQB[] = {
+ {I_GF2P8AFFINEINVQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29032, 262},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGF2P8AFFINEINVQB[] = {
+ {I_VGF2P8AFFINEINVQB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29040, 263},
+ {I_VGF2P8AFFINEINVQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29048, 263},
+ {I_VGF2P8AFFINEINVQB, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29056, 263},
+ {I_VGF2P8AFFINEINVQB, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29064, 263},
+ {I_VGF2P8AFFINEINVQB, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11593, 264},
+ {I_VGF2P8AFFINEINVQB, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11602, 264},
+ {I_VGF2P8AFFINEINVQB, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11611, 264},
+ {I_VGF2P8AFFINEINVQB, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11620, 264},
+ {I_VGF2P8AFFINEINVQB, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11629, 265},
+ {I_VGF2P8AFFINEINVQB, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11638, 265},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_GF2P8AFFINEQB[] = {
+ {I_GF2P8AFFINEQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29072, 262},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGF2P8AFFINEQB[] = {
+ {I_VGF2P8AFFINEQB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29080, 263},
+ {I_VGF2P8AFFINEQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29088, 263},
+ {I_VGF2P8AFFINEQB, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29096, 263},
+ {I_VGF2P8AFFINEQB, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29104, 263},
+ {I_VGF2P8AFFINEQB, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11647, 264},
+ {I_VGF2P8AFFINEQB, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11656, 264},
+ {I_VGF2P8AFFINEQB, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11665, 264},
+ {I_VGF2P8AFFINEQB, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11674, 264},
+ {I_VGF2P8AFFINEQB, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11683, 265},
+ {I_VGF2P8AFFINEQB, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11692, 265},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_GF2P8MULB[] = {
+ {I_GF2P8MULB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+42356, 262},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGF2P8MULB[] = {
+ {I_VGF2P8MULB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+42363, 263},
+ {I_VGF2P8MULB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+42370, 263},
+ {I_VGF2P8MULB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+42377, 263},
+ {I_VGF2P8MULB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+42384, 263},
+ {I_VGF2P8MULB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29112, 264},
+ {I_VGF2P8MULB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29120, 264},
+ {I_VGF2P8MULB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29128, 264},
+ {I_VGF2P8MULB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29136, 264},
+ {I_VGF2P8MULB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29144, 265},
+ {I_VGF2P8MULB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29152, 265},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMPRESSB[] = {
+ {I_VPCOMPRESSB, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29160, 266},
+ {I_VPCOMPRESSB, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29168, 266},
+ {I_VPCOMPRESSB, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29176, 267},
+ {I_VPCOMPRESSB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29184, 266},
+ {I_VPCOMPRESSB, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29192, 266},
+ {I_VPCOMPRESSB, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29200, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPCOMPRESSW[] = {
+ {I_VPCOMPRESSW, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29208, 266},
+ {I_VPCOMPRESSW, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29216, 266},
+ {I_VPCOMPRESSW, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29224, 267},
+ {I_VPCOMPRESSW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29232, 266},
+ {I_VPCOMPRESSW, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29240, 266},
+ {I_VPCOMPRESSW, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29248, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXPANDB[] = {
+ {I_VPEXPANDB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29256, 266},
+ {I_VPEXPANDB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29264, 266},
+ {I_VPEXPANDB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29272, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPEXPANDW[] = {
+ {I_VPEXPANDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29280, 266},
+ {I_VPEXPANDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29288, 266},
+ {I_VPEXPANDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29296, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLDW[] = {
+ {I_VPSHLDW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11701, 266},
+ {I_VPSHLDW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11710, 266},
+ {I_VPSHLDW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11719, 266},
+ {I_VPSHLDW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11728, 266},
+ {I_VPSHLDW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11737, 267},
+ {I_VPSHLDW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11746, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLDD[] = {
+ {I_VPSHLDD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11755, 266},
+ {I_VPSHLDD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11764, 266},
+ {I_VPSHLDD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11773, 266},
+ {I_VPSHLDD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11782, 266},
+ {I_VPSHLDD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11791, 267},
+ {I_VPSHLDD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11800, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLDQ[] = {
+ {I_VPSHLDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11809, 266},
+ {I_VPSHLDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11818, 266},
+ {I_VPSHLDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11827, 266},
+ {I_VPSHLDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11836, 266},
+ {I_VPSHLDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11845, 267},
+ {I_VPSHLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11854, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLDVW[] = {
+ {I_VPSHLDVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29304, 266},
+ {I_VPSHLDVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29312, 266},
+ {I_VPSHLDVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29320, 266},
+ {I_VPSHLDVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29328, 266},
+ {I_VPSHLDVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29336, 267},
+ {I_VPSHLDVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29344, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLDVD[] = {
+ {I_VPSHLDVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29352, 266},
+ {I_VPSHLDVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29360, 266},
+ {I_VPSHLDVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29368, 266},
+ {I_VPSHLDVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29376, 266},
+ {I_VPSHLDVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29384, 267},
+ {I_VPSHLDVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29392, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHLDVQ[] = {
+ {I_VPSHLDVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29400, 266},
+ {I_VPSHLDVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29408, 266},
+ {I_VPSHLDVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29416, 266},
+ {I_VPSHLDVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29424, 266},
+ {I_VPSHLDVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29432, 267},
+ {I_VPSHLDVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29440, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHRDW[] = {
+ {I_VPSHRDW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11863, 266},
+ {I_VPSHRDW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11872, 266},
+ {I_VPSHRDW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11881, 266},
+ {I_VPSHRDW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11890, 266},
+ {I_VPSHRDW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11899, 267},
+ {I_VPSHRDW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11908, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHRDD[] = {
+ {I_VPSHRDD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11917, 266},
+ {I_VPSHRDD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11926, 266},
+ {I_VPSHRDD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11935, 266},
+ {I_VPSHRDD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11944, 266},
+ {I_VPSHRDD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11953, 267},
+ {I_VPSHRDD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11962, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHRDQ[] = {
+ {I_VPSHRDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11971, 266},
+ {I_VPSHRDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11980, 266},
+ {I_VPSHRDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11989, 266},
+ {I_VPSHRDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11998, 266},
+ {I_VPSHRDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+12007, 267},
+ {I_VPSHRDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+12016, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHRDVW[] = {
+ {I_VPSHRDVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29448, 266},
+ {I_VPSHRDVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29456, 266},
+ {I_VPSHRDVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29464, 266},
+ {I_VPSHRDVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29472, 266},
+ {I_VPSHRDVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29480, 267},
+ {I_VPSHRDVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29488, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHRDVD[] = {
+ {I_VPSHRDVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29496, 266},
+ {I_VPSHRDVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29504, 266},
+ {I_VPSHRDVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29512, 266},
+ {I_VPSHRDVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29520, 266},
+ {I_VPSHRDVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29528, 267},
+ {I_VPSHRDVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29536, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHRDVQ[] = {
+ {I_VPSHRDVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29544, 266},
+ {I_VPSHRDVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29552, 266},
+ {I_VPSHRDVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29560, 266},
+ {I_VPSHRDVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29568, 266},
+ {I_VPSHRDVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29576, 267},
+ {I_VPSHRDVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29584, 267},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBUSD[] = {
+ {I_VPDPBUSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29592, 268},
+ {I_VPDPBUSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29600, 268},
+ {I_VPDPBUSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29608, 268},
+ {I_VPDPBUSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29616, 268},
+ {I_VPDPBUSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29624, 269},
+ {I_VPDPBUSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29632, 269},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPBUSDS[] = {
+ {I_VPDPBUSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29640, 268},
+ {I_VPDPBUSDS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29648, 268},
+ {I_VPDPBUSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29656, 268},
+ {I_VPDPBUSDS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29664, 268},
+ {I_VPDPBUSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29672, 269},
+ {I_VPDPBUSDS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29680, 269},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPWSSD[] = {
+ {I_VPDPWSSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29688, 268},
+ {I_VPDPWSSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29696, 268},
+ {I_VPDPWSSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29704, 268},
+ {I_VPDPWSSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29712, 268},
+ {I_VPDPWSSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29720, 269},
+ {I_VPDPWSSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29728, 269},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPDPWSSDS[] = {
+ {I_VPDPWSSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29736, 268},
+ {I_VPDPWSSDS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29744, 268},
+ {I_VPDPWSSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29752, 268},
+ {I_VPDPWSSDS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29760, 268},
+ {I_VPDPWSSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29768, 269},
+ {I_VPDPWSSDS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29776, 269},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPOPCNTB[] = {
+ {I_VPOPCNTB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29784, 270},
+ {I_VPOPCNTB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29792, 270},
+ {I_VPOPCNTB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29800, 271},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPOPCNTW[] = {
+ {I_VPOPCNTW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29808, 270},
+ {I_VPOPCNTW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29816, 270},
+ {I_VPOPCNTW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29824, 271},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPOPCNTD[] = {
+ {I_VPOPCNTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29832, 272},
+ {I_VPOPCNTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29840, 272},
+ {I_VPOPCNTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29848, 273},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPOPCNTQ[] = {
+ {I_VPOPCNTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29856, 272},
+ {I_VPOPCNTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29864, 272},
+ {I_VPOPCNTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29872, 273},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPSHUFBITQMB[] = {
+ {I_VPSHUFBITQMB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29880, 270},
+ {I_VPSHUFBITQMB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29888, 270},
+ {I_VPSHUFBITQMB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29896, 271},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_V4FMADDPS[] = {
+ {I_V4FMADDPS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29904, 274},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_V4FNMADDPS[] = {
+ {I_V4FNMADDPS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29912, 274},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_V4FMADDSS[] = {
+ {I_V4FMADDSS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29920, 274},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_V4FNMADDSS[] = {
+ {I_V4FNMADDSS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29928, 274},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_V4DPWSSDS[] = {
+ {I_V4DPWSSDS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29936, 275},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_V4DPWSSD[] = {
+ {I_V4DPWSSD, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29944, 275},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENCLS[] = {
+ {I_ENCLS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46005, 276},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENCLU[] = {
+ {I_ENCLU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46011, 276},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENCLV[] = {
+ {I_ENCLV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46017, 276},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLRSSBSY[] = {
+ {I_CLRSSBSY, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42350, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENDBR32[] = {
+ {I_ENDBR32, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46023, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENDBR64[] = {
+ {I_ENDBR64, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46029, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INCSSPD[] = {
+ {I_INCSSPD, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42391, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_INCSSPQ[] = {
+ {I_INCSSPQ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42398, 278},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDSSPD[] = {
+ {I_RDSSPD, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42405, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDSSPQ[] = {
+ {I_RDSSPQ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42412, 278},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RSTORSSP[] = {
+ {I_RSTORSSP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46035, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SAVEPREVSSP[] = {
+ {I_SAVEPREVSSP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46041, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SETSSBSY[] = {
+ {I_SETSSBSY, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46047, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRUSSD[] = {
+ {I_WRUSSD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29952, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRUSSQ[] = {
+ {I_WRUSSQ, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29960, 278},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRSSD[] = {
+ {I_WRSSD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42419, 277},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRSSQ[] = {
+ {I_WRSSQ, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42426, 278},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENQCMD[] = {
+ {I_ENQCMD, 2, {REG_GPR|BITS16,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29968, 279},
+ {I_ENQCMD, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29968, 279},
+ {I_ENQCMD, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29976, 280},
+ {I_ENQCMD, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29984, 281},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_ENQCMDS[] = {
+ {I_ENQCMDS, 2, {REG_GPR|BITS16,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29992, 282},
+ {I_ENQCMDS, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29992, 282},
+ {I_ENQCMDS, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+30000, 283},
+ {I_ENQCMDS, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+30008, 284},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SERIALIZE[] = {
+ {I_SERIALIZE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46053, 286},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XRESLDTRK[] = {
+ {I_XRESLDTRK, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46059, 288},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_XSUSLDTRK[] = {
+ {I_XSUSLDTRK, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46065, 288},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTNE2PS2BF16[] = {
+ {I_VCVTNE2PS2BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30016, 289},
+ {I_VCVTNE2PS2BF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30024, 289},
+ {I_VCVTNE2PS2BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30032, 289},
+ {I_VCVTNE2PS2BF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30040, 289},
+ {I_VCVTNE2PS2BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30048, 289},
+ {I_VCVTNE2PS2BF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30056, 289},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDPBF16PS[] = {
+ {I_VDPBF16PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30112, 289},
+ {I_VDPBF16PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30120, 289},
+ {I_VDPBF16PS, 3, {YMMREG,YMMREG,RM_YMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30128, 289},
+ {I_VDPBF16PS, 2, {YMMREG,RM_YMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30136, 289},
+ {I_VDPBF16PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30144, 289},
+ {I_VDPBF16PS, 2, {ZMMREG,RM_ZMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30152, 289},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VP2INTERSECTD[] = {
+ {I_VP2INTERSECTD, 3, {KREG|RS2,XMMREG,RM_XMM|BITS128,0,0}, {0,0,B32,0,0}, nasm_bytecodes+30160, 289},
+ {I_VP2INTERSECTD, 3, {KREG|RS2,YMMREG,RM_YMM|BITS128,0,0}, {0,0,B32,0,0}, nasm_bytecodes+30168, 289},
+ {I_VP2INTERSECTD, 3, {KREG|RS2,ZMMREG,RM_ZMM|BITS128,0,0}, {0,0,B32,0,0}, nasm_bytecodes+30176, 289},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_LDTILECFG[] = {
+ {I_LDTILECFG, 1, {MEMORY|BITS512,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42433, 290},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STTILECFG[] = {
+ {I_STTILECFG, 1, {MEMORY|BITS512,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42440, 290},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TDPBF16PS[] = {
+ {I_TDPBF16PS, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42447, 291},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TDPBSSD[] = {
+ {I_TDPBSSD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42454, 292},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TDPBSUD[] = {
+ {I_TDPBSUD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42461, 292},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TDPBUSD[] = {
+ {I_TDPBUSD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42468, 292},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TDPBUUD[] = {
+ {I_TDPBUUD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42475, 292},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TILELOADD[] = {
+ {I_TILELOADD, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42482, 293},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TILELOADDT1[] = {
+ {I_TILELOADDT1, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42489, 293},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TILERELEASE[] = {
+ {I_TILERELEASE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42496, 294},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TILESTORED[] = {
+ {I_TILESTORED, 2, {MEMORY,TMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42503, 293},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TILEZERO[] = {
+ {I_TILEZERO, 1, {TMMREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30184, 294},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDPH[] = {
+ {I_VADDPH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30192, 295},
+ {I_VADDPH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30200, 295},
+ {I_VADDPH, 3, {YMMREG,YMMREG,RM_YMM|BITS16,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30208, 295},
+ {I_VADDPH, 2, {YMMREG,RM_YMM|BITS16,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30216, 295},
+ {I_VADDPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS16,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+30224, 296},
+ {I_VADDPH, 2, {ZMMREG,RM_ZMM|BITS16,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30232, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VADDSH[] = {
+ {I_VADDSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+30240, 296},
+ {I_VADDSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+30248, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPPH[] = {
+ {I_VCMPPH, 4, {KREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+12025, 295},
+ {I_VCMPPH, 3, {KREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12034, 295},
+ {I_VCMPPH, 4, {KREG,YMMREG,RM_YMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+12043, 295},
+ {I_VCMPPH, 3, {KREG,RM_YMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12052, 295},
+ {I_VCMPPH, 4, {KREG,ZMMREG,RM_ZMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,B16|SAE,0,0}, nasm_bytecodes+12061, 296},
+ {I_VCMPPH, 3, {KREG,RM_ZMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,B16|SAE,0,0,0}, nasm_bytecodes+12070, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCMPSH[] = {
+ {I_VCMPSH, 4, {KREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+12079, 296},
+ {I_VCMPSH, 3, {KREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+12088, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCOMISH[] = {
+ {I_VCOMISH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30256, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTDQ2PH[] = {
+ {I_VCVTDQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30264, 295},
+ {I_VCVTDQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30272, 295},
+ {I_VCVTDQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+30280, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPD2PH[] = {
+ {I_VCVTPD2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30288, 295},
+ {I_VCVTPD2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30296, 295},
+ {I_VCVTPD2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+30304, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2DQ[] = {
+ {I_VCVTPH2DQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30312, 295},
+ {I_VCVTPH2DQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30320, 295},
+ {I_VCVTPH2DQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30328, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2PD[] = {
+ {I_VCVTPH2PD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30336, 295},
+ {I_VCVTPH2PD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30344, 295},
+ {I_VCVTPH2PD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30352, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2PSX[] = {
+ {I_VCVTPH2PSX, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30360, 295},
+ {I_VCVTPH2PSX, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30368, 295},
+ {I_VCVTPH2PSX, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30376, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2QQ[] = {
+ {I_VCVTPH2QQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30384, 295},
+ {I_VCVTPH2QQ, 2, {YMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30392, 295},
+ {I_VCVTPH2QQ, 2, {ZMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30400, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2UDQ[] = {
+ {I_VCVTPH2UDQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30408, 295},
+ {I_VCVTPH2UDQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30416, 295},
+ {I_VCVTPH2UDQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30424, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2UQQ[] = {
+ {I_VCVTPH2UQQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30432, 295},
+ {I_VCVTPH2UQQ, 2, {YMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30440, 295},
+ {I_VCVTPH2UQQ, 2, {ZMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30448, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2UW[] = {
+ {I_VCVTPH2UW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30456, 295},
+ {I_VCVTPH2UW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30464, 295},
+ {I_VCVTPH2UW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30472, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTPH2W[] = {
+ {I_VCVTPH2W, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30480, 295},
+ {I_VCVTPH2W, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30488, 295},
+ {I_VCVTPH2W, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30496, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTQQ2PH[] = {
+ {I_VCVTQQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30528, 295},
+ {I_VCVTQQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30536, 295},
+ {I_VCVTQQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+30544, 295},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSD2SH[] = {
+ {I_VCVTSD2SH, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+30552, 296},
+ {I_VCVTSD2SH, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+30560, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSH2SD[] = {
+ {I_VCVTSH2SD, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {0,0,SAE,0,0}, nasm_bytecodes+30568, 296},
+ {I_VCVTSH2SD, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30576, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSH2SI[] = {
+ {I_VCVTSH2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30584, 296},
+ {I_VCVTSH2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30592, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSH2SS[] = {
+ {I_VCVTSH2SS, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+30600, 296},
+ {I_VCVTSH2SS, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+30608, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSH2USI[] = {
+ {I_VCVTSH2USI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30616, 296},
+ {I_VCVTSH2USI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30624, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSI2SH[] = {
+ {I_VCVTSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,0,ER,0,0}, nasm_bytecodes+30632, 296},
+ {I_VCVTSI2SH, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30640, 296},
+ {I_VCVTSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,0,ER,0,0}, nasm_bytecodes+30648, 296},
+ {I_VCVTSI2SH, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30656, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTSS2SH[] = {
+ {I_VCVTSS2SH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {0,0,ER,0,0}, nasm_bytecodes+30664, 296},
+ {I_VCVTSS2SH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30672, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPH2DQ[] = {
+ {I_VCVTTPH2DQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30680, 295},
+ {I_VCVTTPH2DQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30688, 295},
+ {I_VCVTTPH2DQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30696, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPH2QQ[] = {
+ {I_VCVTTPH2QQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30704, 295},
+ {I_VCVTTPH2QQ, 2, {YMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30712, 295},
+ {I_VCVTTPH2QQ, 2, {ZMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30720, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPH2UDQ[] = {
+ {I_VCVTTPH2UDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30728, 295},
+ {I_VCVTTPH2UDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30736, 295},
+ {I_VCVTTPH2UDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30744, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPH2UQQ[] = {
+ {I_VCVTTPH2UQQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30752, 295},
+ {I_VCVTTPH2UQQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30760, 295},
+ {I_VCVTTPH2UQQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30768, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPH2UW[] = {
+ {I_VCVTTPH2UW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30776, 295},
+ {I_VCVTTPH2UW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30784, 295},
+ {I_VCVTTPH2UW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30792, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTPH2W[] = {
+ {I_VCVTTPH2W, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30800, 295},
+ {I_VCVTTPH2W, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30808, 295},
+ {I_VCVTTPH2W, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30816, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTSH2SI[] = {
+ {I_VCVTTSH2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30824, 296},
+ {I_VCVTTSH2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30832, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTTSH2USI[] = {
+ {I_VCVTTSH2USI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30840, 296},
+ {I_VCVTTSH2USI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30848, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUDQ2PH[] = {
+ {I_VCVTUDQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30856, 295},
+ {I_VCVTUDQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30864, 295},
+ {I_VCVTUDQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30872, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUQQ2PH[] = {
+ {I_VCVTUQQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30880, 295},
+ {I_VCVTUQQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30888, 295},
+ {I_VCVTUQQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30896, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUSI2SH[] = {
+ {I_VCVTUSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,ER,0,0}, nasm_bytecodes+30904, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTUW2PH[] = {
+ {I_VCVTUW2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30920, 295},
+ {I_VCVTUW2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30928, 295},
+ {I_VCVTUW2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30936, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VCVTW2PH[] = {
+ {I_VCVTW2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30944, 295},
+ {I_VCVTW2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30952, 295},
+ {I_VCVTW2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30960, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDIVPH[] = {
+ {I_VDIVPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30968, 295},
+ {I_VDIVPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30976, 295},
+ {I_VDIVPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30984, 295},
+ {I_VDIVPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30992, 295},
+ {I_VDIVPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31000, 296},
+ {I_VDIVPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31008, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VDIVSH[] = {
+ {I_VDIVSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31016, 296},
+ {I_VDIVSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31024, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFCMADDCPH[] = {
+ {I_VFCMADDCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31032, 295},
+ {I_VFCMADDCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31040, 295},
+ {I_VFCMADDCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31048, 295},
+ {I_VFCMADDCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31056, 295},
+ {I_VFCMADDCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31064, 295},
+ {I_VFCMADDCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31072, 295},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDCPH[] = {
+ {I_VFMADDCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31080, 295},
+ {I_VFMADDCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31088, 295},
+ {I_VFMADDCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31096, 295},
+ {I_VFMADDCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31104, 295},
+ {I_VFMADDCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31112, 295},
+ {I_VFMADDCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31120, 295},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFCMADDCSH[] = {
+ {I_VFCMADDCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31128, 296},
+ {I_VFCMADDCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31136, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDCSH[] = {
+ {I_VFMADDCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31144, 296},
+ {I_VFMADDCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31152, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFCMULCPCH[] = {
+ {I_VFCMULCPCH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31160, 295},
+ {I_VFCMULCPCH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31168, 295},
+ {I_VFCMULCPCH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31176, 295},
+ {I_VFCMULCPCH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31184, 295},
+ {I_VFCMULCPCH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31192, 295},
+ {I_VFCMULCPCH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31200, 295},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMULCPCH[] = {
+ {I_VFMULCPCH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31208, 295},
+ {I_VFMULCPCH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31216, 295},
+ {I_VFMULCPCH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31224, 295},
+ {I_VFMULCPCH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31232, 295},
+ {I_VFMULCPCH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31240, 295},
+ {I_VFMULCPCH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31248, 295},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFCMULCSH[] = {
+ {I_VFCMULCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31256, 296},
+ {I_VFCMULCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31264, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMULCSH[] = {
+ {I_VFMULCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31272, 296},
+ {I_VFMULCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31280, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB132PH[] = {
+ {I_VFMADDSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31288, 295},
+ {I_VFMADDSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31296, 295},
+ {I_VFMADDSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31304, 295},
+ {I_VFMADDSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31312, 295},
+ {I_VFMADDSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31320, 296},
+ {I_VFMADDSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31328, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB213PH[] = {
+ {I_VFMADDSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31336, 295},
+ {I_VFMADDSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31344, 295},
+ {I_VFMADDSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31352, 295},
+ {I_VFMADDSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31360, 295},
+ {I_VFMADDSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31368, 296},
+ {I_VFMADDSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31376, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADDSUB231PH[] = {
+ {I_VFMADDSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31384, 295},
+ {I_VFMADDSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31392, 295},
+ {I_VFMADDSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31400, 295},
+ {I_VFMADDSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31408, 295},
+ {I_VFMADDSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31416, 296},
+ {I_VFMADDSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31424, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD132PH[] = {
+ {I_VFMSUBADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31432, 295},
+ {I_VFMSUBADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31440, 295},
+ {I_VFMSUBADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31448, 295},
+ {I_VFMSUBADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31456, 295},
+ {I_VFMSUBADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31464, 296},
+ {I_VFMSUBADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31472, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD213PH[] = {
+ {I_VFMSUBADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31480, 295},
+ {I_VFMSUBADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31488, 295},
+ {I_VFMSUBADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31496, 295},
+ {I_VFMSUBADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31504, 295},
+ {I_VFMSUBADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31512, 296},
+ {I_VFMSUBADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31520, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUBADD231PH[] = {
+ {I_VFMSUBADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31528, 295},
+ {I_VFMSUBADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31536, 295},
+ {I_VFMSUBADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31544, 295},
+ {I_VFMSUBADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31552, 295},
+ {I_VFMSUBADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31560, 296},
+ {I_VFMSUBADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31568, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD132PH[] = {
+ {I_VPMADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31576, 295},
+ {I_VPMADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31584, 295},
+ {I_VPMADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31592, 295},
+ {I_VPMADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31600, 295},
+ {I_VPMADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31608, 296},
+ {I_VPMADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31616, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD213PH[] = {
+ {I_VPMADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31624, 295},
+ {I_VPMADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31632, 295},
+ {I_VPMADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31640, 295},
+ {I_VPMADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31648, 295},
+ {I_VPMADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31656, 296},
+ {I_VPMADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31664, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD231PH[] = {
+ {I_VPMADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31672, 295},
+ {I_VPMADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31680, 295},
+ {I_VPMADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31688, 295},
+ {I_VPMADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31696, 295},
+ {I_VPMADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31704, 296},
+ {I_VPMADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31712, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD132PH[] = {
+ {I_VFMADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31720, 295},
+ {I_VFMADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31728, 295},
+ {I_VFMADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31736, 295},
+ {I_VFMADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31744, 295},
+ {I_VFMADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31752, 296},
+ {I_VFMADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31760, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD213PH[] = {
+ {I_VFMADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31768, 295},
+ {I_VFMADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31776, 295},
+ {I_VFMADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31784, 295},
+ {I_VFMADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31792, 295},
+ {I_VFMADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31800, 296},
+ {I_VFMADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31808, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMADD231PH[] = {
+ {I_VFMADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31816, 295},
+ {I_VFMADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31824, 295},
+ {I_VFMADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31832, 295},
+ {I_VFMADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31840, 295},
+ {I_VFMADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31848, 296},
+ {I_VFMADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31856, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD132SH[] = {
+ {I_VPMADD132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31864, 296},
+ {I_VPMADD132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31872, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD213SH[] = {
+ {I_VPMADD213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31880, 296},
+ {I_VPMADD213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31888, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMADD231SH[] = {
+ {I_VPMADD231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31896, 296},
+ {I_VPMADD231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31904, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPNMADD132SH[] = {
+ {I_VPNMADD132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31912, 296},
+ {I_VPNMADD132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31920, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPNMADD213SH[] = {
+ {I_VPNMADD213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31928, 296},
+ {I_VPNMADD213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31936, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPNMADD231SH[] = {
+ {I_VPNMADD231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31944, 296},
+ {I_VPNMADD231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31952, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMSUB132PH[] = {
+ {I_VPMSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31960, 295},
+ {I_VPMSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31968, 295},
+ {I_VPMSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31976, 295},
+ {I_VPMSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31984, 295},
+ {I_VPMSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31992, 296},
+ {I_VPMSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32000, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMSUB213PH[] = {
+ {I_VPMSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32008, 295},
+ {I_VPMSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32016, 295},
+ {I_VPMSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32024, 295},
+ {I_VPMSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32032, 295},
+ {I_VPMSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32040, 296},
+ {I_VPMSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32048, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMSUB231PH[] = {
+ {I_VPMSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32056, 295},
+ {I_VPMSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32064, 295},
+ {I_VPMSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32072, 295},
+ {I_VPMSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32080, 295},
+ {I_VPMSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32088, 296},
+ {I_VPMSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32096, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB132PH[] = {
+ {I_VFMSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32104, 295},
+ {I_VFMSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32112, 295},
+ {I_VFMSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32120, 295},
+ {I_VFMSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32128, 295},
+ {I_VFMSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32136, 296},
+ {I_VFMSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32144, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB213PH[] = {
+ {I_VFMSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32152, 295},
+ {I_VFMSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32160, 295},
+ {I_VFMSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32168, 295},
+ {I_VFMSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32176, 295},
+ {I_VFMSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32184, 296},
+ {I_VFMSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32192, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFMSUB231PH[] = {
+ {I_VFMSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32200, 295},
+ {I_VFMSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32208, 295},
+ {I_VFMSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32216, 295},
+ {I_VFMSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32224, 295},
+ {I_VFMSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32232, 296},
+ {I_VFMSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32240, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMSUB132SH[] = {
+ {I_VPMSUB132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32248, 296},
+ {I_VPMSUB132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32256, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMSUB213SH[] = {
+ {I_VPMSUB213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32264, 296},
+ {I_VPMSUB213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32272, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPMSUB231SH[] = {
+ {I_VPMSUB231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32280, 296},
+ {I_VPMSUB231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32288, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPNMSUB132SH[] = {
+ {I_VPNMSUB132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32296, 296},
+ {I_VPNMSUB132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32304, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPNMSUB213SH[] = {
+ {I_VPNMSUB213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32312, 296},
+ {I_VPNMSUB213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32320, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VPNMSUB231SH[] = {
+ {I_VPNMSUB231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32328, 296},
+ {I_VPNMSUB231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32336, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFPCLASSPH[] = {
+ {I_VFPCLASSPH, 3, {KREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12097, 295},
+ {I_VFPCLASSPH, 3, {KREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12106, 295},
+ {I_VFPCLASSPH, 3, {KREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12115, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VFPCLASSSH[] = {
+ {I_VFPCLASSSH, 3, {KREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+12124, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETEXPPH[] = {
+ {I_VGETEXPPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32344, 295},
+ {I_VGETEXPPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32352, 295},
+ {I_VGETEXPPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+32360, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETEXPSH[] = {
+ {I_VGETEXPSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32368, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMANTPH[] = {
+ {I_VGETMANTPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12133, 295},
+ {I_VGETMANTPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12142, 295},
+ {I_VGETMANTPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12151, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMANTSH[] = {
+ {I_VGETMANTSH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12160, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMAXPH[] = {
+ {I_VGETMAXPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32376, 295},
+ {I_VGETMAXPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32384, 295},
+ {I_VGETMAXPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+32392, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMAXSH[] = {
+ {I_VGETMAXSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32400, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMINPH[] = {
+ {I_VGETMINPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32408, 295},
+ {I_VGETMINPH, 2, {YMMREG,RM_XMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32416, 295},
+ {I_VGETMINPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+32424, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VGETMINSH[] = {
+ {I_VGETMINSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32432, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVSH[] = {
+ {I_VMOVSH, 2, {XMMREG,MEMORY|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32440, 296},
+ {I_VMOVSH, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+32448, 296},
+ {I_VMOVSH, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32456, 296},
+ {I_VMOVSH, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32464, 296},
+ {I_VMOVSH, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32472, 296},
+ {I_VMOVSH, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32480, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMOVW[] = {
+ {I_VMOVW, 2, {XMMREG,RM_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32488, 296},
+ {I_VMOVW, 2, {RM_GPR|BITS16,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+32496, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMULPH[] = {
+ {I_VMULPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32504, 295},
+ {I_VMULPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32512, 295},
+ {I_VMULPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32520, 295},
+ {I_VMULPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32528, 295},
+ {I_VMULPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32536, 296},
+ {I_VMULPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32544, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VMULSH[] = {
+ {I_VMULSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32552, 296},
+ {I_VMULSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32560, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCPPH[] = {
+ {I_VRCPPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32568, 295},
+ {I_VRCPPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32576, 295},
+ {I_VRCPPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32584, 295},
+ {I_VRCPPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32592, 295},
+ {I_VRCPPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32600, 296},
+ {I_VRCPPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32608, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRCPSH[] = {
+ {I_VRCPSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+32616, 296},
+ {I_VRCPSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32624, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VREDUCEPH[] = {
+ {I_VREDUCEPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12169, 295},
+ {I_VREDUCEPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12178, 295},
+ {I_VREDUCEPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12187, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VREDUCESH[] = {
+ {I_VREDUCESH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+12196, 296},
+ {I_VREDUCESH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12205, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VENDSCALEPH[] = {
+ {I_VENDSCALEPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12214, 295},
+ {I_VENDSCALEPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12223, 295},
+ {I_VENDSCALEPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12232, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VENDSCALESH[] = {
+ {I_VENDSCALESH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+12241, 296},
+ {I_VENDSCALESH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12250, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRTPH[] = {
+ {I_VRSQRTPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12259, 295},
+ {I_VRSQRTPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12268, 295},
+ {I_VRSQRTPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12277, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VRSQRTSH[] = {
+ {I_VRSQRTSH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+12286, 296},
+ {I_VRSQRTSH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12295, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCALEFPH[] = {
+ {I_VSCALEFPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32632, 295},
+ {I_VSCALEFPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32640, 295},
+ {I_VSCALEFPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32648, 295},
+ {I_VSCALEFPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32656, 295},
+ {I_VSCALEFPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32664, 296},
+ {I_VSCALEFPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32672, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSCALEFSH[] = {
+ {I_VSCALEFSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32680, 296},
+ {I_VSCALEFSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32688, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSQRTPH[] = {
+ {I_VSQRTPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32696, 295},
+ {I_VSQRTPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32704, 295},
+ {I_VSQRTPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32712, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSQRTSH[] = {
+ {I_VSQRTSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32720, 296},
+ {I_VSQRTSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32728, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSUBPH[] = {
+ {I_VSUBPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32736, 295},
+ {I_VSUBPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32744, 295},
+ {I_VSUBPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32752, 295},
+ {I_VSUBPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32760, 295},
+ {I_VSUBPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32768, 296},
+ {I_VSUBPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32776, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VSUBSH[] = {
+ {I_VSUBSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32784, 296},
+ {I_VSUBSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32792, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_VUCOMISH[] = {
+ {I_VUCOMISH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32800, 296},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AADD[] = {
+ {I_AADD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32808, 299},
+ {I_AADD, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+32816, 300},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AAND[] = {
+ {I_AAND, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32824, 299},
+ {I_AAND, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+32832, 300},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_AXOR[] = {
+ {I_AXOR, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32840, 299},
+ {I_AXOR, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+32848, 300},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CLUI[] = {
+ {I_CLUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46071, 301},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_SENDUIPI[] = {
+ {I_SENDUIPI, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42510, 301},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_STUI[] = {
+ {I_STUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46077, 301},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_TESTUI[] = {
+ {I_TESTUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46083, 301},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_UIRET[] = {
+ {I_UIRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46089, 301},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPAXADD[] = {
+ {I_CMPAXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42517, 302},
+ {I_CMPAXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42629, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPAEXADD[] = {
+ {I_CMPAEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42524, 302},
+ {I_CMPAEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42636, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPBXADD[] = {
+ {I_CMPBXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42531, 302},
+ {I_CMPBXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42643, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPBEXADD[] = {
+ {I_CMPBEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42538, 302},
+ {I_CMPBEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42650, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPCXADD[] = {
+ {I_CMPCXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42531, 302},
+ {I_CMPCXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42643, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPEXADD[] = {
+ {I_CMPEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42545, 302},
+ {I_CMPEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42657, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPGXADD[] = {
+ {I_CMPGXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42552, 302},
+ {I_CMPGXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42664, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPGEXADD[] = {
+ {I_CMPGEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42559, 302},
+ {I_CMPGEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42671, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLXADD[] = {
+ {I_CMPLXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42566, 302},
+ {I_CMPLXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42678, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPLEXADD[] = {
+ {I_CMPLEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42573, 302},
+ {I_CMPLEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42685, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNAXADD[] = {
+ {I_CMPNAXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42538, 302},
+ {I_CMPNAXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42650, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNAEXADD[] = {
+ {I_CMPNAEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42531, 302},
+ {I_CMPNAEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42643, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNBXADD[] = {
+ {I_CMPNBXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42524, 302},
+ {I_CMPNBXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42636, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNBEXADD[] = {
+ {I_CMPNBEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42517, 302},
+ {I_CMPNBEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42629, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNCXADD[] = {
+ {I_CMPNCXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42524, 302},
+ {I_CMPNCXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42636, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNEXADD[] = {
+ {I_CMPNEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42580, 302},
+ {I_CMPNEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42692, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNGXADD[] = {
+ {I_CMPNGXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42573, 302},
+ {I_CMPNGXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42685, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNGEXADD[] = {
+ {I_CMPNGEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42566, 302},
+ {I_CMPNGEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42678, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLXADD[] = {
+ {I_CMPNLXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42559, 302},
+ {I_CMPNLXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42671, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNLEXADD[] = {
+ {I_CMPNLEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42552, 302},
+ {I_CMPNLEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42664, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNOXADD[] = {
+ {I_CMPNOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42587, 302},
+ {I_CMPNOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42699, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNPXADD[] = {
+ {I_CMPNPXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42594, 302},
+ {I_CMPNPXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42706, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNSXADD[] = {
+ {I_CMPNSXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42601, 302},
+ {I_CMPNSXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42713, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPNZXADD[] = {
+ {I_CMPNZXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42580, 302},
+ {I_CMPNZXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42692, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPOXADD[] = {
+ {I_CMPOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42608, 302},
+ {I_CMPOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42720, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPPXADD[] = {
+ {I_CMPPXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42615, 302},
+ {I_CMPPXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42727, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPPEXADD[] = {
+ {I_CMPPEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42615, 302},
+ {I_CMPPEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42727, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPPOXADD[] = {
+ {I_CMPPOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42594, 302},
+ {I_CMPPOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42706, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPSXADD[] = {
+ {I_CMPSXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42622, 302},
+ {I_CMPSXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42734, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_CMPZXADD[] = {
+ {I_CMPZXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42545, 302},
+ {I_CMPZXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42657, 303},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRMSRNS[] = {
+ {I_WRMSRNS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46095, 304},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_RDMSRLIST[] = {
+ {I_RDMSRLIST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46101, 305},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_WRMSRLIST[] = {
+ {I_WRMSRLIST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46107, 305},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HRESET[] = {
+ {I_HRESET, 2, {IMMEDIATE,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+32856, 306},
+ {I_HRESET, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+32856, 306},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP0[] = {
+ {I_HINT_NOP0, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46113, 307},
+ {I_HINT_NOP0, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46119, 307},
+ {I_HINT_NOP0, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46125, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP1[] = {
+ {I_HINT_NOP1, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46131, 307},
+ {I_HINT_NOP1, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46137, 307},
+ {I_HINT_NOP1, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46143, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP2[] = {
+ {I_HINT_NOP2, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46149, 307},
+ {I_HINT_NOP2, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46155, 307},
+ {I_HINT_NOP2, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46161, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP3[] = {
+ {I_HINT_NOP3, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46167, 307},
+ {I_HINT_NOP3, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46173, 307},
+ {I_HINT_NOP3, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46179, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP4[] = {
+ {I_HINT_NOP4, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46185, 307},
+ {I_HINT_NOP4, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46191, 307},
+ {I_HINT_NOP4, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46197, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP5[] = {
+ {I_HINT_NOP5, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46203, 307},
+ {I_HINT_NOP5, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46209, 307},
+ {I_HINT_NOP5, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46215, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP6[] = {
+ {I_HINT_NOP6, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46221, 307},
+ {I_HINT_NOP6, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46227, 307},
+ {I_HINT_NOP6, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46233, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP7[] = {
+ {I_HINT_NOP7, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46239, 307},
+ {I_HINT_NOP7, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46245, 307},
+ {I_HINT_NOP7, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46251, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP8[] = {
+ {I_HINT_NOP8, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46257, 307},
+ {I_HINT_NOP8, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46263, 307},
+ {I_HINT_NOP8, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46269, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP9[] = {
+ {I_HINT_NOP9, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46275, 307},
+ {I_HINT_NOP9, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46281, 307},
+ {I_HINT_NOP9, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46287, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP10[] = {
+ {I_HINT_NOP10, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46293, 307},
+ {I_HINT_NOP10, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46299, 307},
+ {I_HINT_NOP10, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46305, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP11[] = {
+ {I_HINT_NOP11, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46311, 307},
+ {I_HINT_NOP11, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46317, 307},
+ {I_HINT_NOP11, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46323, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP12[] = {
+ {I_HINT_NOP12, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46329, 307},
+ {I_HINT_NOP12, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46335, 307},
+ {I_HINT_NOP12, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46341, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP13[] = {
+ {I_HINT_NOP13, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46347, 307},
+ {I_HINT_NOP13, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46353, 307},
+ {I_HINT_NOP13, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46359, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP14[] = {
+ {I_HINT_NOP14, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46365, 307},
+ {I_HINT_NOP14, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46371, 307},
+ {I_HINT_NOP14, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46377, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP15[] = {
+ {I_HINT_NOP15, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46383, 307},
+ {I_HINT_NOP15, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46389, 307},
+ {I_HINT_NOP15, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46395, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP16[] = {
+ {I_HINT_NOP16, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46401, 307},
+ {I_HINT_NOP16, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46407, 307},
+ {I_HINT_NOP16, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46413, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP17[] = {
+ {I_HINT_NOP17, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46419, 307},
+ {I_HINT_NOP17, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46425, 307},
+ {I_HINT_NOP17, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46431, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP18[] = {
+ {I_HINT_NOP18, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46437, 307},
+ {I_HINT_NOP18, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46443, 307},
+ {I_HINT_NOP18, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46449, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP19[] = {
+ {I_HINT_NOP19, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46455, 307},
+ {I_HINT_NOP19, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46461, 307},
+ {I_HINT_NOP19, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46467, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP20[] = {
+ {I_HINT_NOP20, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46473, 307},
+ {I_HINT_NOP20, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46479, 307},
+ {I_HINT_NOP20, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46485, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP21[] = {
+ {I_HINT_NOP21, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46491, 307},
+ {I_HINT_NOP21, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46497, 307},
+ {I_HINT_NOP21, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46503, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP22[] = {
+ {I_HINT_NOP22, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46509, 307},
+ {I_HINT_NOP22, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46515, 307},
+ {I_HINT_NOP22, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46521, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP23[] = {
+ {I_HINT_NOP23, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46527, 307},
+ {I_HINT_NOP23, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46533, 307},
+ {I_HINT_NOP23, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46539, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP24[] = {
+ {I_HINT_NOP24, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46545, 307},
+ {I_HINT_NOP24, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46551, 307},
+ {I_HINT_NOP24, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46557, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP25[] = {
+ {I_HINT_NOP25, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46563, 307},
+ {I_HINT_NOP25, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46569, 307},
+ {I_HINT_NOP25, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46575, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP26[] = {
+ {I_HINT_NOP26, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46581, 307},
+ {I_HINT_NOP26, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46587, 307},
+ {I_HINT_NOP26, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46593, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP27[] = {
+ {I_HINT_NOP27, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46599, 307},
+ {I_HINT_NOP27, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46605, 307},
+ {I_HINT_NOP27, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46611, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP28[] = {
+ {I_HINT_NOP28, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46617, 307},
+ {I_HINT_NOP28, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46623, 307},
+ {I_HINT_NOP28, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46629, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP29[] = {
+ {I_HINT_NOP29, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46635, 307},
+ {I_HINT_NOP29, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46641, 307},
+ {I_HINT_NOP29, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46647, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP30[] = {
+ {I_HINT_NOP30, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46653, 307},
+ {I_HINT_NOP30, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46659, 307},
+ {I_HINT_NOP30, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46665, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP31[] = {
+ {I_HINT_NOP31, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46671, 307},
+ {I_HINT_NOP31, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46677, 307},
+ {I_HINT_NOP31, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46683, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP32[] = {
+ {I_HINT_NOP32, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46689, 307},
+ {I_HINT_NOP32, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46695, 307},
+ {I_HINT_NOP32, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46701, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP33[] = {
+ {I_HINT_NOP33, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46707, 307},
+ {I_HINT_NOP33, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46713, 307},
+ {I_HINT_NOP33, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46719, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP34[] = {
+ {I_HINT_NOP34, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46725, 307},
+ {I_HINT_NOP34, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46731, 307},
+ {I_HINT_NOP34, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46737, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP35[] = {
+ {I_HINT_NOP35, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46743, 307},
+ {I_HINT_NOP35, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46749, 307},
+ {I_HINT_NOP35, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46755, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP36[] = {
+ {I_HINT_NOP36, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46761, 307},
+ {I_HINT_NOP36, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46767, 307},
+ {I_HINT_NOP36, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46773, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP37[] = {
+ {I_HINT_NOP37, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46779, 307},
+ {I_HINT_NOP37, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46785, 307},
+ {I_HINT_NOP37, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46791, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP38[] = {
+ {I_HINT_NOP38, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46797, 307},
+ {I_HINT_NOP38, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46803, 307},
+ {I_HINT_NOP38, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46809, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP39[] = {
+ {I_HINT_NOP39, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46815, 307},
+ {I_HINT_NOP39, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46821, 307},
+ {I_HINT_NOP39, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46827, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP40[] = {
+ {I_HINT_NOP40, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46833, 307},
+ {I_HINT_NOP40, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46839, 307},
+ {I_HINT_NOP40, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46845, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP41[] = {
+ {I_HINT_NOP41, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46851, 307},
+ {I_HINT_NOP41, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46857, 307},
+ {I_HINT_NOP41, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46863, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP42[] = {
+ {I_HINT_NOP42, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46869, 307},
+ {I_HINT_NOP42, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46875, 307},
+ {I_HINT_NOP42, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46881, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP43[] = {
+ {I_HINT_NOP43, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46887, 307},
+ {I_HINT_NOP43, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46893, 307},
+ {I_HINT_NOP43, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46899, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP44[] = {
+ {I_HINT_NOP44, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46905, 307},
+ {I_HINT_NOP44, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46911, 307},
+ {I_HINT_NOP44, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46917, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP45[] = {
+ {I_HINT_NOP45, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46923, 307},
+ {I_HINT_NOP45, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46929, 307},
+ {I_HINT_NOP45, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46935, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP46[] = {
+ {I_HINT_NOP46, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46941, 307},
+ {I_HINT_NOP46, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46947, 307},
+ {I_HINT_NOP46, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46953, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP47[] = {
+ {I_HINT_NOP47, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46959, 307},
+ {I_HINT_NOP47, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46965, 307},
+ {I_HINT_NOP47, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46971, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP48[] = {
+ {I_HINT_NOP48, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46977, 307},
+ {I_HINT_NOP48, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46983, 307},
+ {I_HINT_NOP48, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46989, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP49[] = {
+ {I_HINT_NOP49, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46995, 307},
+ {I_HINT_NOP49, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47001, 307},
+ {I_HINT_NOP49, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47007, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP50[] = {
+ {I_HINT_NOP50, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47013, 307},
+ {I_HINT_NOP50, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47019, 307},
+ {I_HINT_NOP50, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47025, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP51[] = {
+ {I_HINT_NOP51, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47031, 307},
+ {I_HINT_NOP51, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47037, 307},
+ {I_HINT_NOP51, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47043, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP52[] = {
+ {I_HINT_NOP52, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47049, 307},
+ {I_HINT_NOP52, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47055, 307},
+ {I_HINT_NOP52, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47061, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP53[] = {
+ {I_HINT_NOP53, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47067, 307},
+ {I_HINT_NOP53, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47073, 307},
+ {I_HINT_NOP53, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47079, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP54[] = {
+ {I_HINT_NOP54, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47085, 307},
+ {I_HINT_NOP54, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47091, 307},
+ {I_HINT_NOP54, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47097, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP55[] = {
+ {I_HINT_NOP55, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47103, 307},
+ {I_HINT_NOP55, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47109, 307},
+ {I_HINT_NOP55, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47115, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP56[] = {
+ {I_HINT_NOP56, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43437, 307},
+ {I_HINT_NOP56, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43443, 307},
+ {I_HINT_NOP56, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43449, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP57[] = {
+ {I_HINT_NOP57, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47121, 307},
+ {I_HINT_NOP57, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47127, 307},
+ {I_HINT_NOP57, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47133, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP58[] = {
+ {I_HINT_NOP58, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47139, 307},
+ {I_HINT_NOP58, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47145, 307},
+ {I_HINT_NOP58, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47151, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP59[] = {
+ {I_HINT_NOP59, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47157, 307},
+ {I_HINT_NOP59, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47163, 307},
+ {I_HINT_NOP59, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47169, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP60[] = {
+ {I_HINT_NOP60, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47175, 307},
+ {I_HINT_NOP60, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47181, 307},
+ {I_HINT_NOP60, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47187, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP61[] = {
+ {I_HINT_NOP61, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47193, 307},
+ {I_HINT_NOP61, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47199, 307},
+ {I_HINT_NOP61, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47205, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP62[] = {
+ {I_HINT_NOP62, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47211, 307},
+ {I_HINT_NOP62, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47217, 307},
+ {I_HINT_NOP62, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47223, 308},
+ ITEMPLATE_END
+};
+
+static const struct itemplate instrux_HINT_NOP63[] = {
+ {I_HINT_NOP63, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47229, 307},
+ {I_HINT_NOP63, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47235, 307},
+ {I_HINT_NOP63, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47241, 308},
+ ITEMPLATE_END
+};
+
+const struct itemplate * const nasm_instructions[] = {
+ instrux_DB,
+ instrux_DW,
+ instrux_DD,
+ instrux_DQ,
+ instrux_DT,
+ instrux_DO,
+ instrux_DY,
+ instrux_DZ,
+ instrux_RESB,
+ instrux_RESW,
+ instrux_RESD,
+ instrux_RESQ,
+ instrux_REST,
+ instrux_RESO,
+ instrux_RESY,
+ instrux_RESZ,
+ instrux_INCBIN,
+ instrux_AAA,
+ instrux_AAD,
+ instrux_AAM,
+ instrux_AAS,
+ instrux_ADC,
+ instrux_ADD,
+ instrux_AND,
+ instrux_ARPL,
+ instrux_BB0_RESET,
+ instrux_BB1_RESET,
+ instrux_BOUND,
+ instrux_BSF,
+ instrux_BSR,
+ instrux_BSWAP,
+ instrux_BT,
+ instrux_BTC,
+ instrux_BTR,
+ instrux_BTS,
+ instrux_CALL,
+ instrux_CBW,
+ instrux_CDQ,
+ instrux_CDQE,
+ instrux_CLC,
+ instrux_CLD,
+ instrux_CLI,
+ instrux_CLTS,
+ instrux_CMC,
+ instrux_CMP,
+ instrux_CMPSB,
+ instrux_CMPSD,
+ instrux_CMPSQ,
+ instrux_CMPSW,
+ instrux_CMPXCHG,
+ instrux_CMPXCHG486,
+ instrux_CMPXCHG8B,
+ instrux_CMPXCHG16B,
+ instrux_CPUID,
+ instrux_CPU_READ,
+ instrux_CPU_WRITE,
+ instrux_CQO,
+ instrux_CWD,
+ instrux_CWDE,
+ instrux_DAA,
+ instrux_DAS,
+ instrux_DEC,
+ instrux_DIV,
+ instrux_DMINT,
+ instrux_EMMS,
+ instrux_ENTER,
+ instrux_EQU,
+ instrux_F2XM1,
+ instrux_FABS,
+ instrux_FADD,
+ instrux_FADDP,
+ instrux_FBLD,
+ instrux_FBSTP,
+ instrux_FCHS,
+ instrux_FCLEX,
+ instrux_FCMOVB,
+ instrux_FCMOVBE,
+ instrux_FCMOVE,
+ instrux_FCMOVNB,
+ instrux_FCMOVNBE,
+ instrux_FCMOVNE,
+ instrux_FCMOVNU,
+ instrux_FCMOVU,
+ instrux_FCOM,
+ instrux_FCOMI,
+ instrux_FCOMIP,
+ instrux_FCOMP,
+ instrux_FCOMPP,
+ instrux_FCOS,
+ instrux_FDECSTP,
+ instrux_FDISI,
+ instrux_FDIV,
+ instrux_FDIVP,
+ instrux_FDIVR,
+ instrux_FDIVRP,
+ instrux_FEMMS,
+ instrux_FENI,
+ instrux_FFREE,
+ instrux_FFREEP,
+ instrux_FIADD,
+ instrux_FICOM,
+ instrux_FICOMP,
+ instrux_FIDIV,
+ instrux_FIDIVR,
+ instrux_FILD,
+ instrux_FIMUL,
+ instrux_FINCSTP,
+ instrux_FINIT,
+ instrux_FIST,
+ instrux_FISTP,
+ instrux_FISTTP,
+ instrux_FISUB,
+ instrux_FISUBR,
+ instrux_FLD,
+ instrux_FLD1,
+ instrux_FLDCW,
+ instrux_FLDENV,
+ instrux_FLDL2E,
+ instrux_FLDL2T,
+ instrux_FLDLG2,
+ instrux_FLDLN2,
+ instrux_FLDPI,
+ instrux_FLDZ,
+ instrux_FMUL,
+ instrux_FMULP,
+ instrux_FNCLEX,
+ instrux_FNDISI,
+ instrux_FNENI,
+ instrux_FNINIT,
+ instrux_FNOP,
+ instrux_FNSAVE,
+ instrux_FNSTCW,
+ instrux_FNSTENV,
+ instrux_FNSTSW,
+ instrux_FPATAN,
+ instrux_FPREM,
+ instrux_FPREM1,
+ instrux_FPTAN,
+ instrux_FRNDINT,
+ instrux_FRSTOR,
+ instrux_FSAVE,
+ instrux_FSCALE,
+ instrux_FSETPM,
+ instrux_FSIN,
+ instrux_FSINCOS,
+ instrux_FSQRT,
+ instrux_FST,
+ instrux_FSTCW,
+ instrux_FSTENV,
+ instrux_FSTP,
+ instrux_FSTSW,
+ instrux_FSUB,
+ instrux_FSUBP,
+ instrux_FSUBR,
+ instrux_FSUBRP,
+ instrux_FTST,
+ instrux_FUCOM,
+ instrux_FUCOMI,
+ instrux_FUCOMIP,
+ instrux_FUCOMP,
+ instrux_FUCOMPP,
+ instrux_FXAM,
+ instrux_FXCH,
+ instrux_FXTRACT,
+ instrux_FYL2X,
+ instrux_FYL2XP1,
+ instrux_HLT,
+ instrux_IBTS,
+ instrux_ICEBP,
+ instrux_IDIV,
+ instrux_IMUL,
+ instrux_IN,
+ instrux_INC,
+ instrux_INSB,
+ instrux_INSD,
+ instrux_INSW,
+ instrux_INT,
+ instrux_INT01,
+ instrux_INT1,
+ instrux_INT03,
+ instrux_INT3,
+ instrux_INTO,
+ instrux_INVD,
+ instrux_INVPCID,
+ instrux_INVLPG,
+ instrux_INVLPGA,
+ instrux_IRET,
+ instrux_IRETD,
+ instrux_IRETQ,
+ instrux_IRETW,
+ instrux_JCXZ,
+ instrux_JECXZ,
+ instrux_JRCXZ,
+ instrux_JMP,
+ instrux_JMPE,
+ instrux_LAHF,
+ instrux_LAR,
+ instrux_LDS,
+ instrux_LEA,
+ instrux_LEAVE,
+ instrux_LES,
+ instrux_LFENCE,
+ instrux_LFS,
+ instrux_LGDT,
+ instrux_LGS,
+ instrux_LIDT,
+ instrux_LLDT,
+ instrux_LMSW,
+ instrux_LOADALL,
+ instrux_LOADALL286,
+ instrux_LODSB,
+ instrux_LODSD,
+ instrux_LODSQ,
+ instrux_LODSW,
+ instrux_LOOP,
+ instrux_LOOPE,
+ instrux_LOOPNE,
+ instrux_LOOPNZ,
+ instrux_LOOPZ,
+ instrux_LSL,
+ instrux_LSS,
+ instrux_LTR,
+ instrux_MFENCE,
+ instrux_MONITOR,
+ instrux_MONITORX,
+ instrux_MOV,
+ instrux_MOVD,
+ instrux_MOVQ,
+ instrux_MOVSB,
+ instrux_MOVSD,
+ instrux_MOVSQ,
+ instrux_MOVSW,
+ instrux_MOVSX,
+ instrux_MOVSXD,
+ instrux_MOVZX,
+ instrux_MUL,
+ instrux_MWAIT,
+ instrux_MWAITX,
+ instrux_NEG,
+ instrux_NOP,
+ instrux_NOT,
+ instrux_OR,
+ instrux_OUT,
+ instrux_OUTSB,
+ instrux_OUTSD,
+ instrux_OUTSW,
+ instrux_PACKSSDW,
+ instrux_PACKSSWB,
+ instrux_PACKUSWB,
+ instrux_PADDB,
+ instrux_PADDD,
+ instrux_PADDSB,
+ instrux_PADDSIW,
+ instrux_PADDSW,
+ instrux_PADDUSB,
+ instrux_PADDUSW,
+ instrux_PADDW,
+ instrux_PAND,
+ instrux_PANDN,
+ instrux_PAUSE,
+ instrux_PAVEB,
+ instrux_PAVGUSB,
+ instrux_PCMPEQB,
+ instrux_PCMPEQD,
+ instrux_PCMPEQW,
+ instrux_PCMPGTB,
+ instrux_PCMPGTD,
+ instrux_PCMPGTW,
+ instrux_PDISTIB,
+ instrux_PF2ID,
+ instrux_PFACC,
+ instrux_PFADD,
+ instrux_PFCMPEQ,
+ instrux_PFCMPGE,
+ instrux_PFCMPGT,
+ instrux_PFMAX,
+ instrux_PFMIN,
+ instrux_PFMUL,
+ instrux_PFRCP,
+ instrux_PFRCPIT1,
+ instrux_PFRCPIT2,
+ instrux_PFRSQIT1,
+ instrux_PFRSQRT,
+ instrux_PFSUB,
+ instrux_PFSUBR,
+ instrux_PI2FD,
+ instrux_PMACHRIW,
+ instrux_PMADDWD,
+ instrux_PMAGW,
+ instrux_PMULHRIW,
+ instrux_PMULHRWA,
+ instrux_PMULHRWC,
+ instrux_PMULHW,
+ instrux_PMULLW,
+ instrux_PMVGEZB,
+ instrux_PMVLZB,
+ instrux_PMVNZB,
+ instrux_PMVZB,
+ instrux_POP,
+ instrux_POPA,
+ instrux_POPAD,
+ instrux_POPAW,
+ instrux_POPF,
+ instrux_POPFD,
+ instrux_POPFQ,
+ instrux_POPFW,
+ instrux_POR,
+ instrux_PREFETCH,
+ instrux_PREFETCHW,
+ instrux_PSLLD,
+ instrux_PSLLQ,
+ instrux_PSLLW,
+ instrux_PSRAD,
+ instrux_PSRAW,
+ instrux_PSRLD,
+ instrux_PSRLQ,
+ instrux_PSRLW,
+ instrux_PSUBB,
+ instrux_PSUBD,
+ instrux_PSUBSB,
+ instrux_PSUBSIW,
+ instrux_PSUBSW,
+ instrux_PSUBUSB,
+ instrux_PSUBUSW,
+ instrux_PSUBW,
+ instrux_PUNPCKHBW,
+ instrux_PUNPCKHDQ,
+ instrux_PUNPCKHWD,
+ instrux_PUNPCKLBW,
+ instrux_PUNPCKLDQ,
+ instrux_PUNPCKLWD,
+ instrux_PUSH,
+ instrux_PUSHA,
+ instrux_PUSHAD,
+ instrux_PUSHAW,
+ instrux_PUSHF,
+ instrux_PUSHFD,
+ instrux_PUSHFQ,
+ instrux_PUSHFW,
+ instrux_PXOR,
+ instrux_RCL,
+ instrux_RCR,
+ instrux_RDSHR,
+ instrux_RDMSR,
+ instrux_RDPMC,
+ instrux_RDTSC,
+ instrux_RDTSCP,
+ instrux_RET,
+ instrux_RETF,
+ instrux_RETN,
+ instrux_RETW,
+ instrux_RETFW,
+ instrux_RETNW,
+ instrux_RETD,
+ instrux_RETFD,
+ instrux_RETND,
+ instrux_RETQ,
+ instrux_RETFQ,
+ instrux_RETNQ,
+ instrux_ROL,
+ instrux_ROR,
+ instrux_RDM,
+ instrux_RSDC,
+ instrux_RSLDT,
+ instrux_RSM,
+ instrux_RSTS,
+ instrux_SAHF,
+ instrux_SAL,
+ instrux_SALC,
+ instrux_SAR,
+ instrux_SBB,
+ instrux_SCASB,
+ instrux_SCASD,
+ instrux_SCASQ,
+ instrux_SCASW,
+ instrux_SFENCE,
+ instrux_SGDT,
+ instrux_SHL,
+ instrux_SHLD,
+ instrux_SHR,
+ instrux_SHRD,
+ instrux_SIDT,
+ instrux_SLDT,
+ instrux_SKINIT,
+ instrux_SMI,
+ instrux_SMINT,
+ instrux_SMINTOLD,
+ instrux_SMSW,
+ instrux_STC,
+ instrux_STD,
+ instrux_STI,
+ instrux_STOSB,
+ instrux_STOSD,
+ instrux_STOSQ,
+ instrux_STOSW,
+ instrux_STR,
+ instrux_SUB,
+ instrux_SVDC,
+ instrux_SVLDT,
+ instrux_SVTS,
+ instrux_SWAPGS,
+ instrux_SYSCALL,
+ instrux_SYSENTER,
+ instrux_SYSEXIT,
+ instrux_SYSRET,
+ instrux_TEST,
+ instrux_UD0,
+ instrux_UD1,
+ instrux_UD2B,
+ instrux_UD2,
+ instrux_UD2A,
+ instrux_UMOV,
+ instrux_VERR,
+ instrux_VERW,
+ instrux_FWAIT,
+ instrux_WBINVD,
+ instrux_WRSHR,
+ instrux_WRMSR,
+ instrux_XADD,
+ instrux_XBTS,
+ instrux_XCHG,
+ instrux_XLATB,
+ instrux_XLAT,
+ instrux_XOR,
+ instrux_CMOVA,
+ instrux_CMOVAE,
+ instrux_CMOVB,
+ instrux_CMOVBE,
+ instrux_CMOVC,
+ instrux_CMOVE,
+ instrux_CMOVG,
+ instrux_CMOVGE,
+ instrux_CMOVL,
+ instrux_CMOVLE,
+ instrux_CMOVNA,
+ instrux_CMOVNAE,
+ instrux_CMOVNB,
+ instrux_CMOVNBE,
+ instrux_CMOVNC,
+ instrux_CMOVNE,
+ instrux_CMOVNG,
+ instrux_CMOVNGE,
+ instrux_CMOVNL,
+ instrux_CMOVNLE,
+ instrux_CMOVNO,
+ instrux_CMOVNP,
+ instrux_CMOVNS,
+ instrux_CMOVNZ,
+ instrux_CMOVO,
+ instrux_CMOVP,
+ instrux_CMOVPE,
+ instrux_CMOVPO,
+ instrux_CMOVS,
+ instrux_CMOVZ,
+ instrux_JA,
+ instrux_JAE,
+ instrux_JB,
+ instrux_JBE,
+ instrux_JC,
+ instrux_JE,
+ instrux_JG,
+ instrux_JGE,
+ instrux_JL,
+ instrux_JLE,
+ instrux_JNA,
+ instrux_JNAE,
+ instrux_JNB,
+ instrux_JNBE,
+ instrux_JNC,
+ instrux_JNE,
+ instrux_JNG,
+ instrux_JNGE,
+ instrux_JNL,
+ instrux_JNLE,
+ instrux_JNO,
+ instrux_JNP,
+ instrux_JNS,
+ instrux_JNZ,
+ instrux_JO,
+ instrux_JP,
+ instrux_JPE,
+ instrux_JPO,
+ instrux_JS,
+ instrux_JZ,
+ instrux_SETA,
+ instrux_SETAE,
+ instrux_SETB,
+ instrux_SETBE,
+ instrux_SETC,
+ instrux_SETE,
+ instrux_SETG,
+ instrux_SETGE,
+ instrux_SETL,
+ instrux_SETLE,
+ instrux_SETNA,
+ instrux_SETNAE,
+ instrux_SETNB,
+ instrux_SETNBE,
+ instrux_SETNC,
+ instrux_SETNE,
+ instrux_SETNG,
+ instrux_SETNGE,
+ instrux_SETNL,
+ instrux_SETNLE,
+ instrux_SETNO,
+ instrux_SETNP,
+ instrux_SETNS,
+ instrux_SETNZ,
+ instrux_SETO,
+ instrux_SETP,
+ instrux_SETPE,
+ instrux_SETPO,
+ instrux_SETS,
+ instrux_SETZ,
+ instrux_ADDPS,
+ instrux_ADDSS,
+ instrux_ANDNPS,
+ instrux_ANDPS,
+ instrux_CMPEQPS,
+ instrux_CMPEQSS,
+ instrux_CMPLEPS,
+ instrux_CMPLESS,
+ instrux_CMPLTPS,
+ instrux_CMPLTSS,
+ instrux_CMPNEQPS,
+ instrux_CMPNEQSS,
+ instrux_CMPNLEPS,
+ instrux_CMPNLESS,
+ instrux_CMPNLTPS,
+ instrux_CMPNLTSS,
+ instrux_CMPORDPS,
+ instrux_CMPORDSS,
+ instrux_CMPUNORDPS,
+ instrux_CMPUNORDSS,
+ instrux_CMPPS,
+ instrux_CMPSS,
+ instrux_COMISS,
+ instrux_CVTPI2PS,
+ instrux_CVTPS2PI,
+ instrux_CVTSI2SS,
+ instrux_CVTSS2SI,
+ instrux_CVTTPS2PI,
+ instrux_CVTTSS2SI,
+ instrux_DIVPS,
+ instrux_DIVSS,
+ instrux_LDMXCSR,
+ instrux_MAXPS,
+ instrux_MAXSS,
+ instrux_MINPS,
+ instrux_MINSS,
+ instrux_MOVAPS,
+ instrux_MOVHPS,
+ instrux_MOVLHPS,
+ instrux_MOVLPS,
+ instrux_MOVHLPS,
+ instrux_MOVMSKPS,
+ instrux_MOVNTPS,
+ instrux_MOVSS,
+ instrux_MOVUPS,
+ instrux_MULPS,
+ instrux_MULSS,
+ instrux_ORPS,
+ instrux_RCPPS,
+ instrux_RCPSS,
+ instrux_RSQRTPS,
+ instrux_RSQRTSS,
+ instrux_SHUFPS,
+ instrux_SQRTPS,
+ instrux_SQRTSS,
+ instrux_STMXCSR,
+ instrux_SUBPS,
+ instrux_SUBSS,
+ instrux_UCOMISS,
+ instrux_UNPCKHPS,
+ instrux_UNPCKLPS,
+ instrux_XORPS,
+ instrux_FXRSTOR,
+ instrux_FXRSTOR64,
+ instrux_FXSAVE,
+ instrux_FXSAVE64,
+ instrux_XGETBV,
+ instrux_XSETBV,
+ instrux_XSAVE,
+ instrux_XSAVE64,
+ instrux_XSAVEC,
+ instrux_XSAVEC64,
+ instrux_XSAVEOPT,
+ instrux_XSAVEOPT64,
+ instrux_XSAVES,
+ instrux_XSAVES64,
+ instrux_XRSTOR,
+ instrux_XRSTOR64,
+ instrux_XRSTORS,
+ instrux_XRSTORS64,
+ instrux_PREFETCHNTA,
+ instrux_PREFETCHT0,
+ instrux_PREFETCHT1,
+ instrux_PREFETCHT2,
+ instrux_PREFETCHIT0,
+ instrux_PREFETCHIT1,
+ instrux_MASKMOVQ,
+ instrux_MOVNTQ,
+ instrux_PAVGB,
+ instrux_PAVGW,
+ instrux_PEXTRW,
+ instrux_PINSRW,
+ instrux_PMAXSW,
+ instrux_PMAXUB,
+ instrux_PMINSW,
+ instrux_PMINUB,
+ instrux_PMOVMSKB,
+ instrux_PMULHUW,
+ instrux_PSADBW,
+ instrux_PSHUFW,
+ instrux_PF2IW,
+ instrux_PFNACC,
+ instrux_PFPNACC,
+ instrux_PI2FW,
+ instrux_PSWAPD,
+ instrux_MASKMOVDQU,
+ instrux_CLFLUSH,
+ instrux_MOVNTDQ,
+ instrux_MOVNTI,
+ instrux_MOVNTPD,
+ instrux_MOVDQA,
+ instrux_MOVDQU,
+ instrux_MOVDQ2Q,
+ instrux_MOVQ2DQ,
+ instrux_PADDQ,
+ instrux_PMULUDQ,
+ instrux_PSHUFD,
+ instrux_PSHUFHW,
+ instrux_PSHUFLW,
+ instrux_PSLLDQ,
+ instrux_PSRLDQ,
+ instrux_PSUBQ,
+ instrux_PUNPCKHQDQ,
+ instrux_PUNPCKLQDQ,
+ instrux_ADDPD,
+ instrux_ADDSD,
+ instrux_ANDNPD,
+ instrux_ANDPD,
+ instrux_CMPEQPD,
+ instrux_CMPEQSD,
+ instrux_CMPLEPD,
+ instrux_CMPLESD,
+ instrux_CMPLTPD,
+ instrux_CMPLTSD,
+ instrux_CMPNEQPD,
+ instrux_CMPNEQSD,
+ instrux_CMPNLEPD,
+ instrux_CMPNLESD,
+ instrux_CMPNLTPD,
+ instrux_CMPNLTSD,
+ instrux_CMPORDPD,
+ instrux_CMPORDSD,
+ instrux_CMPUNORDPD,
+ instrux_CMPUNORDSD,
+ instrux_CMPPD,
+ instrux_COMISD,
+ instrux_CVTDQ2PD,
+ instrux_CVTDQ2PS,
+ instrux_CVTPD2DQ,
+ instrux_CVTPD2PI,
+ instrux_CVTPD2PS,
+ instrux_CVTPI2PD,
+ instrux_CVTPS2DQ,
+ instrux_CVTPS2PD,
+ instrux_CVTSD2SI,
+ instrux_CVTSD2SS,
+ instrux_CVTSI2SD,
+ instrux_CVTSS2SD,
+ instrux_CVTTPD2PI,
+ instrux_CVTTPD2DQ,
+ instrux_CVTTPS2DQ,
+ instrux_CVTTSD2SI,
+ instrux_DIVPD,
+ instrux_DIVSD,
+ instrux_MAXPD,
+ instrux_MAXSD,
+ instrux_MINPD,
+ instrux_MINSD,
+ instrux_MOVAPD,
+ instrux_MOVHPD,
+ instrux_MOVLPD,
+ instrux_MOVMSKPD,
+ instrux_MOVUPD,
+ instrux_MULPD,
+ instrux_MULSD,
+ instrux_ORPD,
+ instrux_SHUFPD,
+ instrux_SQRTPD,
+ instrux_SQRTSD,
+ instrux_SUBPD,
+ instrux_SUBSD,
+ instrux_UCOMISD,
+ instrux_UNPCKHPD,
+ instrux_UNPCKLPD,
+ instrux_XORPD,
+ instrux_ADDSUBPD,
+ instrux_ADDSUBPS,
+ instrux_HADDPD,
+ instrux_HADDPS,
+ instrux_HSUBPD,
+ instrux_HSUBPS,
+ instrux_LDDQU,
+ instrux_MOVDDUP,
+ instrux_MOVSHDUP,
+ instrux_MOVSLDUP,
+ instrux_CLGI,
+ instrux_STGI,
+ instrux_VMCALL,
+ instrux_VMCLEAR,
+ instrux_VMFUNC,
+ instrux_VMLAUNCH,
+ instrux_VMLOAD,
+ instrux_VMMCALL,
+ instrux_VMPTRLD,
+ instrux_VMPTRST,
+ instrux_VMREAD,
+ instrux_VMRESUME,
+ instrux_VMRUN,
+ instrux_VMSAVE,
+ instrux_VMWRITE,
+ instrux_VMXOFF,
+ instrux_VMXON,
+ instrux_INVEPT,
+ instrux_INVVPID,
+ instrux_PVALIDATE,
+ instrux_RMPADJUST,
+ instrux_VMGEXIT,
+ instrux_PABSB,
+ instrux_PABSW,
+ instrux_PABSD,
+ instrux_PALIGNR,
+ instrux_PHADDW,
+ instrux_PHADDD,
+ instrux_PHADDSW,
+ instrux_PHSUBW,
+ instrux_PHSUBD,
+ instrux_PHSUBSW,
+ instrux_PMADDUBSW,
+ instrux_PMULHRSW,
+ instrux_PSHUFB,
+ instrux_PSIGNB,
+ instrux_PSIGNW,
+ instrux_PSIGND,
+ instrux_EXTRQ,
+ instrux_INSERTQ,
+ instrux_MOVNTSD,
+ instrux_MOVNTSS,
+ instrux_LZCNT,
+ instrux_BLENDPD,
+ instrux_BLENDPS,
+ instrux_BLENDVPD,
+ instrux_BLENDVPS,
+ instrux_DPPD,
+ instrux_DPPS,
+ instrux_EXTRACTPS,
+ instrux_INSERTPS,
+ instrux_MOVNTDQA,
+ instrux_MPSADBW,
+ instrux_PACKUSDW,
+ instrux_PBLENDVB,
+ instrux_PBLENDW,
+ instrux_PCMPEQQ,
+ instrux_PEXTRB,
+ instrux_PEXTRD,
+ instrux_PEXTRQ,
+ instrux_PHMINPOSUW,
+ instrux_PINSRB,
+ instrux_PINSRD,
+ instrux_PINSRQ,
+ instrux_PMAXSB,
+ instrux_PMAXSD,
+ instrux_PMAXUD,
+ instrux_PMAXUW,
+ instrux_PMINSB,
+ instrux_PMINSD,
+ instrux_PMINUD,
+ instrux_PMINUW,
+ instrux_PMOVSXBW,
+ instrux_PMOVSXBD,
+ instrux_PMOVSXBQ,
+ instrux_PMOVSXWD,
+ instrux_PMOVSXWQ,
+ instrux_PMOVSXDQ,
+ instrux_PMOVZXBW,
+ instrux_PMOVZXBD,
+ instrux_PMOVZXBQ,
+ instrux_PMOVZXWD,
+ instrux_PMOVZXWQ,
+ instrux_PMOVZXDQ,
+ instrux_PMULDQ,
+ instrux_PMULLD,
+ instrux_PTEST,
+ instrux_ROUNDPD,
+ instrux_ROUNDPS,
+ instrux_ROUNDSD,
+ instrux_ROUNDSS,
+ instrux_CRC32,
+ instrux_PCMPESTRI,
+ instrux_PCMPESTRM,
+ instrux_PCMPISTRI,
+ instrux_PCMPISTRM,
+ instrux_PCMPGTQ,
+ instrux_POPCNT,
+ instrux_GETSEC,
+ instrux_PFRCPV,
+ instrux_PFRSQRTV,
+ instrux_MOVBE,
+ instrux_AESENC,
+ instrux_AESENCLAST,
+ instrux_AESDEC,
+ instrux_AESDECLAST,
+ instrux_AESIMC,
+ instrux_AESKEYGENASSIST,
+ instrux_VAESENC,
+ instrux_VAESENCLAST,
+ instrux_VAESDEC,
+ instrux_VAESDECLAST,
+ instrux_VAESIMC,
+ instrux_VAESKEYGENASSIST,
+ instrux_VADDPD,
+ instrux_VADDPS,
+ instrux_VADDSD,
+ instrux_VADDSS,
+ instrux_VADDSUBPD,
+ instrux_VADDSUBPS,
+ instrux_VANDPD,
+ instrux_VANDPS,
+ instrux_VANDNPD,
+ instrux_VANDNPS,
+ instrux_VBLENDPD,
+ instrux_VBLENDPS,
+ instrux_VBLENDVPD,
+ instrux_VBLENDVPS,
+ instrux_VBROADCASTSS,
+ instrux_VBROADCASTSD,
+ instrux_VBROADCASTF128,
+ instrux_VCMPEQ_OSPD,
+ instrux_VCMPEQPD,
+ instrux_VCMPLT_OSPD,
+ instrux_VCMPLTPD,
+ instrux_VCMPLE_OSPD,
+ instrux_VCMPLEPD,
+ instrux_VCMPUNORD_QPD,
+ instrux_VCMPUNORDPD,
+ instrux_VCMPNEQ_UQPD,
+ instrux_VCMPNEQPD,
+ instrux_VCMPNLT_USPD,
+ instrux_VCMPNLTPD,
+ instrux_VCMPNLE_USPD,
+ instrux_VCMPNLEPD,
+ instrux_VCMPORD_QPD,
+ instrux_VCMPORDPD,
+ instrux_VCMPEQ_UQPD,
+ instrux_VCMPNGE_USPD,
+ instrux_VCMPNGEPD,
+ instrux_VCMPNGT_USPD,
+ instrux_VCMPNGTPD,
+ instrux_VCMPFALSE_OQPD,
+ instrux_VCMPFALSEPD,
+ instrux_VCMPNEQ_OQPD,
+ instrux_VCMPGE_OSPD,
+ instrux_VCMPGEPD,
+ instrux_VCMPGT_OSPD,
+ instrux_VCMPGTPD,
+ instrux_VCMPTRUE_UQPD,
+ instrux_VCMPTRUEPD,
+ instrux_VCMPLT_OQPD,
+ instrux_VCMPLE_OQPD,
+ instrux_VCMPUNORD_SPD,
+ instrux_VCMPNEQ_USPD,
+ instrux_VCMPNLT_UQPD,
+ instrux_VCMPNLE_UQPD,
+ instrux_VCMPORD_SPD,
+ instrux_VCMPEQ_USPD,
+ instrux_VCMPNGE_UQPD,
+ instrux_VCMPNGT_UQPD,
+ instrux_VCMPFALSE_OSPD,
+ instrux_VCMPNEQ_OSPD,
+ instrux_VCMPGE_OQPD,
+ instrux_VCMPGT_OQPD,
+ instrux_VCMPTRUE_USPD,
+ instrux_VCMPPD,
+ instrux_VCMPEQ_OSPS,
+ instrux_VCMPEQPS,
+ instrux_VCMPLT_OSPS,
+ instrux_VCMPLTPS,
+ instrux_VCMPLE_OSPS,
+ instrux_VCMPLEPS,
+ instrux_VCMPUNORD_QPS,
+ instrux_VCMPUNORDPS,
+ instrux_VCMPNEQ_UQPS,
+ instrux_VCMPNEQPS,
+ instrux_VCMPNLT_USPS,
+ instrux_VCMPNLTPS,
+ instrux_VCMPNLE_USPS,
+ instrux_VCMPNLEPS,
+ instrux_VCMPORD_QPS,
+ instrux_VCMPORDPS,
+ instrux_VCMPEQ_UQPS,
+ instrux_VCMPNGE_USPS,
+ instrux_VCMPNGEPS,
+ instrux_VCMPNGT_USPS,
+ instrux_VCMPNGTPS,
+ instrux_VCMPFALSE_OQPS,
+ instrux_VCMPFALSEPS,
+ instrux_VCMPNEQ_OQPS,
+ instrux_VCMPGE_OSPS,
+ instrux_VCMPGEPS,
+ instrux_VCMPGT_OSPS,
+ instrux_VCMPGTPS,
+ instrux_VCMPTRUE_UQPS,
+ instrux_VCMPTRUEPS,
+ instrux_VCMPLT_OQPS,
+ instrux_VCMPLE_OQPS,
+ instrux_VCMPUNORD_SPS,
+ instrux_VCMPNEQ_USPS,
+ instrux_VCMPNLT_UQPS,
+ instrux_VCMPNLE_UQPS,
+ instrux_VCMPORD_SPS,
+ instrux_VCMPEQ_USPS,
+ instrux_VCMPNGE_UQPS,
+ instrux_VCMPNGT_UQPS,
+ instrux_VCMPFALSE_OSPS,
+ instrux_VCMPNEQ_OSPS,
+ instrux_VCMPGE_OQPS,
+ instrux_VCMPGT_OQPS,
+ instrux_VCMPTRUE_USPS,
+ instrux_VCMPPS,
+ instrux_VCMPEQ_OSSD,
+ instrux_VCMPEQSD,
+ instrux_VCMPLT_OSSD,
+ instrux_VCMPLTSD,
+ instrux_VCMPLE_OSSD,
+ instrux_VCMPLESD,
+ instrux_VCMPUNORD_QSD,
+ instrux_VCMPUNORDSD,
+ instrux_VCMPNEQ_UQSD,
+ instrux_VCMPNEQSD,
+ instrux_VCMPNLT_USSD,
+ instrux_VCMPNLTSD,
+ instrux_VCMPNLE_USSD,
+ instrux_VCMPNLESD,
+ instrux_VCMPORD_QSD,
+ instrux_VCMPORDSD,
+ instrux_VCMPEQ_UQSD,
+ instrux_VCMPNGE_USSD,
+ instrux_VCMPNGESD,
+ instrux_VCMPNGT_USSD,
+ instrux_VCMPNGTSD,
+ instrux_VCMPFALSE_OQSD,
+ instrux_VCMPFALSESD,
+ instrux_VCMPNEQ_OQSD,
+ instrux_VCMPGE_OSSD,
+ instrux_VCMPGESD,
+ instrux_VCMPGT_OSSD,
+ instrux_VCMPGTSD,
+ instrux_VCMPTRUE_UQSD,
+ instrux_VCMPTRUESD,
+ instrux_VCMPLT_OQSD,
+ instrux_VCMPLE_OQSD,
+ instrux_VCMPUNORD_SSD,
+ instrux_VCMPNEQ_USSD,
+ instrux_VCMPNLT_UQSD,
+ instrux_VCMPNLE_UQSD,
+ instrux_VCMPORD_SSD,
+ instrux_VCMPEQ_USSD,
+ instrux_VCMPNGE_UQSD,
+ instrux_VCMPNGT_UQSD,
+ instrux_VCMPFALSE_OSSD,
+ instrux_VCMPNEQ_OSSD,
+ instrux_VCMPGE_OQSD,
+ instrux_VCMPGT_OQSD,
+ instrux_VCMPTRUE_USSD,
+ instrux_VCMPSD,
+ instrux_VCMPEQ_OSSS,
+ instrux_VCMPEQSS,
+ instrux_VCMPLT_OSSS,
+ instrux_VCMPLTSS,
+ instrux_VCMPLE_OSSS,
+ instrux_VCMPLESS,
+ instrux_VCMPUNORD_QSS,
+ instrux_VCMPUNORDSS,
+ instrux_VCMPNEQ_UQSS,
+ instrux_VCMPNEQSS,
+ instrux_VCMPNLT_USSS,
+ instrux_VCMPNLTSS,
+ instrux_VCMPNLE_USSS,
+ instrux_VCMPNLESS,
+ instrux_VCMPORD_QSS,
+ instrux_VCMPORDSS,
+ instrux_VCMPEQ_UQSS,
+ instrux_VCMPNGE_USSS,
+ instrux_VCMPNGESS,
+ instrux_VCMPNGT_USSS,
+ instrux_VCMPNGTSS,
+ instrux_VCMPFALSE_OQSS,
+ instrux_VCMPFALSESS,
+ instrux_VCMPNEQ_OQSS,
+ instrux_VCMPGE_OSSS,
+ instrux_VCMPGESS,
+ instrux_VCMPGT_OSSS,
+ instrux_VCMPGTSS,
+ instrux_VCMPTRUE_UQSS,
+ instrux_VCMPTRUESS,
+ instrux_VCMPLT_OQSS,
+ instrux_VCMPLE_OQSS,
+ instrux_VCMPUNORD_SSS,
+ instrux_VCMPNEQ_USSS,
+ instrux_VCMPNLT_UQSS,
+ instrux_VCMPNLE_UQSS,
+ instrux_VCMPORD_SSS,
+ instrux_VCMPEQ_USSS,
+ instrux_VCMPNGE_UQSS,
+ instrux_VCMPNGT_UQSS,
+ instrux_VCMPFALSE_OSSS,
+ instrux_VCMPNEQ_OSSS,
+ instrux_VCMPGE_OQSS,
+ instrux_VCMPGT_OQSS,
+ instrux_VCMPTRUE_USSS,
+ instrux_VCMPSS,
+ instrux_VCOMISD,
+ instrux_VCOMISS,
+ instrux_VCVTDQ2PD,
+ instrux_VCVTDQ2PS,
+ instrux_VCVTPD2DQ,
+ instrux_VCVTPD2PS,
+ instrux_VCVTPS2DQ,
+ instrux_VCVTPS2PD,
+ instrux_VCVTSD2SI,
+ instrux_VCVTSD2SS,
+ instrux_VCVTSI2SD,
+ instrux_VCVTSI2SS,
+ instrux_VCVTSS2SD,
+ instrux_VCVTSS2SI,
+ instrux_VCVTTPD2DQ,
+ instrux_VCVTTPS2DQ,
+ instrux_VCVTTSD2SI,
+ instrux_VCVTTSS2SI,
+ instrux_VDIVPD,
+ instrux_VDIVPS,
+ instrux_VDIVSD,
+ instrux_VDIVSS,
+ instrux_VDPPD,
+ instrux_VDPPS,
+ instrux_VEXTRACTF128,
+ instrux_VEXTRACTPS,
+ instrux_VHADDPD,
+ instrux_VHADDPS,
+ instrux_VHSUBPD,
+ instrux_VHSUBPS,
+ instrux_VINSERTF128,
+ instrux_VINSERTPS,
+ instrux_VLDDQU,
+ instrux_VLDQQU,
+ instrux_VLDMXCSR,
+ instrux_VMASKMOVDQU,
+ instrux_VMASKMOVPS,
+ instrux_VMASKMOVPD,
+ instrux_VMAXPD,
+ instrux_VMAXPS,
+ instrux_VMAXSD,
+ instrux_VMAXSS,
+ instrux_VMINPD,
+ instrux_VMINPS,
+ instrux_VMINSD,
+ instrux_VMINSS,
+ instrux_VMOVAPD,
+ instrux_VMOVAPS,
+ instrux_VMOVD,
+ instrux_VMOVQ,
+ instrux_VMOVDDUP,
+ instrux_VMOVDQA,
+ instrux_VMOVQQA,
+ instrux_VMOVDQU,
+ instrux_VMOVQQU,
+ instrux_VMOVHLPS,
+ instrux_VMOVHPD,
+ instrux_VMOVHPS,
+ instrux_VMOVLHPS,
+ instrux_VMOVLPD,
+ instrux_VMOVLPS,
+ instrux_VMOVMSKPD,
+ instrux_VMOVMSKPS,
+ instrux_VMOVNTDQ,
+ instrux_VMOVNTQQ,
+ instrux_VMOVNTDQA,
+ instrux_VMOVNTPD,
+ instrux_VMOVNTPS,
+ instrux_VMOVSD,
+ instrux_VMOVSHDUP,
+ instrux_VMOVSLDUP,
+ instrux_VMOVSS,
+ instrux_VMOVUPD,
+ instrux_VMOVUPS,
+ instrux_VMPSADBW,
+ instrux_VMULPD,
+ instrux_VMULPS,
+ instrux_VMULSD,
+ instrux_VMULSS,
+ instrux_VORPD,
+ instrux_VORPS,
+ instrux_VPABSB,
+ instrux_VPABSW,
+ instrux_VPABSD,
+ instrux_VPACKSSWB,
+ instrux_VPACKSSDW,
+ instrux_VPACKUSWB,
+ instrux_VPACKUSDW,
+ instrux_VPADDB,
+ instrux_VPADDW,
+ instrux_VPADDD,
+ instrux_VPADDQ,
+ instrux_VPADDSB,
+ instrux_VPADDSW,
+ instrux_VPADDUSB,
+ instrux_VPADDUSW,
+ instrux_VPALIGNR,
+ instrux_VPAND,
+ instrux_VPANDN,
+ instrux_VPAVGB,
+ instrux_VPAVGW,
+ instrux_VPBLENDVB,
+ instrux_VPBLENDW,
+ instrux_VPCMPESTRI,
+ instrux_VPCMPESTRM,
+ instrux_VPCMPISTRI,
+ instrux_VPCMPISTRM,
+ instrux_VPCMPEQB,
+ instrux_VPCMPEQW,
+ instrux_VPCMPEQD,
+ instrux_VPCMPEQQ,
+ instrux_VPCMPGTB,
+ instrux_VPCMPGTW,
+ instrux_VPCMPGTD,
+ instrux_VPCMPGTQ,
+ instrux_VPERMILPD,
+ instrux_VPERMILPS,
+ instrux_VPERM2F128,
+ instrux_VPEXTRB,
+ instrux_VPEXTRW,
+ instrux_VPEXTRD,
+ instrux_VPEXTRQ,
+ instrux_VPHADDW,
+ instrux_VPHADDD,
+ instrux_VPHADDSW,
+ instrux_VPHMINPOSUW,
+ instrux_VPHSUBW,
+ instrux_VPHSUBD,
+ instrux_VPHSUBSW,
+ instrux_VPINSRB,
+ instrux_VPINSRW,
+ instrux_VPINSRD,
+ instrux_VPINSRQ,
+ instrux_VPMADDWD,
+ instrux_VPMADDUBSW,
+ instrux_VPMAXSB,
+ instrux_VPMAXSW,
+ instrux_VPMAXSD,
+ instrux_VPMAXUB,
+ instrux_VPMAXUW,
+ instrux_VPMAXUD,
+ instrux_VPMINSB,
+ instrux_VPMINSW,
+ instrux_VPMINSD,
+ instrux_VPMINUB,
+ instrux_VPMINUW,
+ instrux_VPMINUD,
+ instrux_VPMOVMSKB,
+ instrux_VPMOVSXBW,
+ instrux_VPMOVSXBD,
+ instrux_VPMOVSXBQ,
+ instrux_VPMOVSXWD,
+ instrux_VPMOVSXWQ,
+ instrux_VPMOVSXDQ,
+ instrux_VPMOVZXBW,
+ instrux_VPMOVZXBD,
+ instrux_VPMOVZXBQ,
+ instrux_VPMOVZXWD,
+ instrux_VPMOVZXWQ,
+ instrux_VPMOVZXDQ,
+ instrux_VPMULHUW,
+ instrux_VPMULHRSW,
+ instrux_VPMULHW,
+ instrux_VPMULLW,
+ instrux_VPMULLD,
+ instrux_VPMULUDQ,
+ instrux_VPMULDQ,
+ instrux_VPOR,
+ instrux_VPSADBW,
+ instrux_VPSHUFB,
+ instrux_VPSHUFD,
+ instrux_VPSHUFHW,
+ instrux_VPSHUFLW,
+ instrux_VPSIGNB,
+ instrux_VPSIGNW,
+ instrux_VPSIGND,
+ instrux_VPSLLDQ,
+ instrux_VPSRLDQ,
+ instrux_VPSLLW,
+ instrux_VPSLLD,
+ instrux_VPSLLQ,
+ instrux_VPSRAW,
+ instrux_VPSRAD,
+ instrux_VPSRLW,
+ instrux_VPSRLD,
+ instrux_VPSRLQ,
+ instrux_VPTEST,
+ instrux_VPSUBB,
+ instrux_VPSUBW,
+ instrux_VPSUBD,
+ instrux_VPSUBQ,
+ instrux_VPSUBSB,
+ instrux_VPSUBSW,
+ instrux_VPSUBUSB,
+ instrux_VPSUBUSW,
+ instrux_VPUNPCKHBW,
+ instrux_VPUNPCKHWD,
+ instrux_VPUNPCKHDQ,
+ instrux_VPUNPCKHQDQ,
+ instrux_VPUNPCKLBW,
+ instrux_VPUNPCKLWD,
+ instrux_VPUNPCKLDQ,
+ instrux_VPUNPCKLQDQ,
+ instrux_VPXOR,
+ instrux_VRCPPS,
+ instrux_VRCPSS,
+ instrux_VRSQRTPS,
+ instrux_VRSQRTSS,
+ instrux_VROUNDPD,
+ instrux_VROUNDPS,
+ instrux_VROUNDSD,
+ instrux_VROUNDSS,
+ instrux_VSHUFPD,
+ instrux_VSHUFPS,
+ instrux_VSQRTPD,
+ instrux_VSQRTPS,
+ instrux_VSQRTSD,
+ instrux_VSQRTSS,
+ instrux_VSTMXCSR,
+ instrux_VSUBPD,
+ instrux_VSUBPS,
+ instrux_VSUBSD,
+ instrux_VSUBSS,
+ instrux_VTESTPS,
+ instrux_VTESTPD,
+ instrux_VUCOMISD,
+ instrux_VUCOMISS,
+ instrux_VUNPCKHPD,
+ instrux_VUNPCKHPS,
+ instrux_VUNPCKLPD,
+ instrux_VUNPCKLPS,
+ instrux_VXORPD,
+ instrux_VXORPS,
+ instrux_VZEROALL,
+ instrux_VZEROUPPER,
+ instrux_PCLMULLQLQDQ,
+ instrux_PCLMULHQLQDQ,
+ instrux_PCLMULLQHQDQ,
+ instrux_PCLMULHQHQDQ,
+ instrux_PCLMULQDQ,
+ instrux_VPCLMULLQLQDQ,
+ instrux_VPCLMULHQLQDQ,
+ instrux_VPCLMULLQHQDQ,
+ instrux_VPCLMULHQHQDQ,
+ instrux_VPCLMULQDQ,
+ instrux_VFMADD132PS,
+ instrux_VFMADD132PD,
+ instrux_VFMADD312PS,
+ instrux_VFMADD312PD,
+ instrux_VFMADD213PS,
+ instrux_VFMADD213PD,
+ instrux_VFMADD123PS,
+ instrux_VFMADD123PD,
+ instrux_VFMADD231PS,
+ instrux_VFMADD231PD,
+ instrux_VFMADD321PS,
+ instrux_VFMADD321PD,
+ instrux_VFMADDSUB132PS,
+ instrux_VFMADDSUB132PD,
+ instrux_VFMADDSUB312PS,
+ instrux_VFMADDSUB312PD,
+ instrux_VFMADDSUB213PS,
+ instrux_VFMADDSUB213PD,
+ instrux_VFMADDSUB123PS,
+ instrux_VFMADDSUB123PD,
+ instrux_VFMADDSUB231PS,
+ instrux_VFMADDSUB231PD,
+ instrux_VFMADDSUB321PS,
+ instrux_VFMADDSUB321PD,
+ instrux_VFMSUB132PS,
+ instrux_VFMSUB132PD,
+ instrux_VFMSUB312PS,
+ instrux_VFMSUB312PD,
+ instrux_VFMSUB213PS,
+ instrux_VFMSUB213PD,
+ instrux_VFMSUB123PS,
+ instrux_VFMSUB123PD,
+ instrux_VFMSUB231PS,
+ instrux_VFMSUB231PD,
+ instrux_VFMSUB321PS,
+ instrux_VFMSUB321PD,
+ instrux_VFMSUBADD132PS,
+ instrux_VFMSUBADD132PD,
+ instrux_VFMSUBADD312PS,
+ instrux_VFMSUBADD312PD,
+ instrux_VFMSUBADD213PS,
+ instrux_VFMSUBADD213PD,
+ instrux_VFMSUBADD123PS,
+ instrux_VFMSUBADD123PD,
+ instrux_VFMSUBADD231PS,
+ instrux_VFMSUBADD231PD,
+ instrux_VFMSUBADD321PS,
+ instrux_VFMSUBADD321PD,
+ instrux_VFNMADD132PS,
+ instrux_VFNMADD132PD,
+ instrux_VFNMADD312PS,
+ instrux_VFNMADD312PD,
+ instrux_VFNMADD213PS,
+ instrux_VFNMADD213PD,
+ instrux_VFNMADD123PS,
+ instrux_VFNMADD123PD,
+ instrux_VFNMADD231PS,
+ instrux_VFNMADD231PD,
+ instrux_VFNMADD321PS,
+ instrux_VFNMADD321PD,
+ instrux_VFNMSUB132PS,
+ instrux_VFNMSUB132PD,
+ instrux_VFNMSUB312PS,
+ instrux_VFNMSUB312PD,
+ instrux_VFNMSUB213PS,
+ instrux_VFNMSUB213PD,
+ instrux_VFNMSUB123PS,
+ instrux_VFNMSUB123PD,
+ instrux_VFNMSUB231PS,
+ instrux_VFNMSUB231PD,
+ instrux_VFNMSUB321PS,
+ instrux_VFNMSUB321PD,
+ instrux_VFMADD132SS,
+ instrux_VFMADD132SD,
+ instrux_VFMADD312SS,
+ instrux_VFMADD312SD,
+ instrux_VFMADD213SS,
+ instrux_VFMADD213SD,
+ instrux_VFMADD123SS,
+ instrux_VFMADD123SD,
+ instrux_VFMADD231SS,
+ instrux_VFMADD231SD,
+ instrux_VFMADD321SS,
+ instrux_VFMADD321SD,
+ instrux_VFMSUB132SS,
+ instrux_VFMSUB132SD,
+ instrux_VFMSUB312SS,
+ instrux_VFMSUB312SD,
+ instrux_VFMSUB213SS,
+ instrux_VFMSUB213SD,
+ instrux_VFMSUB123SS,
+ instrux_VFMSUB123SD,
+ instrux_VFMSUB231SS,
+ instrux_VFMSUB231SD,
+ instrux_VFMSUB321SS,
+ instrux_VFMSUB321SD,
+ instrux_VFNMADD132SS,
+ instrux_VFNMADD132SD,
+ instrux_VFNMADD312SS,
+ instrux_VFNMADD312SD,
+ instrux_VFNMADD213SS,
+ instrux_VFNMADD213SD,
+ instrux_VFNMADD123SS,
+ instrux_VFNMADD123SD,
+ instrux_VFNMADD231SS,
+ instrux_VFNMADD231SD,
+ instrux_VFNMADD321SS,
+ instrux_VFNMADD321SD,
+ instrux_VFNMSUB132SS,
+ instrux_VFNMSUB132SD,
+ instrux_VFNMSUB312SS,
+ instrux_VFNMSUB312SD,
+ instrux_VFNMSUB213SS,
+ instrux_VFNMSUB213SD,
+ instrux_VFNMSUB123SS,
+ instrux_VFNMSUB123SD,
+ instrux_VFNMSUB231SS,
+ instrux_VFNMSUB231SD,
+ instrux_VFNMSUB321SS,
+ instrux_VFNMSUB321SD,
+ instrux_RDFSBASE,
+ instrux_RDGSBASE,
+ instrux_RDRAND,
+ instrux_WRFSBASE,
+ instrux_WRGSBASE,
+ instrux_VCVTPH2PS,
+ instrux_VCVTPS2PH,
+ instrux_ADCX,
+ instrux_ADOX,
+ instrux_RDSEED,
+ instrux_CLAC,
+ instrux_STAC,
+ instrux_XSTORE,
+ instrux_XCRYPTECB,
+ instrux_XCRYPTCBC,
+ instrux_XCRYPTCTR,
+ instrux_XCRYPTCFB,
+ instrux_XCRYPTOFB,
+ instrux_MONTMUL,
+ instrux_XSHA1,
+ instrux_XSHA256,
+ instrux_LLWPCB,
+ instrux_SLWPCB,
+ instrux_LWPVAL,
+ instrux_LWPINS,
+ instrux_VFMADDPD,
+ instrux_VFMADDPS,
+ instrux_VFMADDSD,
+ instrux_VFMADDSS,
+ instrux_VFMADDSUBPD,
+ instrux_VFMADDSUBPS,
+ instrux_VFMSUBADDPD,
+ instrux_VFMSUBADDPS,
+ instrux_VFMSUBPD,
+ instrux_VFMSUBPS,
+ instrux_VFMSUBSD,
+ instrux_VFMSUBSS,
+ instrux_VFNMADDPD,
+ instrux_VFNMADDPS,
+ instrux_VFNMADDSD,
+ instrux_VFNMADDSS,
+ instrux_VFNMSUBPD,
+ instrux_VFNMSUBPS,
+ instrux_VFNMSUBSD,
+ instrux_VFNMSUBSS,
+ instrux_VFRCZPD,
+ instrux_VFRCZPS,
+ instrux_VFRCZSD,
+ instrux_VFRCZSS,
+ instrux_VPCMOV,
+ instrux_VPCOMB,
+ instrux_VPCOMD,
+ instrux_VPCOMQ,
+ instrux_VPCOMUB,
+ instrux_VPCOMUD,
+ instrux_VPCOMUQ,
+ instrux_VPCOMUW,
+ instrux_VPCOMW,
+ instrux_VPHADDBD,
+ instrux_VPHADDBQ,
+ instrux_VPHADDBW,
+ instrux_VPHADDDQ,
+ instrux_VPHADDUBD,
+ instrux_VPHADDUBQ,
+ instrux_VPHADDUBW,
+ instrux_VPHADDUDQ,
+ instrux_VPHADDUWD,
+ instrux_VPHADDUWQ,
+ instrux_VPHADDWD,
+ instrux_VPHADDWQ,
+ instrux_VPHSUBBW,
+ instrux_VPHSUBDQ,
+ instrux_VPHSUBWD,
+ instrux_VPMACSDD,
+ instrux_VPMACSDQH,
+ instrux_VPMACSDQL,
+ instrux_VPMACSSDD,
+ instrux_VPMACSSDQH,
+ instrux_VPMACSSDQL,
+ instrux_VPMACSSWD,
+ instrux_VPMACSSWW,
+ instrux_VPMACSWD,
+ instrux_VPMACSWW,
+ instrux_VPMADCSSWD,
+ instrux_VPMADCSWD,
+ instrux_VPPERM,
+ instrux_VPROTB,
+ instrux_VPROTD,
+ instrux_VPROTQ,
+ instrux_VPROTW,
+ instrux_VPSHAB,
+ instrux_VPSHAD,
+ instrux_VPSHAQ,
+ instrux_VPSHAW,
+ instrux_VPSHLB,
+ instrux_VPSHLD,
+ instrux_VPSHLQ,
+ instrux_VPSHLW,
+ instrux_VBROADCASTI128,
+ instrux_VPBLENDD,
+ instrux_VPBROADCASTB,
+ instrux_VPBROADCASTW,
+ instrux_VPBROADCASTD,
+ instrux_VPBROADCASTQ,
+ instrux_VPERMD,
+ instrux_VPERMPD,
+ instrux_VPERMPS,
+ instrux_VPERMQ,
+ instrux_VPERM2I128,
+ instrux_VEXTRACTI128,
+ instrux_VINSERTI128,
+ instrux_VPMASKMOVD,
+ instrux_VPMASKMOVQ,
+ instrux_VPSLLVD,
+ instrux_VPSLLVQ,
+ instrux_VPSRAVD,
+ instrux_VPSRLVD,
+ instrux_VPSRLVQ,
+ instrux_VGATHERDPD,
+ instrux_VGATHERQPD,
+ instrux_VGATHERDPS,
+ instrux_VGATHERQPS,
+ instrux_VPGATHERDD,
+ instrux_VPGATHERQD,
+ instrux_VPGATHERDQ,
+ instrux_VPGATHERQQ,
+ instrux_XABORT,
+ instrux_XBEGIN,
+ instrux_XEND,
+ instrux_XTEST,
+ instrux_ANDN,
+ instrux_BEXTR,
+ instrux_BLCI,
+ instrux_BLCIC,
+ instrux_BLSI,
+ instrux_BLSIC,
+ instrux_BLCFILL,
+ instrux_BLSFILL,
+ instrux_BLCMSK,
+ instrux_BLSMSK,
+ instrux_BLSR,
+ instrux_BLCS,
+ instrux_BZHI,
+ instrux_MULX,
+ instrux_PDEP,
+ instrux_PEXT,
+ instrux_RORX,
+ instrux_SARX,
+ instrux_SHLX,
+ instrux_SHRX,
+ instrux_TZCNT,
+ instrux_TZMSK,
+ instrux_T1MSKC,
+ instrux_PREFETCHWT1,
+ instrux_BNDMK,
+ instrux_BNDCL,
+ instrux_BNDCU,
+ instrux_BNDCN,
+ instrux_BNDMOV,
+ instrux_BNDLDX,
+ instrux_BNDSTX,
+ instrux_SHA1MSG1,
+ instrux_SHA1MSG2,
+ instrux_SHA1NEXTE,
+ instrux_SHA1RNDS4,
+ instrux_SHA256MSG1,
+ instrux_SHA256MSG2,
+ instrux_SHA256RNDS2,
+ instrux_VBCSTNEBF16PS,
+ instrux_VBCSTNESH2PS,
+ instrux_VCVTNEEBF162PS,
+ instrux_VCVTNEEPH2PS,
+ instrux_VCVTNEOBF162PS,
+ instrux_VCVTNEOPH2PS,
+ instrux_VCVTNEPS2BF16,
+ instrux_VPDPBSSD,
+ instrux_VPDPBSSDS,
+ instrux_VPDPBSUD,
+ instrux_VPDPBSUDS,
+ instrux_VPDPBUUD,
+ instrux_VPDPBUUDS,
+ instrux_VPMADD52HUQ,
+ instrux_VPMADD52LUQ,
+ instrux_KADDB,
+ instrux_KADDD,
+ instrux_KADDQ,
+ instrux_KADDW,
+ instrux_KANDB,
+ instrux_KANDD,
+ instrux_KANDNB,
+ instrux_KANDND,
+ instrux_KANDNQ,
+ instrux_KANDNW,
+ instrux_KANDQ,
+ instrux_KANDW,
+ instrux_KMOVB,
+ instrux_KMOVD,
+ instrux_KMOVQ,
+ instrux_KMOVW,
+ instrux_KNOTB,
+ instrux_KNOTD,
+ instrux_KNOTQ,
+ instrux_KNOTW,
+ instrux_KORB,
+ instrux_KORD,
+ instrux_KORQ,
+ instrux_KORW,
+ instrux_KORTESTB,
+ instrux_KORTESTD,
+ instrux_KORTESTQ,
+ instrux_KORTESTW,
+ instrux_KSHIFTLB,
+ instrux_KSHIFTLD,
+ instrux_KSHIFTLQ,
+ instrux_KSHIFTLW,
+ instrux_KSHIFTRB,
+ instrux_KSHIFTRD,
+ instrux_KSHIFTRQ,
+ instrux_KSHIFTRW,
+ instrux_KTESTB,
+ instrux_KTESTD,
+ instrux_KTESTQ,
+ instrux_KTESTW,
+ instrux_KUNPCKBW,
+ instrux_KUNPCKDQ,
+ instrux_KUNPCKWD,
+ instrux_KXNORB,
+ instrux_KXNORD,
+ instrux_KXNORQ,
+ instrux_KXNORW,
+ instrux_KXORB,
+ instrux_KXORD,
+ instrux_KXORQ,
+ instrux_KXORW,
+ instrux_KADD,
+ instrux_KAND,
+ instrux_KANDN,
+ instrux_KMOV,
+ instrux_KNOT,
+ instrux_KOR,
+ instrux_KORTEST,
+ instrux_KSHIFTL,
+ instrux_KSHIFTR,
+ instrux_KTEST,
+ instrux_KUNPCK,
+ instrux_KXNOR,
+ instrux_KXOR,
+ instrux_VALIGND,
+ instrux_VALIGNQ,
+ instrux_VBLENDMPD,
+ instrux_VBLENDMPS,
+ instrux_VBROADCASTF32X2,
+ instrux_VBROADCASTF32X4,
+ instrux_VBROADCASTF32X8,
+ instrux_VBROADCASTF64X2,
+ instrux_VBROADCASTF64X4,
+ instrux_VBROADCASTI32X2,
+ instrux_VBROADCASTI32X4,
+ instrux_VBROADCASTI32X8,
+ instrux_VBROADCASTI64X2,
+ instrux_VBROADCASTI64X4,
+ instrux_VCMPEQ_OQPD,
+ instrux_VCMPEQ_OQPS,
+ instrux_VCMPEQ_OQSD,
+ instrux_VCMPEQ_OQSS,
+ instrux_VCOMPRESSPD,
+ instrux_VCOMPRESSPS,
+ instrux_VCVTPD2QQ,
+ instrux_VCVTPD2UDQ,
+ instrux_VCVTPD2UQQ,
+ instrux_VCVTPS2QQ,
+ instrux_VCVTPS2UDQ,
+ instrux_VCVTPS2UQQ,
+ instrux_VCVTQQ2PD,
+ instrux_VCVTQQ2PS,
+ instrux_VCVTSD2USI,
+ instrux_VCVTSS2USI,
+ instrux_VCVTTPD2QQ,
+ instrux_VCVTTPD2UDQ,
+ instrux_VCVTTPD2UQQ,
+ instrux_VCVTTPS2QQ,
+ instrux_VCVTTPS2UDQ,
+ instrux_VCVTTPS2UQQ,
+ instrux_VCVTTSD2USI,
+ instrux_VCVTTSS2USI,
+ instrux_VCVTUDQ2PD,
+ instrux_VCVTUDQ2PS,
+ instrux_VCVTUQQ2PD,
+ instrux_VCVTUQQ2PS,
+ instrux_VCVTUSI2SD,
+ instrux_VCVTUSI2SS,
+ instrux_VDBPSADBW,
+ instrux_VEXP2PD,
+ instrux_VEXP2PS,
+ instrux_VEXPANDPD,
+ instrux_VEXPANDPS,
+ instrux_VEXTRACTF32X4,
+ instrux_VEXTRACTF32X8,
+ instrux_VEXTRACTF64X2,
+ instrux_VEXTRACTF64X4,
+ instrux_VEXTRACTI32X4,
+ instrux_VEXTRACTI32X8,
+ instrux_VEXTRACTI64X2,
+ instrux_VEXTRACTI64X4,
+ instrux_VFIXUPIMMPD,
+ instrux_VFIXUPIMMPS,
+ instrux_VFIXUPIMMSD,
+ instrux_VFIXUPIMMSS,
+ instrux_VFPCLASSPD,
+ instrux_VFPCLASSPS,
+ instrux_VFPCLASSSD,
+ instrux_VFPCLASSSS,
+ instrux_VGATHERPF0DPD,
+ instrux_VGATHERPF0DPS,
+ instrux_VGATHERPF0QPD,
+ instrux_VGATHERPF0QPS,
+ instrux_VGATHERPF1DPD,
+ instrux_VGATHERPF1DPS,
+ instrux_VGATHERPF1QPD,
+ instrux_VGATHERPF1QPS,
+ instrux_VGETEXPPD,
+ instrux_VGETEXPPS,
+ instrux_VGETEXPSD,
+ instrux_VGETEXPSS,
+ instrux_VGETMANTPD,
+ instrux_VGETMANTPS,
+ instrux_VGETMANTSD,
+ instrux_VGETMANTSS,
+ instrux_VINSERTF32X4,
+ instrux_VINSERTF32X8,
+ instrux_VINSERTF64X2,
+ instrux_VINSERTF64X4,
+ instrux_VINSERTI32X4,
+ instrux_VINSERTI32X8,
+ instrux_VINSERTI64X2,
+ instrux_VINSERTI64X4,
+ instrux_VMOVDQA32,
+ instrux_VMOVDQA64,
+ instrux_VMOVDQU16,
+ instrux_VMOVDQU32,
+ instrux_VMOVDQU64,
+ instrux_VMOVDQU8,
+ instrux_VPABSQ,
+ instrux_VPANDD,
+ instrux_VPANDND,
+ instrux_VPANDNQ,
+ instrux_VPANDQ,
+ instrux_VPBLENDMB,
+ instrux_VPBLENDMD,
+ instrux_VPBLENDMQ,
+ instrux_VPBLENDMW,
+ instrux_VPBROADCASTMB2Q,
+ instrux_VPBROADCASTMW2D,
+ instrux_VPCMPEQUB,
+ instrux_VPCMPEQUD,
+ instrux_VPCMPEQUQ,
+ instrux_VPCMPEQUW,
+ instrux_VPCMPGEB,
+ instrux_VPCMPGED,
+ instrux_VPCMPGEQ,
+ instrux_VPCMPGEUB,
+ instrux_VPCMPGEUD,
+ instrux_VPCMPGEUQ,
+ instrux_VPCMPGEUW,
+ instrux_VPCMPGEW,
+ instrux_VPCMPGTUB,
+ instrux_VPCMPGTUD,
+ instrux_VPCMPGTUQ,
+ instrux_VPCMPGTUW,
+ instrux_VPCMPLEB,
+ instrux_VPCMPLED,
+ instrux_VPCMPLEQ,
+ instrux_VPCMPLEUB,
+ instrux_VPCMPLEUD,
+ instrux_VPCMPLEUQ,
+ instrux_VPCMPLEUW,
+ instrux_VPCMPLEW,
+ instrux_VPCMPLTB,
+ instrux_VPCMPLTD,
+ instrux_VPCMPLTQ,
+ instrux_VPCMPLTUB,
+ instrux_VPCMPLTUD,
+ instrux_VPCMPLTUQ,
+ instrux_VPCMPLTUW,
+ instrux_VPCMPLTW,
+ instrux_VPCMPNEQB,
+ instrux_VPCMPNEQD,
+ instrux_VPCMPNEQQ,
+ instrux_VPCMPNEQUB,
+ instrux_VPCMPNEQUD,
+ instrux_VPCMPNEQUQ,
+ instrux_VPCMPNEQUW,
+ instrux_VPCMPNEQW,
+ instrux_VPCMPNGTB,
+ instrux_VPCMPNGTD,
+ instrux_VPCMPNGTQ,
+ instrux_VPCMPNGTUB,
+ instrux_VPCMPNGTUD,
+ instrux_VPCMPNGTUQ,
+ instrux_VPCMPNGTUW,
+ instrux_VPCMPNGTW,
+ instrux_VPCMPNLEB,
+ instrux_VPCMPNLED,
+ instrux_VPCMPNLEQ,
+ instrux_VPCMPNLEUB,
+ instrux_VPCMPNLEUD,
+ instrux_VPCMPNLEUQ,
+ instrux_VPCMPNLEUW,
+ instrux_VPCMPNLEW,
+ instrux_VPCMPNLTB,
+ instrux_VPCMPNLTD,
+ instrux_VPCMPNLTQ,
+ instrux_VPCMPNLTUB,
+ instrux_VPCMPNLTUD,
+ instrux_VPCMPNLTUQ,
+ instrux_VPCMPNLTUW,
+ instrux_VPCMPNLTW,
+ instrux_VPCMPB,
+ instrux_VPCMPD,
+ instrux_VPCMPQ,
+ instrux_VPCMPUB,
+ instrux_VPCMPUD,
+ instrux_VPCMPUQ,
+ instrux_VPCMPUW,
+ instrux_VPCMPW,
+ instrux_VPCOMPRESSD,
+ instrux_VPCOMPRESSQ,
+ instrux_VPCONFLICTD,
+ instrux_VPCONFLICTQ,
+ instrux_VPERMB,
+ instrux_VPERMI2B,
+ instrux_VPERMI2D,
+ instrux_VPERMI2PD,
+ instrux_VPERMI2PS,
+ instrux_VPERMI2Q,
+ instrux_VPERMI2W,
+ instrux_VPERMT2B,
+ instrux_VPERMT2D,
+ instrux_VPERMT2PD,
+ instrux_VPERMT2PS,
+ instrux_VPERMT2Q,
+ instrux_VPERMT2W,
+ instrux_VPERMW,
+ instrux_VPEXPANDD,
+ instrux_VPEXPANDQ,
+ instrux_VPLZCNTD,
+ instrux_VPLZCNTQ,
+ instrux_VPMAXSQ,
+ instrux_VPMAXUQ,
+ instrux_VPMINSQ,
+ instrux_VPMINUQ,
+ instrux_VPMOVB2M,
+ instrux_VPMOVD2M,
+ instrux_VPMOVDB,
+ instrux_VPMOVDW,
+ instrux_VPMOVM2B,
+ instrux_VPMOVM2D,
+ instrux_VPMOVM2Q,
+ instrux_VPMOVM2W,
+ instrux_VPMOVQ2M,
+ instrux_VPMOVQB,
+ instrux_VPMOVQD,
+ instrux_VPMOVQW,
+ instrux_VPMOVSDB,
+ instrux_VPMOVSDW,
+ instrux_VPMOVSQB,
+ instrux_VPMOVSQD,
+ instrux_VPMOVSQW,
+ instrux_VPMOVSWB,
+ instrux_VPMOVUSDB,
+ instrux_VPMOVUSDW,
+ instrux_VPMOVUSQB,
+ instrux_VPMOVUSQD,
+ instrux_VPMOVUSQW,
+ instrux_VPMOVUSWB,
+ instrux_VPMOVW2M,
+ instrux_VPMOVWB,
+ instrux_VPMULLQ,
+ instrux_VPMULTISHIFTQB,
+ instrux_VPORD,
+ instrux_VPORQ,
+ instrux_VPROLD,
+ instrux_VPROLQ,
+ instrux_VPROLVD,
+ instrux_VPROLVQ,
+ instrux_VPRORD,
+ instrux_VPRORQ,
+ instrux_VPRORVD,
+ instrux_VPRORVQ,
+ instrux_VPSCATTERDD,
+ instrux_VPSCATTERDQ,
+ instrux_VPSCATTERQD,
+ instrux_VPSCATTERQQ,
+ instrux_VPSLLVW,
+ instrux_VPSRAQ,
+ instrux_VPSRAVQ,
+ instrux_VPSRAVW,
+ instrux_VPSRLVW,
+ instrux_VPTERNLOGD,
+ instrux_VPTERNLOGQ,
+ instrux_VPTESTMB,
+ instrux_VPTESTMD,
+ instrux_VPTESTMQ,
+ instrux_VPTESTMW,
+ instrux_VPTESTNMB,
+ instrux_VPTESTNMD,
+ instrux_VPTESTNMQ,
+ instrux_VPTESTNMW,
+ instrux_VPXORD,
+ instrux_VPXORQ,
+ instrux_VRANGEPD,
+ instrux_VRANGEPS,
+ instrux_VRANGESD,
+ instrux_VRANGESS,
+ instrux_VRCP14PD,
+ instrux_VRCP14PS,
+ instrux_VRCP14SD,
+ instrux_VRCP14SS,
+ instrux_VRCP28PD,
+ instrux_VRCP28PS,
+ instrux_VRCP28SD,
+ instrux_VRCP28SS,
+ instrux_VREDUCEPD,
+ instrux_VREDUCEPS,
+ instrux_VREDUCESD,
+ instrux_VREDUCESS,
+ instrux_VRNDSCALEPD,
+ instrux_VRNDSCALEPS,
+ instrux_VRNDSCALESD,
+ instrux_VRNDSCALESS,
+ instrux_VRSQRT14PD,
+ instrux_VRSQRT14PS,
+ instrux_VRSQRT14SD,
+ instrux_VRSQRT14SS,
+ instrux_VRSQRT28PD,
+ instrux_VRSQRT28PS,
+ instrux_VRSQRT28SD,
+ instrux_VRSQRT28SS,
+ instrux_VSCALEFPD,
+ instrux_VSCALEFPS,
+ instrux_VSCALEFSD,
+ instrux_VSCALEFSS,
+ instrux_VSCATTERDPD,
+ instrux_VSCATTERDPS,
+ instrux_VSCATTERPF0DPD,
+ instrux_VSCATTERPF0DPS,
+ instrux_VSCATTERPF0QPD,
+ instrux_VSCATTERPF0QPS,
+ instrux_VSCATTERPF1DPD,
+ instrux_VSCATTERPF1DPS,
+ instrux_VSCATTERPF1QPD,
+ instrux_VSCATTERPF1QPS,
+ instrux_VSCATTERQPD,
+ instrux_VSCATTERQPS,
+ instrux_VSHUFF32X4,
+ instrux_VSHUFF64X2,
+ instrux_VSHUFI32X4,
+ instrux_VSHUFI64X2,
+ instrux_RDPKRU,
+ instrux_WRPKRU,
+ instrux_RDPID,
+ instrux_CLFLUSHOPT,
+ instrux_CLWB,
+ instrux_PCOMMIT,
+ instrux_CLZERO,
+ instrux_PTWRITE,
+ instrux_CLDEMOTE,
+ instrux_MOVDIRI,
+ instrux_MOVDIR64B,
+ instrux_PCONFIG,
+ instrux_TPAUSE,
+ instrux_UMONITOR,
+ instrux_UMWAIT,
+ instrux_WBNOINVD,
+ instrux_GF2P8AFFINEINVQB,
+ instrux_VGF2P8AFFINEINVQB,
+ instrux_GF2P8AFFINEQB,
+ instrux_VGF2P8AFFINEQB,
+ instrux_GF2P8MULB,
+ instrux_VGF2P8MULB,
+ instrux_VPCOMPRESSB,
+ instrux_VPCOMPRESSW,
+ instrux_VPEXPANDB,
+ instrux_VPEXPANDW,
+ instrux_VPSHLDW,
+ instrux_VPSHLDD,
+ instrux_VPSHLDQ,
+ instrux_VPSHLDVW,
+ instrux_VPSHLDVD,
+ instrux_VPSHLDVQ,
+ instrux_VPSHRDW,
+ instrux_VPSHRDD,
+ instrux_VPSHRDQ,
+ instrux_VPSHRDVW,
+ instrux_VPSHRDVD,
+ instrux_VPSHRDVQ,
+ instrux_VPDPBUSD,
+ instrux_VPDPBUSDS,
+ instrux_VPDPWSSD,
+ instrux_VPDPWSSDS,
+ instrux_VPOPCNTB,
+ instrux_VPOPCNTW,
+ instrux_VPOPCNTD,
+ instrux_VPOPCNTQ,
+ instrux_VPSHUFBITQMB,
+ instrux_V4FMADDPS,
+ instrux_V4FNMADDPS,
+ instrux_V4FMADDSS,
+ instrux_V4FNMADDSS,
+ instrux_V4DPWSSDS,
+ instrux_V4DPWSSD,
+ instrux_ENCLS,
+ instrux_ENCLU,
+ instrux_ENCLV,
+ instrux_CLRSSBSY,
+ instrux_ENDBR32,
+ instrux_ENDBR64,
+ instrux_INCSSPD,
+ instrux_INCSSPQ,
+ instrux_RDSSPD,
+ instrux_RDSSPQ,
+ instrux_RSTORSSP,
+ instrux_SAVEPREVSSP,
+ instrux_SETSSBSY,
+ instrux_WRUSSD,
+ instrux_WRUSSQ,
+ instrux_WRSSD,
+ instrux_WRSSQ,
+ instrux_ENQCMD,
+ instrux_ENQCMDS,
+ instrux_SERIALIZE,
+ instrux_XRESLDTRK,
+ instrux_XSUSLDTRK,
+ instrux_VCVTNE2PS2BF16,
+ instrux_VDPBF16PS,
+ instrux_VP2INTERSECTD,
+ instrux_LDTILECFG,
+ instrux_STTILECFG,
+ instrux_TDPBF16PS,
+ instrux_TDPBSSD,
+ instrux_TDPBSUD,
+ instrux_TDPBUSD,
+ instrux_TDPBUUD,
+ instrux_TILELOADD,
+ instrux_TILELOADDT1,
+ instrux_TILERELEASE,
+ instrux_TILESTORED,
+ instrux_TILEZERO,
+ instrux_VADDPH,
+ instrux_VADDSH,
+ instrux_VCMPPH,
+ instrux_VCMPSH,
+ instrux_VCOMISH,
+ instrux_VCVTDQ2PH,
+ instrux_VCVTPD2PH,
+ instrux_VCVTPH2DQ,
+ instrux_VCVTPH2PD,
+ instrux_VCVTPH2PSX,
+ instrux_VCVTPH2QQ,
+ instrux_VCVTPH2UDQ,
+ instrux_VCVTPH2UQQ,
+ instrux_VCVTPH2UW,
+ instrux_VCVTPH2W,
+ instrux_VCVTQQ2PH,
+ instrux_VCVTSD2SH,
+ instrux_VCVTSH2SD,
+ instrux_VCVTSH2SI,
+ instrux_VCVTSH2SS,
+ instrux_VCVTSH2USI,
+ instrux_VCVTSI2SH,
+ instrux_VCVTSS2SH,
+ instrux_VCVTTPH2DQ,
+ instrux_VCVTTPH2QQ,
+ instrux_VCVTTPH2UDQ,
+ instrux_VCVTTPH2UQQ,
+ instrux_VCVTTPH2UW,
+ instrux_VCVTTPH2W,
+ instrux_VCVTTSH2SI,
+ instrux_VCVTTSH2USI,
+ instrux_VCVTUDQ2PH,
+ instrux_VCVTUQQ2PH,
+ instrux_VCVTUSI2SH,
+ instrux_VCVTUW2PH,
+ instrux_VCVTW2PH,
+ instrux_VDIVPH,
+ instrux_VDIVSH,
+ instrux_VFCMADDCPH,
+ instrux_VFMADDCPH,
+ instrux_VFCMADDCSH,
+ instrux_VFMADDCSH,
+ instrux_VFCMULCPCH,
+ instrux_VFMULCPCH,
+ instrux_VFCMULCSH,
+ instrux_VFMULCSH,
+ instrux_VFMADDSUB132PH,
+ instrux_VFMADDSUB213PH,
+ instrux_VFMADDSUB231PH,
+ instrux_VFMSUBADD132PH,
+ instrux_VFMSUBADD213PH,
+ instrux_VFMSUBADD231PH,
+ instrux_VPMADD132PH,
+ instrux_VPMADD213PH,
+ instrux_VPMADD231PH,
+ instrux_VFMADD132PH,
+ instrux_VFMADD213PH,
+ instrux_VFMADD231PH,
+ instrux_VPMADD132SH,
+ instrux_VPMADD213SH,
+ instrux_VPMADD231SH,
+ instrux_VPNMADD132SH,
+ instrux_VPNMADD213SH,
+ instrux_VPNMADD231SH,
+ instrux_VPMSUB132PH,
+ instrux_VPMSUB213PH,
+ instrux_VPMSUB231PH,
+ instrux_VFMSUB132PH,
+ instrux_VFMSUB213PH,
+ instrux_VFMSUB231PH,
+ instrux_VPMSUB132SH,
+ instrux_VPMSUB213SH,
+ instrux_VPMSUB231SH,
+ instrux_VPNMSUB132SH,
+ instrux_VPNMSUB213SH,
+ instrux_VPNMSUB231SH,
+ instrux_VFPCLASSPH,
+ instrux_VFPCLASSSH,
+ instrux_VGETEXPPH,
+ instrux_VGETEXPSH,
+ instrux_VGETMANTPH,
+ instrux_VGETMANTSH,
+ instrux_VGETMAXPH,
+ instrux_VGETMAXSH,
+ instrux_VGETMINPH,
+ instrux_VGETMINSH,
+ instrux_VMOVSH,
+ instrux_VMOVW,
+ instrux_VMULPH,
+ instrux_VMULSH,
+ instrux_VRCPPH,
+ instrux_VRCPSH,
+ instrux_VREDUCEPH,
+ instrux_VREDUCESH,
+ instrux_VENDSCALEPH,
+ instrux_VENDSCALESH,
+ instrux_VRSQRTPH,
+ instrux_VRSQRTSH,
+ instrux_VSCALEFPH,
+ instrux_VSCALEFSH,
+ instrux_VSQRTPH,
+ instrux_VSQRTSH,
+ instrux_VSUBPH,
+ instrux_VSUBSH,
+ instrux_VUCOMISH,
+ instrux_AADD,
+ instrux_AAND,
+ instrux_AXOR,
+ instrux_CLUI,
+ instrux_SENDUIPI,
+ instrux_STUI,
+ instrux_TESTUI,
+ instrux_UIRET,
+ instrux_CMPAXADD,
+ instrux_CMPAEXADD,
+ instrux_CMPBXADD,
+ instrux_CMPBEXADD,
+ instrux_CMPCXADD,
+ instrux_CMPEXADD,
+ instrux_CMPGXADD,
+ instrux_CMPGEXADD,
+ instrux_CMPLXADD,
+ instrux_CMPLEXADD,
+ instrux_CMPNAXADD,
+ instrux_CMPNAEXADD,
+ instrux_CMPNBXADD,
+ instrux_CMPNBEXADD,
+ instrux_CMPNCXADD,
+ instrux_CMPNEXADD,
+ instrux_CMPNGXADD,
+ instrux_CMPNGEXADD,
+ instrux_CMPNLXADD,
+ instrux_CMPNLEXADD,
+ instrux_CMPNOXADD,
+ instrux_CMPNPXADD,
+ instrux_CMPNSXADD,
+ instrux_CMPNZXADD,
+ instrux_CMPOXADD,
+ instrux_CMPPXADD,
+ instrux_CMPPEXADD,
+ instrux_CMPPOXADD,
+ instrux_CMPSXADD,
+ instrux_CMPZXADD,
+ instrux_WRMSRNS,
+ instrux_RDMSRLIST,
+ instrux_WRMSRLIST,
+ instrux_HRESET,
+ instrux_HINT_NOP0,
+ instrux_HINT_NOP1,
+ instrux_HINT_NOP2,
+ instrux_HINT_NOP3,
+ instrux_HINT_NOP4,
+ instrux_HINT_NOP5,
+ instrux_HINT_NOP6,
+ instrux_HINT_NOP7,
+ instrux_HINT_NOP8,
+ instrux_HINT_NOP9,
+ instrux_HINT_NOP10,
+ instrux_HINT_NOP11,
+ instrux_HINT_NOP12,
+ instrux_HINT_NOP13,
+ instrux_HINT_NOP14,
+ instrux_HINT_NOP15,
+ instrux_HINT_NOP16,
+ instrux_HINT_NOP17,
+ instrux_HINT_NOP18,
+ instrux_HINT_NOP19,
+ instrux_HINT_NOP20,
+ instrux_HINT_NOP21,
+ instrux_HINT_NOP22,
+ instrux_HINT_NOP23,
+ instrux_HINT_NOP24,
+ instrux_HINT_NOP25,
+ instrux_HINT_NOP26,
+ instrux_HINT_NOP27,
+ instrux_HINT_NOP28,
+ instrux_HINT_NOP29,
+ instrux_HINT_NOP30,
+ instrux_HINT_NOP31,
+ instrux_HINT_NOP32,
+ instrux_HINT_NOP33,
+ instrux_HINT_NOP34,
+ instrux_HINT_NOP35,
+ instrux_HINT_NOP36,
+ instrux_HINT_NOP37,
+ instrux_HINT_NOP38,
+ instrux_HINT_NOP39,
+ instrux_HINT_NOP40,
+ instrux_HINT_NOP41,
+ instrux_HINT_NOP42,
+ instrux_HINT_NOP43,
+ instrux_HINT_NOP44,
+ instrux_HINT_NOP45,
+ instrux_HINT_NOP46,
+ instrux_HINT_NOP47,
+ instrux_HINT_NOP48,
+ instrux_HINT_NOP49,
+ instrux_HINT_NOP50,
+ instrux_HINT_NOP51,
+ instrux_HINT_NOP52,
+ instrux_HINT_NOP53,
+ instrux_HINT_NOP54,
+ instrux_HINT_NOP55,
+ instrux_HINT_NOP56,
+ instrux_HINT_NOP57,
+ instrux_HINT_NOP58,
+ instrux_HINT_NOP59,
+ instrux_HINT_NOP60,
+ instrux_HINT_NOP61,
+ instrux_HINT_NOP62,
+ instrux_HINT_NOP63,
+};
diff --git a/vere/ext/nasm/x86/insnsb.c b/vere/ext/nasm/x86/insnsb.c
new file mode 100644
index 0000000..decc3db
--- /dev/null
+++ b/vere/ext/nasm/x86/insnsb.c
@@ -0,0 +1,6748 @@
+/* This file auto-generated from insns.dat by insns.pl - don't edit it */
+
+#include "nasm.h"
+#include "insns.h"
+
+const uint8_t nasm_bytecodes[50229] = {
+ /* 0 */ 0241,0203,041,0301,01,0104,0120,01,0,0,
+ /* 10 */ 0240,0203,041,0301,01,0104,0110,01,0,0,
+ /* 20 */ 0241,0203,041,0301,01,0104,0120,01,01,0,
+ /* 30 */ 0240,0203,041,0301,01,0104,0110,01,01,0,
+ /* 40 */ 0241,0203,041,0301,01,0104,0120,01,020,0,
+ /* 50 */ 0240,0203,041,0301,01,0104,0110,01,020,0,
+ /* 60 */ 0241,0203,041,0301,01,0104,0120,01,021,0,
+ /* 70 */ 0240,0203,041,0301,01,0104,0110,01,021,0,
+ /* 80 */ 0241,0203,045,0301,01,0104,0120,01,0,0,
+ /* 90 */ 0240,0203,045,0301,01,0104,0110,01,0,0,
+ /* 100 */ 0241,0203,045,0301,01,0104,0120,01,01,0,
+ /* 110 */ 0240,0203,045,0301,01,0104,0110,01,01,0,
+ /* 120 */ 0241,0203,045,0301,01,0104,0120,01,020,0,
+ /* 130 */ 0240,0203,045,0301,01,0104,0110,01,020,0,
+ /* 140 */ 0241,0203,045,0301,01,0104,0120,01,021,0,
+ /* 150 */ 0240,0203,045,0301,01,0104,0110,01,021,0,
+ /* 160 */ 0241,0203,051,0301,01,0104,0120,01,0,0,
+ /* 170 */ 0240,0203,051,0301,01,0104,0110,01,0,0,
+ /* 180 */ 0241,0203,051,0301,01,0104,0120,01,01,0,
+ /* 190 */ 0240,0203,051,0301,01,0104,0110,01,01,0,
+ /* 200 */ 0241,0203,051,0301,01,0104,0120,01,020,0,
+ /* 210 */ 0240,0203,051,0301,01,0104,0110,01,020,0,
+ /* 220 */ 0241,0203,051,0301,01,0104,0120,01,021,0,
+ /* 230 */ 0240,0203,051,0301,01,0104,0110,01,021,0,
+ /* 240 */ 0241,0201,021,0301,01,0302,0120,01,0,0,
+ /* 250 */ 0241,0201,025,0301,01,0302,0120,01,0,0,
+ /* 260 */ 0241,0201,031,0301,01,0302,0120,01,0,0,
+ /* 270 */ 0241,0201,0,0301,01,0302,0120,01,0,0,
+ /* 280 */ 0241,0201,04,0301,01,0302,0120,01,0,0,
+ /* 290 */ 0241,0201,010,0301,01,0302,0120,01,0,0,
+ /* 300 */ 0241,0201,023,0306,01,0302,0120,01,0,0,
+ /* 310 */ 0241,0201,02,0306,01,0302,0120,01,0,0,
+ /* 320 */ 0241,0201,021,0301,01,0302,0120,01,01,0,
+ /* 330 */ 0241,0201,025,0301,01,0302,0120,01,01,0,
+ /* 340 */ 0241,0201,031,0301,01,0302,0120,01,01,0,
+ /* 350 */ 0241,0201,0,0301,01,0302,0120,01,01,0,
+ /* 360 */ 0241,0201,04,0301,01,0302,0120,01,01,0,
+ /* 370 */ 0241,0201,010,0301,01,0302,0120,01,01,0,
+ /* 380 */ 0241,0201,023,0306,01,0302,0120,01,01,0,
+ /* 390 */ 0241,0201,02,0306,01,0302,0120,01,01,0,
+ /* 400 */ 0241,0201,021,0301,01,0302,0120,01,02,0,
+ /* 410 */ 0241,0201,025,0301,01,0302,0120,01,02,0,
+ /* 420 */ 0241,0201,031,0301,01,0302,0120,01,02,0,
+ /* 430 */ 0241,0201,0,0301,01,0302,0120,01,02,0,
+ /* 440 */ 0241,0201,04,0301,01,0302,0120,01,02,0,
+ /* 450 */ 0241,0201,010,0301,01,0302,0120,01,02,0,
+ /* 460 */ 0241,0201,023,0306,01,0302,0120,01,02,0,
+ /* 470 */ 0241,0201,02,0306,01,0302,0120,01,02,0,
+ /* 480 */ 0241,0201,021,0301,01,0302,0120,01,03,0,
+ /* 490 */ 0241,0201,025,0301,01,0302,0120,01,03,0,
+ /* 500 */ 0241,0201,031,0301,01,0302,0120,01,03,0,
+ /* 510 */ 0241,0201,0,0301,01,0302,0120,01,03,0,
+ /* 520 */ 0241,0201,04,0301,01,0302,0120,01,03,0,
+ /* 530 */ 0241,0201,010,0301,01,0302,0120,01,03,0,
+ /* 540 */ 0241,0201,023,0306,01,0302,0120,01,03,0,
+ /* 550 */ 0241,0201,02,0306,01,0302,0120,01,03,0,
+ /* 560 */ 0241,0201,021,0301,01,0302,0120,01,04,0,
+ /* 570 */ 0241,0201,025,0301,01,0302,0120,01,04,0,
+ /* 580 */ 0241,0201,031,0301,01,0302,0120,01,04,0,
+ /* 590 */ 0241,0201,0,0301,01,0302,0120,01,04,0,
+ /* 600 */ 0241,0201,04,0301,01,0302,0120,01,04,0,
+ /* 610 */ 0241,0201,010,0301,01,0302,0120,01,04,0,
+ /* 620 */ 0241,0201,023,0306,01,0302,0120,01,04,0,
+ /* 630 */ 0241,0201,02,0306,01,0302,0120,01,04,0,
+ /* 640 */ 0241,0201,021,0301,01,0302,0120,01,05,0,
+ /* 650 */ 0241,0201,025,0301,01,0302,0120,01,05,0,
+ /* 660 */ 0241,0201,031,0301,01,0302,0120,01,05,0,
+ /* 670 */ 0241,0201,0,0301,01,0302,0120,01,05,0,
+ /* 680 */ 0241,0201,04,0301,01,0302,0120,01,05,0,
+ /* 690 */ 0241,0201,010,0301,01,0302,0120,01,05,0,
+ /* 700 */ 0241,0201,023,0306,01,0302,0120,01,05,0,
+ /* 710 */ 0241,0201,02,0306,01,0302,0120,01,05,0,
+ /* 720 */ 0241,0201,021,0301,01,0302,0120,01,06,0,
+ /* 730 */ 0241,0201,025,0301,01,0302,0120,01,06,0,
+ /* 740 */ 0241,0201,031,0301,01,0302,0120,01,06,0,
+ /* 750 */ 0241,0201,0,0301,01,0302,0120,01,06,0,
+ /* 760 */ 0241,0201,04,0301,01,0302,0120,01,06,0,
+ /* 770 */ 0241,0201,010,0301,01,0302,0120,01,06,0,
+ /* 780 */ 0241,0201,023,0306,01,0302,0120,01,06,0,
+ /* 790 */ 0241,0201,02,0306,01,0302,0120,01,06,0,
+ /* 800 */ 0241,0201,021,0301,01,0302,0120,01,07,0,
+ /* 810 */ 0241,0201,025,0301,01,0302,0120,01,07,0,
+ /* 820 */ 0241,0201,031,0301,01,0302,0120,01,07,0,
+ /* 830 */ 0241,0201,0,0301,01,0302,0120,01,07,0,
+ /* 840 */ 0241,0201,04,0301,01,0302,0120,01,07,0,
+ /* 850 */ 0241,0201,010,0301,01,0302,0120,01,07,0,
+ /* 860 */ 0241,0201,023,0306,01,0302,0120,01,07,0,
+ /* 870 */ 0241,0201,02,0306,01,0302,0120,01,07,0,
+ /* 880 */ 0241,0201,021,0301,01,0302,0120,01,010,0,
+ /* 890 */ 0241,0201,025,0301,01,0302,0120,01,010,0,
+ /* 900 */ 0241,0201,031,0301,01,0302,0120,01,010,0,
+ /* 910 */ 0241,0201,0,0301,01,0302,0120,01,010,0,
+ /* 920 */ 0241,0201,04,0301,01,0302,0120,01,010,0,
+ /* 930 */ 0241,0201,010,0301,01,0302,0120,01,010,0,
+ /* 940 */ 0241,0201,023,0306,01,0302,0120,01,010,0,
+ /* 950 */ 0241,0201,02,0306,01,0302,0120,01,010,0,
+ /* 960 */ 0241,0201,021,0301,01,0302,0120,01,011,0,
+ /* 970 */ 0241,0201,025,0301,01,0302,0120,01,011,0,
+ /* 980 */ 0241,0201,031,0301,01,0302,0120,01,011,0,
+ /* 990 */ 0241,0201,0,0301,01,0302,0120,01,011,0,
+ /* 1000 */ 0241,0201,04,0301,01,0302,0120,01,011,0,
+ /* 1010 */ 0241,0201,010,0301,01,0302,0120,01,011,0,
+ /* 1020 */ 0241,0201,023,0306,01,0302,0120,01,011,0,
+ /* 1030 */ 0241,0201,02,0306,01,0302,0120,01,011,0,
+ /* 1040 */ 0241,0201,021,0301,01,0302,0120,01,012,0,
+ /* 1050 */ 0241,0201,025,0301,01,0302,0120,01,012,0,
+ /* 1060 */ 0241,0201,031,0301,01,0302,0120,01,012,0,
+ /* 1070 */ 0241,0201,0,0301,01,0302,0120,01,012,0,
+ /* 1080 */ 0241,0201,04,0301,01,0302,0120,01,012,0,
+ /* 1090 */ 0241,0201,010,0301,01,0302,0120,01,012,0,
+ /* 1100 */ 0241,0201,023,0306,01,0302,0120,01,012,0,
+ /* 1110 */ 0241,0201,02,0306,01,0302,0120,01,012,0,
+ /* 1120 */ 0241,0201,021,0301,01,0302,0120,01,013,0,
+ /* 1130 */ 0241,0201,025,0301,01,0302,0120,01,013,0,
+ /* 1140 */ 0241,0201,031,0301,01,0302,0120,01,013,0,
+ /* 1150 */ 0241,0201,0,0301,01,0302,0120,01,013,0,
+ /* 1160 */ 0241,0201,04,0301,01,0302,0120,01,013,0,
+ /* 1170 */ 0241,0201,010,0301,01,0302,0120,01,013,0,
+ /* 1180 */ 0241,0201,023,0306,01,0302,0120,01,013,0,
+ /* 1190 */ 0241,0201,02,0306,01,0302,0120,01,013,0,
+ /* 1200 */ 0241,0201,021,0301,01,0302,0120,01,014,0,
+ /* 1210 */ 0241,0201,025,0301,01,0302,0120,01,014,0,
+ /* 1220 */ 0241,0201,031,0301,01,0302,0120,01,014,0,
+ /* 1230 */ 0241,0201,0,0301,01,0302,0120,01,014,0,
+ /* 1240 */ 0241,0201,04,0301,01,0302,0120,01,014,0,
+ /* 1250 */ 0241,0201,010,0301,01,0302,0120,01,014,0,
+ /* 1260 */ 0241,0201,023,0306,01,0302,0120,01,014,0,
+ /* 1270 */ 0241,0201,02,0306,01,0302,0120,01,014,0,
+ /* 1280 */ 0241,0201,021,0301,01,0302,0120,01,015,0,
+ /* 1290 */ 0241,0201,025,0301,01,0302,0120,01,015,0,
+ /* 1300 */ 0241,0201,031,0301,01,0302,0120,01,015,0,
+ /* 1310 */ 0241,0201,0,0301,01,0302,0120,01,015,0,
+ /* 1320 */ 0241,0201,04,0301,01,0302,0120,01,015,0,
+ /* 1330 */ 0241,0201,010,0301,01,0302,0120,01,015,0,
+ /* 1340 */ 0241,0201,023,0306,01,0302,0120,01,015,0,
+ /* 1350 */ 0241,0201,02,0306,01,0302,0120,01,015,0,
+ /* 1360 */ 0241,0201,021,0301,01,0302,0120,01,016,0,
+ /* 1370 */ 0241,0201,025,0301,01,0302,0120,01,016,0,
+ /* 1380 */ 0241,0201,031,0301,01,0302,0120,01,016,0,
+ /* 1390 */ 0241,0201,0,0301,01,0302,0120,01,016,0,
+ /* 1400 */ 0241,0201,04,0301,01,0302,0120,01,016,0,
+ /* 1410 */ 0241,0201,010,0301,01,0302,0120,01,016,0,
+ /* 1420 */ 0241,0201,023,0306,01,0302,0120,01,016,0,
+ /* 1430 */ 0241,0201,02,0306,01,0302,0120,01,016,0,
+ /* 1440 */ 0241,0201,021,0301,01,0302,0120,01,017,0,
+ /* 1450 */ 0241,0201,025,0301,01,0302,0120,01,017,0,
+ /* 1460 */ 0241,0201,031,0301,01,0302,0120,01,017,0,
+ /* 1470 */ 0241,0201,0,0301,01,0302,0120,01,017,0,
+ /* 1480 */ 0241,0201,04,0301,01,0302,0120,01,017,0,
+ /* 1490 */ 0241,0201,010,0301,01,0302,0120,01,017,0,
+ /* 1500 */ 0241,0201,023,0306,01,0302,0120,01,017,0,
+ /* 1510 */ 0241,0201,02,0306,01,0302,0120,01,017,0,
+ /* 1520 */ 0241,0201,021,0301,01,0302,0120,01,020,0,
+ /* 1530 */ 0241,0201,025,0301,01,0302,0120,01,020,0,
+ /* 1540 */ 0241,0201,031,0301,01,0302,0120,01,020,0,
+ /* 1550 */ 0241,0201,0,0301,01,0302,0120,01,020,0,
+ /* 1560 */ 0241,0201,04,0301,01,0302,0120,01,020,0,
+ /* 1570 */ 0241,0201,010,0301,01,0302,0120,01,020,0,
+ /* 1580 */ 0241,0201,023,0306,01,0302,0120,01,020,0,
+ /* 1590 */ 0241,0201,02,0306,01,0302,0120,01,020,0,
+ /* 1600 */ 0241,0201,021,0301,01,0302,0120,01,021,0,
+ /* 1610 */ 0241,0201,025,0301,01,0302,0120,01,021,0,
+ /* 1620 */ 0241,0201,031,0301,01,0302,0120,01,021,0,
+ /* 1630 */ 0241,0201,0,0301,01,0302,0120,01,021,0,
+ /* 1640 */ 0241,0201,04,0301,01,0302,0120,01,021,0,
+ /* 1650 */ 0241,0201,010,0301,01,0302,0120,01,021,0,
+ /* 1660 */ 0241,0201,023,0306,01,0302,0120,01,021,0,
+ /* 1670 */ 0241,0201,02,0306,01,0302,0120,01,021,0,
+ /* 1680 */ 0241,0201,021,0301,01,0302,0120,01,022,0,
+ /* 1690 */ 0241,0201,025,0301,01,0302,0120,01,022,0,
+ /* 1700 */ 0241,0201,031,0301,01,0302,0120,01,022,0,
+ /* 1710 */ 0241,0201,0,0301,01,0302,0120,01,022,0,
+ /* 1720 */ 0241,0201,04,0301,01,0302,0120,01,022,0,
+ /* 1730 */ 0241,0201,010,0301,01,0302,0120,01,022,0,
+ /* 1740 */ 0241,0201,023,0306,01,0302,0120,01,022,0,
+ /* 1750 */ 0241,0201,02,0306,01,0302,0120,01,022,0,
+ /* 1760 */ 0241,0201,021,0301,01,0302,0120,01,023,0,
+ /* 1770 */ 0241,0201,025,0301,01,0302,0120,01,023,0,
+ /* 1780 */ 0241,0201,031,0301,01,0302,0120,01,023,0,
+ /* 1790 */ 0241,0201,0,0301,01,0302,0120,01,023,0,
+ /* 1800 */ 0241,0201,04,0301,01,0302,0120,01,023,0,
+ /* 1810 */ 0241,0201,010,0301,01,0302,0120,01,023,0,
+ /* 1820 */ 0241,0201,023,0306,01,0302,0120,01,023,0,
+ /* 1830 */ 0241,0201,02,0306,01,0302,0120,01,023,0,
+ /* 1840 */ 0241,0201,021,0301,01,0302,0120,01,024,0,
+ /* 1850 */ 0241,0201,025,0301,01,0302,0120,01,024,0,
+ /* 1860 */ 0241,0201,031,0301,01,0302,0120,01,024,0,
+ /* 1870 */ 0241,0201,0,0301,01,0302,0120,01,024,0,
+ /* 1880 */ 0241,0201,04,0301,01,0302,0120,01,024,0,
+ /* 1890 */ 0241,0201,010,0301,01,0302,0120,01,024,0,
+ /* 1900 */ 0241,0201,023,0306,01,0302,0120,01,024,0,
+ /* 1910 */ 0241,0201,02,0306,01,0302,0120,01,024,0,
+ /* 1920 */ 0241,0201,021,0301,01,0302,0120,01,025,0,
+ /* 1930 */ 0241,0201,025,0301,01,0302,0120,01,025,0,
+ /* 1940 */ 0241,0201,031,0301,01,0302,0120,01,025,0,
+ /* 1950 */ 0241,0201,0,0301,01,0302,0120,01,025,0,
+ /* 1960 */ 0241,0201,04,0301,01,0302,0120,01,025,0,
+ /* 1970 */ 0241,0201,010,0301,01,0302,0120,01,025,0,
+ /* 1980 */ 0241,0201,023,0306,01,0302,0120,01,025,0,
+ /* 1990 */ 0241,0201,02,0306,01,0302,0120,01,025,0,
+ /* 2000 */ 0241,0201,021,0301,01,0302,0120,01,026,0,
+ /* 2010 */ 0241,0201,025,0301,01,0302,0120,01,026,0,
+ /* 2020 */ 0241,0201,031,0301,01,0302,0120,01,026,0,
+ /* 2030 */ 0241,0201,0,0301,01,0302,0120,01,026,0,
+ /* 2040 */ 0241,0201,04,0301,01,0302,0120,01,026,0,
+ /* 2050 */ 0241,0201,010,0301,01,0302,0120,01,026,0,
+ /* 2060 */ 0241,0201,023,0306,01,0302,0120,01,026,0,
+ /* 2070 */ 0241,0201,02,0306,01,0302,0120,01,026,0,
+ /* 2080 */ 0241,0201,021,0301,01,0302,0120,01,027,0,
+ /* 2090 */ 0241,0201,025,0301,01,0302,0120,01,027,0,
+ /* 2100 */ 0241,0201,031,0301,01,0302,0120,01,027,0,
+ /* 2110 */ 0241,0201,0,0301,01,0302,0120,01,027,0,
+ /* 2120 */ 0241,0201,04,0301,01,0302,0120,01,027,0,
+ /* 2130 */ 0241,0201,010,0301,01,0302,0120,01,027,0,
+ /* 2140 */ 0241,0201,023,0306,01,0302,0120,01,027,0,
+ /* 2150 */ 0241,0201,02,0306,01,0302,0120,01,027,0,
+ /* 2160 */ 0241,0201,021,0301,01,0302,0120,01,030,0,
+ /* 2170 */ 0241,0201,025,0301,01,0302,0120,01,030,0,
+ /* 2180 */ 0241,0201,031,0301,01,0302,0120,01,030,0,
+ /* 2190 */ 0241,0201,0,0301,01,0302,0120,01,030,0,
+ /* 2200 */ 0241,0201,04,0301,01,0302,0120,01,030,0,
+ /* 2210 */ 0241,0201,010,0301,01,0302,0120,01,030,0,
+ /* 2220 */ 0241,0201,023,0306,01,0302,0120,01,030,0,
+ /* 2230 */ 0241,0201,02,0306,01,0302,0120,01,030,0,
+ /* 2240 */ 0241,0201,021,0301,01,0302,0120,01,031,0,
+ /* 2250 */ 0241,0201,025,0301,01,0302,0120,01,031,0,
+ /* 2260 */ 0241,0201,031,0301,01,0302,0120,01,031,0,
+ /* 2270 */ 0241,0201,0,0301,01,0302,0120,01,031,0,
+ /* 2280 */ 0241,0201,04,0301,01,0302,0120,01,031,0,
+ /* 2290 */ 0241,0201,010,0301,01,0302,0120,01,031,0,
+ /* 2300 */ 0241,0201,023,0306,01,0302,0120,01,031,0,
+ /* 2310 */ 0241,0201,02,0306,01,0302,0120,01,031,0,
+ /* 2320 */ 0241,0201,021,0301,01,0302,0120,01,032,0,
+ /* 2330 */ 0241,0201,025,0301,01,0302,0120,01,032,0,
+ /* 2340 */ 0241,0201,031,0301,01,0302,0120,01,032,0,
+ /* 2350 */ 0241,0201,0,0301,01,0302,0120,01,032,0,
+ /* 2360 */ 0241,0201,04,0301,01,0302,0120,01,032,0,
+ /* 2370 */ 0241,0201,010,0301,01,0302,0120,01,032,0,
+ /* 2380 */ 0241,0201,023,0306,01,0302,0120,01,032,0,
+ /* 2390 */ 0241,0201,02,0306,01,0302,0120,01,032,0,
+ /* 2400 */ 0241,0201,021,0301,01,0302,0120,01,033,0,
+ /* 2410 */ 0241,0201,025,0301,01,0302,0120,01,033,0,
+ /* 2420 */ 0241,0201,031,0301,01,0302,0120,01,033,0,
+ /* 2430 */ 0241,0201,0,0301,01,0302,0120,01,033,0,
+ /* 2440 */ 0241,0201,04,0301,01,0302,0120,01,033,0,
+ /* 2450 */ 0241,0201,010,0301,01,0302,0120,01,033,0,
+ /* 2460 */ 0241,0201,023,0306,01,0302,0120,01,033,0,
+ /* 2470 */ 0241,0201,02,0306,01,0302,0120,01,033,0,
+ /* 2480 */ 0241,0201,021,0301,01,0302,0120,01,034,0,
+ /* 2490 */ 0241,0201,025,0301,01,0302,0120,01,034,0,
+ /* 2500 */ 0241,0201,031,0301,01,0302,0120,01,034,0,
+ /* 2510 */ 0241,0201,0,0301,01,0302,0120,01,034,0,
+ /* 2520 */ 0241,0201,04,0301,01,0302,0120,01,034,0,
+ /* 2530 */ 0241,0201,010,0301,01,0302,0120,01,034,0,
+ /* 2540 */ 0241,0201,023,0306,01,0302,0120,01,034,0,
+ /* 2550 */ 0241,0201,02,0306,01,0302,0120,01,034,0,
+ /* 2560 */ 0241,0201,021,0301,01,0302,0120,01,035,0,
+ /* 2570 */ 0241,0201,025,0301,01,0302,0120,01,035,0,
+ /* 2580 */ 0241,0201,031,0301,01,0302,0120,01,035,0,
+ /* 2590 */ 0241,0201,0,0301,01,0302,0120,01,035,0,
+ /* 2600 */ 0241,0201,04,0301,01,0302,0120,01,035,0,
+ /* 2610 */ 0241,0201,010,0301,01,0302,0120,01,035,0,
+ /* 2620 */ 0241,0201,023,0306,01,0302,0120,01,035,0,
+ /* 2630 */ 0241,0201,02,0306,01,0302,0120,01,035,0,
+ /* 2640 */ 0241,0201,021,0301,01,0302,0120,01,036,0,
+ /* 2650 */ 0241,0201,025,0301,01,0302,0120,01,036,0,
+ /* 2660 */ 0241,0201,031,0301,01,0302,0120,01,036,0,
+ /* 2670 */ 0241,0201,0,0301,01,0302,0120,01,036,0,
+ /* 2680 */ 0241,0201,04,0301,01,0302,0120,01,036,0,
+ /* 2690 */ 0241,0201,010,0301,01,0302,0120,01,036,0,
+ /* 2700 */ 0241,0201,023,0306,01,0302,0120,01,036,0,
+ /* 2710 */ 0241,0201,02,0306,01,0302,0120,01,036,0,
+ /* 2720 */ 0241,0201,021,0301,01,0302,0120,01,037,0,
+ /* 2730 */ 0241,0201,025,0301,01,0302,0120,01,037,0,
+ /* 2740 */ 0241,0201,031,0301,01,0302,0120,01,037,0,
+ /* 2750 */ 0241,0201,0,0301,01,0302,0120,01,037,0,
+ /* 2760 */ 0241,0201,04,0301,01,0302,0120,01,037,0,
+ /* 2770 */ 0241,0201,010,0301,01,0302,0120,01,037,0,
+ /* 2780 */ 0241,0201,023,0306,01,0302,0120,01,037,0,
+ /* 2790 */ 0241,0201,02,0306,01,0302,0120,01,037,0,
+ /* 2800 */ 0241,0203,01,0303,01,077,0120,01,0,0,
+ /* 2810 */ 0241,0203,05,0303,01,077,0120,01,0,0,
+ /* 2820 */ 0241,0203,011,0303,01,077,0120,01,0,0,
+ /* 2830 */ 0241,0203,01,0301,01,037,0120,01,0,0,
+ /* 2840 */ 0241,0203,05,0301,01,037,0120,01,0,0,
+ /* 2850 */ 0241,0203,011,0301,01,037,0120,01,0,0,
+ /* 2860 */ 0241,0203,021,0301,01,037,0120,01,0,0,
+ /* 2870 */ 0241,0203,025,0301,01,037,0120,01,0,0,
+ /* 2880 */ 0241,0203,031,0301,01,037,0120,01,0,0,
+ /* 2890 */ 0241,0203,01,0303,01,076,0120,01,0,0,
+ /* 2900 */ 0241,0203,05,0303,01,076,0120,01,0,0,
+ /* 2910 */ 0241,0203,011,0303,01,076,0120,01,0,0,
+ /* 2920 */ 0241,0203,01,0301,01,036,0120,01,0,0,
+ /* 2930 */ 0241,0203,05,0301,01,036,0120,01,0,0,
+ /* 2940 */ 0241,0203,011,0301,01,036,0120,01,0,0,
+ /* 2950 */ 0241,0203,021,0301,01,036,0120,01,0,0,
+ /* 2960 */ 0241,0203,025,0301,01,036,0120,01,0,0,
+ /* 2970 */ 0241,0203,031,0301,01,036,0120,01,0,0,
+ /* 2980 */ 0241,0203,021,0303,01,076,0120,01,0,0,
+ /* 2990 */ 0241,0203,025,0303,01,076,0120,01,0,0,
+ /* 3000 */ 0241,0203,031,0303,01,076,0120,01,0,0,
+ /* 3010 */ 0241,0203,021,0303,01,077,0120,01,0,0,
+ /* 3020 */ 0241,0203,025,0303,01,077,0120,01,0,0,
+ /* 3030 */ 0241,0203,031,0303,01,077,0120,01,0,0,
+ /* 3040 */ 0241,0203,01,0303,01,077,0120,01,05,0,
+ /* 3050 */ 0241,0203,05,0303,01,077,0120,01,05,0,
+ /* 3060 */ 0241,0203,011,0303,01,077,0120,01,05,0,
+ /* 3070 */ 0241,0203,01,0301,01,037,0120,01,05,0,
+ /* 3080 */ 0241,0203,05,0301,01,037,0120,01,05,0,
+ /* 3090 */ 0241,0203,011,0301,01,037,0120,01,05,0,
+ /* 3100 */ 0241,0203,021,0301,01,037,0120,01,05,0,
+ /* 3110 */ 0241,0203,025,0301,01,037,0120,01,05,0,
+ /* 3120 */ 0241,0203,031,0301,01,037,0120,01,05,0,
+ /* 3130 */ 0241,0203,01,0303,01,076,0120,01,05,0,
+ /* 3140 */ 0241,0203,05,0303,01,076,0120,01,05,0,
+ /* 3150 */ 0241,0203,011,0303,01,076,0120,01,05,0,
+ /* 3160 */ 0241,0203,01,0301,01,036,0120,01,05,0,
+ /* 3170 */ 0241,0203,05,0301,01,036,0120,01,05,0,
+ /* 3180 */ 0241,0203,011,0301,01,036,0120,01,05,0,
+ /* 3190 */ 0241,0203,021,0301,01,036,0120,01,05,0,
+ /* 3200 */ 0241,0203,025,0301,01,036,0120,01,05,0,
+ /* 3210 */ 0241,0203,031,0301,01,036,0120,01,05,0,
+ /* 3220 */ 0241,0203,021,0303,01,076,0120,01,05,0,
+ /* 3230 */ 0241,0203,025,0303,01,076,0120,01,05,0,
+ /* 3240 */ 0241,0203,031,0303,01,076,0120,01,05,0,
+ /* 3250 */ 0241,0203,021,0303,01,077,0120,01,05,0,
+ /* 3260 */ 0241,0203,025,0303,01,077,0120,01,05,0,
+ /* 3270 */ 0241,0203,031,0303,01,077,0120,01,05,0,
+ /* 3280 */ 0241,0203,01,0303,01,077,0120,01,06,0,
+ /* 3290 */ 0241,0203,05,0303,01,077,0120,01,06,0,
+ /* 3300 */ 0241,0203,011,0303,01,077,0120,01,06,0,
+ /* 3310 */ 0241,0203,01,0301,01,037,0120,01,06,0,
+ /* 3320 */ 0241,0203,05,0301,01,037,0120,01,06,0,
+ /* 3330 */ 0241,0203,011,0301,01,037,0120,01,06,0,
+ /* 3340 */ 0241,0203,021,0301,01,037,0120,01,06,0,
+ /* 3350 */ 0241,0203,025,0301,01,037,0120,01,06,0,
+ /* 3360 */ 0241,0203,031,0301,01,037,0120,01,06,0,
+ /* 3370 */ 0241,0203,01,0303,01,076,0120,01,06,0,
+ /* 3380 */ 0241,0203,05,0303,01,076,0120,01,06,0,
+ /* 3390 */ 0241,0203,011,0303,01,076,0120,01,06,0,
+ /* 3400 */ 0241,0203,01,0301,01,036,0120,01,06,0,
+ /* 3410 */ 0241,0203,05,0301,01,036,0120,01,06,0,
+ /* 3420 */ 0241,0203,011,0301,01,036,0120,01,06,0,
+ /* 3430 */ 0241,0203,021,0301,01,036,0120,01,06,0,
+ /* 3440 */ 0241,0203,025,0301,01,036,0120,01,06,0,
+ /* 3450 */ 0241,0203,031,0301,01,036,0120,01,06,0,
+ /* 3460 */ 0241,0203,021,0303,01,076,0120,01,06,0,
+ /* 3470 */ 0241,0203,025,0303,01,076,0120,01,06,0,
+ /* 3480 */ 0241,0203,031,0303,01,076,0120,01,06,0,
+ /* 3490 */ 0241,0203,021,0303,01,077,0120,01,06,0,
+ /* 3500 */ 0241,0203,025,0303,01,077,0120,01,06,0,
+ /* 3510 */ 0241,0203,031,0303,01,077,0120,01,06,0,
+ /* 3520 */ 0241,0203,01,0303,01,077,0120,01,02,0,
+ /* 3530 */ 0241,0203,05,0303,01,077,0120,01,02,0,
+ /* 3540 */ 0241,0203,011,0303,01,077,0120,01,02,0,
+ /* 3550 */ 0241,0203,01,0301,01,037,0120,01,02,0,
+ /* 3560 */ 0241,0203,05,0301,01,037,0120,01,02,0,
+ /* 3570 */ 0241,0203,011,0301,01,037,0120,01,02,0,
+ /* 3580 */ 0241,0203,021,0301,01,037,0120,01,02,0,
+ /* 3590 */ 0241,0203,025,0301,01,037,0120,01,02,0,
+ /* 3600 */ 0241,0203,031,0301,01,037,0120,01,02,0,
+ /* 3610 */ 0241,0203,01,0303,01,076,0120,01,02,0,
+ /* 3620 */ 0241,0203,05,0303,01,076,0120,01,02,0,
+ /* 3630 */ 0241,0203,011,0303,01,076,0120,01,02,0,
+ /* 3640 */ 0241,0203,01,0301,01,036,0120,01,02,0,
+ /* 3650 */ 0241,0203,05,0301,01,036,0120,01,02,0,
+ /* 3660 */ 0241,0203,011,0301,01,036,0120,01,02,0,
+ /* 3670 */ 0241,0203,021,0301,01,036,0120,01,02,0,
+ /* 3680 */ 0241,0203,025,0301,01,036,0120,01,02,0,
+ /* 3690 */ 0241,0203,031,0301,01,036,0120,01,02,0,
+ /* 3700 */ 0241,0203,021,0303,01,076,0120,01,02,0,
+ /* 3710 */ 0241,0203,025,0303,01,076,0120,01,02,0,
+ /* 3720 */ 0241,0203,031,0303,01,076,0120,01,02,0,
+ /* 3730 */ 0241,0203,021,0303,01,077,0120,01,02,0,
+ /* 3740 */ 0241,0203,025,0303,01,077,0120,01,02,0,
+ /* 3750 */ 0241,0203,031,0303,01,077,0120,01,02,0,
+ /* 3760 */ 0241,0203,01,0303,01,077,0120,01,01,0,
+ /* 3770 */ 0241,0203,05,0303,01,077,0120,01,01,0,
+ /* 3780 */ 0241,0203,011,0303,01,077,0120,01,01,0,
+ /* 3790 */ 0241,0203,01,0301,01,037,0120,01,01,0,
+ /* 3800 */ 0241,0203,05,0301,01,037,0120,01,01,0,
+ /* 3810 */ 0241,0203,011,0301,01,037,0120,01,01,0,
+ /* 3820 */ 0241,0203,021,0301,01,037,0120,01,01,0,
+ /* 3830 */ 0241,0203,025,0301,01,037,0120,01,01,0,
+ /* 3840 */ 0241,0203,031,0301,01,037,0120,01,01,0,
+ /* 3850 */ 0241,0203,01,0303,01,076,0120,01,01,0,
+ /* 3860 */ 0241,0203,05,0303,01,076,0120,01,01,0,
+ /* 3870 */ 0241,0203,011,0303,01,076,0120,01,01,0,
+ /* 3880 */ 0241,0203,01,0301,01,036,0120,01,01,0,
+ /* 3890 */ 0241,0203,05,0301,01,036,0120,01,01,0,
+ /* 3900 */ 0241,0203,011,0301,01,036,0120,01,01,0,
+ /* 3910 */ 0241,0203,021,0301,01,036,0120,01,01,0,
+ /* 3920 */ 0241,0203,025,0301,01,036,0120,01,01,0,
+ /* 3930 */ 0241,0203,031,0301,01,036,0120,01,01,0,
+ /* 3940 */ 0241,0203,021,0303,01,076,0120,01,01,0,
+ /* 3950 */ 0241,0203,025,0303,01,076,0120,01,01,0,
+ /* 3960 */ 0241,0203,031,0303,01,076,0120,01,01,0,
+ /* 3970 */ 0241,0203,021,0303,01,077,0120,01,01,0,
+ /* 3980 */ 0241,0203,025,0303,01,077,0120,01,01,0,
+ /* 3990 */ 0241,0203,031,0303,01,077,0120,01,01,0,
+ /* 4000 */ 0241,0203,01,0303,01,077,0120,01,04,0,
+ /* 4010 */ 0241,0203,05,0303,01,077,0120,01,04,0,
+ /* 4020 */ 0241,0203,011,0303,01,077,0120,01,04,0,
+ /* 4030 */ 0241,0203,01,0301,01,037,0120,01,04,0,
+ /* 4040 */ 0241,0203,05,0301,01,037,0120,01,04,0,
+ /* 4050 */ 0241,0203,011,0301,01,037,0120,01,04,0,
+ /* 4060 */ 0241,0203,021,0301,01,037,0120,01,04,0,
+ /* 4070 */ 0241,0203,025,0301,01,037,0120,01,04,0,
+ /* 4080 */ 0241,0203,031,0301,01,037,0120,01,04,0,
+ /* 4090 */ 0241,0203,01,0303,01,076,0120,01,04,0,
+ /* 4100 */ 0241,0203,05,0303,01,076,0120,01,04,0,
+ /* 4110 */ 0241,0203,011,0303,01,076,0120,01,04,0,
+ /* 4120 */ 0241,0203,01,0301,01,036,0120,01,04,0,
+ /* 4130 */ 0241,0203,05,0301,01,036,0120,01,04,0,
+ /* 4140 */ 0241,0203,011,0301,01,036,0120,01,04,0,
+ /* 4150 */ 0241,0203,021,0301,01,036,0120,01,04,0,
+ /* 4160 */ 0241,0203,025,0301,01,036,0120,01,04,0,
+ /* 4170 */ 0241,0203,031,0301,01,036,0120,01,04,0,
+ /* 4180 */ 0241,0203,021,0303,01,076,0120,01,04,0,
+ /* 4190 */ 0241,0203,025,0303,01,076,0120,01,04,0,
+ /* 4200 */ 0241,0203,031,0303,01,076,0120,01,04,0,
+ /* 4210 */ 0241,0203,021,0303,01,077,0120,01,04,0,
+ /* 4220 */ 0241,0203,025,0303,01,077,0120,01,04,0,
+ /* 4230 */ 0241,0203,031,0303,01,077,0120,01,04,0,
+ /* 4240 */ 0324,0361,03,017,072,027,0101,026,0,
+ /* 4249 */ 0323,0361,03,017,072,024,0101,026,0,
+ /* 4258 */ 0317,0361,03,017,072,026,0101,026,0,
+ /* 4267 */ 0324,0361,03,017,072,026,0101,026,0,
+ /* 4276 */ 0324,0361,03,017,072,025,0101,026,0,
+ /* 4285 */ 0325,0361,03,017,072,040,0110,026,0,
+ /* 4294 */ 0317,0361,03,017,072,042,0110,026,0,
+ /* 4303 */ 0324,0361,03,017,072,042,0110,026,0,
+ /* 4312 */ 0261,01,041,01,0302,0120,01,020,0,
+ /* 4321 */ 0260,01,041,01,0302,0110,01,020,0,
+ /* 4330 */ 0261,01,045,01,0302,0120,01,020,0,
+ /* 4339 */ 0260,01,045,01,0302,0110,01,020,0,
+ /* 4348 */ 0261,01,041,01,0302,0120,01,0,0,
+ /* 4357 */ 0260,01,041,01,0302,0110,01,0,0,
+ /* 4366 */ 0261,01,045,01,0302,0120,01,0,0,
+ /* 4375 */ 0260,01,045,01,0302,0110,01,0,0,
+ /* 4384 */ 0261,01,041,01,0302,0120,01,01,0,
+ /* 4393 */ 0260,01,041,01,0302,0110,01,01,0,
+ /* 4402 */ 0261,01,045,01,0302,0120,01,01,0,
+ /* 4411 */ 0260,01,045,01,0302,0110,01,01,0,
+ /* 4420 */ 0261,01,041,01,0302,0120,01,02,0,
+ /* 4429 */ 0260,01,041,01,0302,0110,01,02,0,
+ /* 4438 */ 0261,01,045,01,0302,0120,01,02,0,
+ /* 4447 */ 0260,01,045,01,0302,0110,01,02,0,
+ /* 4456 */ 0261,01,041,01,0302,0120,01,03,0,
+ /* 4465 */ 0260,01,041,01,0302,0110,01,03,0,
+ /* 4474 */ 0261,01,045,01,0302,0120,01,03,0,
+ /* 4483 */ 0260,01,045,01,0302,0110,01,03,0,
+ /* 4492 */ 0261,01,041,01,0302,0120,01,04,0,
+ /* 4501 */ 0260,01,041,01,0302,0110,01,04,0,
+ /* 4510 */ 0261,01,045,01,0302,0120,01,04,0,
+ /* 4519 */ 0260,01,045,01,0302,0110,01,04,0,
+ /* 4528 */ 0261,01,041,01,0302,0120,01,05,0,
+ /* 4537 */ 0260,01,041,01,0302,0110,01,05,0,
+ /* 4546 */ 0261,01,045,01,0302,0120,01,05,0,
+ /* 4555 */ 0260,01,045,01,0302,0110,01,05,0,
+ /* 4564 */ 0261,01,041,01,0302,0120,01,06,0,
+ /* 4573 */ 0260,01,041,01,0302,0110,01,06,0,
+ /* 4582 */ 0261,01,045,01,0302,0120,01,06,0,
+ /* 4591 */ 0260,01,045,01,0302,0110,01,06,0,
+ /* 4600 */ 0261,01,041,01,0302,0120,01,07,0,
+ /* 4609 */ 0260,01,041,01,0302,0110,01,07,0,
+ /* 4618 */ 0261,01,045,01,0302,0120,01,07,0,
+ /* 4627 */ 0260,01,045,01,0302,0110,01,07,0,
+ /* 4636 */ 0261,01,041,01,0302,0120,01,010,0,
+ /* 4645 */ 0260,01,041,01,0302,0110,01,010,0,
+ /* 4654 */ 0261,01,045,01,0302,0120,01,010,0,
+ /* 4663 */ 0260,01,045,01,0302,0110,01,010,0,
+ /* 4672 */ 0261,01,041,01,0302,0120,01,011,0,
+ /* 4681 */ 0260,01,041,01,0302,0110,01,011,0,
+ /* 4690 */ 0261,01,045,01,0302,0120,01,011,0,
+ /* 4699 */ 0260,01,045,01,0302,0110,01,011,0,
+ /* 4708 */ 0261,01,041,01,0302,0120,01,012,0,
+ /* 4717 */ 0260,01,041,01,0302,0110,01,012,0,
+ /* 4726 */ 0261,01,045,01,0302,0120,01,012,0,
+ /* 4735 */ 0260,01,045,01,0302,0110,01,012,0,
+ /* 4744 */ 0261,01,041,01,0302,0120,01,013,0,
+ /* 4753 */ 0260,01,041,01,0302,0110,01,013,0,
+ /* 4762 */ 0261,01,045,01,0302,0120,01,013,0,
+ /* 4771 */ 0260,01,045,01,0302,0110,01,013,0,
+ /* 4780 */ 0261,01,041,01,0302,0120,01,014,0,
+ /* 4789 */ 0260,01,041,01,0302,0110,01,014,0,
+ /* 4798 */ 0261,01,045,01,0302,0120,01,014,0,
+ /* 4807 */ 0260,01,045,01,0302,0110,01,014,0,
+ /* 4816 */ 0261,01,041,01,0302,0120,01,015,0,
+ /* 4825 */ 0260,01,041,01,0302,0110,01,015,0,
+ /* 4834 */ 0261,01,045,01,0302,0120,01,015,0,
+ /* 4843 */ 0260,01,045,01,0302,0110,01,015,0,
+ /* 4852 */ 0261,01,041,01,0302,0120,01,016,0,
+ /* 4861 */ 0260,01,041,01,0302,0110,01,016,0,
+ /* 4870 */ 0261,01,045,01,0302,0120,01,016,0,
+ /* 4879 */ 0260,01,045,01,0302,0110,01,016,0,
+ /* 4888 */ 0261,01,041,01,0302,0120,01,017,0,
+ /* 4897 */ 0260,01,041,01,0302,0110,01,017,0,
+ /* 4906 */ 0261,01,045,01,0302,0120,01,017,0,
+ /* 4915 */ 0260,01,045,01,0302,0110,01,017,0,
+ /* 4924 */ 0261,01,041,01,0302,0120,01,021,0,
+ /* 4933 */ 0260,01,041,01,0302,0110,01,021,0,
+ /* 4942 */ 0261,01,045,01,0302,0120,01,021,0,
+ /* 4951 */ 0260,01,045,01,0302,0110,01,021,0,
+ /* 4960 */ 0261,01,041,01,0302,0120,01,022,0,
+ /* 4969 */ 0260,01,041,01,0302,0110,01,022,0,
+ /* 4978 */ 0261,01,045,01,0302,0120,01,022,0,
+ /* 4987 */ 0260,01,045,01,0302,0110,01,022,0,
+ /* 4996 */ 0261,01,041,01,0302,0120,01,023,0,
+ /* 5005 */ 0260,01,041,01,0302,0110,01,023,0,
+ /* 5014 */ 0261,01,045,01,0302,0120,01,023,0,
+ /* 5023 */ 0260,01,045,01,0302,0110,01,023,0,
+ /* 5032 */ 0261,01,041,01,0302,0120,01,024,0,
+ /* 5041 */ 0260,01,041,01,0302,0110,01,024,0,
+ /* 5050 */ 0261,01,045,01,0302,0120,01,024,0,
+ /* 5059 */ 0260,01,045,01,0302,0110,01,024,0,
+ /* 5068 */ 0261,01,041,01,0302,0120,01,025,0,
+ /* 5077 */ 0260,01,041,01,0302,0110,01,025,0,
+ /* 5086 */ 0261,01,045,01,0302,0120,01,025,0,
+ /* 5095 */ 0260,01,045,01,0302,0110,01,025,0,
+ /* 5104 */ 0261,01,041,01,0302,0120,01,026,0,
+ /* 5113 */ 0260,01,041,01,0302,0110,01,026,0,
+ /* 5122 */ 0261,01,045,01,0302,0120,01,026,0,
+ /* 5131 */ 0260,01,045,01,0302,0110,01,026,0,
+ /* 5140 */ 0261,01,041,01,0302,0120,01,027,0,
+ /* 5149 */ 0260,01,041,01,0302,0110,01,027,0,
+ /* 5158 */ 0261,01,045,01,0302,0120,01,027,0,
+ /* 5167 */ 0260,01,045,01,0302,0110,01,027,0,
+ /* 5176 */ 0261,01,041,01,0302,0120,01,030,0,
+ /* 5185 */ 0260,01,041,01,0302,0110,01,030,0,
+ /* 5194 */ 0261,01,045,01,0302,0120,01,030,0,
+ /* 5203 */ 0260,01,045,01,0302,0110,01,030,0,
+ /* 5212 */ 0261,01,041,01,0302,0120,01,031,0,
+ /* 5221 */ 0260,01,041,01,0302,0110,01,031,0,
+ /* 5230 */ 0261,01,045,01,0302,0120,01,031,0,
+ /* 5239 */ 0260,01,045,01,0302,0110,01,031,0,
+ /* 5248 */ 0261,01,041,01,0302,0120,01,032,0,
+ /* 5257 */ 0260,01,041,01,0302,0110,01,032,0,
+ /* 5266 */ 0261,01,045,01,0302,0120,01,032,0,
+ /* 5275 */ 0260,01,045,01,0302,0110,01,032,0,
+ /* 5284 */ 0261,01,041,01,0302,0120,01,033,0,
+ /* 5293 */ 0260,01,041,01,0302,0110,01,033,0,
+ /* 5302 */ 0261,01,045,01,0302,0120,01,033,0,
+ /* 5311 */ 0260,01,045,01,0302,0110,01,033,0,
+ /* 5320 */ 0261,01,041,01,0302,0120,01,034,0,
+ /* 5329 */ 0260,01,041,01,0302,0110,01,034,0,
+ /* 5338 */ 0261,01,045,01,0302,0120,01,034,0,
+ /* 5347 */ 0260,01,045,01,0302,0110,01,034,0,
+ /* 5356 */ 0261,01,041,01,0302,0120,01,035,0,
+ /* 5365 */ 0260,01,041,01,0302,0110,01,035,0,
+ /* 5374 */ 0261,01,045,01,0302,0120,01,035,0,
+ /* 5383 */ 0260,01,045,01,0302,0110,01,035,0,
+ /* 5392 */ 0261,01,041,01,0302,0120,01,036,0,
+ /* 5401 */ 0260,01,041,01,0302,0110,01,036,0,
+ /* 5410 */ 0261,01,045,01,0302,0120,01,036,0,
+ /* 5419 */ 0260,01,045,01,0302,0110,01,036,0,
+ /* 5428 */ 0261,01,041,01,0302,0120,01,037,0,
+ /* 5437 */ 0260,01,041,01,0302,0110,01,037,0,
+ /* 5446 */ 0261,01,045,01,0302,0120,01,037,0,
+ /* 5455 */ 0260,01,045,01,0302,0110,01,037,0,
+ /* 5464 */ 0261,01,040,01,0302,0120,01,020,0,
+ /* 5473 */ 0260,01,040,01,0302,0110,01,020,0,
+ /* 5482 */ 0261,01,044,01,0302,0120,01,020,0,
+ /* 5491 */ 0260,01,044,01,0302,0110,01,020,0,
+ /* 5500 */ 0261,01,040,01,0302,0120,01,0,0,
+ /* 5509 */ 0260,01,040,01,0302,0110,01,0,0,
+ /* 5518 */ 0261,01,044,01,0302,0120,01,0,0,
+ /* 5527 */ 0260,01,044,01,0302,0110,01,0,0,
+ /* 5536 */ 0261,01,040,01,0302,0120,01,01,0,
+ /* 5545 */ 0260,01,040,01,0302,0110,01,01,0,
+ /* 5554 */ 0261,01,044,01,0302,0120,01,01,0,
+ /* 5563 */ 0260,01,044,01,0302,0110,01,01,0,
+ /* 5572 */ 0261,01,040,01,0302,0120,01,02,0,
+ /* 5581 */ 0260,01,040,01,0302,0110,01,02,0,
+ /* 5590 */ 0261,01,044,01,0302,0120,01,02,0,
+ /* 5599 */ 0260,01,044,01,0302,0110,01,02,0,
+ /* 5608 */ 0261,01,040,01,0302,0120,01,03,0,
+ /* 5617 */ 0260,01,040,01,0302,0110,01,03,0,
+ /* 5626 */ 0261,01,044,01,0302,0120,01,03,0,
+ /* 5635 */ 0260,01,044,01,0302,0110,01,03,0,
+ /* 5644 */ 0261,01,040,01,0302,0120,01,04,0,
+ /* 5653 */ 0260,01,040,01,0302,0110,01,04,0,
+ /* 5662 */ 0261,01,044,01,0302,0120,01,04,0,
+ /* 5671 */ 0260,01,044,01,0302,0110,01,04,0,
+ /* 5680 */ 0261,01,040,01,0302,0120,01,05,0,
+ /* 5689 */ 0260,01,040,01,0302,0110,01,05,0,
+ /* 5698 */ 0261,01,044,01,0302,0120,01,05,0,
+ /* 5707 */ 0260,01,044,01,0302,0110,01,05,0,
+ /* 5716 */ 0261,01,040,01,0302,0120,01,06,0,
+ /* 5725 */ 0260,01,040,01,0302,0110,01,06,0,
+ /* 5734 */ 0261,01,044,01,0302,0120,01,06,0,
+ /* 5743 */ 0260,01,044,01,0302,0110,01,06,0,
+ /* 5752 */ 0261,01,040,01,0302,0120,01,07,0,
+ /* 5761 */ 0260,01,040,01,0302,0110,01,07,0,
+ /* 5770 */ 0261,01,044,01,0302,0120,01,07,0,
+ /* 5779 */ 0260,01,044,01,0302,0110,01,07,0,
+ /* 5788 */ 0261,01,040,01,0302,0120,01,010,0,
+ /* 5797 */ 0260,01,040,01,0302,0110,01,010,0,
+ /* 5806 */ 0261,01,044,01,0302,0120,01,010,0,
+ /* 5815 */ 0260,01,044,01,0302,0110,01,010,0,
+ /* 5824 */ 0261,01,040,01,0302,0120,01,011,0,
+ /* 5833 */ 0260,01,040,01,0302,0110,01,011,0,
+ /* 5842 */ 0261,01,044,01,0302,0120,01,011,0,
+ /* 5851 */ 0260,01,044,01,0302,0110,01,011,0,
+ /* 5860 */ 0261,01,040,01,0302,0120,01,012,0,
+ /* 5869 */ 0260,01,040,01,0302,0110,01,012,0,
+ /* 5878 */ 0261,01,044,01,0302,0120,01,012,0,
+ /* 5887 */ 0260,01,044,01,0302,0110,01,012,0,
+ /* 5896 */ 0261,01,040,01,0302,0120,01,013,0,
+ /* 5905 */ 0260,01,040,01,0302,0110,01,013,0,
+ /* 5914 */ 0261,01,044,01,0302,0120,01,013,0,
+ /* 5923 */ 0260,01,044,01,0302,0110,01,013,0,
+ /* 5932 */ 0261,01,040,01,0302,0120,01,014,0,
+ /* 5941 */ 0260,01,040,01,0302,0110,01,014,0,
+ /* 5950 */ 0261,01,044,01,0302,0120,01,014,0,
+ /* 5959 */ 0260,01,044,01,0302,0110,01,014,0,
+ /* 5968 */ 0261,01,040,01,0302,0120,01,015,0,
+ /* 5977 */ 0260,01,040,01,0302,0110,01,015,0,
+ /* 5986 */ 0261,01,044,01,0302,0120,01,015,0,
+ /* 5995 */ 0260,01,044,01,0302,0110,01,015,0,
+ /* 6004 */ 0261,01,040,01,0302,0120,01,016,0,
+ /* 6013 */ 0260,01,040,01,0302,0110,01,016,0,
+ /* 6022 */ 0261,01,044,01,0302,0120,01,016,0,
+ /* 6031 */ 0260,01,044,01,0302,0110,01,016,0,
+ /* 6040 */ 0261,01,040,01,0302,0120,01,017,0,
+ /* 6049 */ 0260,01,040,01,0302,0110,01,017,0,
+ /* 6058 */ 0261,01,044,01,0302,0120,01,017,0,
+ /* 6067 */ 0260,01,044,01,0302,0110,01,017,0,
+ /* 6076 */ 0261,01,040,01,0302,0120,01,021,0,
+ /* 6085 */ 0260,01,040,01,0302,0110,01,021,0,
+ /* 6094 */ 0261,01,044,01,0302,0120,01,021,0,
+ /* 6103 */ 0260,01,044,01,0302,0110,01,021,0,
+ /* 6112 */ 0261,01,040,01,0302,0120,01,022,0,
+ /* 6121 */ 0260,01,040,01,0302,0110,01,022,0,
+ /* 6130 */ 0261,01,044,01,0302,0120,01,022,0,
+ /* 6139 */ 0260,01,044,01,0302,0110,01,022,0,
+ /* 6148 */ 0261,01,040,01,0302,0120,01,023,0,
+ /* 6157 */ 0260,01,040,01,0302,0110,01,023,0,
+ /* 6166 */ 0261,01,044,01,0302,0120,01,023,0,
+ /* 6175 */ 0260,01,044,01,0302,0110,01,023,0,
+ /* 6184 */ 0261,01,040,01,0302,0120,01,024,0,
+ /* 6193 */ 0260,01,040,01,0302,0110,01,024,0,
+ /* 6202 */ 0261,01,044,01,0302,0120,01,024,0,
+ /* 6211 */ 0260,01,044,01,0302,0110,01,024,0,
+ /* 6220 */ 0261,01,040,01,0302,0120,01,025,0,
+ /* 6229 */ 0260,01,040,01,0302,0110,01,025,0,
+ /* 6238 */ 0261,01,044,01,0302,0120,01,025,0,
+ /* 6247 */ 0260,01,044,01,0302,0110,01,025,0,
+ /* 6256 */ 0261,01,040,01,0302,0120,01,026,0,
+ /* 6265 */ 0260,01,040,01,0302,0110,01,026,0,
+ /* 6274 */ 0261,01,044,01,0302,0120,01,026,0,
+ /* 6283 */ 0260,01,044,01,0302,0110,01,026,0,
+ /* 6292 */ 0261,01,040,01,0302,0120,01,027,0,
+ /* 6301 */ 0260,01,040,01,0302,0110,01,027,0,
+ /* 6310 */ 0261,01,044,01,0302,0120,01,027,0,
+ /* 6319 */ 0260,01,044,01,0302,0110,01,027,0,
+ /* 6328 */ 0261,01,040,01,0302,0120,01,030,0,
+ /* 6337 */ 0260,01,040,01,0302,0110,01,030,0,
+ /* 6346 */ 0261,01,044,01,0302,0120,01,030,0,
+ /* 6355 */ 0260,01,044,01,0302,0110,01,030,0,
+ /* 6364 */ 0261,01,040,01,0302,0120,01,031,0,
+ /* 6373 */ 0260,01,040,01,0302,0110,01,031,0,
+ /* 6382 */ 0261,01,044,01,0302,0120,01,031,0,
+ /* 6391 */ 0260,01,044,01,0302,0110,01,031,0,
+ /* 6400 */ 0261,01,040,01,0302,0120,01,032,0,
+ /* 6409 */ 0260,01,040,01,0302,0110,01,032,0,
+ /* 6418 */ 0261,01,044,01,0302,0120,01,032,0,
+ /* 6427 */ 0260,01,044,01,0302,0110,01,032,0,
+ /* 6436 */ 0261,01,040,01,0302,0120,01,033,0,
+ /* 6445 */ 0260,01,040,01,0302,0110,01,033,0,
+ /* 6454 */ 0261,01,044,01,0302,0120,01,033,0,
+ /* 6463 */ 0260,01,044,01,0302,0110,01,033,0,
+ /* 6472 */ 0261,01,040,01,0302,0120,01,034,0,
+ /* 6481 */ 0260,01,040,01,0302,0110,01,034,0,
+ /* 6490 */ 0261,01,044,01,0302,0120,01,034,0,
+ /* 6499 */ 0260,01,044,01,0302,0110,01,034,0,
+ /* 6508 */ 0261,01,040,01,0302,0120,01,035,0,
+ /* 6517 */ 0260,01,040,01,0302,0110,01,035,0,
+ /* 6526 */ 0261,01,044,01,0302,0120,01,035,0,
+ /* 6535 */ 0260,01,044,01,0302,0110,01,035,0,
+ /* 6544 */ 0261,01,040,01,0302,0120,01,036,0,
+ /* 6553 */ 0260,01,040,01,0302,0110,01,036,0,
+ /* 6562 */ 0261,01,044,01,0302,0120,01,036,0,
+ /* 6571 */ 0260,01,044,01,0302,0110,01,036,0,
+ /* 6580 */ 0261,01,040,01,0302,0120,01,037,0,
+ /* 6589 */ 0260,01,040,01,0302,0110,01,037,0,
+ /* 6598 */ 0261,01,044,01,0302,0120,01,037,0,
+ /* 6607 */ 0260,01,044,01,0302,0110,01,037,0,
+ /* 6616 */ 0261,01,053,01,0302,0120,01,020,0,
+ /* 6625 */ 0260,01,053,01,0302,0110,01,020,0,
+ /* 6634 */ 0261,01,053,01,0302,0120,01,0,0,
+ /* 6643 */ 0260,01,053,01,0302,0110,01,0,0,
+ /* 6652 */ 0261,01,053,01,0302,0120,01,01,0,
+ /* 6661 */ 0260,01,053,01,0302,0110,01,01,0,
+ /* 6670 */ 0261,01,053,01,0302,0120,01,02,0,
+ /* 6679 */ 0260,01,053,01,0302,0110,01,02,0,
+ /* 6688 */ 0261,01,053,01,0302,0120,01,03,0,
+ /* 6697 */ 0260,01,053,01,0302,0110,01,03,0,
+ /* 6706 */ 0261,01,053,01,0302,0120,01,04,0,
+ /* 6715 */ 0260,01,053,01,0302,0110,01,04,0,
+ /* 6724 */ 0261,01,053,01,0302,0120,01,05,0,
+ /* 6733 */ 0260,01,053,01,0302,0110,01,05,0,
+ /* 6742 */ 0261,01,053,01,0302,0120,01,06,0,
+ /* 6751 */ 0260,01,053,01,0302,0110,01,06,0,
+ /* 6760 */ 0261,01,053,01,0302,0120,01,07,0,
+ /* 6769 */ 0260,01,053,01,0302,0110,01,07,0,
+ /* 6778 */ 0261,01,053,01,0302,0120,01,010,0,
+ /* 6787 */ 0260,01,053,01,0302,0110,01,010,0,
+ /* 6796 */ 0261,01,053,01,0302,0120,01,011,0,
+ /* 6805 */ 0260,01,053,01,0302,0110,01,011,0,
+ /* 6814 */ 0261,01,053,01,0302,0120,01,012,0,
+ /* 6823 */ 0260,01,053,01,0302,0110,01,012,0,
+ /* 6832 */ 0261,01,053,01,0302,0120,01,013,0,
+ /* 6841 */ 0260,01,053,01,0302,0110,01,013,0,
+ /* 6850 */ 0261,01,053,01,0302,0120,01,014,0,
+ /* 6859 */ 0260,01,053,01,0302,0110,01,014,0,
+ /* 6868 */ 0261,01,053,01,0302,0120,01,015,0,
+ /* 6877 */ 0260,01,053,01,0302,0110,01,015,0,
+ /* 6886 */ 0261,01,053,01,0302,0120,01,016,0,
+ /* 6895 */ 0260,01,053,01,0302,0110,01,016,0,
+ /* 6904 */ 0261,01,053,01,0302,0120,01,017,0,
+ /* 6913 */ 0260,01,053,01,0302,0110,01,017,0,
+ /* 6922 */ 0261,01,053,01,0302,0120,01,021,0,
+ /* 6931 */ 0260,01,053,01,0302,0110,01,021,0,
+ /* 6940 */ 0261,01,053,01,0302,0120,01,022,0,
+ /* 6949 */ 0260,01,053,01,0302,0110,01,022,0,
+ /* 6958 */ 0261,01,053,01,0302,0120,01,023,0,
+ /* 6967 */ 0260,01,053,01,0302,0110,01,023,0,
+ /* 6976 */ 0261,01,053,01,0302,0120,01,024,0,
+ /* 6985 */ 0260,01,053,01,0302,0110,01,024,0,
+ /* 6994 */ 0261,01,053,01,0302,0120,01,025,0,
+ /* 7003 */ 0260,01,053,01,0302,0110,01,025,0,
+ /* 7012 */ 0261,01,053,01,0302,0120,01,026,0,
+ /* 7021 */ 0260,01,053,01,0302,0110,01,026,0,
+ /* 7030 */ 0261,01,053,01,0302,0120,01,027,0,
+ /* 7039 */ 0260,01,053,01,0302,0110,01,027,0,
+ /* 7048 */ 0261,01,053,01,0302,0120,01,030,0,
+ /* 7057 */ 0260,01,053,01,0302,0110,01,030,0,
+ /* 7066 */ 0261,01,053,01,0302,0120,01,031,0,
+ /* 7075 */ 0260,01,053,01,0302,0110,01,031,0,
+ /* 7084 */ 0261,01,053,01,0302,0120,01,032,0,
+ /* 7093 */ 0260,01,053,01,0302,0110,01,032,0,
+ /* 7102 */ 0261,01,053,01,0302,0120,01,033,0,
+ /* 7111 */ 0260,01,053,01,0302,0110,01,033,0,
+ /* 7120 */ 0261,01,053,01,0302,0120,01,034,0,
+ /* 7129 */ 0260,01,053,01,0302,0110,01,034,0,
+ /* 7138 */ 0261,01,053,01,0302,0120,01,035,0,
+ /* 7147 */ 0260,01,053,01,0302,0110,01,035,0,
+ /* 7156 */ 0261,01,053,01,0302,0120,01,036,0,
+ /* 7165 */ 0260,01,053,01,0302,0110,01,036,0,
+ /* 7174 */ 0261,01,053,01,0302,0120,01,037,0,
+ /* 7183 */ 0260,01,053,01,0302,0110,01,037,0,
+ /* 7192 */ 0261,01,052,01,0302,0120,01,020,0,
+ /* 7201 */ 0260,01,052,01,0302,0110,01,020,0,
+ /* 7210 */ 0261,01,052,01,0302,0120,01,0,0,
+ /* 7219 */ 0260,01,052,01,0302,0110,01,0,0,
+ /* 7228 */ 0261,01,052,01,0302,0120,01,01,0,
+ /* 7237 */ 0260,01,052,01,0302,0110,01,01,0,
+ /* 7246 */ 0261,01,052,01,0302,0120,01,02,0,
+ /* 7255 */ 0260,01,052,01,0302,0110,01,02,0,
+ /* 7264 */ 0261,01,052,01,0302,0120,01,03,0,
+ /* 7273 */ 0260,01,052,01,0302,0110,01,03,0,
+ /* 7282 */ 0261,01,052,01,0302,0120,01,04,0,
+ /* 7291 */ 0260,01,052,01,0302,0110,01,04,0,
+ /* 7300 */ 0261,01,052,01,0302,0120,01,05,0,
+ /* 7309 */ 0260,01,052,01,0302,0110,01,05,0,
+ /* 7318 */ 0261,01,052,01,0302,0120,01,06,0,
+ /* 7327 */ 0260,01,052,01,0302,0110,01,06,0,
+ /* 7336 */ 0261,01,052,01,0302,0120,01,07,0,
+ /* 7345 */ 0260,01,052,01,0302,0110,01,07,0,
+ /* 7354 */ 0261,01,052,01,0302,0120,01,010,0,
+ /* 7363 */ 0260,01,052,01,0302,0110,01,010,0,
+ /* 7372 */ 0261,01,052,01,0302,0120,01,011,0,
+ /* 7381 */ 0260,01,052,01,0302,0110,01,011,0,
+ /* 7390 */ 0261,01,052,01,0302,0120,01,012,0,
+ /* 7399 */ 0260,01,052,01,0302,0110,01,012,0,
+ /* 7408 */ 0261,01,052,01,0302,0120,01,013,0,
+ /* 7417 */ 0260,01,052,01,0302,0110,01,013,0,
+ /* 7426 */ 0261,01,052,01,0302,0120,01,014,0,
+ /* 7435 */ 0260,01,052,01,0302,0110,01,014,0,
+ /* 7444 */ 0261,01,052,01,0302,0120,01,015,0,
+ /* 7453 */ 0260,01,052,01,0302,0110,01,015,0,
+ /* 7462 */ 0261,01,052,01,0302,0120,01,016,0,
+ /* 7471 */ 0260,01,052,01,0302,0110,01,016,0,
+ /* 7480 */ 0261,01,052,01,0302,0120,01,017,0,
+ /* 7489 */ 0260,01,052,01,0302,0110,01,017,0,
+ /* 7498 */ 0261,01,052,01,0302,0120,01,021,0,
+ /* 7507 */ 0260,01,052,01,0302,0110,01,021,0,
+ /* 7516 */ 0261,01,052,01,0302,0120,01,022,0,
+ /* 7525 */ 0260,01,052,01,0302,0110,01,022,0,
+ /* 7534 */ 0261,01,052,01,0302,0120,01,023,0,
+ /* 7543 */ 0260,01,052,01,0302,0110,01,023,0,
+ /* 7552 */ 0261,01,052,01,0302,0120,01,024,0,
+ /* 7561 */ 0260,01,052,01,0302,0110,01,024,0,
+ /* 7570 */ 0261,01,052,01,0302,0120,01,025,0,
+ /* 7579 */ 0260,01,052,01,0302,0110,01,025,0,
+ /* 7588 */ 0261,01,052,01,0302,0120,01,026,0,
+ /* 7597 */ 0260,01,052,01,0302,0110,01,026,0,
+ /* 7606 */ 0261,01,052,01,0302,0120,01,027,0,
+ /* 7615 */ 0260,01,052,01,0302,0110,01,027,0,
+ /* 7624 */ 0261,01,052,01,0302,0120,01,030,0,
+ /* 7633 */ 0260,01,052,01,0302,0110,01,030,0,
+ /* 7642 */ 0261,01,052,01,0302,0120,01,031,0,
+ /* 7651 */ 0260,01,052,01,0302,0110,01,031,0,
+ /* 7660 */ 0261,01,052,01,0302,0120,01,032,0,
+ /* 7669 */ 0260,01,052,01,0302,0110,01,032,0,
+ /* 7678 */ 0261,01,052,01,0302,0120,01,033,0,
+ /* 7687 */ 0260,01,052,01,0302,0110,01,033,0,
+ /* 7696 */ 0261,01,052,01,0302,0120,01,034,0,
+ /* 7705 */ 0260,01,052,01,0302,0110,01,034,0,
+ /* 7714 */ 0261,01,052,01,0302,0120,01,035,0,
+ /* 7723 */ 0260,01,052,01,0302,0110,01,035,0,
+ /* 7732 */ 0261,01,052,01,0302,0120,01,036,0,
+ /* 7741 */ 0260,01,052,01,0302,0110,01,036,0,
+ /* 7750 */ 0261,01,052,01,0302,0120,01,037,0,
+ /* 7759 */ 0260,01,052,01,0302,0110,01,037,0,
+ /* 7768 */ 0361,03,017,072,0104,0110,01,0,0,
+ /* 7777 */ 0361,03,017,072,0104,0110,01,01,0,
+ /* 7786 */ 0361,03,017,072,0104,0110,01,020,0,
+ /* 7795 */ 0361,03,017,072,0104,0110,01,021,0,
+ /* 7804 */ 0261,03,041,01,0104,0120,01,0,0,
+ /* 7813 */ 0260,03,041,01,0104,0110,01,0,0,
+ /* 7822 */ 0261,03,041,01,0104,0120,01,01,0,
+ /* 7831 */ 0260,03,041,01,0104,0110,01,01,0,
+ /* 7840 */ 0261,03,041,01,0104,0120,01,020,0,
+ /* 7849 */ 0260,03,041,01,0104,0110,01,020,0,
+ /* 7858 */ 0261,03,041,01,0104,0120,01,021,0,
+ /* 7867 */ 0260,03,041,01,0104,0110,01,021,0,
+ /* 7876 */ 0261,03,045,01,0104,0120,01,0,0,
+ /* 7885 */ 0260,03,045,01,0104,0110,01,0,0,
+ /* 7894 */ 0261,03,045,01,0104,0120,01,01,0,
+ /* 7903 */ 0260,03,045,01,0104,0110,01,01,0,
+ /* 7912 */ 0261,03,045,01,0104,0120,01,020,0,
+ /* 7921 */ 0260,03,045,01,0104,0110,01,020,0,
+ /* 7930 */ 0261,03,045,01,0104,0120,01,021,0,
+ /* 7939 */ 0260,03,045,01,0104,0110,01,021,0,
+ /* 7948 */ 0241,0203,041,0301,01,0104,0120,023,0,
+ /* 7957 */ 0240,0203,041,0301,01,0104,0110,022,0,
+ /* 7966 */ 0241,0203,045,0301,01,0104,0120,023,0,
+ /* 7975 */ 0240,0203,045,0301,01,0104,0110,022,0,
+ /* 7984 */ 0241,0203,051,0301,01,0104,0120,023,0,
+ /* 7993 */ 0240,0203,051,0301,01,0104,0110,022,0,
+ /* 8002 */ 0241,0203,01,0301,01,03,0120,023,0,
+ /* 8011 */ 0240,0203,01,0301,01,03,0110,022,0,
+ /* 8020 */ 0241,0203,05,0301,01,03,0120,023,0,
+ /* 8029 */ 0240,0203,05,0301,01,03,0110,022,0,
+ /* 8038 */ 0241,0203,011,0301,01,03,0120,023,0,
+ /* 8047 */ 0240,0203,011,0301,01,03,0110,022,0,
+ /* 8056 */ 0241,0203,021,0301,01,03,0120,023,0,
+ /* 8065 */ 0240,0203,021,0301,01,03,0110,022,0,
+ /* 8074 */ 0241,0203,025,0301,01,03,0120,023,0,
+ /* 8083 */ 0240,0203,025,0301,01,03,0110,022,0,
+ /* 8092 */ 0241,0203,031,0301,01,03,0120,023,0,
+ /* 8101 */ 0240,0203,031,0301,01,03,0110,022,0,
+ /* 8110 */ 0241,0201,021,0301,01,0302,0120,023,0,
+ /* 8119 */ 0241,0201,025,0301,01,0302,0120,023,0,
+ /* 8128 */ 0241,0201,031,0301,01,0302,0120,023,0,
+ /* 8137 */ 0241,0201,0,0301,01,0302,0120,023,0,
+ /* 8146 */ 0241,0201,04,0301,01,0302,0120,023,0,
+ /* 8155 */ 0241,0201,010,0301,01,0302,0120,023,0,
+ /* 8164 */ 0241,0201,023,0306,01,0302,0120,023,0,
+ /* 8173 */ 0241,0201,02,0306,01,0302,0120,023,0,
+ /* 8182 */ 0250,0203,01,0314,01,035,0101,022,0,
+ /* 8191 */ 0250,0203,05,0314,01,035,0101,022,0,
+ /* 8200 */ 0250,0203,011,0314,01,035,0101,022,0,
+ /* 8209 */ 0241,0203,01,0303,01,0102,0120,023,0,
+ /* 8218 */ 0240,0203,01,0303,01,0102,0110,022,0,
+ /* 8227 */ 0241,0203,05,0303,01,0102,0120,023,0,
+ /* 8236 */ 0240,0203,05,0303,01,0102,0110,022,0,
+ /* 8245 */ 0241,0203,011,0303,01,0102,0120,023,0,
+ /* 8254 */ 0240,0203,011,0303,01,0102,0110,022,0,
+ /* 8263 */ 0250,0203,05,0300,01,031,0101,022,0,
+ /* 8272 */ 0250,0203,011,0300,01,031,0101,022,0,
+ /* 8281 */ 0250,0203,05,0312,01,031,0101,022,0,
+ /* 8290 */ 0250,0203,011,0312,01,031,0101,022,0,
+ /* 8299 */ 0250,0203,011,0300,01,033,0101,022,0,
+ /* 8308 */ 0250,0203,011,0313,01,033,0101,022,0,
+ /* 8317 */ 0250,0203,025,0300,01,031,0101,022,0,
+ /* 8326 */ 0250,0203,031,0300,01,031,0101,022,0,
+ /* 8335 */ 0250,0203,025,0311,01,031,0101,022,0,
+ /* 8344 */ 0250,0203,031,0311,01,031,0101,022,0,
+ /* 8353 */ 0250,0203,031,0300,01,033,0101,022,0,
+ /* 8362 */ 0250,0203,031,0312,01,033,0101,022,0,
+ /* 8371 */ 0250,0203,05,0300,01,071,0101,022,0,
+ /* 8380 */ 0250,0203,011,0300,01,071,0101,022,0,
+ /* 8389 */ 0250,0203,05,0312,01,071,0101,022,0,
+ /* 8398 */ 0250,0203,011,0312,01,071,0101,022,0,
+ /* 8407 */ 0250,0203,011,0300,01,073,0101,022,0,
+ /* 8416 */ 0250,0203,011,0313,01,073,0101,022,0,
+ /* 8425 */ 0250,0203,025,0300,01,071,0101,022,0,
+ /* 8434 */ 0250,0203,031,0300,01,071,0101,022,0,
+ /* 8443 */ 0250,0203,025,0311,01,071,0101,022,0,
+ /* 8452 */ 0250,0203,031,0311,01,071,0101,022,0,
+ /* 8461 */ 0250,0203,031,0300,01,073,0101,022,0,
+ /* 8470 */ 0250,0203,031,0312,01,073,0101,022,0,
+ /* 8479 */ 0250,0203,041,0306,01,027,0101,022,0,
+ /* 8488 */ 0241,0203,021,0301,01,0124,0120,023,0,
+ /* 8497 */ 0240,0203,021,0301,01,0124,0110,022,0,
+ /* 8506 */ 0241,0203,025,0301,01,0124,0120,023,0,
+ /* 8515 */ 0240,0203,025,0301,01,0124,0110,022,0,
+ /* 8524 */ 0241,0203,031,0301,01,0124,0120,023,0,
+ /* 8533 */ 0240,0203,031,0301,01,0124,0110,022,0,
+ /* 8542 */ 0241,0203,01,0301,01,0124,0120,023,0,
+ /* 8551 */ 0240,0203,01,0301,01,0124,0110,022,0,
+ /* 8560 */ 0241,0203,05,0301,01,0124,0120,023,0,
+ /* 8569 */ 0240,0203,05,0301,01,0124,0110,022,0,
+ /* 8578 */ 0241,0203,011,0301,01,0124,0120,023,0,
+ /* 8587 */ 0240,0203,011,0301,01,0124,0110,022,0,
+ /* 8596 */ 0241,0203,021,0306,01,0125,0120,023,0,
+ /* 8605 */ 0240,0203,021,0306,01,0125,0110,022,0,
+ /* 8614 */ 0241,0203,01,0306,01,0125,0120,023,0,
+ /* 8623 */ 0240,0203,01,0306,01,0125,0110,022,0,
+ /* 8632 */ 0250,0203,021,0301,01,0146,0110,022,0,
+ /* 8641 */ 0250,0203,025,0301,01,0146,0110,022,0,
+ /* 8650 */ 0250,0203,031,0301,01,0146,0110,022,0,
+ /* 8659 */ 0250,0203,01,0301,01,0146,0110,022,0,
+ /* 8668 */ 0250,0203,05,0301,01,0146,0110,022,0,
+ /* 8677 */ 0250,0203,011,0301,01,0146,0110,022,0,
+ /* 8686 */ 0250,0203,021,0306,01,0147,0110,022,0,
+ /* 8695 */ 0250,0203,01,0306,01,0147,0110,022,0,
+ /* 8704 */ 0374,0250,0202,021,0306,01,0222,0110,0,
+ /* 8713 */ 0374,0250,0202,025,0306,01,0222,0110,0,
+ /* 8722 */ 0375,0250,0202,031,0306,01,0222,0110,0,
+ /* 8731 */ 0374,0250,0202,01,0306,01,0222,0110,0,
+ /* 8740 */ 0375,0250,0202,05,0306,01,0222,0110,0,
+ /* 8749 */ 0376,0250,0202,011,0306,01,0222,0110,0,
+ /* 8758 */ 0375,0250,0202,031,0306,01,0306,0201,0,
+ /* 8767 */ 0376,0250,0202,011,0306,01,0306,0201,0,
+ /* 8776 */ 0376,0250,0202,031,0306,01,0307,0201,0,
+ /* 8785 */ 0376,0250,0202,011,0306,01,0307,0201,0,
+ /* 8794 */ 0375,0250,0202,031,0306,01,0306,0202,0,
+ /* 8803 */ 0376,0250,0202,011,0306,01,0306,0202,0,
+ /* 8812 */ 0376,0250,0202,031,0306,01,0307,0202,0,
+ /* 8821 */ 0376,0250,0202,011,0306,01,0307,0202,0,
+ /* 8830 */ 0374,0250,0202,021,0306,01,0223,0110,0,
+ /* 8839 */ 0375,0250,0202,025,0306,01,0223,0110,0,
+ /* 8848 */ 0376,0250,0202,031,0306,01,0223,0110,0,
+ /* 8857 */ 0374,0250,0202,01,0306,01,0223,0110,0,
+ /* 8866 */ 0375,0250,0202,05,0306,01,0223,0110,0,
+ /* 8875 */ 0376,0250,0202,011,0306,01,0223,0110,0,
+ /* 8884 */ 0250,0203,021,0301,01,046,0110,022,0,
+ /* 8893 */ 0250,0203,025,0301,01,046,0110,022,0,
+ /* 8902 */ 0250,0203,031,0301,01,046,0110,022,0,
+ /* 8911 */ 0250,0203,01,0301,01,046,0110,022,0,
+ /* 8920 */ 0250,0203,05,0301,01,046,0110,022,0,
+ /* 8929 */ 0250,0203,011,0301,01,046,0110,022,0,
+ /* 8938 */ 0241,0203,021,0306,01,047,0120,023,0,
+ /* 8947 */ 0241,0203,01,0306,01,047,0120,023,0,
+ /* 8956 */ 0241,0203,05,0312,01,030,0120,023,0,
+ /* 8965 */ 0240,0203,05,0312,01,030,0110,022,0,
+ /* 8974 */ 0241,0203,011,0312,01,030,0120,023,0,
+ /* 8983 */ 0240,0203,011,0312,01,030,0110,022,0,
+ /* 8992 */ 0241,0203,011,0313,01,032,0120,023,0,
+ /* 9001 */ 0240,0203,011,0313,01,032,0110,022,0,
+ /* 9010 */ 0241,0203,025,0311,01,030,0120,023,0,
+ /* 9019 */ 0240,0203,025,0311,01,030,0110,022,0,
+ /* 9028 */ 0241,0203,031,0311,01,030,0120,023,0,
+ /* 9037 */ 0240,0203,031,0311,01,030,0110,022,0,
+ /* 9046 */ 0241,0203,031,0312,01,032,0120,023,0,
+ /* 9055 */ 0240,0203,031,0312,01,032,0110,022,0,
+ /* 9064 */ 0241,0203,05,0312,01,070,0120,023,0,
+ /* 9073 */ 0240,0203,05,0312,01,070,0110,022,0,
+ /* 9082 */ 0241,0203,011,0312,01,070,0120,023,0,
+ /* 9091 */ 0240,0203,011,0312,01,070,0110,022,0,
+ /* 9100 */ 0241,0203,011,0313,01,072,0120,023,0,
+ /* 9109 */ 0240,0203,011,0313,01,072,0110,022,0,
+ /* 9118 */ 0241,0203,025,0311,01,070,0120,023,0,
+ /* 9127 */ 0240,0203,025,0311,01,070,0110,022,0,
+ /* 9136 */ 0241,0203,031,0311,01,070,0120,023,0,
+ /* 9145 */ 0240,0203,031,0311,01,070,0110,022,0,
+ /* 9154 */ 0241,0203,031,0312,01,072,0120,023,0,
+ /* 9163 */ 0240,0203,031,0312,01,072,0110,022,0,
+ /* 9172 */ 0241,0203,01,0306,01,041,0120,023,0,
+ /* 9181 */ 0240,0203,01,0306,01,041,0110,022,0,
+ /* 9190 */ 0241,0203,041,0303,01,017,0120,023,0,
+ /* 9199 */ 0240,0203,041,0303,01,017,0110,022,0,
+ /* 9208 */ 0241,0203,045,0303,01,017,0120,023,0,
+ /* 9217 */ 0240,0203,045,0303,01,017,0110,022,0,
+ /* 9226 */ 0241,0203,051,0303,01,017,0120,023,0,
+ /* 9235 */ 0240,0203,051,0303,01,017,0110,022,0,
+ /* 9244 */ 0241,0203,01,0303,01,077,0120,023,0,
+ /* 9253 */ 0241,0203,05,0303,01,077,0120,023,0,
+ /* 9262 */ 0241,0203,011,0303,01,077,0120,023,0,
+ /* 9271 */ 0241,0203,01,0301,01,037,0120,023,0,
+ /* 9280 */ 0241,0203,05,0301,01,037,0120,023,0,
+ /* 9289 */ 0241,0203,011,0301,01,037,0120,023,0,
+ /* 9298 */ 0241,0203,021,0301,01,037,0120,023,0,
+ /* 9307 */ 0241,0203,025,0301,01,037,0120,023,0,
+ /* 9316 */ 0241,0203,031,0301,01,037,0120,023,0,
+ /* 9325 */ 0241,0203,01,0303,01,076,0120,023,0,
+ /* 9334 */ 0241,0203,05,0303,01,076,0120,023,0,
+ /* 9343 */ 0241,0203,011,0303,01,076,0120,023,0,
+ /* 9352 */ 0241,0203,01,0301,01,036,0120,023,0,
+ /* 9361 */ 0241,0203,05,0301,01,036,0120,023,0,
+ /* 9370 */ 0241,0203,011,0301,01,036,0120,023,0,
+ /* 9379 */ 0241,0203,021,0301,01,036,0120,023,0,
+ /* 9388 */ 0241,0203,025,0301,01,036,0120,023,0,
+ /* 9397 */ 0241,0203,031,0301,01,036,0120,023,0,
+ /* 9406 */ 0241,0203,021,0303,01,076,0120,023,0,
+ /* 9415 */ 0241,0203,025,0303,01,076,0120,023,0,
+ /* 9424 */ 0241,0203,031,0303,01,076,0120,023,0,
+ /* 9433 */ 0241,0203,021,0303,01,077,0120,023,0,
+ /* 9442 */ 0241,0203,025,0303,01,077,0120,023,0,
+ /* 9451 */ 0241,0203,031,0303,01,077,0120,023,0,
+ /* 9460 */ 0250,0203,021,0301,01,05,0110,022,0,
+ /* 9469 */ 0250,0203,025,0301,01,05,0110,022,0,
+ /* 9478 */ 0250,0203,031,0301,01,05,0110,022,0,
+ /* 9487 */ 0250,0203,01,0301,01,04,0110,022,0,
+ /* 9496 */ 0250,0203,05,0301,01,04,0110,022,0,
+ /* 9505 */ 0250,0203,011,0301,01,04,0110,022,0,
+ /* 9514 */ 0250,0203,025,0301,01,01,0110,022,0,
+ /* 9523 */ 0250,0203,031,0301,01,01,0110,022,0,
+ /* 9532 */ 0250,0203,025,0301,01,0,0110,022,0,
+ /* 9541 */ 0250,0203,031,0301,01,0,0110,022,0,
+ /* 9550 */ 0250,0203,041,0304,01,024,0101,022,0,
+ /* 9559 */ 0250,0203,01,0306,01,026,0101,022,0,
+ /* 9568 */ 0250,0203,021,0306,01,026,0101,022,0,
+ /* 9577 */ 0250,0203,041,0305,01,025,0101,022,0,
+ /* 9586 */ 0250,0201,041,0300,01,0305,0110,022,0,
+ /* 9595 */ 0374,0250,0202,01,0306,01,0220,0110,0,
+ /* 9604 */ 0375,0250,0202,05,0306,01,0220,0110,0,
+ /* 9613 */ 0376,0250,0202,011,0306,01,0220,0110,0,
+ /* 9622 */ 0374,0250,0202,021,0306,01,0220,0110,0,
+ /* 9631 */ 0374,0250,0202,025,0306,01,0220,0110,0,
+ /* 9640 */ 0375,0250,0202,031,0306,01,0220,0110,0,
+ /* 9649 */ 0374,0250,0202,01,0306,01,0221,0110,0,
+ /* 9658 */ 0375,0250,0202,05,0306,01,0221,0110,0,
+ /* 9667 */ 0376,0250,0202,011,0306,01,0221,0110,0,
+ /* 9676 */ 0374,0250,0202,021,0306,01,0221,0110,0,
+ /* 9685 */ 0375,0250,0202,025,0306,01,0221,0110,0,
+ /* 9694 */ 0376,0250,0202,031,0306,01,0221,0110,0,
+ /* 9703 */ 0241,0203,041,0304,01,040,0120,023,0,
+ /* 9712 */ 0240,0203,041,0304,01,040,0110,022,0,
+ /* 9721 */ 0241,0203,01,0306,01,042,0120,023,0,
+ /* 9730 */ 0240,0203,01,0306,01,042,0110,022,0,
+ /* 9739 */ 0241,0203,021,0306,01,042,0120,023,0,
+ /* 9748 */ 0240,0203,021,0306,01,042,0110,022,0,
+ /* 9757 */ 0241,0201,041,0305,01,0304,0120,023,0,
+ /* 9766 */ 0240,0201,041,0305,01,0304,0110,022,0,
+ /* 9775 */ 0240,0201,01,0301,01,0162,0211,022,0,
+ /* 9784 */ 0240,0201,01,0301,01,0162,0201,021,0,
+ /* 9793 */ 0240,0201,05,0301,01,0162,0211,022,0,
+ /* 9802 */ 0240,0201,05,0301,01,0162,0201,021,0,
+ /* 9811 */ 0240,0201,011,0301,01,0162,0211,022,0,
+ /* 9820 */ 0240,0201,011,0301,01,0162,0201,021,0,
+ /* 9829 */ 0240,0201,021,0301,01,0162,0211,022,0,
+ /* 9838 */ 0240,0201,021,0301,01,0162,0201,021,0,
+ /* 9847 */ 0240,0201,025,0301,01,0162,0211,022,0,
+ /* 9856 */ 0240,0201,025,0301,01,0162,0201,021,0,
+ /* 9865 */ 0240,0201,031,0301,01,0162,0211,022,0,
+ /* 9874 */ 0240,0201,031,0301,01,0162,0201,021,0,
+ /* 9883 */ 0240,0201,01,0301,01,0162,0210,022,0,
+ /* 9892 */ 0240,0201,01,0301,01,0162,0200,021,0,
+ /* 9901 */ 0240,0201,05,0301,01,0162,0210,022,0,
+ /* 9910 */ 0240,0201,05,0301,01,0162,0200,021,0,
+ /* 9919 */ 0240,0201,011,0301,01,0162,0210,022,0,
+ /* 9928 */ 0240,0201,011,0301,01,0162,0200,021,0,
+ /* 9937 */ 0240,0201,021,0301,01,0162,0210,022,0,
+ /* 9946 */ 0240,0201,021,0301,01,0162,0200,021,0,
+ /* 9955 */ 0240,0201,025,0301,01,0162,0210,022,0,
+ /* 9964 */ 0240,0201,025,0301,01,0162,0200,021,0,
+ /* 9973 */ 0240,0201,031,0301,01,0162,0210,022,0,
+ /* 9982 */ 0240,0201,031,0301,01,0162,0200,021,0,
+ /* 9991 */ 0374,0250,0202,01,0306,01,0240,0101,0,
+ /* 10000 */ 0375,0250,0202,05,0306,01,0240,0101,0,
+ /* 10009 */ 0376,0250,0202,011,0306,01,0240,0101,0,
+ /* 10018 */ 0374,0250,0202,021,0306,01,0240,0101,0,
+ /* 10027 */ 0374,0250,0202,025,0306,01,0240,0101,0,
+ /* 10036 */ 0375,0250,0202,031,0306,01,0240,0101,0,
+ /* 10045 */ 0374,0250,0202,01,0306,01,0241,0101,0,
+ /* 10054 */ 0375,0250,0202,05,0306,01,0241,0101,0,
+ /* 10063 */ 0376,0250,0202,011,0306,01,0241,0101,0,
+ /* 10072 */ 0374,0250,0202,021,0306,01,0241,0101,0,
+ /* 10081 */ 0375,0250,0202,025,0306,01,0241,0101,0,
+ /* 10090 */ 0376,0250,0202,031,0306,01,0241,0101,0,
+ /* 10099 */ 0250,0201,01,0301,01,0160,0110,022,0,
+ /* 10108 */ 0250,0201,05,0301,01,0160,0110,022,0,
+ /* 10117 */ 0250,0201,011,0301,01,0160,0110,022,0,
+ /* 10126 */ 0250,0201,042,0303,01,0160,0110,022,0,
+ /* 10135 */ 0250,0201,046,0303,01,0160,0110,022,0,
+ /* 10144 */ 0250,0201,052,0303,01,0160,0110,022,0,
+ /* 10153 */ 0250,0201,043,0303,01,0160,0110,022,0,
+ /* 10162 */ 0250,0201,047,0303,01,0160,0110,022,0,
+ /* 10171 */ 0250,0201,053,0303,01,0160,0110,022,0,
+ /* 10180 */ 0240,0201,01,0301,01,0162,0216,022,0,
+ /* 10189 */ 0240,0201,01,0301,01,0162,0206,021,0,
+ /* 10198 */ 0240,0201,05,0301,01,0162,0216,022,0,
+ /* 10207 */ 0240,0201,05,0301,01,0162,0206,021,0,
+ /* 10216 */ 0240,0201,011,0301,01,0162,0216,022,0,
+ /* 10225 */ 0240,0201,011,0301,01,0162,0206,021,0,
+ /* 10234 */ 0240,0201,041,0303,01,0163,0217,022,0,
+ /* 10243 */ 0240,0201,041,0303,01,0163,0207,021,0,
+ /* 10252 */ 0240,0201,045,0303,01,0163,0217,022,0,
+ /* 10261 */ 0240,0201,045,0303,01,0163,0207,021,0,
+ /* 10270 */ 0240,0201,051,0303,01,0163,0217,022,0,
+ /* 10279 */ 0240,0201,051,0303,01,0163,0207,021,0,
+ /* 10288 */ 0240,0201,021,0301,01,0163,0216,022,0,
+ /* 10297 */ 0240,0201,021,0301,01,0163,0206,021,0,
+ /* 10306 */ 0240,0201,025,0301,01,0163,0216,022,0,
+ /* 10315 */ 0240,0201,025,0301,01,0163,0206,021,0,
+ /* 10324 */ 0240,0201,031,0301,01,0163,0216,022,0,
+ /* 10333 */ 0240,0201,031,0301,01,0163,0206,021,0,
+ /* 10342 */ 0240,0201,041,0303,01,0161,0216,022,0,
+ /* 10351 */ 0240,0201,041,0303,01,0161,0206,021,0,
+ /* 10360 */ 0240,0201,045,0303,01,0161,0216,022,0,
+ /* 10369 */ 0240,0201,045,0303,01,0161,0206,021,0,
+ /* 10378 */ 0240,0201,051,0303,01,0161,0216,022,0,
+ /* 10387 */ 0240,0201,051,0303,01,0161,0206,021,0,
+ /* 10396 */ 0240,0201,01,0301,01,0162,0214,022,0,
+ /* 10405 */ 0240,0201,01,0301,01,0162,0204,021,0,
+ /* 10414 */ 0240,0201,05,0301,01,0162,0214,022,0,
+ /* 10423 */ 0240,0201,05,0301,01,0162,0204,021,0,
+ /* 10432 */ 0240,0201,011,0301,01,0162,0214,022,0,
+ /* 10441 */ 0240,0201,011,0301,01,0162,0204,021,0,
+ /* 10450 */ 0240,0201,021,0301,01,0162,0214,022,0,
+ /* 10459 */ 0240,0201,021,0301,01,0162,0204,021,0,
+ /* 10468 */ 0240,0201,025,0301,01,0162,0214,022,0,
+ /* 10477 */ 0240,0201,025,0301,01,0162,0204,021,0,
+ /* 10486 */ 0240,0201,031,0301,01,0162,0214,022,0,
+ /* 10495 */ 0240,0201,031,0301,01,0162,0204,021,0,
+ /* 10504 */ 0240,0201,041,0303,01,0161,0214,022,0,
+ /* 10513 */ 0240,0201,041,0303,01,0161,0204,021,0,
+ /* 10522 */ 0240,0201,045,0303,01,0161,0214,022,0,
+ /* 10531 */ 0240,0201,045,0303,01,0161,0204,021,0,
+ /* 10540 */ 0240,0201,051,0303,01,0161,0214,022,0,
+ /* 10549 */ 0240,0201,051,0303,01,0161,0204,021,0,
+ /* 10558 */ 0240,0201,01,0301,01,0162,0212,022,0,
+ /* 10567 */ 0240,0201,01,0301,01,0162,0202,021,0,
+ /* 10576 */ 0240,0201,05,0301,01,0162,0212,022,0,
+ /* 10585 */ 0240,0201,05,0301,01,0162,0202,021,0,
+ /* 10594 */ 0240,0201,011,0301,01,0162,0212,022,0,
+ /* 10603 */ 0240,0201,011,0301,01,0162,0202,021,0,
+ /* 10612 */ 0240,0201,041,0303,01,0163,0213,022,0,
+ /* 10621 */ 0240,0201,041,0303,01,0163,0203,021,0,
+ /* 10630 */ 0240,0201,045,0303,01,0163,0213,022,0,
+ /* 10639 */ 0240,0201,045,0303,01,0163,0203,021,0,
+ /* 10648 */ 0240,0201,051,0303,01,0163,0213,022,0,
+ /* 10657 */ 0240,0201,051,0303,01,0163,0203,021,0,
+ /* 10666 */ 0240,0201,021,0301,01,0163,0212,022,0,
+ /* 10675 */ 0240,0201,021,0301,01,0163,0202,021,0,
+ /* 10684 */ 0240,0201,025,0301,01,0163,0212,022,0,
+ /* 10693 */ 0240,0201,025,0301,01,0163,0202,021,0,
+ /* 10702 */ 0240,0201,031,0301,01,0163,0212,022,0,
+ /* 10711 */ 0240,0201,031,0301,01,0163,0202,021,0,
+ /* 10720 */ 0240,0201,041,0303,01,0161,0212,022,0,
+ /* 10729 */ 0240,0201,041,0303,01,0161,0202,021,0,
+ /* 10738 */ 0240,0201,045,0303,01,0161,0212,022,0,
+ /* 10747 */ 0240,0201,045,0303,01,0161,0202,021,0,
+ /* 10756 */ 0240,0201,051,0303,01,0161,0212,022,0,
+ /* 10765 */ 0240,0201,051,0303,01,0161,0202,021,0,
+ /* 10774 */ 0241,0203,01,0301,01,045,0120,023,0,
+ /* 10783 */ 0241,0203,05,0301,01,045,0120,023,0,
+ /* 10792 */ 0241,0203,011,0301,01,045,0120,023,0,
+ /* 10801 */ 0241,0203,021,0301,01,045,0120,023,0,
+ /* 10810 */ 0241,0203,025,0301,01,045,0120,023,0,
+ /* 10819 */ 0241,0203,031,0301,01,045,0120,023,0,
+ /* 10828 */ 0241,0203,021,0301,01,0120,0120,023,0,
+ /* 10837 */ 0240,0203,021,0301,01,0120,0110,022,0,
+ /* 10846 */ 0241,0203,025,0301,01,0120,0120,023,0,
+ /* 10855 */ 0240,0203,025,0301,01,0120,0110,022,0,
+ /* 10864 */ 0241,0203,031,0301,01,0120,0120,023,0,
+ /* 10873 */ 0240,0203,031,0301,01,0120,0110,022,0,
+ /* 10882 */ 0241,0203,01,0301,01,0120,0120,023,0,
+ /* 10891 */ 0240,0203,01,0301,01,0120,0110,022,0,
+ /* 10900 */ 0241,0203,05,0301,01,0120,0120,023,0,
+ /* 10909 */ 0240,0203,05,0301,01,0120,0110,022,0,
+ /* 10918 */ 0241,0203,011,0301,01,0120,0120,023,0,
+ /* 10927 */ 0240,0203,011,0301,01,0120,0110,022,0,
+ /* 10936 */ 0241,0203,021,0306,01,0121,0120,023,0,
+ /* 10945 */ 0240,0203,021,0306,01,0121,0110,022,0,
+ /* 10954 */ 0241,0203,01,0306,01,0121,0120,023,0,
+ /* 10963 */ 0240,0203,01,0306,01,0121,0110,022,0,
+ /* 10972 */ 0250,0203,021,0301,01,0126,0110,022,0,
+ /* 10981 */ 0250,0203,025,0301,01,0126,0110,022,0,
+ /* 10990 */ 0250,0203,031,0301,01,0126,0110,022,0,
+ /* 10999 */ 0250,0203,01,0301,01,0126,0110,022,0,
+ /* 11008 */ 0250,0203,05,0301,01,0126,0110,022,0,
+ /* 11017 */ 0250,0203,011,0301,01,0126,0110,022,0,
+ /* 11026 */ 0241,0203,021,0306,01,0127,0120,023,0,
+ /* 11035 */ 0240,0203,021,0306,01,0127,0110,022,0,
+ /* 11044 */ 0241,0203,01,0306,01,0127,0120,023,0,
+ /* 11053 */ 0240,0203,01,0306,01,0127,0110,022,0,
+ /* 11062 */ 0250,0203,021,0301,01,011,0110,022,0,
+ /* 11071 */ 0250,0203,025,0301,01,011,0110,022,0,
+ /* 11080 */ 0250,0203,031,0301,01,011,0110,022,0,
+ /* 11089 */ 0250,0203,01,0301,01,010,0110,022,0,
+ /* 11098 */ 0250,0203,05,0301,01,010,0110,022,0,
+ /* 11107 */ 0250,0203,011,0301,01,010,0110,022,0,
+ /* 11116 */ 0241,0203,021,0306,01,013,0120,023,0,
+ /* 11125 */ 0240,0203,021,0306,01,013,0110,022,0,
+ /* 11134 */ 0241,0203,01,0306,01,012,0120,023,0,
+ /* 11143 */ 0240,0203,01,0306,01,012,0110,022,0,
+ /* 11152 */ 0374,0250,0202,021,0306,01,0242,0101,0,
+ /* 11161 */ 0374,0250,0202,025,0306,01,0242,0101,0,
+ /* 11170 */ 0375,0250,0202,031,0306,01,0242,0101,0,
+ /* 11179 */ 0374,0250,0202,01,0306,01,0242,0101,0,
+ /* 11188 */ 0375,0250,0202,05,0306,01,0242,0101,0,
+ /* 11197 */ 0376,0250,0202,011,0306,01,0242,0101,0,
+ /* 11206 */ 0375,0250,0202,031,0306,01,0306,0205,0,
+ /* 11215 */ 0376,0250,0202,011,0306,01,0306,0205,0,
+ /* 11224 */ 0376,0250,0202,031,0306,01,0307,0205,0,
+ /* 11233 */ 0376,0250,0202,011,0306,01,0307,0205,0,
+ /* 11242 */ 0375,0250,0202,031,0306,01,0306,0206,0,
+ /* 11251 */ 0376,0250,0202,011,0306,01,0306,0206,0,
+ /* 11260 */ 0376,0250,0202,031,0306,01,0307,0206,0,
+ /* 11269 */ 0376,0250,0202,011,0306,01,0307,0206,0,
+ /* 11278 */ 0374,0250,0202,021,0306,01,0243,0101,0,
+ /* 11287 */ 0375,0250,0202,025,0306,01,0243,0101,0,
+ /* 11296 */ 0376,0250,0202,031,0306,01,0243,0101,0,
+ /* 11305 */ 0374,0250,0202,01,0306,01,0243,0101,0,
+ /* 11314 */ 0375,0250,0202,05,0306,01,0243,0101,0,
+ /* 11323 */ 0376,0250,0202,011,0306,01,0243,0101,0,
+ /* 11332 */ 0241,0203,05,0301,01,043,0120,023,0,
+ /* 11341 */ 0240,0203,05,0301,01,043,0110,022,0,
+ /* 11350 */ 0241,0203,011,0301,01,043,0120,023,0,
+ /* 11359 */ 0240,0203,011,0301,01,043,0110,022,0,
+ /* 11368 */ 0241,0203,025,0301,01,043,0120,023,0,
+ /* 11377 */ 0240,0203,025,0301,01,043,0110,022,0,
+ /* 11386 */ 0241,0203,031,0301,01,043,0120,023,0,
+ /* 11395 */ 0240,0203,031,0301,01,043,0110,022,0,
+ /* 11404 */ 0241,0203,05,0301,01,0103,0120,023,0,
+ /* 11413 */ 0240,0203,05,0301,01,0103,0110,022,0,
+ /* 11422 */ 0241,0203,011,0301,01,0103,0120,023,0,
+ /* 11431 */ 0240,0203,011,0301,01,0103,0110,022,0,
+ /* 11440 */ 0241,0203,025,0301,01,0103,0120,023,0,
+ /* 11449 */ 0240,0203,025,0301,01,0103,0110,022,0,
+ /* 11458 */ 0241,0203,031,0301,01,0103,0120,023,0,
+ /* 11467 */ 0240,0203,031,0301,01,0103,0110,022,0,
+ /* 11476 */ 0241,0201,021,0301,01,0306,0120,023,0,
+ /* 11485 */ 0240,0201,021,0301,01,0306,0110,022,0,
+ /* 11494 */ 0241,0201,025,0301,01,0306,0120,023,0,
+ /* 11503 */ 0240,0201,025,0301,01,0306,0110,022,0,
+ /* 11512 */ 0241,0201,031,0301,01,0306,0120,023,0,
+ /* 11521 */ 0240,0201,031,0301,01,0306,0110,022,0,
+ /* 11530 */ 0241,0201,0,0301,01,0306,0120,023,0,
+ /* 11539 */ 0240,0201,0,0301,01,0306,0110,022,0,
+ /* 11548 */ 0241,0201,04,0301,01,0306,0120,023,0,
+ /* 11557 */ 0240,0201,04,0301,01,0306,0110,022,0,
+ /* 11566 */ 0241,0201,010,0301,01,0306,0120,023,0,
+ /* 11575 */ 0240,0201,010,0301,01,0306,0110,022,0,
+ /* 11584 */ 0323,0313,0361,03,017,070,0370,0110,0,
+ /* 11593 */ 0241,0203,021,0301,01,0317,0120,023,0,
+ /* 11602 */ 0240,0203,021,0301,01,0317,0110,022,0,
+ /* 11611 */ 0241,0203,025,0301,01,0317,0120,023,0,
+ /* 11620 */ 0240,0203,025,0301,01,0317,0110,022,0,
+ /* 11629 */ 0241,0203,031,0301,01,0317,0120,023,0,
+ /* 11638 */ 0240,0203,031,0301,01,0317,0110,022,0,
+ /* 11647 */ 0241,0203,021,0301,01,0316,0120,023,0,
+ /* 11656 */ 0240,0203,021,0301,01,0316,0110,022,0,
+ /* 11665 */ 0241,0203,025,0301,01,0316,0120,023,0,
+ /* 11674 */ 0240,0203,025,0301,01,0316,0110,022,0,
+ /* 11683 */ 0241,0203,031,0301,01,0316,0120,023,0,
+ /* 11692 */ 0240,0203,031,0301,01,0316,0110,022,0,
+ /* 11701 */ 0241,0203,021,0303,01,0160,0120,023,0,
+ /* 11710 */ 0240,0203,021,0303,01,0160,0110,022,0,
+ /* 11719 */ 0241,0203,025,0303,01,0160,0120,023,0,
+ /* 11728 */ 0240,0203,025,0303,01,0160,0110,022,0,
+ /* 11737 */ 0241,0203,031,0303,01,0160,0120,023,0,
+ /* 11746 */ 0240,0203,031,0303,01,0160,0110,022,0,
+ /* 11755 */ 0241,0203,01,0301,01,0161,0120,023,0,
+ /* 11764 */ 0240,0203,01,0301,01,0161,0110,022,0,
+ /* 11773 */ 0241,0203,05,0301,01,0161,0120,023,0,
+ /* 11782 */ 0240,0203,05,0301,01,0161,0110,022,0,
+ /* 11791 */ 0241,0203,011,0301,01,0161,0120,023,0,
+ /* 11800 */ 0240,0203,011,0301,01,0161,0110,022,0,
+ /* 11809 */ 0241,0203,021,0301,01,0161,0120,023,0,
+ /* 11818 */ 0240,0203,021,0301,01,0161,0110,022,0,
+ /* 11827 */ 0241,0203,025,0301,01,0161,0120,023,0,
+ /* 11836 */ 0240,0203,025,0301,01,0161,0110,022,0,
+ /* 11845 */ 0241,0203,031,0301,01,0161,0120,023,0,
+ /* 11854 */ 0240,0203,031,0301,01,0161,0110,022,0,
+ /* 11863 */ 0241,0203,021,0303,01,0162,0120,023,0,
+ /* 11872 */ 0240,0203,021,0303,01,0162,0110,022,0,
+ /* 11881 */ 0241,0203,025,0303,01,0162,0120,023,0,
+ /* 11890 */ 0240,0203,025,0303,01,0162,0110,022,0,
+ /* 11899 */ 0241,0203,031,0303,01,0162,0120,023,0,
+ /* 11908 */ 0240,0203,031,0303,01,0162,0110,022,0,
+ /* 11917 */ 0241,0203,01,0301,01,0163,0120,023,0,
+ /* 11926 */ 0240,0203,01,0301,01,0163,0110,022,0,
+ /* 11935 */ 0241,0203,05,0301,01,0163,0120,023,0,
+ /* 11944 */ 0240,0203,05,0301,01,0163,0110,022,0,
+ /* 11953 */ 0241,0203,011,0301,01,0163,0120,023,0,
+ /* 11962 */ 0240,0203,011,0301,01,0163,0110,022,0,
+ /* 11971 */ 0241,0203,021,0301,01,0163,0120,023,0,
+ /* 11980 */ 0240,0203,021,0301,01,0163,0110,022,0,
+ /* 11989 */ 0241,0203,025,0301,01,0163,0120,023,0,
+ /* 11998 */ 0240,0203,025,0301,01,0163,0110,022,0,
+ /* 12007 */ 0241,0203,031,0301,01,0163,0120,023,0,
+ /* 12016 */ 0240,0203,031,0301,01,0163,0110,022,0,
+ /* 12025 */ 0241,0203,0,0301,01,0302,0120,023,0,
+ /* 12034 */ 0240,0203,0,0301,01,0302,0110,022,0,
+ /* 12043 */ 0241,0203,04,0301,01,0302,0120,023,0,
+ /* 12052 */ 0240,0203,04,0301,01,0302,0110,022,0,
+ /* 12061 */ 0241,0203,010,0301,01,0302,0120,023,0,
+ /* 12070 */ 0240,0203,010,0301,01,0302,0110,022,0,
+ /* 12079 */ 0241,0203,02,0306,01,0302,0120,023,0,
+ /* 12088 */ 0240,0203,02,0306,01,0302,0110,022,0,
+ /* 12097 */ 0250,0203,0,0301,01,0146,0110,022,0,
+ /* 12106 */ 0250,0203,04,0301,01,0146,0110,022,0,
+ /* 12115 */ 0250,0203,010,0301,01,0146,0110,022,0,
+ /* 12124 */ 0250,0203,0,0306,01,0147,0110,022,0,
+ /* 12133 */ 0250,0203,0,0301,01,045,0110,022,0,
+ /* 12142 */ 0250,0203,04,0301,01,045,0110,022,0,
+ /* 12151 */ 0250,0203,010,0301,01,045,0110,022,0,
+ /* 12160 */ 0250,0203,0,0306,01,047,0110,022,0,
+ /* 12169 */ 0250,0203,0,0301,01,0126,0110,022,0,
+ /* 12178 */ 0250,0203,04,0301,01,0126,0110,022,0,
+ /* 12187 */ 0250,0203,010,0301,01,0126,0110,022,0,
+ /* 12196 */ 0242,0203,0,0306,01,0127,0110,023,0,
+ /* 12205 */ 0241,0203,0,0306,01,0127,0100,022,0,
+ /* 12214 */ 0250,0203,0,0301,01,010,0110,022,0,
+ /* 12223 */ 0250,0203,04,0301,01,010,0110,022,0,
+ /* 12232 */ 0250,0203,010,0301,01,010,0110,022,0,
+ /* 12241 */ 0241,0203,0,0306,01,012,0120,023,0,
+ /* 12250 */ 0240,0203,0,0306,01,012,0110,022,0,
+ /* 12259 */ 0250,0206,01,0301,01,0116,0110,022,0,
+ /* 12268 */ 0250,0206,05,0301,01,0116,0110,022,0,
+ /* 12277 */ 0250,0206,011,0301,01,0116,0110,022,0,
+ /* 12286 */ 0241,0206,01,0306,01,0117,0120,023,0,
+ /* 12295 */ 0240,0206,01,0306,01,0117,0110,022,0,
+ /* 12304 */ 0273,0320,02,017,0272,0207,025,0,
+ /* 12312 */ 0273,0321,02,017,0272,0207,025,0,
+ /* 12320 */ 0273,0324,02,017,0272,0207,025,0,
+ /* 12328 */ 0273,0320,02,017,0272,0206,025,0,
+ /* 12336 */ 0273,0321,02,017,0272,0206,025,0,
+ /* 12344 */ 0273,0324,02,017,0272,0206,025,0,
+ /* 12352 */ 0273,0320,02,017,0272,0205,025,0,
+ /* 12360 */ 0273,0321,02,017,0272,0205,025,0,
+ /* 12368 */ 0273,0324,02,017,0272,0205,025,0,
+ /* 12376 */ 0323,02,017,017,0110,01,0277,0,
+ /* 12384 */ 0323,02,017,017,0110,01,035,0,
+ /* 12392 */ 0323,02,017,017,0110,01,0256,0,
+ /* 12400 */ 0323,02,017,017,0110,01,0236,0,
+ /* 12408 */ 0323,02,017,017,0110,01,0260,0,
+ /* 12416 */ 0323,02,017,017,0110,01,0220,0,
+ /* 12424 */ 0323,02,017,017,0110,01,0240,0,
+ /* 12432 */ 0323,02,017,017,0110,01,0244,0,
+ /* 12440 */ 0323,02,017,017,0110,01,0224,0,
+ /* 12448 */ 0323,02,017,017,0110,01,0264,0,
+ /* 12456 */ 0323,02,017,017,0110,01,0226,0,
+ /* 12464 */ 0323,02,017,017,0110,01,0246,0,
+ /* 12472 */ 0323,02,017,017,0110,01,0266,0,
+ /* 12480 */ 0323,02,017,017,0110,01,0247,0,
+ /* 12488 */ 0323,02,017,017,0110,01,0227,0,
+ /* 12496 */ 0323,02,017,017,0110,01,0232,0,
+ /* 12504 */ 0323,02,017,017,0110,01,0252,0,
+ /* 12512 */ 0323,02,017,017,0110,01,015,0,
+ /* 12520 */ 0323,02,017,017,0110,01,0267,0,
+ /* 12528 */ 0360,02,017,0302,0110,01,0,0,
+ /* 12536 */ 0333,02,017,0302,0110,01,0,0,
+ /* 12544 */ 0360,02,017,0302,0110,01,02,0,
+ /* 12552 */ 0333,02,017,0302,0110,01,02,0,
+ /* 12560 */ 0360,02,017,0302,0110,01,01,0,
+ /* 12568 */ 0333,02,017,0302,0110,01,01,0,
+ /* 12576 */ 0360,02,017,0302,0110,01,04,0,
+ /* 12584 */ 0333,02,017,0302,0110,01,04,0,
+ /* 12592 */ 0360,02,017,0302,0110,01,06,0,
+ /* 12600 */ 0333,02,017,0302,0110,01,06,0,
+ /* 12608 */ 0360,02,017,0302,0110,01,05,0,
+ /* 12616 */ 0333,02,017,0302,0110,01,05,0,
+ /* 12624 */ 0360,02,017,0302,0110,01,07,0,
+ /* 12632 */ 0333,02,017,0302,0110,01,07,0,
+ /* 12640 */ 0360,02,017,0302,0110,01,03,0,
+ /* 12648 */ 0333,02,017,0302,0110,01,03,0,
+ /* 12656 */ 0360,0323,02,017,0160,0110,022,0,
+ /* 12664 */ 0323,02,017,017,0110,01,034,0,
+ /* 12672 */ 0323,02,017,017,0110,01,0212,0,
+ /* 12680 */ 0323,02,017,017,0110,01,0216,0,
+ /* 12688 */ 0323,02,017,017,0110,01,014,0,
+ /* 12696 */ 0323,02,017,017,0110,01,0273,0,
+ /* 12704 */ 0361,02,017,0302,0110,01,0,0,
+ /* 12712 */ 0332,02,017,0302,0110,01,0,0,
+ /* 12720 */ 0361,02,017,0302,0110,01,02,0,
+ /* 12728 */ 0332,02,017,0302,0110,01,02,0,
+ /* 12736 */ 0361,02,017,0302,0110,01,01,0,
+ /* 12744 */ 0332,02,017,0302,0110,01,01,0,
+ /* 12752 */ 0361,02,017,0302,0110,01,04,0,
+ /* 12760 */ 0332,02,017,0302,0110,01,04,0,
+ /* 12768 */ 0361,02,017,0302,0110,01,06,0,
+ /* 12776 */ 0332,02,017,0302,0110,01,06,0,
+ /* 12784 */ 0361,02,017,0302,0110,01,05,0,
+ /* 12792 */ 0332,02,017,0302,0110,01,05,0,
+ /* 12800 */ 0361,02,017,0302,0110,01,07,0,
+ /* 12808 */ 0332,02,017,0302,0110,01,07,0,
+ /* 12816 */ 0361,02,017,0302,0110,01,03,0,
+ /* 12824 */ 0332,02,017,0302,0110,01,03,0,
+ /* 12832 */ 0323,0361,03,017,070,0200,0110,0,
+ /* 12840 */ 0323,0361,03,017,070,0201,0110,0,
+ /* 12848 */ 0360,03,017,072,017,0110,026,0,
+ /* 12856 */ 0361,03,017,072,017,0110,026,0,
+ /* 12864 */ 0361,02,017,0170,0200,025,026,0,
+ /* 12872 */ 0332,02,017,0170,0110,026,027,0,
+ /* 12880 */ 0361,03,017,072,015,0110,026,0,
+ /* 12888 */ 0361,03,017,072,014,0110,026,0,
+ /* 12896 */ 0361,03,017,072,0101,0110,026,0,
+ /* 12904 */ 0361,03,017,072,0100,0110,026,0,
+ /* 12912 */ 0361,03,017,072,041,0110,026,0,
+ /* 12920 */ 0361,03,017,072,0102,0110,026,0,
+ /* 12928 */ 0361,03,017,072,016,0110,026,0,
+ /* 12936 */ 0361,03,017,072,011,0110,026,0,
+ /* 12944 */ 0361,03,017,072,010,0110,026,0,
+ /* 12952 */ 0361,03,017,072,013,0110,026,0,
+ /* 12960 */ 0361,03,017,072,012,0110,026,0,
+ /* 12968 */ 0320,0332,03,017,070,0361,0110,0,
+ /* 12976 */ 0321,0332,03,017,070,0361,0110,0,
+ /* 12984 */ 0324,0332,03,017,070,0360,0110,0,
+ /* 12992 */ 0324,0332,03,017,070,0361,0110,0,
+ /* 13000 */ 0361,03,017,072,0141,0110,026,0,
+ /* 13008 */ 0361,03,017,072,0140,0110,026,0,
+ /* 13016 */ 0361,03,017,072,0143,0110,026,0,
+ /* 13024 */ 0361,03,017,072,0142,0110,026,0,
+ /* 13032 */ 0323,02,017,017,0110,01,0206,0,
+ /* 13040 */ 0323,02,017,017,0110,01,0207,0,
+ /* 13048 */ 0320,0331,03,017,070,0360,0110,0,
+ /* 13056 */ 0321,0331,03,017,070,0360,0110,0,
+ /* 13064 */ 0324,0331,03,017,070,0360,0110,0,
+ /* 13072 */ 0320,0331,03,017,070,0361,0101,0,
+ /* 13080 */ 0321,0331,03,017,070,0361,0101,0,
+ /* 13088 */ 0324,0331,03,017,070,0361,0101,0,
+ /* 13096 */ 0361,03,017,072,0337,0110,022,0,
+ /* 13104 */ 0270,03,041,01,0337,0110,022,0,
+ /* 13112 */ 0241,0202,041,0301,01,0334,0120,0,
+ /* 13120 */ 0240,0202,041,0301,01,0334,0110,0,
+ /* 13128 */ 0241,0202,045,0301,01,0334,0120,0,
+ /* 13136 */ 0240,0202,045,0301,01,0334,0110,0,
+ /* 13144 */ 0241,0202,041,0301,01,0335,0120,0,
+ /* 13152 */ 0240,0202,041,0301,01,0335,0110,0,
+ /* 13160 */ 0241,0202,045,0301,01,0335,0120,0,
+ /* 13168 */ 0240,0202,045,0301,01,0335,0110,0,
+ /* 13176 */ 0241,0202,041,0301,01,0336,0120,0,
+ /* 13184 */ 0240,0202,041,0301,01,0336,0110,0,
+ /* 13192 */ 0241,0202,045,0301,01,0336,0120,0,
+ /* 13200 */ 0240,0202,045,0301,01,0336,0110,0,
+ /* 13208 */ 0241,0202,041,0301,01,0337,0120,0,
+ /* 13216 */ 0240,0202,041,0301,01,0337,0110,0,
+ /* 13224 */ 0241,0202,045,0301,01,0337,0120,0,
+ /* 13232 */ 0240,0202,045,0301,01,0337,0110,0,
+ /* 13240 */ 0241,0202,051,0301,01,0334,0120,0,
+ /* 13248 */ 0240,0202,051,0301,01,0334,0110,0,
+ /* 13256 */ 0241,0202,051,0301,01,0335,0120,0,
+ /* 13264 */ 0240,0202,051,0301,01,0335,0110,0,
+ /* 13272 */ 0241,0202,051,0301,01,0336,0120,0,
+ /* 13280 */ 0240,0202,051,0301,01,0336,0110,0,
+ /* 13288 */ 0241,0202,051,0301,01,0337,0120,0,
+ /* 13296 */ 0240,0202,051,0301,01,0337,0110,0,
+ /* 13304 */ 0261,03,041,01,015,0120,023,0,
+ /* 13312 */ 0260,03,041,01,015,0110,022,0,
+ /* 13320 */ 0261,03,045,01,015,0120,023,0,
+ /* 13328 */ 0260,03,045,01,015,0110,022,0,
+ /* 13336 */ 0261,03,041,01,014,0120,023,0,
+ /* 13344 */ 0260,03,041,01,014,0110,022,0,
+ /* 13352 */ 0261,03,045,01,014,0120,023,0,
+ /* 13360 */ 0260,03,045,01,014,0110,022,0,
+ /* 13368 */ 0261,03,01,01,0113,0120,0177,0,
+ /* 13376 */ 0260,03,01,01,0113,0110,0176,0,
+ /* 13384 */ 0261,03,05,01,0113,0120,0177,0,
+ /* 13392 */ 0260,03,05,01,0113,0110,0176,0,
+ /* 13400 */ 0261,03,01,01,0112,0120,0177,0,
+ /* 13408 */ 0260,03,01,01,0112,0110,0176,0,
+ /* 13416 */ 0261,03,05,01,0112,0120,0177,0,
+ /* 13424 */ 0260,03,05,01,0112,0110,0176,0,
+ /* 13432 */ 0261,01,041,01,0302,0120,023,0,
+ /* 13440 */ 0260,01,041,01,0302,0110,022,0,
+ /* 13448 */ 0261,01,045,01,0302,0120,023,0,
+ /* 13456 */ 0260,01,045,01,0302,0110,022,0,
+ /* 13464 */ 0261,01,040,01,0302,0120,023,0,
+ /* 13472 */ 0260,01,040,01,0302,0110,022,0,
+ /* 13480 */ 0261,01,044,01,0302,0120,023,0,
+ /* 13488 */ 0260,01,044,01,0302,0110,022,0,
+ /* 13496 */ 0261,01,053,01,0302,0120,023,0,
+ /* 13504 */ 0260,01,053,01,0302,0110,022,0,
+ /* 13512 */ 0261,01,052,01,0302,0120,023,0,
+ /* 13520 */ 0260,01,052,01,0302,0110,022,0,
+ /* 13528 */ 0261,03,041,01,0101,0120,023,0,
+ /* 13536 */ 0260,03,041,01,0101,0110,022,0,
+ /* 13544 */ 0261,03,041,01,0100,0120,023,0,
+ /* 13552 */ 0260,03,041,01,0100,0110,022,0,
+ /* 13560 */ 0261,03,045,01,0100,0120,023,0,
+ /* 13568 */ 0260,03,045,01,0100,0110,022,0,
+ /* 13576 */ 0270,03,05,01,031,0101,022,0,
+ /* 13584 */ 0270,03,041,01,027,0101,022,0,
+ /* 13592 */ 0261,03,05,01,030,0120,023,0,
+ /* 13600 */ 0260,03,05,01,030,0110,022,0,
+ /* 13608 */ 0261,03,041,01,041,0120,023,0,
+ /* 13616 */ 0260,03,041,01,041,0110,022,0,
+ /* 13624 */ 0261,03,041,01,0102,0120,023,0,
+ /* 13632 */ 0260,03,041,01,0102,0110,022,0,
+ /* 13640 */ 0261,03,041,01,017,0120,023,0,
+ /* 13648 */ 0260,03,041,01,017,0110,022,0,
+ /* 13656 */ 0261,03,01,01,0114,0120,0177,0,
+ /* 13664 */ 0260,03,01,01,0114,0110,0176,0,
+ /* 13672 */ 0261,03,041,01,016,0120,023,0,
+ /* 13680 */ 0260,03,041,01,016,0110,022,0,
+ /* 13688 */ 0270,03,041,01,0141,0110,022,0,
+ /* 13696 */ 0270,03,041,01,0140,0110,022,0,
+ /* 13704 */ 0270,03,041,01,0143,0110,022,0,
+ /* 13712 */ 0270,03,041,01,0142,0110,022,0,
+ /* 13720 */ 0270,03,01,01,05,0110,022,0,
+ /* 13728 */ 0270,03,05,01,05,0110,022,0,
+ /* 13736 */ 0270,03,01,01,04,0110,022,0,
+ /* 13744 */ 0270,03,05,01,04,0110,022,0,
+ /* 13752 */ 0261,03,05,01,06,0120,023,0,
+ /* 13760 */ 0260,03,05,01,06,0110,022,0,
+ /* 13768 */ 0270,03,01,01,024,0101,022,0,
+ /* 13776 */ 0270,01,01,01,0305,0110,022,0,
+ /* 13784 */ 0270,03,01,01,025,0101,022,0,
+ /* 13792 */ 0270,03,01,01,026,0101,022,0,
+ /* 13800 */ 0270,03,021,01,026,0101,022,0,
+ /* 13808 */ 0261,03,041,01,040,0120,023,0,
+ /* 13816 */ 0260,03,041,01,040,0110,022,0,
+ /* 13824 */ 0261,01,041,01,0304,0120,023,0,
+ /* 13832 */ 0260,01,041,01,0304,0110,022,0,
+ /* 13840 */ 0261,03,01,01,042,0120,023,0,
+ /* 13848 */ 0260,03,01,01,042,0110,022,0,
+ /* 13856 */ 0261,03,021,01,042,0120,023,0,
+ /* 13864 */ 0260,03,021,01,042,0110,022,0,
+ /* 13872 */ 0270,01,041,01,0160,0110,022,0,
+ /* 13880 */ 0270,01,042,01,0160,0110,022,0,
+ /* 13888 */ 0270,01,043,01,0160,0110,022,0,
+ /* 13896 */ 0260,01,041,01,0163,0217,022,0,
+ /* 13904 */ 0260,01,041,01,0163,0207,021,0,
+ /* 13912 */ 0260,01,041,01,0163,0213,022,0,
+ /* 13920 */ 0260,01,041,01,0163,0203,021,0,
+ /* 13928 */ 0260,01,041,01,0161,0216,022,0,
+ /* 13936 */ 0260,01,041,01,0161,0206,021,0,
+ /* 13944 */ 0260,01,041,01,0162,0216,022,0,
+ /* 13952 */ 0260,01,041,01,0162,0206,021,0,
+ /* 13960 */ 0260,01,041,01,0163,0216,022,0,
+ /* 13968 */ 0260,01,041,01,0163,0206,021,0,
+ /* 13976 */ 0260,01,041,01,0161,0214,022,0,
+ /* 13984 */ 0260,01,041,01,0161,0204,021,0,
+ /* 13992 */ 0260,01,041,01,0162,0214,022,0,
+ /* 14000 */ 0260,01,041,01,0162,0204,021,0,
+ /* 14008 */ 0260,01,041,01,0161,0212,022,0,
+ /* 14016 */ 0260,01,041,01,0161,0202,021,0,
+ /* 14024 */ 0260,01,041,01,0162,0212,022,0,
+ /* 14032 */ 0260,01,041,01,0162,0202,021,0,
+ /* 14040 */ 0260,01,041,01,0163,0212,022,0,
+ /* 14048 */ 0260,01,041,01,0163,0202,021,0,
+ /* 14056 */ 0270,03,041,01,011,0110,022,0,
+ /* 14064 */ 0270,03,045,01,011,0110,022,0,
+ /* 14072 */ 0270,03,041,01,010,0110,022,0,
+ /* 14080 */ 0270,03,045,01,010,0110,022,0,
+ /* 14088 */ 0261,03,041,01,013,0120,023,0,
+ /* 14096 */ 0260,03,041,01,013,0110,022,0,
+ /* 14104 */ 0261,03,041,01,012,0120,023,0,
+ /* 14112 */ 0260,03,041,01,012,0110,022,0,
+ /* 14120 */ 0261,01,041,01,0306,0120,023,0,
+ /* 14128 */ 0260,01,041,01,0306,0110,022,0,
+ /* 14136 */ 0261,01,045,01,0306,0120,023,0,
+ /* 14144 */ 0260,01,045,01,0306,0110,022,0,
+ /* 14152 */ 0261,01,040,01,0306,0120,023,0,
+ /* 14160 */ 0260,01,040,01,0306,0110,022,0,
+ /* 14168 */ 0261,01,044,01,0306,0120,023,0,
+ /* 14176 */ 0260,01,044,01,0306,0110,022,0,
+ /* 14184 */ 0361,03,017,072,0104,0110,022,0,
+ /* 14192 */ 0261,03,041,01,0104,0120,023,0,
+ /* 14200 */ 0260,03,041,01,0104,0110,022,0,
+ /* 14208 */ 0261,03,045,01,0104,0120,023,0,
+ /* 14216 */ 0260,03,045,01,0104,0110,022,0,
+ /* 14224 */ 0270,03,05,01,035,0101,022,0,
+ /* 14232 */ 0270,03,01,01,035,0101,022,0,
+ /* 14240 */ 0317,0361,03,017,070,0366,0110,0,
+ /* 14248 */ 0324,0361,03,017,070,0366,0110,0,
+ /* 14256 */ 0317,0333,03,017,070,0366,0110,0,
+ /* 14264 */ 0324,0333,03,017,070,0366,0110,0,
+ /* 14272 */ 0260,0112,0,01,022,0211,042,0,
+ /* 14280 */ 0260,0112,020,01,022,0211,042,0,
+ /* 14288 */ 0260,0112,0,01,022,0210,042,0,
+ /* 14296 */ 0260,0112,020,01,022,0210,042,0,
+ /* 14304 */ 0261,03,01,01,0151,0120,0177,0,
+ /* 14312 */ 0260,03,01,01,0151,0110,0176,0,
+ /* 14320 */ 0261,03,05,01,0151,0120,0177,0,
+ /* 14328 */ 0260,03,05,01,0151,0110,0176,0,
+ /* 14336 */ 0261,03,021,01,0151,0130,0176,0,
+ /* 14344 */ 0260,03,021,01,0151,0120,0175,0,
+ /* 14352 */ 0261,03,025,01,0151,0130,0176,0,
+ /* 14360 */ 0260,03,025,01,0151,0120,0175,0,
+ /* 14368 */ 0261,03,01,01,0150,0120,0177,0,
+ /* 14376 */ 0260,03,01,01,0150,0110,0176,0,
+ /* 14384 */ 0261,03,05,01,0150,0120,0177,0,
+ /* 14392 */ 0260,03,05,01,0150,0110,0176,0,
+ /* 14400 */ 0261,03,021,01,0150,0130,0176,0,
+ /* 14408 */ 0260,03,021,01,0150,0120,0175,0,
+ /* 14416 */ 0261,03,025,01,0150,0130,0176,0,
+ /* 14424 */ 0260,03,025,01,0150,0120,0175,0,
+ /* 14432 */ 0261,03,01,01,0153,0120,0177,0,
+ /* 14440 */ 0260,03,01,01,0153,0110,0176,0,
+ /* 14448 */ 0261,03,021,01,0153,0130,0176,0,
+ /* 14456 */ 0260,03,021,01,0153,0120,0175,0,
+ /* 14464 */ 0261,03,01,01,0152,0120,0177,0,
+ /* 14472 */ 0260,03,01,01,0152,0110,0176,0,
+ /* 14480 */ 0261,03,021,01,0152,0130,0176,0,
+ /* 14488 */ 0260,03,021,01,0152,0120,0175,0,
+ /* 14496 */ 0261,03,01,01,0135,0120,0177,0,
+ /* 14504 */ 0260,03,01,01,0135,0110,0176,0,
+ /* 14512 */ 0261,03,05,01,0135,0120,0177,0,
+ /* 14520 */ 0260,03,05,01,0135,0110,0176,0,
+ /* 14528 */ 0261,03,021,01,0135,0130,0176,0,
+ /* 14536 */ 0260,03,021,01,0135,0120,0175,0,
+ /* 14544 */ 0261,03,025,01,0135,0130,0176,0,
+ /* 14552 */ 0260,03,025,01,0135,0120,0175,0,
+ /* 14560 */ 0261,03,01,01,0134,0120,0177,0,
+ /* 14568 */ 0260,03,01,01,0134,0110,0176,0,
+ /* 14576 */ 0261,03,05,01,0134,0120,0177,0,
+ /* 14584 */ 0260,03,05,01,0134,0110,0176,0,
+ /* 14592 */ 0261,03,021,01,0134,0130,0176,0,
+ /* 14600 */ 0260,03,021,01,0134,0120,0175,0,
+ /* 14608 */ 0261,03,025,01,0134,0130,0176,0,
+ /* 14616 */ 0260,03,025,01,0134,0120,0175,0,
+ /* 14624 */ 0261,03,01,01,0137,0120,0177,0,
+ /* 14632 */ 0260,03,01,01,0137,0110,0176,0,
+ /* 14640 */ 0261,03,05,01,0137,0120,0177,0,
+ /* 14648 */ 0260,03,05,01,0137,0110,0176,0,
+ /* 14656 */ 0261,03,021,01,0137,0130,0176,0,
+ /* 14664 */ 0260,03,021,01,0137,0120,0175,0,
+ /* 14672 */ 0261,03,025,01,0137,0130,0176,0,
+ /* 14680 */ 0260,03,025,01,0137,0120,0175,0,
+ /* 14688 */ 0261,03,01,01,0136,0120,0177,0,
+ /* 14696 */ 0260,03,01,01,0136,0110,0176,0,
+ /* 14704 */ 0261,03,05,01,0136,0120,0177,0,
+ /* 14712 */ 0260,03,05,01,0136,0110,0176,0,
+ /* 14720 */ 0261,03,021,01,0136,0130,0176,0,
+ /* 14728 */ 0260,03,021,01,0136,0120,0175,0,
+ /* 14736 */ 0261,03,025,01,0136,0130,0176,0,
+ /* 14744 */ 0260,03,025,01,0136,0120,0175,0,
+ /* 14752 */ 0261,03,01,01,0155,0120,0177,0,
+ /* 14760 */ 0260,03,01,01,0155,0110,0176,0,
+ /* 14768 */ 0261,03,05,01,0155,0120,0177,0,
+ /* 14776 */ 0260,03,05,01,0155,0110,0176,0,
+ /* 14784 */ 0261,03,021,01,0155,0130,0176,0,
+ /* 14792 */ 0260,03,021,01,0155,0120,0175,0,
+ /* 14800 */ 0261,03,025,01,0155,0130,0176,0,
+ /* 14808 */ 0260,03,025,01,0155,0120,0175,0,
+ /* 14816 */ 0261,03,01,01,0154,0120,0177,0,
+ /* 14824 */ 0260,03,01,01,0154,0110,0176,0,
+ /* 14832 */ 0261,03,05,01,0154,0120,0177,0,
+ /* 14840 */ 0260,03,05,01,0154,0110,0176,0,
+ /* 14848 */ 0261,03,021,01,0154,0130,0176,0,
+ /* 14856 */ 0260,03,021,01,0154,0120,0175,0,
+ /* 14864 */ 0261,03,025,01,0154,0130,0176,0,
+ /* 14872 */ 0260,03,025,01,0154,0120,0175,0,
+ /* 14880 */ 0261,03,01,01,0157,0120,0177,0,
+ /* 14888 */ 0260,03,01,01,0157,0110,0176,0,
+ /* 14896 */ 0261,03,021,01,0157,0130,0176,0,
+ /* 14904 */ 0260,03,021,01,0157,0120,0175,0,
+ /* 14912 */ 0261,03,01,01,0156,0120,0177,0,
+ /* 14920 */ 0260,03,01,01,0156,0110,0176,0,
+ /* 14928 */ 0261,03,021,01,0156,0130,0176,0,
+ /* 14936 */ 0260,03,021,01,0156,0120,0175,0,
+ /* 14944 */ 0261,03,01,01,0171,0120,0177,0,
+ /* 14952 */ 0260,03,01,01,0171,0110,0176,0,
+ /* 14960 */ 0261,03,05,01,0171,0120,0177,0,
+ /* 14968 */ 0260,03,05,01,0171,0110,0176,0,
+ /* 14976 */ 0261,03,021,01,0171,0130,0176,0,
+ /* 14984 */ 0260,03,021,01,0171,0120,0175,0,
+ /* 14992 */ 0261,03,025,01,0171,0130,0176,0,
+ /* 15000 */ 0260,03,025,01,0171,0120,0175,0,
+ /* 15008 */ 0261,03,01,01,0170,0120,0177,0,
+ /* 15016 */ 0260,03,01,01,0170,0110,0176,0,
+ /* 15024 */ 0261,03,05,01,0170,0120,0177,0,
+ /* 15032 */ 0260,03,05,01,0170,0110,0176,0,
+ /* 15040 */ 0261,03,021,01,0170,0130,0176,0,
+ /* 15048 */ 0260,03,021,01,0170,0120,0175,0,
+ /* 15056 */ 0261,03,025,01,0170,0130,0176,0,
+ /* 15064 */ 0260,03,025,01,0170,0120,0175,0,
+ /* 15072 */ 0261,03,01,01,0173,0120,0177,0,
+ /* 15080 */ 0260,03,01,01,0173,0110,0176,0,
+ /* 15088 */ 0261,03,021,01,0173,0130,0176,0,
+ /* 15096 */ 0260,03,021,01,0173,0120,0175,0,
+ /* 15104 */ 0261,03,01,01,0172,0120,0177,0,
+ /* 15112 */ 0260,03,01,01,0172,0110,0176,0,
+ /* 15120 */ 0261,03,021,01,0172,0130,0176,0,
+ /* 15128 */ 0260,03,021,01,0172,0120,0175,0,
+ /* 15136 */ 0261,03,01,01,0175,0120,0177,0,
+ /* 15144 */ 0260,03,01,01,0175,0110,0176,0,
+ /* 15152 */ 0261,03,05,01,0175,0120,0177,0,
+ /* 15160 */ 0260,03,05,01,0175,0110,0176,0,
+ /* 15168 */ 0261,03,021,01,0175,0130,0176,0,
+ /* 15176 */ 0260,03,021,01,0175,0120,0175,0,
+ /* 15184 */ 0261,03,025,01,0175,0130,0176,0,
+ /* 15192 */ 0260,03,025,01,0175,0120,0175,0,
+ /* 15200 */ 0261,03,01,01,0174,0120,0177,0,
+ /* 15208 */ 0260,03,01,01,0174,0110,0176,0,
+ /* 15216 */ 0261,03,05,01,0174,0120,0177,0,
+ /* 15224 */ 0260,03,05,01,0174,0110,0176,0,
+ /* 15232 */ 0261,03,021,01,0174,0130,0176,0,
+ /* 15240 */ 0260,03,021,01,0174,0120,0175,0,
+ /* 15248 */ 0261,03,025,01,0174,0130,0176,0,
+ /* 15256 */ 0260,03,025,01,0174,0120,0175,0,
+ /* 15264 */ 0261,03,01,01,0177,0120,0177,0,
+ /* 15272 */ 0260,03,01,01,0177,0110,0176,0,
+ /* 15280 */ 0261,03,021,01,0177,0130,0176,0,
+ /* 15288 */ 0260,03,021,01,0177,0120,0175,0,
+ /* 15296 */ 0261,03,01,01,0176,0120,0177,0,
+ /* 15304 */ 0260,03,01,01,0176,0110,0176,0,
+ /* 15312 */ 0261,03,021,01,0176,0130,0176,0,
+ /* 15320 */ 0260,03,021,01,0176,0120,0175,0,
+ /* 15328 */ 0261,0110,0,01,0242,0120,0177,0,
+ /* 15336 */ 0260,0110,0,01,0242,0110,0176,0,
+ /* 15344 */ 0261,0110,04,01,0242,0120,0177,0,
+ /* 15352 */ 0260,0110,04,01,0242,0110,0176,0,
+ /* 15360 */ 0261,0110,020,01,0242,0130,0176,0,
+ /* 15368 */ 0260,0110,020,01,0242,0120,0175,0,
+ /* 15376 */ 0261,0110,024,01,0242,0130,0176,0,
+ /* 15384 */ 0260,0110,024,01,0242,0120,0175,0,
+ /* 15392 */ 0261,0110,0,01,0314,0120,023,0,
+ /* 15400 */ 0260,0110,0,01,0314,0110,022,0,
+ /* 15408 */ 0261,0110,0,01,0316,0120,023,0,
+ /* 15416 */ 0260,0110,0,01,0316,0110,022,0,
+ /* 15424 */ 0261,0110,0,01,0317,0120,023,0,
+ /* 15432 */ 0260,0110,0,01,0317,0110,022,0,
+ /* 15440 */ 0261,0110,0,01,0354,0120,023,0,
+ /* 15448 */ 0260,0110,0,01,0354,0110,022,0,
+ /* 15456 */ 0261,0110,0,01,0356,0120,023,0,
+ /* 15464 */ 0260,0110,0,01,0356,0110,022,0,
+ /* 15472 */ 0261,0110,0,01,0357,0120,023,0,
+ /* 15480 */ 0260,0110,0,01,0357,0110,022,0,
+ /* 15488 */ 0261,0110,0,01,0355,0120,023,0,
+ /* 15496 */ 0260,0110,0,01,0355,0110,022,0,
+ /* 15504 */ 0261,0110,0,01,0315,0120,023,0,
+ /* 15512 */ 0260,0110,0,01,0315,0110,022,0,
+ /* 15520 */ 0261,0110,0,01,0236,0120,0177,0,
+ /* 15528 */ 0260,0110,0,01,0236,0110,0176,0,
+ /* 15536 */ 0261,0110,0,01,0237,0120,0177,0,
+ /* 15544 */ 0260,0110,0,01,0237,0110,0176,0,
+ /* 15552 */ 0261,0110,0,01,0227,0120,0177,0,
+ /* 15560 */ 0260,0110,0,01,0227,0110,0176,0,
+ /* 15568 */ 0261,0110,0,01,0216,0120,0177,0,
+ /* 15576 */ 0260,0110,0,01,0216,0110,0176,0,
+ /* 15584 */ 0261,0110,0,01,0217,0120,0177,0,
+ /* 15592 */ 0260,0110,0,01,0217,0110,0176,0,
+ /* 15600 */ 0261,0110,0,01,0207,0120,0177,0,
+ /* 15608 */ 0260,0110,0,01,0207,0110,0176,0,
+ /* 15616 */ 0261,0110,0,01,0206,0120,0177,0,
+ /* 15624 */ 0260,0110,0,01,0206,0110,0176,0,
+ /* 15632 */ 0261,0110,0,01,0205,0120,0177,0,
+ /* 15640 */ 0260,0110,0,01,0205,0110,0176,0,
+ /* 15648 */ 0261,0110,0,01,0226,0120,0177,0,
+ /* 15656 */ 0260,0110,0,01,0226,0110,0176,0,
+ /* 15664 */ 0261,0110,0,01,0225,0120,0177,0,
+ /* 15672 */ 0260,0110,0,01,0225,0110,0176,0,
+ /* 15680 */ 0261,0110,0,01,0246,0120,0177,0,
+ /* 15688 */ 0260,0110,0,01,0246,0110,0176,0,
+ /* 15696 */ 0261,0110,0,01,0266,0120,0177,0,
+ /* 15704 */ 0260,0110,0,01,0266,0110,0176,0,
+ /* 15712 */ 0261,0110,020,01,0243,0130,0176,0,
+ /* 15720 */ 0260,0110,020,01,0243,0120,0175,0,
+ /* 15728 */ 0261,0110,0,01,0243,0120,0177,0,
+ /* 15736 */ 0260,0110,0,01,0243,0110,0176,0,
+ /* 15744 */ 0270,0110,0,01,0300,0110,022,0,
+ /* 15752 */ 0270,0110,0,01,0300,0100,021,0,
+ /* 15760 */ 0270,0110,0,01,0302,0110,022,0,
+ /* 15768 */ 0270,0110,0,01,0302,0100,021,0,
+ /* 15776 */ 0270,0110,0,01,0303,0110,022,0,
+ /* 15784 */ 0270,0110,0,01,0303,0100,021,0,
+ /* 15792 */ 0270,0110,0,01,0301,0110,022,0,
+ /* 15800 */ 0270,0110,0,01,0301,0100,021,0,
+ /* 15808 */ 0261,03,045,01,0102,0120,023,0,
+ /* 15816 */ 0260,03,045,01,0102,0110,022,0,
+ /* 15824 */ 0261,03,045,01,017,0120,023,0,
+ /* 15832 */ 0260,03,045,01,017,0110,022,0,
+ /* 15840 */ 0261,03,045,01,0114,0120,0177,0,
+ /* 15848 */ 0260,03,045,01,0114,0110,0176,0,
+ /* 15856 */ 0261,03,045,01,016,0120,023,0,
+ /* 15864 */ 0260,03,045,01,016,0110,022,0,
+ /* 15872 */ 0270,01,045,01,0160,0110,022,0,
+ /* 15880 */ 0270,01,046,01,0160,0110,022,0,
+ /* 15888 */ 0270,01,047,01,0160,0110,022,0,
+ /* 15896 */ 0260,01,045,01,0163,0217,022,0,
+ /* 15904 */ 0260,01,045,01,0163,0207,021,0,
+ /* 15912 */ 0260,01,045,01,0161,0216,022,0,
+ /* 15920 */ 0260,01,045,01,0161,0206,021,0,
+ /* 15928 */ 0260,01,045,01,0162,0216,022,0,
+ /* 15936 */ 0260,01,045,01,0162,0206,021,0,
+ /* 15944 */ 0260,01,045,01,0163,0216,022,0,
+ /* 15952 */ 0260,01,045,01,0163,0206,021,0,
+ /* 15960 */ 0260,01,045,01,0161,0214,022,0,
+ /* 15968 */ 0260,01,045,01,0161,0204,021,0,
+ /* 15976 */ 0260,01,045,01,0162,0214,022,0,
+ /* 15984 */ 0260,01,045,01,0162,0204,021,0,
+ /* 15992 */ 0260,01,045,01,0163,0213,022,0,
+ /* 16000 */ 0260,01,045,01,0163,0203,021,0,
+ /* 16008 */ 0260,01,045,01,0161,0212,022,0,
+ /* 16016 */ 0260,01,045,01,0161,0202,021,0,
+ /* 16024 */ 0260,01,045,01,0162,0212,022,0,
+ /* 16032 */ 0260,01,045,01,0162,0202,021,0,
+ /* 16040 */ 0260,01,045,01,0163,0212,022,0,
+ /* 16048 */ 0260,01,045,01,0163,0202,021,0,
+ /* 16056 */ 0261,03,01,01,02,0120,023,0,
+ /* 16064 */ 0260,03,01,01,02,0110,022,0,
+ /* 16072 */ 0261,03,05,01,02,0120,023,0,
+ /* 16080 */ 0260,03,05,01,02,0110,022,0,
+ /* 16088 */ 0270,03,025,01,01,0110,022,0,
+ /* 16096 */ 0270,03,025,01,0,0110,022,0,
+ /* 16104 */ 0261,03,05,01,0106,0120,023,0,
+ /* 16112 */ 0260,03,05,01,0106,0110,022,0,
+ /* 16120 */ 0270,03,05,01,071,0101,022,0,
+ /* 16128 */ 0261,03,05,01,070,0120,023,0,
+ /* 16136 */ 0260,03,05,01,070,0110,022,0,
+ /* 16144 */ 0374,0262,02,021,01,0222,0110,0,
+ /* 16152 */ 0374,0262,02,021,01,0223,0110,0,
+ /* 16160 */ 0374,0262,02,025,01,0222,0110,0,
+ /* 16168 */ 0375,0262,02,025,01,0223,0110,0,
+ /* 16176 */ 0374,0262,02,01,01,0222,0110,0,
+ /* 16184 */ 0374,0262,02,01,01,0223,0110,0,
+ /* 16192 */ 0375,0262,02,05,01,0222,0110,0,
+ /* 16200 */ 0375,0262,02,05,01,0223,0110,0,
+ /* 16208 */ 0374,0262,02,01,01,0220,0110,0,
+ /* 16216 */ 0374,0262,02,01,01,0221,0110,0,
+ /* 16224 */ 0375,0262,02,05,01,0220,0110,0,
+ /* 16232 */ 0375,0262,02,05,01,0221,0110,0,
+ /* 16240 */ 0374,0262,02,021,01,0220,0110,0,
+ /* 16248 */ 0374,0262,02,021,01,0221,0110,0,
+ /* 16256 */ 0374,0262,02,025,01,0220,0110,0,
+ /* 16264 */ 0375,0262,02,025,01,0221,0110,0,
+ /* 16272 */ 0270,0112,0,01,020,0110,042,0,
+ /* 16280 */ 0270,0112,020,01,020,0110,042,0,
+ /* 16288 */ 0270,03,03,01,0360,0110,022,0,
+ /* 16296 */ 0270,03,023,01,0360,0110,022,0,
+ /* 16304 */ 0270,01,01,01,0222,0325,0110,0,
+ /* 16312 */ 0270,03,01,01,062,0110,022,0,
+ /* 16320 */ 0270,03,01,01,063,0110,022,0,
+ /* 16328 */ 0270,03,021,01,063,0110,022,0,
+ /* 16336 */ 0270,03,021,01,062,0110,022,0,
+ /* 16344 */ 0270,03,01,01,060,0110,022,0,
+ /* 16352 */ 0270,03,01,01,061,0110,022,0,
+ /* 16360 */ 0270,03,021,01,061,0110,022,0,
+ /* 16368 */ 0270,03,021,01,060,0110,022,0,
+ /* 16376 */ 0241,0201,021,0301,01,0130,0120,0,
+ /* 16384 */ 0240,0201,021,0301,01,0130,0110,0,
+ /* 16392 */ 0241,0201,025,0301,01,0130,0120,0,
+ /* 16400 */ 0240,0201,025,0301,01,0130,0110,0,
+ /* 16408 */ 0241,0201,031,0301,01,0130,0120,0,
+ /* 16416 */ 0240,0201,031,0301,01,0130,0110,0,
+ /* 16424 */ 0241,0201,0,0301,01,0130,0120,0,
+ /* 16432 */ 0240,0201,0,0301,01,0130,0110,0,
+ /* 16440 */ 0241,0201,04,0301,01,0130,0120,0,
+ /* 16448 */ 0240,0201,04,0301,01,0130,0110,0,
+ /* 16456 */ 0241,0201,010,0301,01,0130,0120,0,
+ /* 16464 */ 0240,0201,010,0301,01,0130,0110,0,
+ /* 16472 */ 0241,0201,023,0306,01,0130,0120,0,
+ /* 16480 */ 0240,0201,023,0306,01,0130,0110,0,
+ /* 16488 */ 0241,0201,02,0306,01,0130,0120,0,
+ /* 16496 */ 0240,0201,02,0306,01,0130,0110,0,
+ /* 16504 */ 0241,0201,021,0301,01,0125,0120,0,
+ /* 16512 */ 0240,0201,021,0301,01,0125,0110,0,
+ /* 16520 */ 0241,0201,025,0301,01,0125,0120,0,
+ /* 16528 */ 0240,0201,025,0301,01,0125,0110,0,
+ /* 16536 */ 0241,0201,031,0301,01,0125,0120,0,
+ /* 16544 */ 0240,0201,031,0301,01,0125,0110,0,
+ /* 16552 */ 0241,0201,0,0301,01,0125,0120,0,
+ /* 16560 */ 0240,0201,0,0301,01,0125,0110,0,
+ /* 16568 */ 0241,0201,04,0301,01,0125,0120,0,
+ /* 16576 */ 0240,0201,04,0301,01,0125,0110,0,
+ /* 16584 */ 0241,0201,010,0301,01,0125,0120,0,
+ /* 16592 */ 0240,0201,010,0301,01,0125,0110,0,
+ /* 16600 */ 0241,0201,021,0301,01,0124,0120,0,
+ /* 16608 */ 0240,0201,021,0301,01,0124,0110,0,
+ /* 16616 */ 0241,0201,025,0301,01,0124,0120,0,
+ /* 16624 */ 0240,0201,025,0301,01,0124,0110,0,
+ /* 16632 */ 0241,0201,031,0301,01,0124,0120,0,
+ /* 16640 */ 0240,0201,031,0301,01,0124,0110,0,
+ /* 16648 */ 0241,0201,0,0301,01,0124,0120,0,
+ /* 16656 */ 0240,0201,0,0301,01,0124,0110,0,
+ /* 16664 */ 0241,0201,04,0301,01,0124,0120,0,
+ /* 16672 */ 0240,0201,04,0301,01,0124,0110,0,
+ /* 16680 */ 0241,0201,010,0301,01,0124,0120,0,
+ /* 16688 */ 0240,0201,010,0301,01,0124,0110,0,
+ /* 16696 */ 0241,0202,021,0301,01,0145,0120,0,
+ /* 16704 */ 0241,0202,025,0301,01,0145,0120,0,
+ /* 16712 */ 0241,0202,031,0301,01,0145,0120,0,
+ /* 16720 */ 0241,0202,01,0301,01,0145,0120,0,
+ /* 16728 */ 0241,0202,05,0301,01,0145,0120,0,
+ /* 16736 */ 0241,0202,011,0301,01,0145,0120,0,
+ /* 16744 */ 0250,0202,05,0311,01,031,0110,0,
+ /* 16752 */ 0250,0202,011,0311,01,031,0110,0,
+ /* 16760 */ 0250,0202,05,0312,01,032,0110,0,
+ /* 16768 */ 0250,0202,011,0312,01,032,0110,0,
+ /* 16776 */ 0250,0202,011,0313,01,033,0110,0,
+ /* 16784 */ 0250,0202,025,0311,01,032,0110,0,
+ /* 16792 */ 0250,0202,031,0311,01,032,0110,0,
+ /* 16800 */ 0250,0202,031,0312,01,033,0110,0,
+ /* 16808 */ 0250,0202,01,0311,01,0131,0110,0,
+ /* 16816 */ 0250,0202,05,0311,01,0131,0110,0,
+ /* 16824 */ 0250,0202,011,0311,01,0131,0110,0,
+ /* 16832 */ 0250,0202,05,0312,01,0132,0110,0,
+ /* 16840 */ 0250,0202,011,0312,01,0132,0110,0,
+ /* 16848 */ 0250,0202,011,0313,01,0133,0110,0,
+ /* 16856 */ 0250,0202,025,0311,01,0132,0110,0,
+ /* 16864 */ 0250,0202,031,0311,01,0132,0110,0,
+ /* 16872 */ 0250,0202,031,0312,01,0133,0110,0,
+ /* 16880 */ 0250,0202,025,0306,01,031,0110,0,
+ /* 16888 */ 0250,0202,031,0306,01,031,0110,0,
+ /* 16896 */ 0250,0202,025,0300,01,031,0110,0,
+ /* 16904 */ 0250,0202,031,0300,01,031,0110,0,
+ /* 16912 */ 0250,0202,01,0306,01,030,0110,0,
+ /* 16920 */ 0250,0202,05,0306,01,030,0110,0,
+ /* 16928 */ 0250,0202,011,0306,01,030,0110,0,
+ /* 16936 */ 0250,0202,01,0300,01,030,0110,0,
+ /* 16944 */ 0250,0202,05,0300,01,030,0110,0,
+ /* 16952 */ 0250,0202,011,0300,01,030,0110,0,
+ /* 16960 */ 0250,0201,021,0306,01,057,0110,0,
+ /* 16968 */ 0250,0201,0,0306,01,057,0110,0,
+ /* 16976 */ 0250,0202,021,0306,01,0212,0101,0,
+ /* 16984 */ 0250,0202,025,0306,01,0212,0101,0,
+ /* 16992 */ 0250,0202,031,0306,01,0212,0101,0,
+ /* 17000 */ 0250,0202,021,0300,01,0212,0101,0,
+ /* 17008 */ 0250,0202,025,0300,01,0212,0101,0,
+ /* 17016 */ 0250,0202,031,0300,01,0212,0101,0,
+ /* 17024 */ 0250,0202,01,0306,01,0212,0101,0,
+ /* 17032 */ 0250,0202,05,0306,01,0212,0101,0,
+ /* 17040 */ 0250,0202,011,0306,01,0212,0101,0,
+ /* 17048 */ 0250,0202,01,0300,01,0212,0101,0,
+ /* 17056 */ 0250,0202,05,0300,01,0212,0101,0,
+ /* 17064 */ 0250,0202,011,0300,01,0212,0101,0,
+ /* 17072 */ 0250,0201,02,0302,01,0346,0110,0,
+ /* 17080 */ 0250,0201,06,0302,01,0346,0110,0,
+ /* 17088 */ 0250,0201,012,0302,01,0346,0110,0,
+ /* 17096 */ 0250,0201,0,0301,01,0133,0110,0,
+ /* 17104 */ 0250,0201,04,0301,01,0133,0110,0,
+ /* 17112 */ 0250,0201,010,0301,01,0133,0110,0,
+ /* 17120 */ 0250,0201,023,0301,01,0346,0110,0,
+ /* 17128 */ 0250,0201,027,0301,01,0346,0110,0,
+ /* 17136 */ 0250,0201,033,0301,01,0346,0110,0,
+ /* 17144 */ 0250,0201,021,0301,01,0132,0110,0,
+ /* 17152 */ 0250,0201,025,0301,01,0132,0110,0,
+ /* 17160 */ 0250,0201,031,0301,01,0132,0110,0,
+ /* 17168 */ 0250,0201,021,0301,01,0173,0110,0,
+ /* 17176 */ 0250,0201,025,0301,01,0173,0110,0,
+ /* 17184 */ 0250,0201,031,0301,01,0173,0110,0,
+ /* 17192 */ 0250,0201,020,0301,01,0171,0110,0,
+ /* 17200 */ 0250,0201,024,0301,01,0171,0110,0,
+ /* 17208 */ 0250,0201,030,0301,01,0171,0110,0,
+ /* 17216 */ 0250,0201,021,0301,01,0171,0110,0,
+ /* 17224 */ 0250,0201,025,0301,01,0171,0110,0,
+ /* 17232 */ 0250,0201,031,0301,01,0171,0110,0,
+ /* 17240 */ 0250,0202,01,0314,01,023,0110,0,
+ /* 17248 */ 0250,0202,05,0314,01,023,0110,0,
+ /* 17256 */ 0250,0202,011,0314,01,023,0110,0,
+ /* 17264 */ 0250,0201,01,0301,01,0133,0110,0,
+ /* 17272 */ 0250,0201,05,0301,01,0133,0110,0,
+ /* 17280 */ 0250,0201,011,0301,01,0133,0110,0,
+ /* 17288 */ 0250,0201,0,0302,01,0132,0110,0,
+ /* 17296 */ 0250,0201,04,0302,01,0132,0110,0,
+ /* 17304 */ 0250,0201,010,0302,01,0132,0110,0,
+ /* 17312 */ 0250,0201,01,0302,01,0173,0110,0,
+ /* 17320 */ 0250,0201,05,0302,01,0173,0110,0,
+ /* 17328 */ 0250,0201,011,0302,01,0173,0110,0,
+ /* 17336 */ 0250,0201,0,0301,01,0171,0110,0,
+ /* 17344 */ 0250,0201,04,0301,01,0171,0110,0,
+ /* 17352 */ 0250,0201,010,0301,01,0171,0110,0,
+ /* 17360 */ 0250,0201,01,0302,01,0171,0110,0,
+ /* 17368 */ 0250,0201,05,0302,01,0171,0110,0,
+ /* 17376 */ 0250,0201,011,0302,01,0171,0110,0,
+ /* 17384 */ 0250,0201,022,0301,01,0346,0110,0,
+ /* 17392 */ 0250,0201,026,0301,01,0346,0110,0,
+ /* 17400 */ 0250,0201,032,0301,01,0346,0110,0,
+ /* 17408 */ 0250,0201,020,0301,01,0133,0110,0,
+ /* 17416 */ 0250,0201,024,0301,01,0133,0110,0,
+ /* 17424 */ 0250,0201,030,0301,01,0133,0110,0,
+ /* 17432 */ 0250,0201,03,0310,01,055,0110,0,
+ /* 17440 */ 0250,0201,023,0310,01,055,0110,0,
+ /* 17448 */ 0241,0201,023,0306,01,0132,0120,0,
+ /* 17456 */ 0250,0201,03,0310,01,0171,0110,0,
+ /* 17464 */ 0250,0201,023,0310,01,0171,0110,0,
+ /* 17472 */ 0241,0201,03,0306,01,052,0120,0,
+ /* 17480 */ 0241,0201,023,0306,01,052,0120,0,
+ /* 17488 */ 0241,0201,02,0306,01,052,0120,0,
+ /* 17496 */ 0241,0201,022,0306,01,052,0120,0,
+ /* 17504 */ 0241,0201,02,0306,01,0132,0120,0,
+ /* 17512 */ 0250,0201,02,0307,01,055,0110,0,
+ /* 17520 */ 0250,0201,022,0307,01,055,0110,0,
+ /* 17528 */ 0250,0201,02,0307,01,0171,0110,0,
+ /* 17536 */ 0250,0201,022,0307,01,0171,0110,0,
+ /* 17544 */ 0250,0201,021,0301,01,0346,0110,0,
+ /* 17552 */ 0250,0201,025,0301,01,0346,0110,0,
+ /* 17560 */ 0250,0201,031,0301,01,0346,0110,0,
+ /* 17568 */ 0250,0201,021,0301,01,0172,0110,0,
+ /* 17576 */ 0250,0201,025,0301,01,0172,0110,0,
+ /* 17584 */ 0250,0201,031,0301,01,0172,0110,0,
+ /* 17592 */ 0250,0201,020,0301,01,0170,0110,0,
+ /* 17600 */ 0250,0201,024,0301,01,0170,0110,0,
+ /* 17608 */ 0250,0201,030,0301,01,0170,0110,0,
+ /* 17616 */ 0250,0201,021,0301,01,0170,0110,0,
+ /* 17624 */ 0250,0201,025,0301,01,0170,0110,0,
+ /* 17632 */ 0250,0201,031,0301,01,0170,0110,0,
+ /* 17640 */ 0250,0201,02,0301,01,0133,0110,0,
+ /* 17648 */ 0250,0201,06,0301,01,0133,0110,0,
+ /* 17656 */ 0250,0201,012,0301,01,0133,0110,0,
+ /* 17664 */ 0250,0201,01,0302,01,0172,0110,0,
+ /* 17672 */ 0250,0201,05,0302,01,0172,0110,0,
+ /* 17680 */ 0250,0201,011,0302,01,0172,0110,0,
+ /* 17688 */ 0250,0201,0,0301,01,0170,0110,0,
+ /* 17696 */ 0250,0201,04,0301,01,0170,0110,0,
+ /* 17704 */ 0250,0201,010,0301,01,0170,0110,0,
+ /* 17712 */ 0250,0201,01,0302,01,0170,0110,0,
+ /* 17720 */ 0250,0201,05,0302,01,0170,0110,0,
+ /* 17728 */ 0250,0201,011,0302,01,0170,0110,0,
+ /* 17736 */ 0250,0201,03,0310,01,054,0110,0,
+ /* 17744 */ 0250,0201,023,0310,01,054,0110,0,
+ /* 17752 */ 0250,0201,03,0310,01,0170,0110,0,
+ /* 17760 */ 0250,0201,023,0310,01,0170,0110,0,
+ /* 17768 */ 0250,0201,02,0307,01,054,0110,0,
+ /* 17776 */ 0250,0201,022,0307,01,054,0110,0,
+ /* 17784 */ 0250,0201,02,0307,01,0170,0110,0,
+ /* 17792 */ 0250,0201,022,0307,01,0170,0110,0,
+ /* 17800 */ 0250,0201,02,0302,01,0172,0110,0,
+ /* 17808 */ 0250,0201,06,0302,01,0172,0110,0,
+ /* 17816 */ 0250,0201,012,0302,01,0172,0110,0,
+ /* 17824 */ 0250,0201,03,0301,01,0172,0110,0,
+ /* 17832 */ 0250,0201,07,0301,01,0172,0110,0,
+ /* 17840 */ 0250,0201,013,0301,01,0172,0110,0,
+ /* 17848 */ 0250,0201,022,0301,01,0172,0110,0,
+ /* 17856 */ 0250,0201,026,0301,01,0172,0110,0,
+ /* 17864 */ 0250,0201,032,0301,01,0172,0110,0,
+ /* 17872 */ 0250,0201,023,0301,01,0172,0110,0,
+ /* 17880 */ 0250,0201,027,0301,01,0172,0110,0,
+ /* 17888 */ 0250,0201,033,0301,01,0172,0110,0,
+ /* 17896 */ 0241,0201,03,0306,01,0173,0120,0,
+ /* 17904 */ 0241,0201,023,0306,01,0173,0120,0,
+ /* 17912 */ 0241,0201,02,0306,01,0173,0120,0,
+ /* 17920 */ 0241,0201,022,0306,01,0173,0120,0,
+ /* 17928 */ 0241,0201,021,0301,01,0136,0120,0,
+ /* 17936 */ 0240,0201,021,0301,01,0136,0110,0,
+ /* 17944 */ 0241,0201,025,0301,01,0136,0120,0,
+ /* 17952 */ 0240,0201,025,0301,01,0136,0110,0,
+ /* 17960 */ 0241,0201,031,0301,01,0136,0120,0,
+ /* 17968 */ 0240,0201,031,0301,01,0136,0110,0,
+ /* 17976 */ 0241,0201,0,0301,01,0136,0120,0,
+ /* 17984 */ 0240,0201,0,0301,01,0136,0110,0,
+ /* 17992 */ 0241,0201,04,0301,01,0136,0120,0,
+ /* 18000 */ 0240,0201,04,0301,01,0136,0110,0,
+ /* 18008 */ 0241,0201,010,0301,01,0136,0120,0,
+ /* 18016 */ 0240,0201,010,0301,01,0136,0110,0,
+ /* 18024 */ 0241,0201,023,0306,01,0136,0120,0,
+ /* 18032 */ 0240,0201,023,0306,01,0136,0110,0,
+ /* 18040 */ 0241,0201,02,0306,01,0136,0120,0,
+ /* 18048 */ 0240,0201,02,0306,01,0136,0110,0,
+ /* 18056 */ 0250,0202,031,0301,01,0310,0110,0,
+ /* 18064 */ 0250,0202,011,0301,01,0310,0110,0,
+ /* 18072 */ 0250,0202,021,0306,01,0210,0110,0,
+ /* 18080 */ 0250,0202,025,0306,01,0210,0110,0,
+ /* 18088 */ 0250,0202,031,0306,01,0210,0110,0,
+ /* 18096 */ 0250,0202,01,0306,01,0210,0110,0,
+ /* 18104 */ 0250,0202,05,0306,01,0210,0110,0,
+ /* 18112 */ 0250,0202,011,0306,01,0210,0110,0,
+ /* 18120 */ 0241,0202,021,0301,01,0230,0120,0,
+ /* 18128 */ 0241,0202,025,0301,01,0230,0120,0,
+ /* 18136 */ 0241,0202,031,0301,01,0230,0120,0,
+ /* 18144 */ 0241,0202,01,0301,01,0230,0120,0,
+ /* 18152 */ 0241,0202,05,0301,01,0230,0120,0,
+ /* 18160 */ 0241,0202,011,0301,01,0230,0120,0,
+ /* 18168 */ 0241,0202,021,0306,01,0231,0120,0,
+ /* 18176 */ 0241,0202,01,0306,01,0231,0120,0,
+ /* 18184 */ 0241,0202,021,0301,01,0250,0120,0,
+ /* 18192 */ 0241,0202,025,0301,01,0250,0120,0,
+ /* 18200 */ 0241,0202,031,0301,01,0250,0120,0,
+ /* 18208 */ 0241,0202,01,0301,01,0250,0120,0,
+ /* 18216 */ 0241,0202,05,0301,01,0250,0120,0,
+ /* 18224 */ 0241,0202,011,0301,01,0250,0120,0,
+ /* 18232 */ 0241,0202,021,0306,01,0251,0120,0,
+ /* 18240 */ 0241,0202,01,0306,01,0251,0120,0,
+ /* 18248 */ 0241,0202,021,0301,01,0270,0120,0,
+ /* 18256 */ 0241,0202,025,0301,01,0270,0120,0,
+ /* 18264 */ 0241,0202,031,0301,01,0270,0120,0,
+ /* 18272 */ 0241,0202,01,0301,01,0270,0120,0,
+ /* 18280 */ 0241,0202,05,0301,01,0270,0120,0,
+ /* 18288 */ 0241,0202,011,0301,01,0270,0120,0,
+ /* 18296 */ 0241,0202,021,0306,01,0271,0120,0,
+ /* 18304 */ 0241,0202,01,0306,01,0271,0120,0,
+ /* 18312 */ 0241,0202,021,0301,01,0226,0120,0,
+ /* 18320 */ 0241,0202,025,0301,01,0226,0120,0,
+ /* 18328 */ 0241,0202,031,0301,01,0226,0120,0,
+ /* 18336 */ 0241,0202,01,0301,01,0226,0120,0,
+ /* 18344 */ 0241,0202,05,0301,01,0226,0120,0,
+ /* 18352 */ 0241,0202,011,0301,01,0226,0120,0,
+ /* 18360 */ 0241,0202,021,0301,01,0246,0120,0,
+ /* 18368 */ 0241,0202,025,0301,01,0246,0120,0,
+ /* 18376 */ 0241,0202,031,0301,01,0246,0120,0,
+ /* 18384 */ 0241,0202,01,0301,01,0246,0120,0,
+ /* 18392 */ 0241,0202,05,0301,01,0246,0120,0,
+ /* 18400 */ 0241,0202,011,0301,01,0246,0120,0,
+ /* 18408 */ 0241,0202,021,0301,01,0266,0120,0,
+ /* 18416 */ 0241,0202,025,0301,01,0266,0120,0,
+ /* 18424 */ 0241,0202,031,0301,01,0266,0120,0,
+ /* 18432 */ 0241,0202,01,0301,01,0266,0120,0,
+ /* 18440 */ 0241,0202,05,0301,01,0266,0120,0,
+ /* 18448 */ 0241,0202,011,0301,01,0266,0120,0,
+ /* 18456 */ 0241,0202,021,0301,01,0232,0120,0,
+ /* 18464 */ 0241,0202,025,0301,01,0232,0120,0,
+ /* 18472 */ 0241,0202,031,0301,01,0232,0120,0,
+ /* 18480 */ 0241,0202,01,0301,01,0232,0120,0,
+ /* 18488 */ 0241,0202,05,0301,01,0232,0120,0,
+ /* 18496 */ 0241,0202,011,0301,01,0232,0120,0,
+ /* 18504 */ 0241,0202,021,0306,01,0233,0120,0,
+ /* 18512 */ 0241,0202,01,0306,01,0233,0120,0,
+ /* 18520 */ 0241,0202,021,0301,01,0252,0120,0,
+ /* 18528 */ 0241,0202,025,0301,01,0252,0120,0,
+ /* 18536 */ 0241,0202,031,0301,01,0252,0120,0,
+ /* 18544 */ 0241,0202,01,0301,01,0252,0120,0,
+ /* 18552 */ 0241,0202,05,0301,01,0252,0120,0,
+ /* 18560 */ 0241,0202,011,0301,01,0252,0120,0,
+ /* 18568 */ 0241,0202,021,0306,01,0253,0120,0,
+ /* 18576 */ 0241,0202,01,0306,01,0253,0120,0,
+ /* 18584 */ 0241,0202,021,0301,01,0272,0120,0,
+ /* 18592 */ 0241,0202,025,0301,01,0272,0120,0,
+ /* 18600 */ 0241,0202,031,0301,01,0272,0120,0,
+ /* 18608 */ 0241,0202,01,0301,01,0272,0120,0,
+ /* 18616 */ 0241,0202,05,0301,01,0272,0120,0,
+ /* 18624 */ 0241,0202,011,0301,01,0272,0120,0,
+ /* 18632 */ 0241,0202,021,0306,01,0273,0120,0,
+ /* 18640 */ 0241,0202,01,0306,01,0273,0120,0,
+ /* 18648 */ 0241,0202,021,0301,01,0227,0120,0,
+ /* 18656 */ 0241,0202,025,0301,01,0227,0120,0,
+ /* 18664 */ 0241,0202,031,0301,01,0227,0120,0,
+ /* 18672 */ 0241,0202,01,0301,01,0227,0120,0,
+ /* 18680 */ 0241,0202,05,0301,01,0227,0120,0,
+ /* 18688 */ 0241,0202,011,0301,01,0227,0120,0,
+ /* 18696 */ 0241,0202,021,0301,01,0247,0120,0,
+ /* 18704 */ 0241,0202,025,0301,01,0247,0120,0,
+ /* 18712 */ 0241,0202,031,0301,01,0247,0120,0,
+ /* 18720 */ 0241,0202,01,0301,01,0247,0120,0,
+ /* 18728 */ 0241,0202,05,0301,01,0247,0120,0,
+ /* 18736 */ 0241,0202,011,0301,01,0247,0120,0,
+ /* 18744 */ 0241,0202,021,0301,01,0267,0120,0,
+ /* 18752 */ 0241,0202,025,0301,01,0267,0120,0,
+ /* 18760 */ 0241,0202,031,0301,01,0267,0120,0,
+ /* 18768 */ 0241,0202,01,0301,01,0267,0120,0,
+ /* 18776 */ 0241,0202,05,0301,01,0267,0120,0,
+ /* 18784 */ 0241,0202,011,0301,01,0267,0120,0,
+ /* 18792 */ 0241,0202,021,0301,01,0234,0120,0,
+ /* 18800 */ 0241,0202,025,0301,01,0234,0120,0,
+ /* 18808 */ 0241,0202,031,0301,01,0234,0120,0,
+ /* 18816 */ 0241,0202,01,0301,01,0234,0120,0,
+ /* 18824 */ 0241,0202,05,0301,01,0234,0120,0,
+ /* 18832 */ 0241,0202,011,0301,01,0234,0120,0,
+ /* 18840 */ 0241,0202,021,0306,01,0235,0120,0,
+ /* 18848 */ 0241,0202,01,0306,01,0235,0120,0,
+ /* 18856 */ 0241,0202,021,0301,01,0254,0120,0,
+ /* 18864 */ 0241,0202,025,0301,01,0254,0120,0,
+ /* 18872 */ 0241,0202,031,0301,01,0254,0120,0,
+ /* 18880 */ 0241,0202,01,0301,01,0254,0120,0,
+ /* 18888 */ 0241,0202,05,0301,01,0254,0120,0,
+ /* 18896 */ 0241,0202,011,0301,01,0254,0120,0,
+ /* 18904 */ 0241,0202,021,0306,01,0255,0120,0,
+ /* 18912 */ 0241,0202,01,0306,01,0255,0120,0,
+ /* 18920 */ 0241,0202,021,0301,01,0274,0120,0,
+ /* 18928 */ 0241,0202,025,0301,01,0274,0120,0,
+ /* 18936 */ 0241,0202,031,0301,01,0274,0120,0,
+ /* 18944 */ 0241,0202,01,0301,01,0274,0120,0,
+ /* 18952 */ 0241,0202,05,0301,01,0274,0120,0,
+ /* 18960 */ 0241,0202,011,0301,01,0274,0120,0,
+ /* 18968 */ 0241,0202,021,0306,01,0275,0120,0,
+ /* 18976 */ 0241,0202,01,0306,01,0275,0120,0,
+ /* 18984 */ 0241,0202,021,0301,01,0236,0120,0,
+ /* 18992 */ 0241,0202,025,0301,01,0236,0120,0,
+ /* 19000 */ 0241,0202,031,0301,01,0236,0120,0,
+ /* 19008 */ 0241,0202,01,0301,01,0236,0120,0,
+ /* 19016 */ 0241,0202,05,0301,01,0236,0120,0,
+ /* 19024 */ 0241,0202,011,0301,01,0236,0120,0,
+ /* 19032 */ 0241,0202,021,0306,01,0237,0120,0,
+ /* 19040 */ 0241,0202,01,0306,01,0237,0120,0,
+ /* 19048 */ 0241,0202,021,0301,01,0256,0120,0,
+ /* 19056 */ 0241,0202,025,0301,01,0256,0120,0,
+ /* 19064 */ 0241,0202,031,0301,01,0256,0120,0,
+ /* 19072 */ 0241,0202,01,0301,01,0256,0120,0,
+ /* 19080 */ 0241,0202,05,0301,01,0256,0120,0,
+ /* 19088 */ 0241,0202,011,0301,01,0256,0120,0,
+ /* 19096 */ 0241,0202,021,0306,01,0257,0120,0,
+ /* 19104 */ 0241,0202,01,0306,01,0257,0120,0,
+ /* 19112 */ 0241,0202,021,0301,01,0276,0120,0,
+ /* 19120 */ 0241,0202,025,0301,01,0276,0120,0,
+ /* 19128 */ 0241,0202,031,0301,01,0276,0120,0,
+ /* 19136 */ 0241,0202,01,0301,01,0276,0120,0,
+ /* 19144 */ 0241,0202,05,0301,01,0276,0120,0,
+ /* 19152 */ 0241,0202,011,0301,01,0276,0120,0,
+ /* 19160 */ 0241,0202,021,0306,01,0277,0120,0,
+ /* 19168 */ 0241,0202,01,0306,01,0277,0120,0,
+ /* 19176 */ 0250,0202,021,0301,01,0102,0110,0,
+ /* 19184 */ 0250,0202,025,0301,01,0102,0110,0,
+ /* 19192 */ 0250,0202,031,0301,01,0102,0110,0,
+ /* 19200 */ 0250,0202,01,0301,01,0102,0110,0,
+ /* 19208 */ 0250,0202,05,0301,01,0102,0110,0,
+ /* 19216 */ 0250,0202,011,0301,01,0102,0110,0,
+ /* 19224 */ 0241,0202,021,0306,01,0103,0120,0,
+ /* 19232 */ 0241,0202,01,0306,01,0103,0120,0,
+ /* 19240 */ 0241,0201,021,0301,01,0137,0120,0,
+ /* 19248 */ 0240,0201,021,0301,01,0137,0110,0,
+ /* 19256 */ 0241,0201,025,0301,01,0137,0120,0,
+ /* 19264 */ 0240,0201,025,0301,01,0137,0110,0,
+ /* 19272 */ 0241,0201,031,0301,01,0137,0120,0,
+ /* 19280 */ 0240,0201,031,0301,01,0137,0110,0,
+ /* 19288 */ 0241,0201,0,0301,01,0137,0120,0,
+ /* 19296 */ 0240,0201,0,0301,01,0137,0110,0,
+ /* 19304 */ 0241,0201,04,0301,01,0137,0120,0,
+ /* 19312 */ 0240,0201,04,0301,01,0137,0110,0,
+ /* 19320 */ 0241,0201,010,0301,01,0137,0120,0,
+ /* 19328 */ 0240,0201,010,0301,01,0137,0110,0,
+ /* 19336 */ 0241,0201,023,0306,01,0137,0120,0,
+ /* 19344 */ 0240,0201,023,0306,01,0137,0110,0,
+ /* 19352 */ 0241,0201,02,0306,01,0137,0120,0,
+ /* 19360 */ 0240,0201,02,0306,01,0137,0110,0,
+ /* 19368 */ 0241,0201,021,0301,01,0135,0120,0,
+ /* 19376 */ 0240,0201,021,0301,01,0135,0110,0,
+ /* 19384 */ 0241,0201,025,0301,01,0135,0120,0,
+ /* 19392 */ 0240,0201,025,0301,01,0135,0110,0,
+ /* 19400 */ 0241,0201,031,0301,01,0135,0120,0,
+ /* 19408 */ 0240,0201,031,0301,01,0135,0110,0,
+ /* 19416 */ 0241,0201,0,0301,01,0135,0120,0,
+ /* 19424 */ 0240,0201,0,0301,01,0135,0110,0,
+ /* 19432 */ 0241,0201,04,0301,01,0135,0120,0,
+ /* 19440 */ 0240,0201,04,0301,01,0135,0110,0,
+ /* 19448 */ 0241,0201,010,0301,01,0135,0120,0,
+ /* 19456 */ 0240,0201,010,0301,01,0135,0110,0,
+ /* 19464 */ 0241,0201,023,0306,01,0135,0120,0,
+ /* 19472 */ 0240,0201,023,0306,01,0135,0110,0,
+ /* 19480 */ 0241,0201,02,0306,01,0135,0120,0,
+ /* 19488 */ 0240,0201,02,0306,01,0135,0110,0,
+ /* 19496 */ 0250,0201,021,0303,01,050,0110,0,
+ /* 19504 */ 0250,0201,025,0303,01,050,0110,0,
+ /* 19512 */ 0250,0201,031,0303,01,050,0110,0,
+ /* 19520 */ 0250,0201,021,0300,01,051,0101,0,
+ /* 19528 */ 0250,0201,025,0300,01,051,0101,0,
+ /* 19536 */ 0250,0201,031,0300,01,051,0101,0,
+ /* 19544 */ 0250,0201,021,0303,01,051,0101,0,
+ /* 19552 */ 0250,0201,025,0303,01,051,0101,0,
+ /* 19560 */ 0250,0201,031,0303,01,051,0101,0,
+ /* 19568 */ 0250,0201,0,0303,01,050,0110,0,
+ /* 19576 */ 0250,0201,04,0303,01,050,0110,0,
+ /* 19584 */ 0250,0201,010,0303,01,050,0110,0,
+ /* 19592 */ 0250,0201,0,0300,01,051,0101,0,
+ /* 19600 */ 0250,0201,04,0300,01,051,0101,0,
+ /* 19608 */ 0250,0201,010,0300,01,051,0101,0,
+ /* 19616 */ 0250,0201,0,0303,01,051,0101,0,
+ /* 19624 */ 0250,0201,04,0303,01,051,0101,0,
+ /* 19632 */ 0250,0201,010,0303,01,051,0101,0,
+ /* 19640 */ 0250,0201,01,0306,01,0156,0110,0,
+ /* 19648 */ 0250,0201,01,0306,01,0176,0101,0,
+ /* 19656 */ 0250,0201,023,0320,01,022,0110,0,
+ /* 19664 */ 0250,0201,027,0320,01,022,0110,0,
+ /* 19672 */ 0250,0201,033,0320,01,022,0110,0,
+ /* 19680 */ 0250,0201,01,0303,01,0157,0110,0,
+ /* 19688 */ 0250,0201,05,0303,01,0157,0110,0,
+ /* 19696 */ 0250,0201,011,0303,01,0157,0110,0,
+ /* 19704 */ 0250,0201,01,0303,01,0177,0101,0,
+ /* 19712 */ 0250,0201,05,0303,01,0177,0101,0,
+ /* 19720 */ 0250,0201,011,0303,01,0177,0101,0,
+ /* 19728 */ 0250,0201,021,0303,01,0157,0110,0,
+ /* 19736 */ 0250,0201,025,0303,01,0157,0110,0,
+ /* 19744 */ 0250,0201,031,0303,01,0157,0110,0,
+ /* 19752 */ 0250,0201,021,0303,01,0177,0101,0,
+ /* 19760 */ 0250,0201,025,0303,01,0177,0101,0,
+ /* 19768 */ 0250,0201,031,0303,01,0177,0101,0,
+ /* 19776 */ 0250,0201,023,0303,01,0157,0110,0,
+ /* 19784 */ 0250,0201,027,0303,01,0157,0110,0,
+ /* 19792 */ 0250,0201,033,0303,01,0157,0110,0,
+ /* 19800 */ 0250,0201,023,0303,01,0177,0101,0,
+ /* 19808 */ 0250,0201,027,0303,01,0177,0101,0,
+ /* 19816 */ 0250,0201,033,0303,01,0177,0101,0,
+ /* 19824 */ 0250,0201,02,0303,01,0157,0110,0,
+ /* 19832 */ 0250,0201,06,0303,01,0157,0110,0,
+ /* 19840 */ 0250,0201,012,0303,01,0157,0110,0,
+ /* 19848 */ 0250,0201,02,0303,01,0177,0101,0,
+ /* 19856 */ 0250,0201,06,0303,01,0177,0101,0,
+ /* 19864 */ 0250,0201,012,0303,01,0177,0101,0,
+ /* 19872 */ 0250,0201,022,0303,01,0157,0110,0,
+ /* 19880 */ 0250,0201,026,0303,01,0157,0110,0,
+ /* 19888 */ 0250,0201,032,0303,01,0157,0110,0,
+ /* 19896 */ 0250,0201,022,0303,01,0177,0101,0,
+ /* 19904 */ 0250,0201,026,0303,01,0177,0101,0,
+ /* 19912 */ 0250,0201,032,0303,01,0177,0101,0,
+ /* 19920 */ 0250,0201,03,0303,01,0157,0110,0,
+ /* 19928 */ 0250,0201,07,0303,01,0157,0110,0,
+ /* 19936 */ 0250,0201,013,0303,01,0157,0110,0,
+ /* 19944 */ 0250,0201,03,0303,01,0177,0101,0,
+ /* 19952 */ 0250,0201,07,0303,01,0177,0101,0,
+ /* 19960 */ 0250,0201,013,0303,01,0177,0101,0,
+ /* 19968 */ 0241,0201,0,0300,01,022,0120,0,
+ /* 19976 */ 0240,0201,0,0300,01,022,0110,0,
+ /* 19984 */ 0241,0201,021,0306,01,026,0120,0,
+ /* 19992 */ 0240,0201,021,0306,01,026,0110,0,
+ /* 20000 */ 0250,0201,021,0306,01,027,0101,0,
+ /* 20008 */ 0241,0201,0,0311,01,026,0120,0,
+ /* 20016 */ 0240,0201,0,0311,01,026,0110,0,
+ /* 20024 */ 0250,0201,0,0311,01,027,0101,0,
+ /* 20032 */ 0241,0201,0,0300,01,026,0120,0,
+ /* 20040 */ 0240,0201,0,0300,01,026,0110,0,
+ /* 20048 */ 0241,0201,021,0306,01,022,0120,0,
+ /* 20056 */ 0240,0201,021,0306,01,022,0110,0,
+ /* 20064 */ 0250,0201,021,0306,01,023,0101,0,
+ /* 20072 */ 0241,0201,0,0311,01,022,0120,0,
+ /* 20080 */ 0240,0201,0,0311,01,022,0110,0,
+ /* 20088 */ 0250,0201,0,0311,01,023,0101,0,
+ /* 20096 */ 0250,0201,01,0303,01,0347,0101,0,
+ /* 20104 */ 0250,0201,05,0303,01,0347,0101,0,
+ /* 20112 */ 0250,0201,011,0303,01,0347,0101,0,
+ /* 20120 */ 0250,0202,01,0303,01,052,0110,0,
+ /* 20128 */ 0250,0202,05,0303,01,052,0110,0,
+ /* 20136 */ 0250,0202,011,0303,01,052,0110,0,
+ /* 20144 */ 0250,0201,021,0303,01,053,0101,0,
+ /* 20152 */ 0250,0201,025,0303,01,053,0101,0,
+ /* 20160 */ 0250,0201,031,0303,01,053,0101,0,
+ /* 20168 */ 0250,0201,0,0303,01,053,0101,0,
+ /* 20176 */ 0250,0201,04,0303,01,053,0101,0,
+ /* 20184 */ 0250,0201,010,0303,01,053,0101,0,
+ /* 20192 */ 0250,0201,021,0306,01,0156,0110,0,
+ /* 20200 */ 0250,0201,021,0306,01,0176,0101,0,
+ /* 20208 */ 0250,0201,022,0306,01,0176,0110,0,
+ /* 20216 */ 0250,0201,021,0306,01,0326,0101,0,
+ /* 20224 */ 0250,0201,023,0306,01,020,0110,0,
+ /* 20232 */ 0250,0201,023,0306,01,021,0101,0,
+ /* 20240 */ 0241,0201,023,0300,01,020,0120,0,
+ /* 20248 */ 0240,0201,023,0300,01,020,0110,0,
+ /* 20256 */ 0241,0201,023,0300,01,021,0102,0,
+ /* 20264 */ 0240,0201,023,0300,01,021,0101,0,
+ /* 20272 */ 0250,0201,02,0303,01,026,0110,0,
+ /* 20280 */ 0250,0201,06,0303,01,026,0110,0,
+ /* 20288 */ 0250,0201,012,0303,01,026,0110,0,
+ /* 20296 */ 0250,0201,02,0303,01,022,0110,0,
+ /* 20304 */ 0250,0201,06,0303,01,022,0110,0,
+ /* 20312 */ 0250,0201,012,0303,01,022,0110,0,
+ /* 20320 */ 0250,0201,02,0306,01,020,0110,0,
+ /* 20328 */ 0250,0201,02,0306,01,021,0101,0,
+ /* 20336 */ 0241,0201,02,0300,01,020,0120,0,
+ /* 20344 */ 0240,0201,02,0300,01,020,0110,0,
+ /* 20352 */ 0241,0201,02,0300,01,021,0102,0,
+ /* 20360 */ 0240,0201,02,0300,01,021,0101,0,
+ /* 20368 */ 0250,0201,021,0303,01,020,0110,0,
+ /* 20376 */ 0250,0201,025,0303,01,020,0110,0,
+ /* 20384 */ 0250,0201,031,0303,01,020,0110,0,
+ /* 20392 */ 0250,0201,021,0300,01,021,0101,0,
+ /* 20400 */ 0250,0201,025,0300,01,021,0101,0,
+ /* 20408 */ 0250,0201,031,0300,01,021,0101,0,
+ /* 20416 */ 0250,0201,021,0303,01,021,0101,0,
+ /* 20424 */ 0250,0201,025,0303,01,021,0101,0,
+ /* 20432 */ 0250,0201,031,0303,01,021,0101,0,
+ /* 20440 */ 0250,0201,0,0303,01,020,0110,0,
+ /* 20448 */ 0250,0201,04,0303,01,020,0110,0,
+ /* 20456 */ 0250,0201,010,0303,01,020,0110,0,
+ /* 20464 */ 0250,0201,0,0300,01,021,0101,0,
+ /* 20472 */ 0250,0201,04,0300,01,021,0101,0,
+ /* 20480 */ 0250,0201,010,0300,01,021,0101,0,
+ /* 20488 */ 0250,0201,0,0303,01,021,0101,0,
+ /* 20496 */ 0250,0201,04,0303,01,021,0101,0,
+ /* 20504 */ 0250,0201,010,0303,01,021,0101,0,
+ /* 20512 */ 0241,0201,021,0301,01,0131,0120,0,
+ /* 20520 */ 0240,0201,021,0301,01,0131,0110,0,
+ /* 20528 */ 0241,0201,025,0301,01,0131,0120,0,
+ /* 20536 */ 0240,0201,025,0301,01,0131,0110,0,
+ /* 20544 */ 0241,0201,031,0301,01,0131,0120,0,
+ /* 20552 */ 0240,0201,031,0301,01,0131,0110,0,
+ /* 20560 */ 0241,0201,0,0301,01,0131,0120,0,
+ /* 20568 */ 0240,0201,0,0301,01,0131,0110,0,
+ /* 20576 */ 0241,0201,04,0301,01,0131,0120,0,
+ /* 20584 */ 0240,0201,04,0301,01,0131,0110,0,
+ /* 20592 */ 0241,0201,010,0301,01,0131,0120,0,
+ /* 20600 */ 0240,0201,010,0301,01,0131,0110,0,
+ /* 20608 */ 0241,0201,023,0306,01,0131,0120,0,
+ /* 20616 */ 0240,0201,023,0306,01,0131,0110,0,
+ /* 20624 */ 0241,0201,02,0306,01,0131,0120,0,
+ /* 20632 */ 0240,0201,02,0306,01,0131,0110,0,
+ /* 20640 */ 0241,0201,021,0301,01,0126,0120,0,
+ /* 20648 */ 0240,0201,021,0301,01,0126,0110,0,
+ /* 20656 */ 0241,0201,025,0301,01,0126,0120,0,
+ /* 20664 */ 0240,0201,025,0301,01,0126,0110,0,
+ /* 20672 */ 0241,0201,031,0301,01,0126,0120,0,
+ /* 20680 */ 0240,0201,031,0301,01,0126,0110,0,
+ /* 20688 */ 0241,0201,0,0301,01,0126,0120,0,
+ /* 20696 */ 0240,0201,0,0301,01,0126,0110,0,
+ /* 20704 */ 0241,0201,04,0301,01,0126,0120,0,
+ /* 20712 */ 0240,0201,04,0301,01,0126,0110,0,
+ /* 20720 */ 0241,0201,010,0301,01,0126,0120,0,
+ /* 20728 */ 0240,0201,010,0301,01,0126,0110,0,
+ /* 20736 */ 0250,0202,041,0303,01,034,0110,0,
+ /* 20744 */ 0250,0202,045,0303,01,034,0110,0,
+ /* 20752 */ 0250,0202,051,0303,01,034,0110,0,
+ /* 20760 */ 0250,0202,01,0301,01,036,0110,0,
+ /* 20768 */ 0250,0202,05,0301,01,036,0110,0,
+ /* 20776 */ 0250,0202,011,0301,01,036,0110,0,
+ /* 20784 */ 0250,0202,021,0301,01,037,0110,0,
+ /* 20792 */ 0250,0202,025,0301,01,037,0110,0,
+ /* 20800 */ 0250,0202,031,0301,01,037,0110,0,
+ /* 20808 */ 0250,0202,041,0303,01,035,0110,0,
+ /* 20816 */ 0250,0202,045,0303,01,035,0110,0,
+ /* 20824 */ 0250,0202,051,0303,01,035,0110,0,
+ /* 20832 */ 0241,0201,01,0301,01,0153,0120,0,
+ /* 20840 */ 0240,0201,01,0301,01,0153,0110,0,
+ /* 20848 */ 0241,0201,05,0301,01,0153,0120,0,
+ /* 20856 */ 0240,0201,05,0301,01,0153,0110,0,
+ /* 20864 */ 0241,0201,011,0301,01,0153,0120,0,
+ /* 20872 */ 0240,0201,011,0301,01,0153,0110,0,
+ /* 20880 */ 0241,0201,041,0303,01,0143,0120,0,
+ /* 20888 */ 0240,0201,041,0303,01,0143,0110,0,
+ /* 20896 */ 0241,0201,045,0303,01,0143,0120,0,
+ /* 20904 */ 0240,0201,045,0303,01,0143,0110,0,
+ /* 20912 */ 0241,0201,051,0303,01,0143,0120,0,
+ /* 20920 */ 0240,0201,051,0303,01,0143,0110,0,
+ /* 20928 */ 0241,0202,01,0301,01,053,0120,0,
+ /* 20936 */ 0240,0202,01,0301,01,053,0110,0,
+ /* 20944 */ 0241,0202,05,0301,01,053,0120,0,
+ /* 20952 */ 0240,0202,05,0301,01,053,0110,0,
+ /* 20960 */ 0241,0202,011,0301,01,053,0120,0,
+ /* 20968 */ 0240,0202,011,0301,01,053,0110,0,
+ /* 20976 */ 0241,0201,041,0303,01,0147,0120,0,
+ /* 20984 */ 0240,0201,041,0303,01,0147,0110,0,
+ /* 20992 */ 0241,0201,045,0303,01,0147,0120,0,
+ /* 21000 */ 0240,0201,045,0303,01,0147,0110,0,
+ /* 21008 */ 0241,0201,051,0303,01,0147,0120,0,
+ /* 21016 */ 0240,0201,051,0303,01,0147,0110,0,
+ /* 21024 */ 0241,0201,041,0303,01,0374,0120,0,
+ /* 21032 */ 0240,0201,041,0303,01,0374,0110,0,
+ /* 21040 */ 0241,0201,045,0303,01,0374,0120,0,
+ /* 21048 */ 0240,0201,045,0303,01,0374,0110,0,
+ /* 21056 */ 0241,0201,051,0303,01,0374,0120,0,
+ /* 21064 */ 0240,0201,051,0303,01,0374,0110,0,
+ /* 21072 */ 0241,0201,01,0301,01,0376,0120,0,
+ /* 21080 */ 0240,0201,01,0301,01,0376,0110,0,
+ /* 21088 */ 0241,0201,05,0301,01,0376,0120,0,
+ /* 21096 */ 0240,0201,05,0301,01,0376,0110,0,
+ /* 21104 */ 0241,0201,011,0301,01,0376,0120,0,
+ /* 21112 */ 0240,0201,011,0301,01,0376,0110,0,
+ /* 21120 */ 0241,0201,021,0301,01,0324,0120,0,
+ /* 21128 */ 0240,0201,021,0301,01,0324,0110,0,
+ /* 21136 */ 0241,0201,025,0301,01,0324,0120,0,
+ /* 21144 */ 0240,0201,025,0301,01,0324,0110,0,
+ /* 21152 */ 0241,0201,031,0301,01,0324,0120,0,
+ /* 21160 */ 0240,0201,031,0301,01,0324,0110,0,
+ /* 21168 */ 0241,0201,041,0303,01,0354,0120,0,
+ /* 21176 */ 0240,0201,041,0303,01,0354,0110,0,
+ /* 21184 */ 0241,0201,045,0303,01,0354,0120,0,
+ /* 21192 */ 0240,0201,045,0303,01,0354,0110,0,
+ /* 21200 */ 0241,0201,051,0303,01,0354,0120,0,
+ /* 21208 */ 0240,0201,051,0303,01,0354,0110,0,
+ /* 21216 */ 0241,0201,041,0303,01,0355,0120,0,
+ /* 21224 */ 0240,0201,041,0303,01,0355,0110,0,
+ /* 21232 */ 0241,0201,045,0303,01,0355,0120,0,
+ /* 21240 */ 0240,0201,045,0303,01,0355,0110,0,
+ /* 21248 */ 0241,0201,051,0303,01,0355,0120,0,
+ /* 21256 */ 0240,0201,051,0303,01,0355,0110,0,
+ /* 21264 */ 0241,0201,041,0303,01,0334,0120,0,
+ /* 21272 */ 0240,0201,041,0303,01,0334,0110,0,
+ /* 21280 */ 0241,0201,045,0303,01,0334,0120,0,
+ /* 21288 */ 0240,0201,045,0303,01,0334,0110,0,
+ /* 21296 */ 0241,0201,051,0303,01,0334,0120,0,
+ /* 21304 */ 0240,0201,051,0303,01,0334,0110,0,
+ /* 21312 */ 0241,0201,041,0303,01,0335,0120,0,
+ /* 21320 */ 0240,0201,041,0303,01,0335,0110,0,
+ /* 21328 */ 0241,0201,045,0303,01,0335,0120,0,
+ /* 21336 */ 0240,0201,045,0303,01,0335,0110,0,
+ /* 21344 */ 0241,0201,051,0303,01,0335,0120,0,
+ /* 21352 */ 0240,0201,051,0303,01,0335,0110,0,
+ /* 21360 */ 0241,0201,041,0303,01,0375,0120,0,
+ /* 21368 */ 0240,0201,041,0303,01,0375,0110,0,
+ /* 21376 */ 0241,0201,045,0303,01,0375,0120,0,
+ /* 21384 */ 0240,0201,045,0303,01,0375,0110,0,
+ /* 21392 */ 0241,0201,051,0303,01,0375,0120,0,
+ /* 21400 */ 0240,0201,051,0303,01,0375,0110,0,
+ /* 21408 */ 0241,0201,01,0301,01,0333,0120,0,
+ /* 21416 */ 0240,0201,01,0301,01,0333,0110,0,
+ /* 21424 */ 0241,0201,05,0301,01,0333,0120,0,
+ /* 21432 */ 0240,0201,05,0301,01,0333,0110,0,
+ /* 21440 */ 0241,0201,011,0301,01,0333,0120,0,
+ /* 21448 */ 0240,0201,011,0301,01,0333,0110,0,
+ /* 21456 */ 0241,0201,01,0301,01,0337,0120,0,
+ /* 21464 */ 0240,0201,01,0301,01,0337,0110,0,
+ /* 21472 */ 0241,0201,05,0301,01,0337,0120,0,
+ /* 21480 */ 0240,0201,05,0301,01,0337,0110,0,
+ /* 21488 */ 0241,0201,011,0301,01,0337,0120,0,
+ /* 21496 */ 0240,0201,011,0301,01,0337,0110,0,
+ /* 21504 */ 0241,0201,021,0301,01,0337,0120,0,
+ /* 21512 */ 0240,0201,021,0301,01,0337,0110,0,
+ /* 21520 */ 0241,0201,025,0301,01,0337,0120,0,
+ /* 21528 */ 0240,0201,025,0301,01,0337,0110,0,
+ /* 21536 */ 0241,0201,031,0301,01,0337,0120,0,
+ /* 21544 */ 0240,0201,031,0301,01,0337,0110,0,
+ /* 21552 */ 0241,0201,021,0301,01,0333,0120,0,
+ /* 21560 */ 0240,0201,021,0301,01,0333,0110,0,
+ /* 21568 */ 0241,0201,025,0301,01,0333,0120,0,
+ /* 21576 */ 0240,0201,025,0301,01,0333,0110,0,
+ /* 21584 */ 0241,0201,031,0301,01,0333,0120,0,
+ /* 21592 */ 0240,0201,031,0301,01,0333,0110,0,
+ /* 21600 */ 0241,0201,041,0303,01,0340,0120,0,
+ /* 21608 */ 0240,0201,041,0303,01,0340,0110,0,
+ /* 21616 */ 0241,0201,045,0303,01,0340,0120,0,
+ /* 21624 */ 0240,0201,045,0303,01,0340,0110,0,
+ /* 21632 */ 0241,0201,051,0303,01,0340,0120,0,
+ /* 21640 */ 0240,0201,051,0303,01,0340,0110,0,
+ /* 21648 */ 0241,0201,041,0303,01,0343,0120,0,
+ /* 21656 */ 0240,0201,041,0303,01,0343,0110,0,
+ /* 21664 */ 0241,0201,045,0303,01,0343,0120,0,
+ /* 21672 */ 0240,0201,045,0303,01,0343,0110,0,
+ /* 21680 */ 0241,0201,051,0303,01,0343,0120,0,
+ /* 21688 */ 0240,0201,051,0303,01,0343,0110,0,
+ /* 21696 */ 0241,0202,01,0303,01,0146,0120,0,
+ /* 21704 */ 0241,0202,05,0303,01,0146,0120,0,
+ /* 21712 */ 0241,0202,011,0303,01,0146,0120,0,
+ /* 21720 */ 0241,0202,01,0301,01,0144,0120,0,
+ /* 21728 */ 0241,0202,05,0301,01,0144,0120,0,
+ /* 21736 */ 0241,0202,011,0301,01,0144,0120,0,
+ /* 21744 */ 0241,0202,021,0301,01,0144,0120,0,
+ /* 21752 */ 0241,0202,025,0301,01,0144,0120,0,
+ /* 21760 */ 0241,0202,031,0301,01,0144,0120,0,
+ /* 21768 */ 0241,0202,021,0303,01,0146,0120,0,
+ /* 21776 */ 0241,0202,025,0303,01,0146,0120,0,
+ /* 21784 */ 0241,0202,031,0303,01,0146,0120,0,
+ /* 21792 */ 0250,0202,01,0304,01,0170,0110,0,
+ /* 21800 */ 0250,0202,05,0304,01,0170,0110,0,
+ /* 21808 */ 0250,0202,011,0304,01,0170,0110,0,
+ /* 21816 */ 0250,0202,01,0300,01,0172,0110,0,
+ /* 21824 */ 0250,0202,05,0300,01,0172,0110,0,
+ /* 21832 */ 0250,0202,011,0300,01,0172,0110,0,
+ /* 21840 */ 0250,0202,01,0306,01,0130,0110,0,
+ /* 21848 */ 0250,0202,05,0306,01,0130,0110,0,
+ /* 21856 */ 0250,0202,011,0306,01,0130,0110,0,
+ /* 21864 */ 0250,0202,01,0300,01,0130,0110,0,
+ /* 21872 */ 0250,0202,05,0300,01,0130,0110,0,
+ /* 21880 */ 0250,0202,011,0300,01,0130,0110,0,
+ /* 21888 */ 0250,0202,01,0300,01,0174,0110,0,
+ /* 21896 */ 0250,0202,05,0300,01,0174,0110,0,
+ /* 21904 */ 0250,0202,011,0300,01,0174,0110,0,
+ /* 21912 */ 0250,0202,022,0300,01,052,0110,0,
+ /* 21920 */ 0250,0202,026,0300,01,052,0110,0,
+ /* 21928 */ 0250,0202,032,0300,01,052,0110,0,
+ /* 21936 */ 0250,0202,02,0300,01,072,0110,0,
+ /* 21944 */ 0250,0202,06,0300,01,072,0110,0,
+ /* 21952 */ 0250,0202,012,0300,01,072,0110,0,
+ /* 21960 */ 0250,0202,021,0306,01,0131,0110,0,
+ /* 21968 */ 0250,0202,025,0306,01,0131,0110,0,
+ /* 21976 */ 0250,0202,031,0306,01,0131,0110,0,
+ /* 21984 */ 0250,0202,021,0300,01,0131,0110,0,
+ /* 21992 */ 0250,0202,025,0300,01,0131,0110,0,
+ /* 22000 */ 0250,0202,031,0300,01,0131,0110,0,
+ /* 22008 */ 0250,0202,021,0300,01,0174,0110,0,
+ /* 22016 */ 0250,0202,025,0300,01,0174,0110,0,
+ /* 22024 */ 0250,0202,031,0300,01,0174,0110,0,
+ /* 22032 */ 0250,0202,01,0305,01,0171,0110,0,
+ /* 22040 */ 0250,0202,05,0305,01,0171,0110,0,
+ /* 22048 */ 0250,0202,011,0305,01,0171,0110,0,
+ /* 22056 */ 0250,0202,01,0300,01,0173,0110,0,
+ /* 22064 */ 0250,0202,05,0300,01,0173,0110,0,
+ /* 22072 */ 0250,0202,011,0300,01,0173,0110,0,
+ /* 22080 */ 0241,0201,041,0303,01,0164,0120,0,
+ /* 22088 */ 0241,0201,045,0303,01,0164,0120,0,
+ /* 22096 */ 0241,0201,051,0303,01,0164,0120,0,
+ /* 22104 */ 0241,0201,01,0301,01,0166,0120,0,
+ /* 22112 */ 0241,0201,05,0301,01,0166,0120,0,
+ /* 22120 */ 0241,0201,011,0301,01,0166,0120,0,
+ /* 22128 */ 0241,0202,021,0301,01,051,0120,0,
+ /* 22136 */ 0241,0202,025,0301,01,051,0120,0,
+ /* 22144 */ 0241,0202,031,0301,01,051,0120,0,
+ /* 22152 */ 0241,0201,041,0303,01,0165,0120,0,
+ /* 22160 */ 0241,0201,045,0303,01,0165,0120,0,
+ /* 22168 */ 0241,0201,051,0303,01,0165,0120,0,
+ /* 22176 */ 0241,0201,041,0303,01,0144,0120,0,
+ /* 22184 */ 0241,0201,045,0303,01,0144,0120,0,
+ /* 22192 */ 0241,0201,051,0303,01,0144,0120,0,
+ /* 22200 */ 0241,0201,01,0301,01,0146,0120,0,
+ /* 22208 */ 0241,0201,05,0301,01,0146,0120,0,
+ /* 22216 */ 0241,0201,011,0301,01,0146,0120,0,
+ /* 22224 */ 0241,0202,021,0301,01,067,0120,0,
+ /* 22232 */ 0241,0202,025,0301,01,067,0120,0,
+ /* 22240 */ 0241,0202,031,0301,01,067,0120,0,
+ /* 22248 */ 0241,0201,041,0303,01,0145,0120,0,
+ /* 22256 */ 0241,0201,045,0303,01,0145,0120,0,
+ /* 22264 */ 0241,0201,051,0303,01,0145,0120,0,
+ /* 22272 */ 0250,0202,01,0306,01,0213,0101,0,
+ /* 22280 */ 0250,0202,05,0306,01,0213,0101,0,
+ /* 22288 */ 0250,0202,011,0306,01,0213,0101,0,
+ /* 22296 */ 0250,0202,01,0300,01,0213,0101,0,
+ /* 22304 */ 0250,0202,05,0300,01,0213,0101,0,
+ /* 22312 */ 0250,0202,011,0300,01,0213,0101,0,
+ /* 22320 */ 0250,0202,021,0306,01,0213,0101,0,
+ /* 22328 */ 0250,0202,025,0306,01,0213,0101,0,
+ /* 22336 */ 0250,0202,031,0306,01,0213,0101,0,
+ /* 22344 */ 0250,0202,021,0300,01,0213,0101,0,
+ /* 22352 */ 0250,0202,025,0300,01,0213,0101,0,
+ /* 22360 */ 0250,0202,031,0300,01,0213,0101,0,
+ /* 22368 */ 0250,0202,01,0301,01,0304,0110,0,
+ /* 22376 */ 0250,0202,05,0301,01,0304,0110,0,
+ /* 22384 */ 0250,0202,011,0301,01,0304,0110,0,
+ /* 22392 */ 0250,0202,021,0301,01,0304,0110,0,
+ /* 22400 */ 0250,0202,025,0301,01,0304,0110,0,
+ /* 22408 */ 0250,0202,031,0301,01,0304,0110,0,
+ /* 22416 */ 0241,0202,01,0303,01,0215,0120,0,
+ /* 22424 */ 0240,0202,01,0303,01,0215,0110,0,
+ /* 22432 */ 0241,0202,05,0303,01,0215,0120,0,
+ /* 22440 */ 0240,0202,05,0303,01,0215,0110,0,
+ /* 22448 */ 0241,0202,011,0303,01,0215,0120,0,
+ /* 22456 */ 0240,0202,011,0303,01,0215,0110,0,
+ /* 22464 */ 0241,0202,05,0301,01,066,0120,0,
+ /* 22472 */ 0240,0202,05,0301,01,066,0110,0,
+ /* 22480 */ 0241,0202,011,0301,01,066,0120,0,
+ /* 22488 */ 0240,0202,011,0301,01,066,0110,0,
+ /* 22496 */ 0241,0202,01,0303,01,0165,0120,0,
+ /* 22504 */ 0241,0202,05,0303,01,0165,0120,0,
+ /* 22512 */ 0241,0202,011,0303,01,0165,0120,0,
+ /* 22520 */ 0241,0202,01,0301,01,0166,0120,0,
+ /* 22528 */ 0241,0202,05,0301,01,0166,0120,0,
+ /* 22536 */ 0241,0202,011,0301,01,0166,0120,0,
+ /* 22544 */ 0241,0202,021,0301,01,0167,0120,0,
+ /* 22552 */ 0241,0202,025,0301,01,0167,0120,0,
+ /* 22560 */ 0241,0202,031,0301,01,0167,0120,0,
+ /* 22568 */ 0241,0202,01,0301,01,0167,0120,0,
+ /* 22576 */ 0241,0202,05,0301,01,0167,0120,0,
+ /* 22584 */ 0241,0202,011,0301,01,0167,0120,0,
+ /* 22592 */ 0241,0202,021,0301,01,0166,0120,0,
+ /* 22600 */ 0241,0202,025,0301,01,0166,0120,0,
+ /* 22608 */ 0241,0202,031,0301,01,0166,0120,0,
+ /* 22616 */ 0241,0202,021,0303,01,0165,0120,0,
+ /* 22624 */ 0241,0202,025,0303,01,0165,0120,0,
+ /* 22632 */ 0241,0202,031,0303,01,0165,0120,0,
+ /* 22640 */ 0241,0202,021,0301,01,015,0120,0,
+ /* 22648 */ 0240,0202,021,0301,01,015,0110,0,
+ /* 22656 */ 0241,0202,025,0301,01,015,0120,0,
+ /* 22664 */ 0240,0202,025,0301,01,015,0110,0,
+ /* 22672 */ 0241,0202,031,0301,01,015,0120,0,
+ /* 22680 */ 0240,0202,031,0301,01,015,0110,0,
+ /* 22688 */ 0241,0202,01,0301,01,014,0120,0,
+ /* 22696 */ 0240,0202,01,0301,01,014,0110,0,
+ /* 22704 */ 0241,0202,05,0301,01,014,0120,0,
+ /* 22712 */ 0240,0202,05,0301,01,014,0110,0,
+ /* 22720 */ 0241,0202,011,0301,01,014,0120,0,
+ /* 22728 */ 0240,0202,011,0301,01,014,0110,0,
+ /* 22736 */ 0241,0202,025,0301,01,026,0120,0,
+ /* 22744 */ 0240,0202,025,0301,01,026,0110,0,
+ /* 22752 */ 0241,0202,031,0301,01,026,0120,0,
+ /* 22760 */ 0240,0202,031,0301,01,026,0110,0,
+ /* 22768 */ 0241,0202,05,0301,01,026,0120,0,
+ /* 22776 */ 0240,0202,05,0301,01,026,0110,0,
+ /* 22784 */ 0241,0202,011,0301,01,026,0120,0,
+ /* 22792 */ 0240,0202,011,0301,01,026,0110,0,
+ /* 22800 */ 0241,0202,025,0301,01,066,0120,0,
+ /* 22808 */ 0240,0202,025,0301,01,066,0110,0,
+ /* 22816 */ 0241,0202,031,0301,01,066,0120,0,
+ /* 22824 */ 0240,0202,031,0301,01,066,0110,0,
+ /* 22832 */ 0241,0202,01,0303,01,0175,0120,0,
+ /* 22840 */ 0241,0202,05,0303,01,0175,0120,0,
+ /* 22848 */ 0241,0202,011,0303,01,0175,0120,0,
+ /* 22856 */ 0241,0202,01,0301,01,0176,0120,0,
+ /* 22864 */ 0241,0202,05,0301,01,0176,0120,0,
+ /* 22872 */ 0241,0202,011,0301,01,0176,0120,0,
+ /* 22880 */ 0241,0202,021,0301,01,0177,0120,0,
+ /* 22888 */ 0241,0202,025,0301,01,0177,0120,0,
+ /* 22896 */ 0241,0202,031,0301,01,0177,0120,0,
+ /* 22904 */ 0241,0202,01,0301,01,0177,0120,0,
+ /* 22912 */ 0241,0202,05,0301,01,0177,0120,0,
+ /* 22920 */ 0241,0202,011,0301,01,0177,0120,0,
+ /* 22928 */ 0241,0202,021,0301,01,0176,0120,0,
+ /* 22936 */ 0241,0202,025,0301,01,0176,0120,0,
+ /* 22944 */ 0241,0202,031,0301,01,0176,0120,0,
+ /* 22952 */ 0241,0202,021,0303,01,0175,0120,0,
+ /* 22960 */ 0241,0202,025,0303,01,0175,0120,0,
+ /* 22968 */ 0241,0202,031,0303,01,0175,0120,0,
+ /* 22976 */ 0241,0202,021,0303,01,0215,0120,0,
+ /* 22984 */ 0240,0202,021,0303,01,0215,0110,0,
+ /* 22992 */ 0241,0202,025,0303,01,0215,0120,0,
+ /* 23000 */ 0240,0202,025,0303,01,0215,0110,0,
+ /* 23008 */ 0241,0202,031,0303,01,0215,0120,0,
+ /* 23016 */ 0240,0202,031,0303,01,0215,0110,0,
+ /* 23024 */ 0250,0202,01,0306,01,0211,0110,0,
+ /* 23032 */ 0250,0202,05,0306,01,0211,0110,0,
+ /* 23040 */ 0250,0202,011,0306,01,0211,0110,0,
+ /* 23048 */ 0250,0202,021,0306,01,0211,0110,0,
+ /* 23056 */ 0250,0202,025,0306,01,0211,0110,0,
+ /* 23064 */ 0250,0202,031,0306,01,0211,0110,0,
+ /* 23072 */ 0250,0202,01,0301,01,0104,0110,0,
+ /* 23080 */ 0250,0202,05,0301,01,0104,0110,0,
+ /* 23088 */ 0250,0202,011,0301,01,0104,0110,0,
+ /* 23096 */ 0250,0202,021,0301,01,0104,0110,0,
+ /* 23104 */ 0250,0202,025,0301,01,0104,0110,0,
+ /* 23112 */ 0250,0202,031,0301,01,0104,0110,0,
+ /* 23120 */ 0241,0202,021,0301,01,0265,0120,0,
+ /* 23128 */ 0241,0202,025,0301,01,0265,0120,0,
+ /* 23136 */ 0241,0202,031,0301,01,0265,0120,0,
+ /* 23144 */ 0241,0202,021,0301,01,0264,0120,0,
+ /* 23152 */ 0241,0202,025,0301,01,0264,0120,0,
+ /* 23160 */ 0241,0202,031,0301,01,0264,0120,0,
+ /* 23168 */ 0241,0202,041,0303,01,04,0120,0,
+ /* 23176 */ 0240,0202,041,0303,01,04,0110,0,
+ /* 23184 */ 0241,0202,045,0303,01,04,0120,0,
+ /* 23192 */ 0240,0202,045,0303,01,04,0110,0,
+ /* 23200 */ 0241,0202,051,0303,01,04,0120,0,
+ /* 23208 */ 0240,0202,051,0303,01,04,0110,0,
+ /* 23216 */ 0241,0201,041,0303,01,0365,0120,0,
+ /* 23224 */ 0240,0201,041,0303,01,0365,0110,0,
+ /* 23232 */ 0241,0201,045,0303,01,0365,0120,0,
+ /* 23240 */ 0240,0201,045,0303,01,0365,0110,0,
+ /* 23248 */ 0241,0201,051,0303,01,0365,0120,0,
+ /* 23256 */ 0240,0201,051,0303,01,0365,0110,0,
+ /* 23264 */ 0241,0202,041,0303,01,074,0120,0,
+ /* 23272 */ 0240,0202,041,0303,01,074,0110,0,
+ /* 23280 */ 0241,0202,045,0303,01,074,0120,0,
+ /* 23288 */ 0240,0202,045,0303,01,074,0110,0,
+ /* 23296 */ 0241,0202,051,0303,01,074,0120,0,
+ /* 23304 */ 0240,0202,051,0303,01,074,0110,0,
+ /* 23312 */ 0241,0202,01,0301,01,075,0120,0,
+ /* 23320 */ 0240,0202,01,0301,01,075,0110,0,
+ /* 23328 */ 0241,0202,05,0301,01,075,0120,0,
+ /* 23336 */ 0240,0202,05,0301,01,075,0110,0,
+ /* 23344 */ 0241,0202,011,0301,01,075,0120,0,
+ /* 23352 */ 0240,0202,011,0301,01,075,0110,0,
+ /* 23360 */ 0241,0202,021,0301,01,075,0120,0,
+ /* 23368 */ 0240,0202,021,0301,01,075,0110,0,
+ /* 23376 */ 0241,0202,025,0301,01,075,0120,0,
+ /* 23384 */ 0240,0202,025,0301,01,075,0110,0,
+ /* 23392 */ 0241,0202,031,0301,01,075,0120,0,
+ /* 23400 */ 0240,0202,031,0301,01,075,0110,0,
+ /* 23408 */ 0241,0201,041,0303,01,0356,0120,0,
+ /* 23416 */ 0240,0201,041,0303,01,0356,0110,0,
+ /* 23424 */ 0241,0201,045,0303,01,0356,0120,0,
+ /* 23432 */ 0240,0201,045,0303,01,0356,0110,0,
+ /* 23440 */ 0241,0201,051,0303,01,0356,0120,0,
+ /* 23448 */ 0240,0201,051,0303,01,0356,0110,0,
+ /* 23456 */ 0241,0201,041,0303,01,0336,0120,0,
+ /* 23464 */ 0240,0201,041,0303,01,0336,0110,0,
+ /* 23472 */ 0241,0201,045,0303,01,0336,0120,0,
+ /* 23480 */ 0240,0201,045,0303,01,0336,0110,0,
+ /* 23488 */ 0241,0201,051,0303,01,0336,0120,0,
+ /* 23496 */ 0240,0201,051,0303,01,0336,0110,0,
+ /* 23504 */ 0241,0202,01,0301,01,077,0120,0,
+ /* 23512 */ 0240,0202,01,0301,01,077,0110,0,
+ /* 23520 */ 0241,0202,05,0301,01,077,0120,0,
+ /* 23528 */ 0240,0202,05,0301,01,077,0110,0,
+ /* 23536 */ 0241,0202,011,0301,01,077,0120,0,
+ /* 23544 */ 0240,0202,011,0301,01,077,0110,0,
+ /* 23552 */ 0241,0202,021,0301,01,077,0120,0,
+ /* 23560 */ 0240,0202,021,0301,01,077,0110,0,
+ /* 23568 */ 0241,0202,025,0301,01,077,0120,0,
+ /* 23576 */ 0240,0202,025,0301,01,077,0110,0,
+ /* 23584 */ 0241,0202,031,0301,01,077,0120,0,
+ /* 23592 */ 0240,0202,031,0301,01,077,0110,0,
+ /* 23600 */ 0241,0202,041,0303,01,076,0120,0,
+ /* 23608 */ 0240,0202,041,0303,01,076,0110,0,
+ /* 23616 */ 0241,0202,045,0303,01,076,0120,0,
+ /* 23624 */ 0240,0202,045,0303,01,076,0110,0,
+ /* 23632 */ 0241,0202,051,0303,01,076,0120,0,
+ /* 23640 */ 0240,0202,051,0303,01,076,0110,0,
+ /* 23648 */ 0241,0202,041,0303,01,070,0120,0,
+ /* 23656 */ 0240,0202,041,0303,01,070,0110,0,
+ /* 23664 */ 0241,0202,045,0303,01,070,0120,0,
+ /* 23672 */ 0240,0202,045,0303,01,070,0110,0,
+ /* 23680 */ 0241,0202,051,0303,01,070,0120,0,
+ /* 23688 */ 0240,0202,051,0303,01,070,0110,0,
+ /* 23696 */ 0241,0202,01,0301,01,071,0120,0,
+ /* 23704 */ 0240,0202,01,0301,01,071,0110,0,
+ /* 23712 */ 0241,0202,05,0301,01,071,0120,0,
+ /* 23720 */ 0240,0202,05,0301,01,071,0110,0,
+ /* 23728 */ 0241,0202,011,0301,01,071,0120,0,
+ /* 23736 */ 0240,0202,011,0301,01,071,0110,0,
+ /* 23744 */ 0241,0202,021,0301,01,071,0120,0,
+ /* 23752 */ 0240,0202,021,0301,01,071,0110,0,
+ /* 23760 */ 0241,0202,025,0301,01,071,0120,0,
+ /* 23768 */ 0240,0202,025,0301,01,071,0110,0,
+ /* 23776 */ 0241,0202,031,0301,01,071,0120,0,
+ /* 23784 */ 0240,0202,031,0301,01,071,0110,0,
+ /* 23792 */ 0241,0201,041,0303,01,0352,0120,0,
+ /* 23800 */ 0240,0201,041,0303,01,0352,0110,0,
+ /* 23808 */ 0241,0201,045,0303,01,0352,0120,0,
+ /* 23816 */ 0240,0201,045,0303,01,0352,0110,0,
+ /* 23824 */ 0241,0201,051,0303,01,0352,0120,0,
+ /* 23832 */ 0240,0201,051,0303,01,0352,0110,0,
+ /* 23840 */ 0241,0201,041,0303,01,0332,0120,0,
+ /* 23848 */ 0240,0201,041,0303,01,0332,0110,0,
+ /* 23856 */ 0241,0201,045,0303,01,0332,0120,0,
+ /* 23864 */ 0240,0201,045,0303,01,0332,0110,0,
+ /* 23872 */ 0241,0201,051,0303,01,0332,0120,0,
+ /* 23880 */ 0240,0201,051,0303,01,0332,0110,0,
+ /* 23888 */ 0241,0202,01,0301,01,073,0120,0,
+ /* 23896 */ 0240,0202,01,0301,01,073,0110,0,
+ /* 23904 */ 0241,0202,05,0301,01,073,0120,0,
+ /* 23912 */ 0240,0202,05,0301,01,073,0110,0,
+ /* 23920 */ 0241,0202,011,0301,01,073,0120,0,
+ /* 23928 */ 0240,0202,011,0301,01,073,0110,0,
+ /* 23936 */ 0241,0202,021,0301,01,073,0120,0,
+ /* 23944 */ 0240,0202,021,0301,01,073,0110,0,
+ /* 23952 */ 0241,0202,025,0301,01,073,0120,0,
+ /* 23960 */ 0240,0202,025,0301,01,073,0110,0,
+ /* 23968 */ 0241,0202,031,0301,01,073,0120,0,
+ /* 23976 */ 0240,0202,031,0301,01,073,0110,0,
+ /* 23984 */ 0241,0202,041,0303,01,072,0120,0,
+ /* 23992 */ 0240,0202,041,0303,01,072,0110,0,
+ /* 24000 */ 0241,0202,045,0303,01,072,0120,0,
+ /* 24008 */ 0240,0202,045,0303,01,072,0110,0,
+ /* 24016 */ 0241,0202,051,0303,01,072,0120,0,
+ /* 24024 */ 0240,0202,051,0303,01,072,0110,0,
+ /* 24032 */ 0250,0202,02,0300,01,051,0110,0,
+ /* 24040 */ 0250,0202,06,0300,01,051,0110,0,
+ /* 24048 */ 0250,0202,012,0300,01,051,0110,0,
+ /* 24056 */ 0250,0202,02,0300,01,071,0110,0,
+ /* 24064 */ 0250,0202,06,0300,01,071,0110,0,
+ /* 24072 */ 0250,0202,012,0300,01,071,0110,0,
+ /* 24080 */ 0250,0202,02,0300,01,061,0101,0,
+ /* 24088 */ 0250,0202,06,0300,01,061,0101,0,
+ /* 24096 */ 0250,0202,012,0300,01,061,0101,0,
+ /* 24104 */ 0250,0202,02,0315,01,061,0101,0,
+ /* 24112 */ 0250,0202,06,0315,01,061,0101,0,
+ /* 24120 */ 0250,0202,012,0315,01,061,0101,0,
+ /* 24128 */ 0250,0202,02,0300,01,063,0101,0,
+ /* 24136 */ 0250,0202,06,0300,01,063,0101,0,
+ /* 24144 */ 0250,0202,012,0300,01,063,0101,0,
+ /* 24152 */ 0250,0202,02,0314,01,063,0101,0,
+ /* 24160 */ 0250,0202,06,0314,01,063,0101,0,
+ /* 24168 */ 0250,0202,012,0314,01,063,0101,0,
+ /* 24176 */ 0250,0202,02,0300,01,050,0110,0,
+ /* 24184 */ 0250,0202,06,0300,01,050,0110,0,
+ /* 24192 */ 0250,0202,012,0300,01,050,0110,0,
+ /* 24200 */ 0250,0202,02,0300,01,070,0110,0,
+ /* 24208 */ 0250,0202,06,0300,01,070,0110,0,
+ /* 24216 */ 0250,0202,012,0300,01,070,0110,0,
+ /* 24224 */ 0250,0202,022,0300,01,070,0110,0,
+ /* 24232 */ 0250,0202,026,0300,01,070,0110,0,
+ /* 24240 */ 0250,0202,032,0300,01,070,0110,0,
+ /* 24248 */ 0250,0202,022,0300,01,050,0110,0,
+ /* 24256 */ 0250,0202,026,0300,01,050,0110,0,
+ /* 24264 */ 0250,0202,032,0300,01,050,0110,0,
+ /* 24272 */ 0250,0202,022,0300,01,071,0110,0,
+ /* 24280 */ 0250,0202,026,0300,01,071,0110,0,
+ /* 24288 */ 0250,0202,032,0300,01,071,0110,0,
+ /* 24296 */ 0250,0202,02,0300,01,062,0101,0,
+ /* 24304 */ 0250,0202,06,0300,01,062,0101,0,
+ /* 24312 */ 0250,0202,012,0300,01,062,0101,0,
+ /* 24320 */ 0250,0202,02,0316,01,062,0101,0,
+ /* 24328 */ 0250,0202,06,0316,01,062,0101,0,
+ /* 24336 */ 0250,0202,012,0316,01,062,0101,0,
+ /* 24344 */ 0250,0202,02,0300,01,065,0101,0,
+ /* 24352 */ 0250,0202,06,0300,01,065,0101,0,
+ /* 24360 */ 0250,0202,012,0300,01,065,0101,0,
+ /* 24368 */ 0250,0202,02,0314,01,065,0101,0,
+ /* 24376 */ 0250,0202,06,0314,01,065,0101,0,
+ /* 24384 */ 0250,0202,012,0314,01,065,0101,0,
+ /* 24392 */ 0250,0202,02,0300,01,064,0101,0,
+ /* 24400 */ 0250,0202,06,0300,01,064,0101,0,
+ /* 24408 */ 0250,0202,012,0300,01,064,0101,0,
+ /* 24416 */ 0250,0202,02,0315,01,064,0101,0,
+ /* 24424 */ 0250,0202,06,0315,01,064,0101,0,
+ /* 24432 */ 0250,0202,012,0315,01,064,0101,0,
+ /* 24440 */ 0250,0202,02,0300,01,041,0101,0,
+ /* 24448 */ 0250,0202,06,0300,01,041,0101,0,
+ /* 24456 */ 0250,0202,012,0300,01,041,0101,0,
+ /* 24464 */ 0250,0202,02,0315,01,041,0101,0,
+ /* 24472 */ 0250,0202,06,0315,01,041,0101,0,
+ /* 24480 */ 0250,0202,012,0315,01,041,0101,0,
+ /* 24488 */ 0250,0202,02,0300,01,043,0101,0,
+ /* 24496 */ 0250,0202,06,0300,01,043,0101,0,
+ /* 24504 */ 0250,0202,012,0300,01,043,0101,0,
+ /* 24512 */ 0250,0202,02,0314,01,043,0101,0,
+ /* 24520 */ 0250,0202,06,0314,01,043,0101,0,
+ /* 24528 */ 0250,0202,012,0314,01,043,0101,0,
+ /* 24536 */ 0250,0202,02,0300,01,042,0101,0,
+ /* 24544 */ 0250,0202,06,0300,01,042,0101,0,
+ /* 24552 */ 0250,0202,012,0300,01,042,0101,0,
+ /* 24560 */ 0250,0202,02,0316,01,042,0101,0,
+ /* 24568 */ 0250,0202,06,0316,01,042,0101,0,
+ /* 24576 */ 0250,0202,012,0316,01,042,0101,0,
+ /* 24584 */ 0250,0202,02,0300,01,045,0101,0,
+ /* 24592 */ 0250,0202,06,0300,01,045,0101,0,
+ /* 24600 */ 0250,0202,012,0300,01,045,0101,0,
+ /* 24608 */ 0250,0202,02,0314,01,045,0101,0,
+ /* 24616 */ 0250,0202,06,0314,01,045,0101,0,
+ /* 24624 */ 0250,0202,012,0314,01,045,0101,0,
+ /* 24632 */ 0250,0202,02,0300,01,044,0101,0,
+ /* 24640 */ 0250,0202,06,0300,01,044,0101,0,
+ /* 24648 */ 0250,0202,012,0300,01,044,0101,0,
+ /* 24656 */ 0250,0202,02,0315,01,044,0101,0,
+ /* 24664 */ 0250,0202,06,0315,01,044,0101,0,
+ /* 24672 */ 0250,0202,012,0315,01,044,0101,0,
+ /* 24680 */ 0250,0202,02,0300,01,040,0101,0,
+ /* 24688 */ 0250,0202,06,0300,01,040,0101,0,
+ /* 24696 */ 0250,0202,012,0300,01,040,0101,0,
+ /* 24704 */ 0250,0202,02,0314,01,040,0101,0,
+ /* 24712 */ 0250,0202,06,0314,01,040,0101,0,
+ /* 24720 */ 0250,0202,012,0314,01,040,0101,0,
+ /* 24728 */ 0250,0202,041,0315,01,041,0110,0,
+ /* 24736 */ 0250,0202,045,0315,01,041,0110,0,
+ /* 24744 */ 0250,0202,051,0315,01,041,0110,0,
+ /* 24752 */ 0250,0202,041,0316,01,042,0110,0,
+ /* 24760 */ 0250,0202,045,0316,01,042,0110,0,
+ /* 24768 */ 0250,0202,051,0316,01,042,0110,0,
+ /* 24776 */ 0250,0202,041,0314,01,040,0110,0,
+ /* 24784 */ 0250,0202,045,0314,01,040,0110,0,
+ /* 24792 */ 0250,0202,051,0314,01,040,0110,0,
+ /* 24800 */ 0250,0202,01,0314,01,045,0110,0,
+ /* 24808 */ 0250,0202,05,0314,01,045,0110,0,
+ /* 24816 */ 0250,0202,011,0314,01,045,0110,0,
+ /* 24824 */ 0250,0202,041,0314,01,043,0110,0,
+ /* 24832 */ 0250,0202,045,0314,01,043,0110,0,
+ /* 24840 */ 0250,0202,051,0314,01,043,0110,0,
+ /* 24848 */ 0250,0202,041,0315,01,044,0110,0,
+ /* 24856 */ 0250,0202,045,0315,01,044,0110,0,
+ /* 24864 */ 0250,0202,051,0315,01,044,0110,0,
+ /* 24872 */ 0250,0202,02,0300,01,021,0101,0,
+ /* 24880 */ 0250,0202,06,0300,01,021,0101,0,
+ /* 24888 */ 0250,0202,012,0300,01,021,0101,0,
+ /* 24896 */ 0250,0202,02,0315,01,021,0101,0,
+ /* 24904 */ 0250,0202,06,0315,01,021,0101,0,
+ /* 24912 */ 0250,0202,012,0315,01,021,0101,0,
+ /* 24920 */ 0250,0202,02,0300,01,023,0101,0,
+ /* 24928 */ 0250,0202,06,0300,01,023,0101,0,
+ /* 24936 */ 0250,0202,012,0300,01,023,0101,0,
+ /* 24944 */ 0250,0202,02,0314,01,023,0101,0,
+ /* 24952 */ 0250,0202,06,0314,01,023,0101,0,
+ /* 24960 */ 0250,0202,012,0314,01,023,0101,0,
+ /* 24968 */ 0250,0202,02,0300,01,022,0101,0,
+ /* 24976 */ 0250,0202,06,0300,01,022,0101,0,
+ /* 24984 */ 0250,0202,012,0300,01,022,0101,0,
+ /* 24992 */ 0250,0202,02,0316,01,022,0101,0,
+ /* 25000 */ 0250,0202,06,0316,01,022,0101,0,
+ /* 25008 */ 0250,0202,012,0316,01,022,0101,0,
+ /* 25016 */ 0250,0202,02,0300,01,025,0101,0,
+ /* 25024 */ 0250,0202,06,0300,01,025,0101,0,
+ /* 25032 */ 0250,0202,012,0300,01,025,0101,0,
+ /* 25040 */ 0250,0202,02,0314,01,025,0101,0,
+ /* 25048 */ 0250,0202,06,0314,01,025,0101,0,
+ /* 25056 */ 0250,0202,012,0314,01,025,0101,0,
+ /* 25064 */ 0250,0202,02,0300,01,024,0101,0,
+ /* 25072 */ 0250,0202,06,0300,01,024,0101,0,
+ /* 25080 */ 0250,0202,012,0300,01,024,0101,0,
+ /* 25088 */ 0250,0202,02,0315,01,024,0101,0,
+ /* 25096 */ 0250,0202,06,0315,01,024,0101,0,
+ /* 25104 */ 0250,0202,012,0315,01,024,0101,0,
+ /* 25112 */ 0250,0202,02,0300,01,020,0101,0,
+ /* 25120 */ 0250,0202,06,0300,01,020,0101,0,
+ /* 25128 */ 0250,0202,012,0300,01,020,0101,0,
+ /* 25136 */ 0250,0202,02,0314,01,020,0101,0,
+ /* 25144 */ 0250,0202,06,0314,01,020,0101,0,
+ /* 25152 */ 0250,0202,012,0314,01,020,0101,0,
+ /* 25160 */ 0250,0202,022,0300,01,051,0110,0,
+ /* 25168 */ 0250,0202,026,0300,01,051,0110,0,
+ /* 25176 */ 0250,0202,032,0300,01,051,0110,0,
+ /* 25184 */ 0250,0202,02,0300,01,060,0101,0,
+ /* 25192 */ 0250,0202,06,0300,01,060,0101,0,
+ /* 25200 */ 0250,0202,012,0300,01,060,0101,0,
+ /* 25208 */ 0250,0202,02,0314,01,060,0101,0,
+ /* 25216 */ 0250,0202,06,0314,01,060,0101,0,
+ /* 25224 */ 0250,0202,012,0314,01,060,0101,0,
+ /* 25232 */ 0250,0202,041,0315,01,061,0110,0,
+ /* 25240 */ 0250,0202,045,0315,01,061,0110,0,
+ /* 25248 */ 0250,0202,051,0315,01,061,0110,0,
+ /* 25256 */ 0250,0202,041,0316,01,062,0110,0,
+ /* 25264 */ 0250,0202,045,0316,01,062,0110,0,
+ /* 25272 */ 0250,0202,051,0316,01,062,0110,0,
+ /* 25280 */ 0250,0202,041,0314,01,060,0110,0,
+ /* 25288 */ 0250,0202,045,0314,01,060,0110,0,
+ /* 25296 */ 0250,0202,051,0314,01,060,0110,0,
+ /* 25304 */ 0250,0202,01,0314,01,065,0110,0,
+ /* 25312 */ 0250,0202,05,0314,01,065,0110,0,
+ /* 25320 */ 0250,0202,011,0314,01,065,0110,0,
+ /* 25328 */ 0250,0202,041,0314,01,063,0110,0,
+ /* 25336 */ 0250,0202,045,0314,01,063,0110,0,
+ /* 25344 */ 0250,0202,051,0314,01,063,0110,0,
+ /* 25352 */ 0250,0202,041,0315,01,064,0110,0,
+ /* 25360 */ 0250,0202,045,0315,01,064,0110,0,
+ /* 25368 */ 0250,0202,051,0315,01,064,0110,0,
+ /* 25376 */ 0241,0202,021,0301,01,050,0120,0,
+ /* 25384 */ 0240,0202,021,0301,01,050,0110,0,
+ /* 25392 */ 0241,0202,025,0301,01,050,0120,0,
+ /* 25400 */ 0240,0202,025,0301,01,050,0110,0,
+ /* 25408 */ 0241,0202,031,0301,01,050,0120,0,
+ /* 25416 */ 0240,0202,031,0301,01,050,0110,0,
+ /* 25424 */ 0241,0202,041,0303,01,013,0120,0,
+ /* 25432 */ 0240,0202,041,0303,01,013,0110,0,
+ /* 25440 */ 0241,0202,045,0303,01,013,0120,0,
+ /* 25448 */ 0240,0202,045,0303,01,013,0110,0,
+ /* 25456 */ 0241,0202,051,0303,01,013,0120,0,
+ /* 25464 */ 0240,0202,051,0303,01,013,0110,0,
+ /* 25472 */ 0241,0201,041,0303,01,0344,0120,0,
+ /* 25480 */ 0240,0201,041,0303,01,0344,0110,0,
+ /* 25488 */ 0241,0201,045,0303,01,0344,0120,0,
+ /* 25496 */ 0240,0201,045,0303,01,0344,0110,0,
+ /* 25504 */ 0241,0201,051,0303,01,0344,0120,0,
+ /* 25512 */ 0240,0201,051,0303,01,0344,0110,0,
+ /* 25520 */ 0241,0201,041,0303,01,0345,0120,0,
+ /* 25528 */ 0240,0201,041,0303,01,0345,0110,0,
+ /* 25536 */ 0241,0201,045,0303,01,0345,0120,0,
+ /* 25544 */ 0240,0201,045,0303,01,0345,0110,0,
+ /* 25552 */ 0241,0201,051,0303,01,0345,0120,0,
+ /* 25560 */ 0240,0201,051,0303,01,0345,0110,0,
+ /* 25568 */ 0241,0202,01,0301,01,0100,0120,0,
+ /* 25576 */ 0240,0202,01,0301,01,0100,0110,0,
+ /* 25584 */ 0241,0202,05,0301,01,0100,0120,0,
+ /* 25592 */ 0240,0202,05,0301,01,0100,0110,0,
+ /* 25600 */ 0241,0202,011,0301,01,0100,0120,0,
+ /* 25608 */ 0240,0202,011,0301,01,0100,0110,0,
+ /* 25616 */ 0241,0202,021,0301,01,0100,0120,0,
+ /* 25624 */ 0240,0202,021,0301,01,0100,0110,0,
+ /* 25632 */ 0241,0202,025,0301,01,0100,0120,0,
+ /* 25640 */ 0240,0202,025,0301,01,0100,0110,0,
+ /* 25648 */ 0241,0202,031,0301,01,0100,0120,0,
+ /* 25656 */ 0240,0202,031,0301,01,0100,0110,0,
+ /* 25664 */ 0241,0201,041,0303,01,0325,0120,0,
+ /* 25672 */ 0240,0201,041,0303,01,0325,0110,0,
+ /* 25680 */ 0241,0201,045,0303,01,0325,0120,0,
+ /* 25688 */ 0240,0201,045,0303,01,0325,0110,0,
+ /* 25696 */ 0241,0201,051,0303,01,0325,0120,0,
+ /* 25704 */ 0240,0201,051,0303,01,0325,0110,0,
+ /* 25712 */ 0241,0202,021,0301,01,0203,0120,0,
+ /* 25720 */ 0240,0202,021,0301,01,0203,0110,0,
+ /* 25728 */ 0241,0202,025,0301,01,0203,0120,0,
+ /* 25736 */ 0240,0202,025,0301,01,0203,0110,0,
+ /* 25744 */ 0241,0202,031,0301,01,0203,0120,0,
+ /* 25752 */ 0240,0202,031,0301,01,0203,0110,0,
+ /* 25760 */ 0241,0201,021,0301,01,0364,0120,0,
+ /* 25768 */ 0240,0201,021,0301,01,0364,0110,0,
+ /* 25776 */ 0241,0201,025,0301,01,0364,0120,0,
+ /* 25784 */ 0240,0201,025,0301,01,0364,0110,0,
+ /* 25792 */ 0241,0201,031,0301,01,0364,0120,0,
+ /* 25800 */ 0240,0201,031,0301,01,0364,0110,0,
+ /* 25808 */ 0241,0201,01,0301,01,0353,0120,0,
+ /* 25816 */ 0240,0201,01,0301,01,0353,0110,0,
+ /* 25824 */ 0241,0201,05,0301,01,0353,0120,0,
+ /* 25832 */ 0240,0201,05,0301,01,0353,0110,0,
+ /* 25840 */ 0241,0201,011,0301,01,0353,0120,0,
+ /* 25848 */ 0240,0201,011,0301,01,0353,0110,0,
+ /* 25856 */ 0241,0201,021,0301,01,0353,0120,0,
+ /* 25864 */ 0240,0201,021,0301,01,0353,0110,0,
+ /* 25872 */ 0241,0201,025,0301,01,0353,0120,0,
+ /* 25880 */ 0240,0201,025,0301,01,0353,0110,0,
+ /* 25888 */ 0241,0201,031,0301,01,0353,0120,0,
+ /* 25896 */ 0240,0201,031,0301,01,0353,0110,0,
+ /* 25904 */ 0241,0202,01,0301,01,025,0120,0,
+ /* 25912 */ 0240,0202,01,0301,01,025,0110,0,
+ /* 25920 */ 0241,0202,05,0301,01,025,0120,0,
+ /* 25928 */ 0240,0202,05,0301,01,025,0110,0,
+ /* 25936 */ 0241,0202,011,0301,01,025,0120,0,
+ /* 25944 */ 0240,0202,011,0301,01,025,0110,0,
+ /* 25952 */ 0241,0202,021,0301,01,025,0120,0,
+ /* 25960 */ 0240,0202,021,0301,01,025,0110,0,
+ /* 25968 */ 0241,0202,025,0301,01,025,0120,0,
+ /* 25976 */ 0240,0202,025,0301,01,025,0110,0,
+ /* 25984 */ 0241,0202,031,0301,01,025,0120,0,
+ /* 25992 */ 0240,0202,031,0301,01,025,0110,0,
+ /* 26000 */ 0241,0202,01,0301,01,024,0120,0,
+ /* 26008 */ 0240,0202,01,0301,01,024,0110,0,
+ /* 26016 */ 0241,0202,05,0301,01,024,0120,0,
+ /* 26024 */ 0240,0202,05,0301,01,024,0110,0,
+ /* 26032 */ 0241,0202,011,0301,01,024,0120,0,
+ /* 26040 */ 0240,0202,011,0301,01,024,0110,0,
+ /* 26048 */ 0241,0202,021,0301,01,024,0120,0,
+ /* 26056 */ 0240,0202,021,0301,01,024,0110,0,
+ /* 26064 */ 0241,0202,025,0301,01,024,0120,0,
+ /* 26072 */ 0240,0202,025,0301,01,024,0110,0,
+ /* 26080 */ 0241,0202,031,0301,01,024,0120,0,
+ /* 26088 */ 0240,0202,031,0301,01,024,0110,0,
+ /* 26096 */ 0241,0201,041,0303,01,0366,0120,0,
+ /* 26104 */ 0240,0201,041,0303,01,0366,0110,0,
+ /* 26112 */ 0241,0201,045,0303,01,0366,0120,0,
+ /* 26120 */ 0240,0201,045,0303,01,0366,0110,0,
+ /* 26128 */ 0241,0201,051,0303,01,0366,0120,0,
+ /* 26136 */ 0240,0201,051,0303,01,0366,0110,0,
+ /* 26144 */ 0241,0202,041,0303,01,0,0120,0,
+ /* 26152 */ 0240,0202,041,0303,01,0,0110,0,
+ /* 26160 */ 0241,0202,045,0303,01,0,0120,0,
+ /* 26168 */ 0240,0202,045,0303,01,0,0110,0,
+ /* 26176 */ 0241,0202,051,0303,01,0,0120,0,
+ /* 26184 */ 0240,0202,051,0303,01,0,0110,0,
+ /* 26192 */ 0241,0201,01,0317,01,0362,0120,0,
+ /* 26200 */ 0240,0201,01,0317,01,0362,0110,0,
+ /* 26208 */ 0241,0201,05,0317,01,0362,0120,0,
+ /* 26216 */ 0240,0201,05,0317,01,0362,0110,0,
+ /* 26224 */ 0241,0201,011,0317,01,0362,0120,0,
+ /* 26232 */ 0240,0201,011,0317,01,0362,0110,0,
+ /* 26240 */ 0241,0201,021,0317,01,0363,0120,0,
+ /* 26248 */ 0240,0201,021,0317,01,0363,0110,0,
+ /* 26256 */ 0241,0201,025,0317,01,0363,0120,0,
+ /* 26264 */ 0240,0201,025,0317,01,0363,0110,0,
+ /* 26272 */ 0241,0201,031,0317,01,0363,0120,0,
+ /* 26280 */ 0240,0201,031,0317,01,0363,0110,0,
+ /* 26288 */ 0241,0202,01,0301,01,0107,0120,0,
+ /* 26296 */ 0240,0202,01,0301,01,0107,0110,0,
+ /* 26304 */ 0241,0202,05,0301,01,0107,0120,0,
+ /* 26312 */ 0240,0202,05,0301,01,0107,0110,0,
+ /* 26320 */ 0241,0202,011,0301,01,0107,0120,0,
+ /* 26328 */ 0240,0202,011,0301,01,0107,0110,0,
+ /* 26336 */ 0241,0202,021,0301,01,0107,0120,0,
+ /* 26344 */ 0240,0202,021,0301,01,0107,0110,0,
+ /* 26352 */ 0241,0202,025,0301,01,0107,0120,0,
+ /* 26360 */ 0240,0202,025,0301,01,0107,0110,0,
+ /* 26368 */ 0241,0202,031,0301,01,0107,0120,0,
+ /* 26376 */ 0240,0202,031,0301,01,0107,0110,0,
+ /* 26384 */ 0241,0202,021,0303,01,022,0120,0,
+ /* 26392 */ 0240,0202,021,0303,01,022,0110,0,
+ /* 26400 */ 0241,0202,025,0303,01,022,0120,0,
+ /* 26408 */ 0240,0202,025,0303,01,022,0110,0,
+ /* 26416 */ 0241,0202,031,0303,01,022,0120,0,
+ /* 26424 */ 0240,0202,031,0303,01,022,0110,0,
+ /* 26432 */ 0241,0201,041,0317,01,0361,0120,0,
+ /* 26440 */ 0240,0201,041,0317,01,0361,0110,0,
+ /* 26448 */ 0241,0201,045,0317,01,0361,0120,0,
+ /* 26456 */ 0240,0201,045,0317,01,0361,0110,0,
+ /* 26464 */ 0241,0201,051,0317,01,0361,0120,0,
+ /* 26472 */ 0240,0201,051,0317,01,0361,0110,0,
+ /* 26480 */ 0241,0201,01,0317,01,0342,0120,0,
+ /* 26488 */ 0240,0201,01,0317,01,0342,0110,0,
+ /* 26496 */ 0241,0201,05,0317,01,0342,0120,0,
+ /* 26504 */ 0240,0201,05,0317,01,0342,0110,0,
+ /* 26512 */ 0241,0201,011,0317,01,0342,0120,0,
+ /* 26520 */ 0240,0201,011,0317,01,0342,0110,0,
+ /* 26528 */ 0241,0201,021,0317,01,0342,0120,0,
+ /* 26536 */ 0240,0201,021,0317,01,0342,0110,0,
+ /* 26544 */ 0241,0201,025,0317,01,0342,0120,0,
+ /* 26552 */ 0240,0201,025,0317,01,0342,0110,0,
+ /* 26560 */ 0241,0201,031,0317,01,0342,0120,0,
+ /* 26568 */ 0240,0201,031,0317,01,0342,0110,0,
+ /* 26576 */ 0241,0202,01,0301,01,0106,0120,0,
+ /* 26584 */ 0240,0202,01,0301,01,0106,0110,0,
+ /* 26592 */ 0241,0202,05,0301,01,0106,0120,0,
+ /* 26600 */ 0240,0202,05,0301,01,0106,0110,0,
+ /* 26608 */ 0241,0202,011,0301,01,0106,0120,0,
+ /* 26616 */ 0240,0202,011,0301,01,0106,0110,0,
+ /* 26624 */ 0241,0202,021,0301,01,0106,0120,0,
+ /* 26632 */ 0240,0202,021,0301,01,0106,0110,0,
+ /* 26640 */ 0241,0202,025,0301,01,0106,0120,0,
+ /* 26648 */ 0240,0202,025,0301,01,0106,0110,0,
+ /* 26656 */ 0241,0202,031,0301,01,0106,0120,0,
+ /* 26664 */ 0240,0202,031,0301,01,0106,0110,0,
+ /* 26672 */ 0241,0202,021,0303,01,021,0120,0,
+ /* 26680 */ 0240,0202,021,0303,01,021,0110,0,
+ /* 26688 */ 0241,0202,025,0303,01,021,0120,0,
+ /* 26696 */ 0240,0202,025,0303,01,021,0110,0,
+ /* 26704 */ 0241,0202,031,0303,01,021,0120,0,
+ /* 26712 */ 0240,0202,031,0303,01,021,0110,0,
+ /* 26720 */ 0241,0201,041,0317,01,0341,0120,0,
+ /* 26728 */ 0240,0201,041,0317,01,0341,0110,0,
+ /* 26736 */ 0241,0201,045,0317,01,0341,0120,0,
+ /* 26744 */ 0240,0201,045,0317,01,0341,0110,0,
+ /* 26752 */ 0241,0201,051,0317,01,0341,0120,0,
+ /* 26760 */ 0240,0201,051,0317,01,0341,0110,0,
+ /* 26768 */ 0241,0201,01,0317,01,0322,0120,0,
+ /* 26776 */ 0240,0201,01,0317,01,0322,0110,0,
+ /* 26784 */ 0241,0201,05,0317,01,0322,0120,0,
+ /* 26792 */ 0240,0201,05,0317,01,0322,0110,0,
+ /* 26800 */ 0241,0201,011,0317,01,0322,0120,0,
+ /* 26808 */ 0240,0201,011,0317,01,0322,0110,0,
+ /* 26816 */ 0241,0201,021,0317,01,0323,0120,0,
+ /* 26824 */ 0240,0201,021,0317,01,0323,0110,0,
+ /* 26832 */ 0241,0201,025,0317,01,0323,0120,0,
+ /* 26840 */ 0240,0201,025,0317,01,0323,0110,0,
+ /* 26848 */ 0241,0201,031,0317,01,0323,0120,0,
+ /* 26856 */ 0240,0201,031,0317,01,0323,0110,0,
+ /* 26864 */ 0241,0202,01,0301,01,0105,0120,0,
+ /* 26872 */ 0240,0202,01,0301,01,0105,0110,0,
+ /* 26880 */ 0241,0202,05,0301,01,0105,0120,0,
+ /* 26888 */ 0240,0202,05,0301,01,0105,0110,0,
+ /* 26896 */ 0241,0202,011,0301,01,0105,0120,0,
+ /* 26904 */ 0240,0202,011,0301,01,0105,0110,0,
+ /* 26912 */ 0241,0202,021,0301,01,0105,0120,0,
+ /* 26920 */ 0240,0202,021,0301,01,0105,0110,0,
+ /* 26928 */ 0241,0202,025,0301,01,0105,0120,0,
+ /* 26936 */ 0240,0202,025,0301,01,0105,0110,0,
+ /* 26944 */ 0241,0202,031,0301,01,0105,0120,0,
+ /* 26952 */ 0240,0202,031,0301,01,0105,0110,0,
+ /* 26960 */ 0241,0202,021,0303,01,020,0120,0,
+ /* 26968 */ 0240,0202,021,0303,01,020,0110,0,
+ /* 26976 */ 0241,0202,025,0303,01,020,0120,0,
+ /* 26984 */ 0240,0202,025,0303,01,020,0110,0,
+ /* 26992 */ 0241,0202,031,0303,01,020,0120,0,
+ /* 27000 */ 0240,0202,031,0303,01,020,0110,0,
+ /* 27008 */ 0241,0201,041,0317,01,0321,0120,0,
+ /* 27016 */ 0240,0201,041,0317,01,0321,0110,0,
+ /* 27024 */ 0241,0201,045,0317,01,0321,0120,0,
+ /* 27032 */ 0240,0201,045,0317,01,0321,0110,0,
+ /* 27040 */ 0241,0201,051,0317,01,0321,0120,0,
+ /* 27048 */ 0240,0201,051,0317,01,0321,0110,0,
+ /* 27056 */ 0241,0201,041,0303,01,0370,0120,0,
+ /* 27064 */ 0240,0201,041,0303,01,0370,0110,0,
+ /* 27072 */ 0241,0201,045,0303,01,0370,0120,0,
+ /* 27080 */ 0240,0201,045,0303,01,0370,0110,0,
+ /* 27088 */ 0241,0201,051,0303,01,0370,0120,0,
+ /* 27096 */ 0240,0201,051,0303,01,0370,0110,0,
+ /* 27104 */ 0241,0201,01,0301,01,0372,0120,0,
+ /* 27112 */ 0240,0201,01,0301,01,0372,0110,0,
+ /* 27120 */ 0241,0201,05,0301,01,0372,0120,0,
+ /* 27128 */ 0240,0201,05,0301,01,0372,0110,0,
+ /* 27136 */ 0241,0201,011,0301,01,0372,0120,0,
+ /* 27144 */ 0240,0201,011,0301,01,0372,0110,0,
+ /* 27152 */ 0241,0201,021,0301,01,0373,0120,0,
+ /* 27160 */ 0240,0201,021,0301,01,0373,0110,0,
+ /* 27168 */ 0241,0201,025,0301,01,0373,0120,0,
+ /* 27176 */ 0240,0201,025,0301,01,0373,0110,0,
+ /* 27184 */ 0241,0201,031,0301,01,0373,0120,0,
+ /* 27192 */ 0240,0201,031,0301,01,0373,0110,0,
+ /* 27200 */ 0241,0201,041,0303,01,0350,0120,0,
+ /* 27208 */ 0240,0201,041,0303,01,0350,0110,0,
+ /* 27216 */ 0241,0201,045,0303,01,0350,0120,0,
+ /* 27224 */ 0240,0201,045,0303,01,0350,0110,0,
+ /* 27232 */ 0241,0201,051,0303,01,0350,0120,0,
+ /* 27240 */ 0240,0201,051,0303,01,0350,0110,0,
+ /* 27248 */ 0241,0201,041,0303,01,0351,0120,0,
+ /* 27256 */ 0240,0201,041,0303,01,0351,0110,0,
+ /* 27264 */ 0241,0201,045,0303,01,0351,0120,0,
+ /* 27272 */ 0240,0201,045,0303,01,0351,0110,0,
+ /* 27280 */ 0241,0201,051,0303,01,0351,0120,0,
+ /* 27288 */ 0240,0201,051,0303,01,0351,0110,0,
+ /* 27296 */ 0241,0201,041,0303,01,0330,0120,0,
+ /* 27304 */ 0240,0201,041,0303,01,0330,0110,0,
+ /* 27312 */ 0241,0201,045,0303,01,0330,0120,0,
+ /* 27320 */ 0240,0201,045,0303,01,0330,0110,0,
+ /* 27328 */ 0241,0201,051,0303,01,0330,0120,0,
+ /* 27336 */ 0240,0201,051,0303,01,0330,0110,0,
+ /* 27344 */ 0241,0201,041,0303,01,0331,0120,0,
+ /* 27352 */ 0240,0201,041,0303,01,0331,0110,0,
+ /* 27360 */ 0241,0201,045,0303,01,0331,0120,0,
+ /* 27368 */ 0240,0201,045,0303,01,0331,0110,0,
+ /* 27376 */ 0241,0201,051,0303,01,0331,0120,0,
+ /* 27384 */ 0240,0201,051,0303,01,0331,0110,0,
+ /* 27392 */ 0241,0201,041,0303,01,0371,0120,0,
+ /* 27400 */ 0240,0201,041,0303,01,0371,0110,0,
+ /* 27408 */ 0241,0201,045,0303,01,0371,0120,0,
+ /* 27416 */ 0240,0201,045,0303,01,0371,0110,0,
+ /* 27424 */ 0241,0201,051,0303,01,0371,0120,0,
+ /* 27432 */ 0240,0201,051,0303,01,0371,0110,0,
+ /* 27440 */ 0241,0202,01,0303,01,046,0120,0,
+ /* 27448 */ 0241,0202,05,0303,01,046,0120,0,
+ /* 27456 */ 0241,0202,011,0303,01,046,0120,0,
+ /* 27464 */ 0241,0202,01,0301,01,047,0120,0,
+ /* 27472 */ 0241,0202,05,0301,01,047,0120,0,
+ /* 27480 */ 0241,0202,011,0301,01,047,0120,0,
+ /* 27488 */ 0241,0202,021,0301,01,047,0120,0,
+ /* 27496 */ 0241,0202,025,0301,01,047,0120,0,
+ /* 27504 */ 0241,0202,031,0301,01,047,0120,0,
+ /* 27512 */ 0241,0202,021,0303,01,046,0120,0,
+ /* 27520 */ 0241,0202,025,0303,01,046,0120,0,
+ /* 27528 */ 0241,0202,031,0303,01,046,0120,0,
+ /* 27536 */ 0241,0202,02,0303,01,046,0120,0,
+ /* 27544 */ 0241,0202,06,0303,01,046,0120,0,
+ /* 27552 */ 0241,0202,012,0303,01,046,0120,0,
+ /* 27560 */ 0241,0202,02,0301,01,047,0120,0,
+ /* 27568 */ 0241,0202,06,0301,01,047,0120,0,
+ /* 27576 */ 0241,0202,012,0301,01,047,0120,0,
+ /* 27584 */ 0241,0202,022,0301,01,047,0120,0,
+ /* 27592 */ 0241,0202,026,0301,01,047,0120,0,
+ /* 27600 */ 0241,0202,032,0301,01,047,0120,0,
+ /* 27608 */ 0241,0202,022,0303,01,046,0120,0,
+ /* 27616 */ 0241,0202,026,0303,01,046,0120,0,
+ /* 27624 */ 0241,0202,032,0303,01,046,0120,0,
+ /* 27632 */ 0241,0201,041,0303,01,0150,0120,0,
+ /* 27640 */ 0240,0201,041,0303,01,0150,0110,0,
+ /* 27648 */ 0241,0201,045,0303,01,0150,0120,0,
+ /* 27656 */ 0240,0201,045,0303,01,0150,0110,0,
+ /* 27664 */ 0241,0201,051,0303,01,0150,0120,0,
+ /* 27672 */ 0240,0201,051,0303,01,0150,0110,0,
+ /* 27680 */ 0241,0201,01,0301,01,0152,0120,0,
+ /* 27688 */ 0240,0201,01,0301,01,0152,0110,0,
+ /* 27696 */ 0241,0201,05,0301,01,0152,0120,0,
+ /* 27704 */ 0240,0201,05,0301,01,0152,0110,0,
+ /* 27712 */ 0241,0201,011,0301,01,0152,0120,0,
+ /* 27720 */ 0240,0201,011,0301,01,0152,0110,0,
+ /* 27728 */ 0241,0201,021,0301,01,0155,0120,0,
+ /* 27736 */ 0240,0201,021,0301,01,0155,0110,0,
+ /* 27744 */ 0241,0201,025,0301,01,0155,0120,0,
+ /* 27752 */ 0240,0201,025,0301,01,0155,0110,0,
+ /* 27760 */ 0241,0201,031,0301,01,0155,0120,0,
+ /* 27768 */ 0240,0201,031,0301,01,0155,0110,0,
+ /* 27776 */ 0241,0201,041,0303,01,0151,0120,0,
+ /* 27784 */ 0240,0201,041,0303,01,0151,0110,0,
+ /* 27792 */ 0241,0201,045,0303,01,0151,0120,0,
+ /* 27800 */ 0240,0201,045,0303,01,0151,0110,0,
+ /* 27808 */ 0241,0201,051,0303,01,0151,0120,0,
+ /* 27816 */ 0240,0201,051,0303,01,0151,0110,0,
+ /* 27824 */ 0241,0201,041,0303,01,0140,0120,0,
+ /* 27832 */ 0240,0201,041,0303,01,0140,0110,0,
+ /* 27840 */ 0241,0201,045,0303,01,0140,0120,0,
+ /* 27848 */ 0240,0201,045,0303,01,0140,0110,0,
+ /* 27856 */ 0241,0201,051,0303,01,0140,0120,0,
+ /* 27864 */ 0240,0201,051,0303,01,0140,0110,0,
+ /* 27872 */ 0241,0201,01,0301,01,0142,0120,0,
+ /* 27880 */ 0240,0201,01,0301,01,0142,0110,0,
+ /* 27888 */ 0241,0201,05,0301,01,0142,0120,0,
+ /* 27896 */ 0240,0201,05,0301,01,0142,0110,0,
+ /* 27904 */ 0241,0201,011,0301,01,0142,0120,0,
+ /* 27912 */ 0240,0201,011,0301,01,0142,0110,0,
+ /* 27920 */ 0241,0201,021,0301,01,0154,0120,0,
+ /* 27928 */ 0240,0201,021,0301,01,0154,0110,0,
+ /* 27936 */ 0241,0201,025,0301,01,0154,0120,0,
+ /* 27944 */ 0240,0201,025,0301,01,0154,0110,0,
+ /* 27952 */ 0241,0201,031,0301,01,0154,0120,0,
+ /* 27960 */ 0240,0201,031,0301,01,0154,0110,0,
+ /* 27968 */ 0241,0201,041,0303,01,0141,0120,0,
+ /* 27976 */ 0240,0201,041,0303,01,0141,0110,0,
+ /* 27984 */ 0241,0201,045,0303,01,0141,0120,0,
+ /* 27992 */ 0240,0201,045,0303,01,0141,0110,0,
+ /* 28000 */ 0241,0201,051,0303,01,0141,0120,0,
+ /* 28008 */ 0240,0201,051,0303,01,0141,0110,0,
+ /* 28016 */ 0241,0201,01,0301,01,0357,0120,0,
+ /* 28024 */ 0240,0201,01,0301,01,0357,0110,0,
+ /* 28032 */ 0241,0201,05,0301,01,0357,0120,0,
+ /* 28040 */ 0240,0201,05,0301,01,0357,0110,0,
+ /* 28048 */ 0241,0201,011,0301,01,0357,0120,0,
+ /* 28056 */ 0240,0201,011,0301,01,0357,0110,0,
+ /* 28064 */ 0241,0201,021,0301,01,0357,0120,0,
+ /* 28072 */ 0240,0201,021,0301,01,0357,0110,0,
+ /* 28080 */ 0241,0201,025,0301,01,0357,0120,0,
+ /* 28088 */ 0240,0201,025,0301,01,0357,0110,0,
+ /* 28096 */ 0241,0201,031,0301,01,0357,0120,0,
+ /* 28104 */ 0240,0201,031,0301,01,0357,0110,0,
+ /* 28112 */ 0250,0202,021,0301,01,0114,0110,0,
+ /* 28120 */ 0250,0202,025,0301,01,0114,0110,0,
+ /* 28128 */ 0250,0202,031,0301,01,0114,0110,0,
+ /* 28136 */ 0250,0202,01,0301,01,0114,0110,0,
+ /* 28144 */ 0250,0202,05,0301,01,0114,0110,0,
+ /* 28152 */ 0250,0202,011,0301,01,0114,0110,0,
+ /* 28160 */ 0241,0202,021,0306,01,0115,0120,0,
+ /* 28168 */ 0240,0202,021,0306,01,0115,0110,0,
+ /* 28176 */ 0241,0202,01,0306,01,0115,0120,0,
+ /* 28184 */ 0240,0202,01,0306,01,0115,0110,0,
+ /* 28192 */ 0250,0202,031,0301,01,0312,0110,0,
+ /* 28200 */ 0250,0202,011,0301,01,0312,0110,0,
+ /* 28208 */ 0241,0202,021,0306,01,0313,0120,0,
+ /* 28216 */ 0240,0202,021,0306,01,0313,0110,0,
+ /* 28224 */ 0241,0202,01,0306,01,0313,0120,0,
+ /* 28232 */ 0240,0202,01,0306,01,0313,0110,0,
+ /* 28240 */ 0250,0202,021,0301,01,0116,0110,0,
+ /* 28248 */ 0250,0202,025,0301,01,0116,0110,0,
+ /* 28256 */ 0250,0202,031,0301,01,0116,0110,0,
+ /* 28264 */ 0250,0202,01,0301,01,0116,0110,0,
+ /* 28272 */ 0250,0202,05,0301,01,0116,0110,0,
+ /* 28280 */ 0250,0202,011,0301,01,0116,0110,0,
+ /* 28288 */ 0241,0202,021,0306,01,0117,0120,0,
+ /* 28296 */ 0240,0202,021,0306,01,0117,0110,0,
+ /* 28304 */ 0241,0202,01,0306,01,0117,0120,0,
+ /* 28312 */ 0240,0202,01,0306,01,0117,0110,0,
+ /* 28320 */ 0250,0202,031,0301,01,0314,0110,0,
+ /* 28328 */ 0250,0202,011,0301,01,0314,0110,0,
+ /* 28336 */ 0241,0202,021,0306,01,0315,0120,0,
+ /* 28344 */ 0240,0202,021,0306,01,0315,0110,0,
+ /* 28352 */ 0241,0202,01,0306,01,0315,0120,0,
+ /* 28360 */ 0240,0202,01,0306,01,0315,0110,0,
+ /* 28368 */ 0241,0202,021,0301,01,054,0120,0,
+ /* 28376 */ 0240,0202,021,0301,01,054,0110,0,
+ /* 28384 */ 0241,0202,025,0301,01,054,0120,0,
+ /* 28392 */ 0240,0202,025,0301,01,054,0110,0,
+ /* 28400 */ 0241,0202,031,0301,01,054,0120,0,
+ /* 28408 */ 0240,0202,031,0301,01,054,0110,0,
+ /* 28416 */ 0241,0202,01,0301,01,054,0120,0,
+ /* 28424 */ 0240,0202,01,0301,01,054,0110,0,
+ /* 28432 */ 0241,0202,05,0301,01,054,0120,0,
+ /* 28440 */ 0240,0202,05,0301,01,054,0110,0,
+ /* 28448 */ 0241,0202,011,0301,01,054,0120,0,
+ /* 28456 */ 0240,0202,011,0301,01,054,0110,0,
+ /* 28464 */ 0241,0202,021,0306,01,055,0120,0,
+ /* 28472 */ 0240,0202,021,0306,01,055,0110,0,
+ /* 28480 */ 0241,0202,01,0306,01,055,0120,0,
+ /* 28488 */ 0240,0202,01,0306,01,055,0110,0,
+ /* 28496 */ 0250,0201,021,0301,01,0121,0110,0,
+ /* 28504 */ 0250,0201,025,0301,01,0121,0110,0,
+ /* 28512 */ 0250,0201,031,0301,01,0121,0110,0,
+ /* 28520 */ 0250,0201,0,0301,01,0121,0110,0,
+ /* 28528 */ 0250,0201,04,0301,01,0121,0110,0,
+ /* 28536 */ 0250,0201,010,0301,01,0121,0110,0,
+ /* 28544 */ 0241,0201,023,0306,01,0121,0120,0,
+ /* 28552 */ 0240,0201,023,0306,01,0121,0110,0,
+ /* 28560 */ 0241,0201,02,0306,01,0121,0120,0,
+ /* 28568 */ 0240,0201,02,0306,01,0121,0110,0,
+ /* 28576 */ 0241,0201,021,0301,01,0134,0120,0,
+ /* 28584 */ 0240,0201,021,0301,01,0134,0110,0,
+ /* 28592 */ 0241,0201,025,0301,01,0134,0120,0,
+ /* 28600 */ 0240,0201,025,0301,01,0134,0110,0,
+ /* 28608 */ 0241,0201,031,0301,01,0134,0120,0,
+ /* 28616 */ 0240,0201,031,0301,01,0134,0110,0,
+ /* 28624 */ 0241,0201,0,0301,01,0134,0120,0,
+ /* 28632 */ 0240,0201,0,0301,01,0134,0110,0,
+ /* 28640 */ 0241,0201,04,0301,01,0134,0120,0,
+ /* 28648 */ 0240,0201,04,0301,01,0134,0110,0,
+ /* 28656 */ 0241,0201,010,0301,01,0134,0120,0,
+ /* 28664 */ 0240,0201,010,0301,01,0134,0110,0,
+ /* 28672 */ 0241,0201,023,0306,01,0134,0120,0,
+ /* 28680 */ 0240,0201,023,0306,01,0134,0110,0,
+ /* 28688 */ 0241,0201,02,0306,01,0134,0120,0,
+ /* 28696 */ 0240,0201,02,0306,01,0134,0110,0,
+ /* 28704 */ 0250,0201,021,0306,01,056,0110,0,
+ /* 28712 */ 0250,0201,0,0306,01,056,0110,0,
+ /* 28720 */ 0241,0201,021,0301,01,025,0120,0,
+ /* 28728 */ 0240,0201,021,0301,01,025,0110,0,
+ /* 28736 */ 0241,0201,025,0301,01,025,0120,0,
+ /* 28744 */ 0240,0201,025,0301,01,025,0110,0,
+ /* 28752 */ 0241,0201,031,0301,01,025,0120,0,
+ /* 28760 */ 0240,0201,031,0301,01,025,0110,0,
+ /* 28768 */ 0241,0201,0,0301,01,025,0120,0,
+ /* 28776 */ 0240,0201,0,0301,01,025,0110,0,
+ /* 28784 */ 0241,0201,04,0301,01,025,0120,0,
+ /* 28792 */ 0240,0201,04,0301,01,025,0110,0,
+ /* 28800 */ 0241,0201,010,0301,01,025,0120,0,
+ /* 28808 */ 0240,0201,010,0301,01,025,0110,0,
+ /* 28816 */ 0241,0201,021,0301,01,024,0120,0,
+ /* 28824 */ 0240,0201,021,0301,01,024,0110,0,
+ /* 28832 */ 0241,0201,025,0301,01,024,0120,0,
+ /* 28840 */ 0240,0201,025,0301,01,024,0110,0,
+ /* 28848 */ 0241,0201,031,0301,01,024,0120,0,
+ /* 28856 */ 0240,0201,031,0301,01,024,0110,0,
+ /* 28864 */ 0241,0201,0,0301,01,024,0120,0,
+ /* 28872 */ 0240,0201,0,0301,01,024,0110,0,
+ /* 28880 */ 0241,0201,04,0301,01,024,0120,0,
+ /* 28888 */ 0240,0201,04,0301,01,024,0110,0,
+ /* 28896 */ 0241,0201,010,0301,01,024,0120,0,
+ /* 28904 */ 0240,0201,010,0301,01,024,0110,0,
+ /* 28912 */ 0241,0201,021,0301,01,0127,0120,0,
+ /* 28920 */ 0240,0201,021,0301,01,0127,0110,0,
+ /* 28928 */ 0241,0201,025,0301,01,0127,0120,0,
+ /* 28936 */ 0240,0201,025,0301,01,0127,0110,0,
+ /* 28944 */ 0241,0201,031,0301,01,0127,0120,0,
+ /* 28952 */ 0240,0201,031,0301,01,0127,0110,0,
+ /* 28960 */ 0241,0201,0,0301,01,0127,0120,0,
+ /* 28968 */ 0240,0201,0,0301,01,0127,0110,0,
+ /* 28976 */ 0241,0201,04,0301,01,0127,0120,0,
+ /* 28984 */ 0240,0201,04,0301,01,0127,0110,0,
+ /* 28992 */ 0241,0201,010,0301,01,0127,0120,0,
+ /* 29000 */ 0240,0201,010,0301,01,0127,0110,0,
+ /* 29008 */ 0310,0361,03,017,070,0370,0110,0,
+ /* 29016 */ 0311,0361,03,017,070,0370,0110,0,
+ /* 29024 */ 0323,0313,0333,02,017,0256,0206,0,
+ /* 29032 */ 0361,03,017,072,0317,0110,022,0,
+ /* 29040 */ 0261,03,021,01,0317,0120,023,0,
+ /* 29048 */ 0260,03,021,01,0317,0110,022,0,
+ /* 29056 */ 0261,03,025,01,0317,0120,023,0,
+ /* 29064 */ 0260,03,025,01,0317,0110,022,0,
+ /* 29072 */ 0361,03,017,072,0316,0110,022,0,
+ /* 29080 */ 0261,03,021,01,0316,0120,023,0,
+ /* 29088 */ 0260,03,021,01,0316,0110,022,0,
+ /* 29096 */ 0261,03,025,01,0316,0120,023,0,
+ /* 29104 */ 0260,03,025,01,0316,0110,022,0,
+ /* 29112 */ 0241,0202,01,0303,01,0317,0120,0,
+ /* 29120 */ 0240,0202,01,0303,01,0317,0110,0,
+ /* 29128 */ 0241,0202,05,0303,01,0317,0120,0,
+ /* 29136 */ 0240,0202,05,0303,01,0317,0110,0,
+ /* 29144 */ 0241,0202,011,0303,01,0317,0120,0,
+ /* 29152 */ 0240,0202,011,0303,01,0317,0110,0,
+ /* 29160 */ 0250,0202,01,0304,01,0143,0101,0,
+ /* 29168 */ 0250,0202,05,0304,01,0143,0101,0,
+ /* 29176 */ 0250,0202,011,0304,01,0143,0101,0,
+ /* 29184 */ 0250,0202,01,0300,01,0143,0101,0,
+ /* 29192 */ 0250,0202,05,0300,01,0143,0101,0,
+ /* 29200 */ 0250,0202,011,0300,01,0143,0101,0,
+ /* 29208 */ 0250,0202,021,0305,01,0143,0101,0,
+ /* 29216 */ 0250,0202,025,0305,01,0143,0101,0,
+ /* 29224 */ 0250,0202,031,0305,01,0143,0101,0,
+ /* 29232 */ 0250,0202,021,0300,01,0143,0101,0,
+ /* 29240 */ 0250,0202,025,0300,01,0143,0101,0,
+ /* 29248 */ 0250,0202,031,0300,01,0143,0101,0,
+ /* 29256 */ 0250,0202,01,0304,01,0142,0110,0,
+ /* 29264 */ 0250,0202,05,0304,01,0142,0110,0,
+ /* 29272 */ 0250,0202,011,0304,01,0142,0110,0,
+ /* 29280 */ 0250,0202,021,0305,01,0142,0110,0,
+ /* 29288 */ 0250,0202,025,0305,01,0142,0110,0,
+ /* 29296 */ 0250,0202,031,0305,01,0142,0110,0,
+ /* 29304 */ 0241,0202,021,0303,01,0160,0120,0,
+ /* 29312 */ 0240,0202,021,0303,01,0160,0110,0,
+ /* 29320 */ 0241,0202,025,0303,01,0160,0120,0,
+ /* 29328 */ 0240,0202,025,0303,01,0160,0110,0,
+ /* 29336 */ 0241,0202,031,0303,01,0160,0120,0,
+ /* 29344 */ 0240,0202,031,0303,01,0160,0110,0,
+ /* 29352 */ 0241,0202,01,0301,01,0161,0120,0,
+ /* 29360 */ 0240,0202,01,0301,01,0161,0110,0,
+ /* 29368 */ 0241,0202,05,0301,01,0161,0120,0,
+ /* 29376 */ 0240,0202,05,0301,01,0161,0110,0,
+ /* 29384 */ 0241,0202,011,0301,01,0161,0120,0,
+ /* 29392 */ 0240,0202,011,0301,01,0161,0110,0,
+ /* 29400 */ 0241,0202,021,0301,01,0161,0120,0,
+ /* 29408 */ 0240,0202,021,0301,01,0161,0110,0,
+ /* 29416 */ 0241,0202,025,0301,01,0161,0120,0,
+ /* 29424 */ 0240,0202,025,0301,01,0161,0110,0,
+ /* 29432 */ 0241,0202,031,0301,01,0161,0120,0,
+ /* 29440 */ 0240,0202,031,0301,01,0161,0110,0,
+ /* 29448 */ 0241,0202,021,0303,01,0162,0120,0,
+ /* 29456 */ 0240,0202,021,0303,01,0162,0110,0,
+ /* 29464 */ 0241,0202,025,0303,01,0162,0120,0,
+ /* 29472 */ 0240,0202,025,0303,01,0162,0110,0,
+ /* 29480 */ 0241,0202,031,0303,01,0162,0120,0,
+ /* 29488 */ 0240,0202,031,0303,01,0162,0110,0,
+ /* 29496 */ 0241,0202,01,0301,01,0163,0120,0,
+ /* 29504 */ 0240,0202,01,0301,01,0163,0110,0,
+ /* 29512 */ 0241,0202,05,0301,01,0163,0120,0,
+ /* 29520 */ 0240,0202,05,0301,01,0163,0110,0,
+ /* 29528 */ 0241,0202,011,0301,01,0163,0120,0,
+ /* 29536 */ 0240,0202,011,0301,01,0163,0110,0,
+ /* 29544 */ 0241,0202,021,0301,01,0163,0120,0,
+ /* 29552 */ 0240,0202,021,0301,01,0163,0110,0,
+ /* 29560 */ 0241,0202,025,0301,01,0163,0120,0,
+ /* 29568 */ 0240,0202,025,0301,01,0163,0110,0,
+ /* 29576 */ 0241,0202,031,0301,01,0163,0120,0,
+ /* 29584 */ 0240,0202,031,0301,01,0163,0110,0,
+ /* 29592 */ 0241,0202,01,0301,01,0120,0120,0,
+ /* 29600 */ 0240,0202,01,0301,01,0120,0110,0,
+ /* 29608 */ 0241,0202,05,0301,01,0120,0120,0,
+ /* 29616 */ 0240,0202,05,0301,01,0120,0110,0,
+ /* 29624 */ 0241,0202,011,0301,01,0120,0120,0,
+ /* 29632 */ 0240,0202,011,0301,01,0120,0110,0,
+ /* 29640 */ 0241,0202,01,0301,01,0121,0120,0,
+ /* 29648 */ 0240,0202,01,0301,01,0121,0110,0,
+ /* 29656 */ 0241,0202,05,0301,01,0121,0120,0,
+ /* 29664 */ 0240,0202,05,0301,01,0121,0110,0,
+ /* 29672 */ 0241,0202,011,0301,01,0121,0120,0,
+ /* 29680 */ 0240,0202,011,0301,01,0121,0110,0,
+ /* 29688 */ 0241,0202,01,0301,01,0122,0120,0,
+ /* 29696 */ 0240,0202,01,0301,01,0122,0110,0,
+ /* 29704 */ 0241,0202,05,0301,01,0122,0120,0,
+ /* 29712 */ 0240,0202,05,0301,01,0122,0110,0,
+ /* 29720 */ 0241,0202,011,0301,01,0122,0120,0,
+ /* 29728 */ 0240,0202,011,0301,01,0122,0110,0,
+ /* 29736 */ 0241,0202,01,0301,01,0123,0120,0,
+ /* 29744 */ 0240,0202,01,0301,01,0123,0110,0,
+ /* 29752 */ 0241,0202,05,0301,01,0123,0120,0,
+ /* 29760 */ 0240,0202,05,0301,01,0123,0110,0,
+ /* 29768 */ 0241,0202,011,0301,01,0123,0120,0,
+ /* 29776 */ 0240,0202,011,0301,01,0123,0110,0,
+ /* 29784 */ 0250,0202,01,0303,01,0124,0110,0,
+ /* 29792 */ 0250,0202,05,0303,01,0124,0110,0,
+ /* 29800 */ 0250,0202,011,0303,01,0124,0110,0,
+ /* 29808 */ 0250,0202,021,0303,01,0124,0110,0,
+ /* 29816 */ 0250,0202,025,0303,01,0124,0110,0,
+ /* 29824 */ 0250,0202,031,0303,01,0124,0110,0,
+ /* 29832 */ 0250,0202,01,0301,01,0125,0110,0,
+ /* 29840 */ 0250,0202,05,0301,01,0125,0110,0,
+ /* 29848 */ 0250,0202,011,0301,01,0125,0110,0,
+ /* 29856 */ 0250,0202,021,0301,01,0125,0110,0,
+ /* 29864 */ 0250,0202,025,0301,01,0125,0110,0,
+ /* 29872 */ 0250,0202,031,0301,01,0125,0110,0,
+ /* 29880 */ 0241,0202,01,0303,01,0217,0120,0,
+ /* 29888 */ 0241,0202,05,0303,01,0217,0120,0,
+ /* 29896 */ 0241,0202,011,0303,01,0217,0120,0,
+ /* 29904 */ 0241,0202,013,0317,01,0232,0120,0,
+ /* 29912 */ 0241,0202,013,0317,01,0252,0120,0,
+ /* 29920 */ 0241,0202,03,0317,01,0233,0120,0,
+ /* 29928 */ 0241,0202,03,0317,01,0253,0120,0,
+ /* 29936 */ 0241,0202,013,0317,01,0123,0120,0,
+ /* 29944 */ 0241,0202,013,0317,01,0122,0120,0,
+ /* 29952 */ 0321,0361,03,017,070,0365,0101,0,
+ /* 29960 */ 0324,0361,03,017,070,0365,0101,0,
+ /* 29968 */ 0310,0332,03,017,070,0370,0110,0,
+ /* 29976 */ 0311,0332,03,017,070,0370,0110,0,
+ /* 29984 */ 0313,0332,03,017,070,0370,0110,0,
+ /* 29992 */ 0310,0333,03,017,070,0370,0110,0,
+ /* 30000 */ 0311,0333,03,017,070,0370,0110,0,
+ /* 30008 */ 0313,0333,03,017,070,0370,0110,0,
+ /* 30016 */ 0241,0202,03,0301,01,0162,0120,0,
+ /* 30024 */ 0240,0202,03,0301,01,0162,0110,0,
+ /* 30032 */ 0241,0202,07,0301,01,0162,0120,0,
+ /* 30040 */ 0240,0202,07,0301,01,0162,0110,0,
+ /* 30048 */ 0241,0202,013,0301,01,0162,0120,0,
+ /* 30056 */ 0240,0202,013,0301,01,0162,0110,0,
+ /* 30064 */ 0241,0202,02,0301,01,0162,0120,0,
+ /* 30072 */ 0240,0202,02,0301,01,0162,0110,0,
+ /* 30080 */ 0241,0202,06,0301,01,0162,0120,0,
+ /* 30088 */ 0240,0202,06,0301,01,0162,0110,0,
+ /* 30096 */ 0241,0202,012,0301,01,0162,0120,0,
+ /* 30104 */ 0240,0202,012,0301,01,0162,0110,0,
+ /* 30112 */ 0241,0202,02,0301,01,0122,0120,0,
+ /* 30120 */ 0240,0202,02,0301,01,0122,0110,0,
+ /* 30128 */ 0241,0202,06,0301,01,0122,0120,0,
+ /* 30136 */ 0240,0202,06,0301,01,0122,0110,0,
+ /* 30144 */ 0241,0202,012,0301,01,0122,0120,0,
+ /* 30152 */ 0240,0202,012,0301,01,0122,0110,0,
+ /* 30160 */ 0241,0202,03,0301,01,0150,0120,0,
+ /* 30168 */ 0241,0202,07,0301,01,0150,0120,0,
+ /* 30176 */ 0241,0202,013,0301,01,0150,0120,0,
+ /* 30184 */ 0270,02,03,01,0111,0171,0300,0,
+ /* 30192 */ 0241,0205,0,0301,01,0130,0120,0,
+ /* 30200 */ 0240,0205,0,0301,01,0130,0110,0,
+ /* 30208 */ 0241,0205,04,0301,01,0130,0120,0,
+ /* 30216 */ 0240,0205,04,0301,01,0130,0110,0,
+ /* 30224 */ 0241,0205,010,0301,01,0130,0120,0,
+ /* 30232 */ 0240,0205,010,0301,01,0130,0110,0,
+ /* 30240 */ 0241,0205,02,0306,01,0130,0120,0,
+ /* 30248 */ 0240,0205,02,0306,01,0130,0110,0,
+ /* 30256 */ 0250,0205,0,0301,01,057,0110,0,
+ /* 30264 */ 0250,0205,0,0301,01,0133,0110,0,
+ /* 30272 */ 0250,0205,04,0301,01,0133,0110,0,
+ /* 30280 */ 0250,0205,010,0301,01,0133,0110,0,
+ /* 30288 */ 0250,0205,021,0301,01,0132,0110,0,
+ /* 30296 */ 0250,0205,025,0301,01,0132,0110,0,
+ /* 30304 */ 0250,0205,031,0301,01,0132,0110,0,
+ /* 30312 */ 0250,0205,01,0302,01,0133,0110,0,
+ /* 30320 */ 0250,0205,05,0302,01,0133,0110,0,
+ /* 30328 */ 0250,0205,011,0302,01,0133,0110,0,
+ /* 30336 */ 0250,0205,0,0315,01,0132,0110,0,
+ /* 30344 */ 0250,0205,04,0315,01,0132,0110,0,
+ /* 30352 */ 0250,0205,010,0315,01,0132,0110,0,
+ /* 30360 */ 0250,0206,01,0302,01,023,0110,0,
+ /* 30368 */ 0250,0206,05,0302,01,023,0110,0,
+ /* 30376 */ 0250,0206,011,0302,01,023,0110,0,
+ /* 30384 */ 0250,0205,01,0315,01,0173,0110,0,
+ /* 30392 */ 0250,0205,05,0315,01,0173,0110,0,
+ /* 30400 */ 0250,0205,011,0315,01,0173,0110,0,
+ /* 30408 */ 0250,0205,0,0302,01,0171,0110,0,
+ /* 30416 */ 0250,0205,04,0302,01,0171,0110,0,
+ /* 30424 */ 0250,0205,010,0302,01,0171,0110,0,
+ /* 30432 */ 0250,0205,01,0315,01,0171,0110,0,
+ /* 30440 */ 0250,0205,05,0315,01,0171,0110,0,
+ /* 30448 */ 0250,0205,011,0315,01,0171,0110,0,
+ /* 30456 */ 0250,0205,0,0301,01,0175,0110,0,
+ /* 30464 */ 0250,0205,04,0301,01,0175,0110,0,
+ /* 30472 */ 0250,0205,010,0301,01,0175,0110,0,
+ /* 30480 */ 0250,0205,01,0301,01,0175,0110,0,
+ /* 30488 */ 0250,0205,05,0301,01,0175,0110,0,
+ /* 30496 */ 0250,0205,011,0301,01,0175,0110,0,
+ /* 30504 */ 0250,0205,01,0301,01,035,0110,0,
+ /* 30512 */ 0250,0205,05,0301,01,035,0110,0,
+ /* 30520 */ 0250,0205,011,0301,01,035,0110,0,
+ /* 30528 */ 0250,0205,020,0301,01,0133,0110,0,
+ /* 30536 */ 0250,0205,024,0301,01,0133,0110,0,
+ /* 30544 */ 0250,0205,030,0301,01,0133,0110,0,
+ /* 30552 */ 0241,0205,023,0306,01,0132,0120,0,
+ /* 30560 */ 0240,0205,023,0306,01,0132,0110,0,
+ /* 30568 */ 0241,0205,02,0306,01,0132,0120,0,
+ /* 30576 */ 0240,0205,02,0306,01,0132,0110,0,
+ /* 30584 */ 0250,0205,02,0306,01,055,0110,0,
+ /* 30592 */ 0250,0205,022,0306,01,055,0110,0,
+ /* 30600 */ 0241,0206,0,0306,01,023,0120,0,
+ /* 30608 */ 0240,0206,0,0306,01,023,0110,0,
+ /* 30616 */ 0250,0205,02,0306,01,0171,0110,0,
+ /* 30624 */ 0250,0205,022,0306,01,0171,0110,0,
+ /* 30632 */ 0241,0205,02,0306,01,052,0120,0,
+ /* 30640 */ 0240,0205,02,0306,01,052,0110,0,
+ /* 30648 */ 0241,0205,022,0306,01,052,0120,0,
+ /* 30656 */ 0240,0205,022,0306,01,052,0110,0,
+ /* 30664 */ 0241,0205,040,0306,01,035,0120,0,
+ /* 30672 */ 0240,0205,040,0306,01,035,0110,0,
+ /* 30680 */ 0250,0205,02,0302,01,0133,0110,0,
+ /* 30688 */ 0250,0205,06,0302,01,0133,0110,0,
+ /* 30696 */ 0250,0205,012,0302,01,0133,0110,0,
+ /* 30704 */ 0250,0205,01,0306,01,0172,0110,0,
+ /* 30712 */ 0250,0205,05,0306,01,0172,0110,0,
+ /* 30720 */ 0250,0205,011,0306,01,0172,0110,0,
+ /* 30728 */ 0250,0205,0,0302,01,0170,0110,0,
+ /* 30736 */ 0250,0205,04,0302,01,0170,0110,0,
+ /* 30744 */ 0250,0205,010,0302,01,0170,0110,0,
+ /* 30752 */ 0250,0205,01,0306,01,0170,0110,0,
+ /* 30760 */ 0250,0205,05,0306,01,0170,0110,0,
+ /* 30768 */ 0250,0205,011,0306,01,0170,0110,0,
+ /* 30776 */ 0250,0205,0,0301,01,0174,0110,0,
+ /* 30784 */ 0250,0205,04,0301,01,0174,0110,0,
+ /* 30792 */ 0250,0205,010,0301,01,0174,0110,0,
+ /* 30800 */ 0250,0205,01,0301,01,0174,0110,0,
+ /* 30808 */ 0250,0205,05,0301,01,0174,0110,0,
+ /* 30816 */ 0250,0205,011,0301,01,0174,0110,0,
+ /* 30824 */ 0250,0205,02,0306,01,054,0110,0,
+ /* 30832 */ 0250,0205,022,0306,01,054,0110,0,
+ /* 30840 */ 0250,0205,02,0306,01,0170,0110,0,
+ /* 30848 */ 0250,0205,022,0306,01,0170,0110,0,
+ /* 30856 */ 0250,0205,03,0301,01,0172,0110,0,
+ /* 30864 */ 0250,0205,07,0301,01,0172,0110,0,
+ /* 30872 */ 0250,0205,013,0301,01,0172,0110,0,
+ /* 30880 */ 0250,0205,023,0301,01,0172,0110,0,
+ /* 30888 */ 0250,0205,027,0301,01,0172,0110,0,
+ /* 30896 */ 0250,0205,033,0301,01,0172,0110,0,
+ /* 30904 */ 0241,0205,02,0306,01,0173,0120,0,
+ /* 30912 */ 0241,0205,022,0306,01,0173,0120,0,
+ /* 30920 */ 0250,0205,03,0301,01,0175,0110,0,
+ /* 30928 */ 0250,0205,07,0301,01,0175,0110,0,
+ /* 30936 */ 0250,0205,013,0301,01,0175,0110,0,
+ /* 30944 */ 0250,0205,02,0301,01,0175,0110,0,
+ /* 30952 */ 0250,0205,06,0301,01,0175,0110,0,
+ /* 30960 */ 0250,0205,012,0301,01,0175,0110,0,
+ /* 30968 */ 0241,0205,040,0301,01,0136,0120,0,
+ /* 30976 */ 0240,0205,040,0301,01,0136,0110,0,
+ /* 30984 */ 0241,0205,044,0301,01,0136,0120,0,
+ /* 30992 */ 0240,0205,044,0301,01,0136,0110,0,
+ /* 31000 */ 0241,0205,050,0301,01,0136,0120,0,
+ /* 31008 */ 0240,0205,050,0301,01,0136,0110,0,
+ /* 31016 */ 0241,0205,042,0306,01,0136,0120,0,
+ /* 31024 */ 0240,0205,042,0306,01,0136,0110,0,
+ /* 31032 */ 0241,0206,03,0301,01,0126,0120,0,
+ /* 31040 */ 0240,0206,03,0301,01,0126,0110,0,
+ /* 31048 */ 0241,0206,07,0301,01,0126,0120,0,
+ /* 31056 */ 0240,0206,07,0301,01,0126,0110,0,
+ /* 31064 */ 0241,0206,013,0301,01,0126,0120,0,
+ /* 31072 */ 0240,0206,013,0301,01,0126,0110,0,
+ /* 31080 */ 0241,0206,02,0301,01,0126,0120,0,
+ /* 31088 */ 0240,0206,02,0301,01,0126,0110,0,
+ /* 31096 */ 0241,0206,06,0301,01,0126,0120,0,
+ /* 31104 */ 0240,0206,06,0301,01,0126,0110,0,
+ /* 31112 */ 0241,0206,012,0301,01,0126,0120,0,
+ /* 31120 */ 0240,0206,012,0301,01,0126,0110,0,
+ /* 31128 */ 0241,0206,03,0306,01,0127,0120,0,
+ /* 31136 */ 0240,0206,03,0306,01,0127,0110,0,
+ /* 31144 */ 0241,0206,02,0306,01,0127,0120,0,
+ /* 31152 */ 0240,0206,02,0306,01,0127,0110,0,
+ /* 31160 */ 0241,0206,03,0301,01,0326,0120,0,
+ /* 31168 */ 0240,0206,03,0301,01,0326,0110,0,
+ /* 31176 */ 0241,0206,07,0301,01,0326,0120,0,
+ /* 31184 */ 0240,0206,07,0301,01,0326,0110,0,
+ /* 31192 */ 0241,0206,013,0301,01,0326,0120,0,
+ /* 31200 */ 0240,0206,013,0301,01,0326,0110,0,
+ /* 31208 */ 0241,0206,02,0301,01,0326,0120,0,
+ /* 31216 */ 0240,0206,02,0301,01,0326,0110,0,
+ /* 31224 */ 0241,0206,06,0301,01,0326,0120,0,
+ /* 31232 */ 0240,0206,06,0301,01,0326,0110,0,
+ /* 31240 */ 0241,0206,012,0301,01,0326,0120,0,
+ /* 31248 */ 0240,0206,012,0301,01,0326,0110,0,
+ /* 31256 */ 0241,0206,03,0306,01,0327,0120,0,
+ /* 31264 */ 0240,0206,03,0306,01,0327,0110,0,
+ /* 31272 */ 0241,0206,02,0306,01,0327,0120,0,
+ /* 31280 */ 0240,0206,02,0306,01,0327,0110,0,
+ /* 31288 */ 0241,0206,01,0301,01,0226,0120,0,
+ /* 31296 */ 0240,0206,01,0301,01,0226,0110,0,
+ /* 31304 */ 0241,0206,05,0301,01,0226,0120,0,
+ /* 31312 */ 0240,0206,05,0301,01,0226,0110,0,
+ /* 31320 */ 0241,0206,011,0301,01,0226,0120,0,
+ /* 31328 */ 0240,0206,011,0301,01,0226,0110,0,
+ /* 31336 */ 0241,0206,01,0301,01,0246,0120,0,
+ /* 31344 */ 0240,0206,01,0301,01,0246,0110,0,
+ /* 31352 */ 0241,0206,05,0301,01,0246,0120,0,
+ /* 31360 */ 0240,0206,05,0301,01,0246,0110,0,
+ /* 31368 */ 0241,0206,011,0301,01,0246,0120,0,
+ /* 31376 */ 0240,0206,011,0301,01,0246,0110,0,
+ /* 31384 */ 0241,0206,01,0301,01,0266,0120,0,
+ /* 31392 */ 0240,0206,01,0301,01,0266,0110,0,
+ /* 31400 */ 0241,0206,05,0301,01,0266,0120,0,
+ /* 31408 */ 0240,0206,05,0301,01,0266,0110,0,
+ /* 31416 */ 0241,0206,011,0301,01,0266,0120,0,
+ /* 31424 */ 0240,0206,011,0301,01,0266,0110,0,
+ /* 31432 */ 0241,0206,01,0301,01,0227,0120,0,
+ /* 31440 */ 0240,0206,01,0301,01,0227,0110,0,
+ /* 31448 */ 0241,0206,05,0301,01,0227,0120,0,
+ /* 31456 */ 0240,0206,05,0301,01,0227,0110,0,
+ /* 31464 */ 0241,0206,011,0301,01,0227,0120,0,
+ /* 31472 */ 0240,0206,011,0301,01,0227,0110,0,
+ /* 31480 */ 0241,0206,01,0301,01,0247,0120,0,
+ /* 31488 */ 0240,0206,01,0301,01,0247,0110,0,
+ /* 31496 */ 0241,0206,05,0301,01,0247,0120,0,
+ /* 31504 */ 0240,0206,05,0301,01,0247,0110,0,
+ /* 31512 */ 0241,0206,011,0301,01,0247,0120,0,
+ /* 31520 */ 0240,0206,011,0301,01,0247,0110,0,
+ /* 31528 */ 0241,0206,01,0301,01,0267,0120,0,
+ /* 31536 */ 0240,0206,01,0301,01,0267,0110,0,
+ /* 31544 */ 0241,0206,05,0301,01,0267,0120,0,
+ /* 31552 */ 0240,0206,05,0301,01,0267,0110,0,
+ /* 31560 */ 0241,0206,011,0301,01,0267,0120,0,
+ /* 31568 */ 0240,0206,011,0301,01,0267,0110,0,
+ /* 31576 */ 0241,0206,01,0301,01,0230,0120,0,
+ /* 31584 */ 0240,0206,01,0301,01,0230,0110,0,
+ /* 31592 */ 0241,0206,05,0301,01,0230,0120,0,
+ /* 31600 */ 0240,0206,05,0301,01,0230,0110,0,
+ /* 31608 */ 0241,0206,011,0301,01,0230,0120,0,
+ /* 31616 */ 0240,0206,011,0301,01,0230,0110,0,
+ /* 31624 */ 0241,0206,01,0301,01,0250,0120,0,
+ /* 31632 */ 0240,0206,01,0301,01,0250,0110,0,
+ /* 31640 */ 0241,0206,05,0301,01,0250,0120,0,
+ /* 31648 */ 0240,0206,05,0301,01,0250,0110,0,
+ /* 31656 */ 0241,0206,011,0301,01,0250,0120,0,
+ /* 31664 */ 0240,0206,011,0301,01,0250,0110,0,
+ /* 31672 */ 0241,0206,01,0301,01,0270,0120,0,
+ /* 31680 */ 0240,0206,01,0301,01,0270,0110,0,
+ /* 31688 */ 0241,0206,05,0301,01,0270,0120,0,
+ /* 31696 */ 0240,0206,05,0301,01,0270,0110,0,
+ /* 31704 */ 0241,0206,011,0301,01,0270,0120,0,
+ /* 31712 */ 0240,0206,011,0301,01,0270,0110,0,
+ /* 31720 */ 0241,0206,01,0301,01,0234,0120,0,
+ /* 31728 */ 0240,0206,01,0301,01,0234,0110,0,
+ /* 31736 */ 0241,0206,05,0301,01,0234,0120,0,
+ /* 31744 */ 0240,0206,05,0301,01,0234,0110,0,
+ /* 31752 */ 0241,0206,011,0301,01,0234,0120,0,
+ /* 31760 */ 0240,0206,011,0301,01,0234,0110,0,
+ /* 31768 */ 0241,0206,01,0301,01,0254,0120,0,
+ /* 31776 */ 0240,0206,01,0301,01,0254,0110,0,
+ /* 31784 */ 0241,0206,05,0301,01,0254,0120,0,
+ /* 31792 */ 0240,0206,05,0301,01,0254,0110,0,
+ /* 31800 */ 0241,0206,011,0301,01,0254,0120,0,
+ /* 31808 */ 0240,0206,011,0301,01,0254,0110,0,
+ /* 31816 */ 0241,0206,01,0301,01,0274,0120,0,
+ /* 31824 */ 0240,0206,01,0301,01,0274,0110,0,
+ /* 31832 */ 0241,0206,05,0301,01,0274,0120,0,
+ /* 31840 */ 0240,0206,05,0301,01,0274,0110,0,
+ /* 31848 */ 0241,0206,011,0301,01,0274,0120,0,
+ /* 31856 */ 0240,0206,011,0301,01,0274,0110,0,
+ /* 31864 */ 0241,0206,01,0306,01,0231,0120,0,
+ /* 31872 */ 0240,0206,01,0306,01,0231,0110,0,
+ /* 31880 */ 0241,0206,01,0306,01,0251,0120,0,
+ /* 31888 */ 0240,0206,01,0306,01,0251,0110,0,
+ /* 31896 */ 0241,0206,01,0306,01,0271,0120,0,
+ /* 31904 */ 0240,0206,01,0306,01,0271,0110,0,
+ /* 31912 */ 0241,0206,01,0306,01,0235,0120,0,
+ /* 31920 */ 0240,0206,01,0306,01,0235,0110,0,
+ /* 31928 */ 0241,0206,01,0306,01,0255,0120,0,
+ /* 31936 */ 0240,0206,01,0306,01,0255,0110,0,
+ /* 31944 */ 0241,0206,01,0306,01,0275,0120,0,
+ /* 31952 */ 0240,0206,01,0306,01,0275,0110,0,
+ /* 31960 */ 0241,0206,01,0301,01,0232,0120,0,
+ /* 31968 */ 0240,0206,01,0301,01,0232,0110,0,
+ /* 31976 */ 0241,0206,05,0301,01,0232,0120,0,
+ /* 31984 */ 0240,0206,05,0301,01,0232,0110,0,
+ /* 31992 */ 0241,0206,011,0301,01,0232,0120,0,
+ /* 32000 */ 0240,0206,011,0301,01,0232,0110,0,
+ /* 32008 */ 0241,0206,01,0301,01,0252,0120,0,
+ /* 32016 */ 0240,0206,01,0301,01,0252,0110,0,
+ /* 32024 */ 0241,0206,05,0301,01,0252,0120,0,
+ /* 32032 */ 0240,0206,05,0301,01,0252,0110,0,
+ /* 32040 */ 0241,0206,011,0301,01,0252,0120,0,
+ /* 32048 */ 0240,0206,011,0301,01,0252,0110,0,
+ /* 32056 */ 0241,0206,01,0301,01,0272,0120,0,
+ /* 32064 */ 0240,0206,01,0301,01,0272,0110,0,
+ /* 32072 */ 0241,0206,05,0301,01,0272,0120,0,
+ /* 32080 */ 0240,0206,05,0301,01,0272,0110,0,
+ /* 32088 */ 0241,0206,011,0301,01,0272,0120,0,
+ /* 32096 */ 0240,0206,011,0301,01,0272,0110,0,
+ /* 32104 */ 0241,0206,01,0301,01,0236,0120,0,
+ /* 32112 */ 0240,0206,01,0301,01,0236,0110,0,
+ /* 32120 */ 0241,0206,05,0301,01,0236,0120,0,
+ /* 32128 */ 0240,0206,05,0301,01,0236,0110,0,
+ /* 32136 */ 0241,0206,011,0301,01,0236,0120,0,
+ /* 32144 */ 0240,0206,011,0301,01,0236,0110,0,
+ /* 32152 */ 0241,0206,01,0301,01,0256,0120,0,
+ /* 32160 */ 0240,0206,01,0301,01,0256,0110,0,
+ /* 32168 */ 0241,0206,05,0301,01,0256,0120,0,
+ /* 32176 */ 0240,0206,05,0301,01,0256,0110,0,
+ /* 32184 */ 0241,0206,011,0301,01,0256,0120,0,
+ /* 32192 */ 0240,0206,011,0301,01,0256,0110,0,
+ /* 32200 */ 0241,0206,01,0301,01,0276,0120,0,
+ /* 32208 */ 0240,0206,01,0301,01,0276,0110,0,
+ /* 32216 */ 0241,0206,05,0301,01,0276,0120,0,
+ /* 32224 */ 0240,0206,05,0301,01,0276,0110,0,
+ /* 32232 */ 0241,0206,011,0301,01,0276,0120,0,
+ /* 32240 */ 0240,0206,011,0301,01,0276,0110,0,
+ /* 32248 */ 0241,0206,01,0306,01,0233,0120,0,
+ /* 32256 */ 0240,0206,01,0306,01,0233,0110,0,
+ /* 32264 */ 0241,0206,01,0306,01,0253,0120,0,
+ /* 32272 */ 0240,0206,01,0306,01,0253,0110,0,
+ /* 32280 */ 0241,0206,01,0306,01,0273,0120,0,
+ /* 32288 */ 0240,0206,01,0306,01,0273,0110,0,
+ /* 32296 */ 0241,0206,01,0306,01,0237,0120,0,
+ /* 32304 */ 0240,0206,01,0306,01,0237,0110,0,
+ /* 32312 */ 0241,0206,01,0306,01,0257,0120,0,
+ /* 32320 */ 0240,0206,01,0306,01,0257,0110,0,
+ /* 32328 */ 0241,0206,01,0306,01,0277,0120,0,
+ /* 32336 */ 0240,0206,01,0306,01,0277,0110,0,
+ /* 32344 */ 0250,0206,01,0301,01,0102,0110,0,
+ /* 32352 */ 0250,0206,05,0301,01,0102,0110,0,
+ /* 32360 */ 0250,0206,011,0301,01,0102,0110,0,
+ /* 32368 */ 0250,0206,01,0306,01,0103,0110,0,
+ /* 32376 */ 0250,0205,0,0301,01,0137,0110,0,
+ /* 32384 */ 0250,0205,04,0301,01,0137,0110,0,
+ /* 32392 */ 0250,0205,010,0301,01,0137,0110,0,
+ /* 32400 */ 0250,0205,02,0306,01,0137,0110,0,
+ /* 32408 */ 0250,0205,0,0301,01,0135,0110,0,
+ /* 32416 */ 0250,0205,04,0301,01,0135,0110,0,
+ /* 32424 */ 0250,0205,010,0301,01,0135,0110,0,
+ /* 32432 */ 0250,0205,02,0306,01,0135,0110,0,
+ /* 32440 */ 0250,0205,02,0306,01,020,0110,0,
+ /* 32448 */ 0250,0205,02,0306,01,021,0101,0,
+ /* 32456 */ 0241,0205,02,0300,01,020,0120,0,
+ /* 32464 */ 0240,0205,02,0300,01,020,0110,0,
+ /* 32472 */ 0241,0205,02,0300,01,021,0120,0,
+ /* 32480 */ 0240,0205,02,0300,01,021,0110,0,
+ /* 32488 */ 0250,0205,041,0306,01,0156,0110,0,
+ /* 32496 */ 0250,0205,041,0306,01,0176,0101,0,
+ /* 32504 */ 0241,0205,0,0301,01,0131,0120,0,
+ /* 32512 */ 0240,0205,0,0301,01,0131,0110,0,
+ /* 32520 */ 0241,0205,04,0301,01,0131,0120,0,
+ /* 32528 */ 0240,0205,04,0301,01,0131,0110,0,
+ /* 32536 */ 0241,0205,010,0301,01,0131,0120,0,
+ /* 32544 */ 0240,0205,010,0301,01,0131,0110,0,
+ /* 32552 */ 0241,0205,02,0306,01,0131,0120,0,
+ /* 32560 */ 0240,0205,02,0306,01,0131,0110,0,
+ /* 32568 */ 0241,0206,01,0301,01,0114,0120,0,
+ /* 32576 */ 0240,0206,01,0301,01,0114,0110,0,
+ /* 32584 */ 0241,0206,05,0301,01,0114,0120,0,
+ /* 32592 */ 0240,0206,05,0301,01,0114,0110,0,
+ /* 32600 */ 0241,0206,011,0301,01,0114,0120,0,
+ /* 32608 */ 0240,0206,011,0301,01,0114,0110,0,
+ /* 32616 */ 0241,0206,01,0306,01,0115,0120,0,
+ /* 32624 */ 0240,0206,01,0306,01,0115,0110,0,
+ /* 32632 */ 0241,0206,01,0301,01,054,0120,0,
+ /* 32640 */ 0240,0206,01,0301,01,054,0110,0,
+ /* 32648 */ 0241,0206,05,0301,01,054,0120,0,
+ /* 32656 */ 0240,0206,05,0301,01,054,0110,0,
+ /* 32664 */ 0241,0206,011,0301,01,054,0120,0,
+ /* 32672 */ 0240,0206,011,0301,01,054,0110,0,
+ /* 32680 */ 0241,0206,01,0306,01,055,0120,0,
+ /* 32688 */ 0240,0206,01,0306,01,055,0110,0,
+ /* 32696 */ 0250,0205,0,0301,01,0121,0110,0,
+ /* 32704 */ 0250,0205,04,0301,01,0121,0110,0,
+ /* 32712 */ 0250,0205,010,0301,01,0121,0110,0,
+ /* 32720 */ 0241,0205,02,0306,01,0121,0120,0,
+ /* 32728 */ 0240,0205,02,0306,01,0121,0110,0,
+ /* 32736 */ 0241,0205,0,0301,01,0134,0120,0,
+ /* 32744 */ 0240,0205,0,0301,01,0134,0110,0,
+ /* 32752 */ 0241,0205,04,0301,01,0134,0120,0,
+ /* 32760 */ 0240,0205,04,0301,01,0134,0110,0,
+ /* 32768 */ 0241,0205,010,0301,01,0134,0120,0,
+ /* 32776 */ 0240,0205,010,0301,01,0134,0110,0,
+ /* 32784 */ 0241,0205,02,0306,01,0134,0120,0,
+ /* 32792 */ 0240,0205,02,0306,01,0134,0110,0,
+ /* 32800 */ 0250,0205,0,0306,01,056,0110,0,
+ /* 32808 */ 0317,0360,03,017,070,0374,0101,0,
+ /* 32816 */ 0324,0360,03,017,070,0374,0101,0,
+ /* 32824 */ 0317,0361,03,017,070,0374,0101,0,
+ /* 32832 */ 0324,0361,03,017,070,0374,0101,0,
+ /* 32840 */ 0317,0333,03,017,070,0374,0101,0,
+ /* 32848 */ 0324,0333,03,017,070,0374,0101,0,
+ /* 32856 */ 0333,04,017,072,0360,0300,020,0,
+ /* 32864 */ 0273,0320,01,0203,0202,0275,0,
+ /* 32871 */ 0273,0321,01,0203,0202,0275,0,
+ /* 32878 */ 0273,0324,01,0203,0202,0275,0,
+ /* 32885 */ 0273,0320,01,0201,0202,031,0,
+ /* 32892 */ 0273,0321,01,0201,0202,041,0,
+ /* 32899 */ 0273,0324,01,0201,0202,0255,0,
+ /* 32906 */ 0273,0320,01,0203,0200,0275,0,
+ /* 32913 */ 0273,0321,01,0203,0200,0275,0,
+ /* 32920 */ 0273,0324,01,0203,0200,0275,0,
+ /* 32927 */ 0273,0320,01,0201,0200,031,0,
+ /* 32934 */ 0273,0321,01,0201,0200,041,0,
+ /* 32941 */ 0273,0324,01,0201,0200,0255,0,
+ /* 32948 */ 0273,0320,01,0203,0204,0275,0,
+ /* 32955 */ 0273,0321,01,0203,0204,0275,0,
+ /* 32962 */ 0273,0324,01,0203,0204,0275,0,
+ /* 32969 */ 0273,0320,01,0201,0204,031,0,
+ /* 32976 */ 0273,0321,01,0201,0204,041,0,
+ /* 32983 */ 0273,0324,01,0201,0204,0255,0,
+ /* 32990 */ 0320,0326,02,017,0274,0110,0,
+ /* 32997 */ 0321,0326,02,017,0274,0110,0,
+ /* 33004 */ 0324,0326,02,017,0274,0110,0,
+ /* 33011 */ 0320,0326,02,017,0275,0110,0,
+ /* 33018 */ 0321,0326,02,017,0275,0110,0,
+ /* 33025 */ 0324,0326,02,017,0275,0110,0,
+ /* 33032 */ 0320,02,017,0272,0204,025,0,
+ /* 33039 */ 0321,02,017,0272,0204,025,0,
+ /* 33046 */ 0324,02,017,0272,0204,025,0,
+ /* 33053 */ 0273,0320,02,017,0273,0101,0,
+ /* 33060 */ 0273,0321,02,017,0273,0101,0,
+ /* 33067 */ 0273,0324,02,017,0273,0101,0,
+ /* 33074 */ 0273,0320,02,017,0263,0101,0,
+ /* 33081 */ 0273,0321,02,017,0263,0101,0,
+ /* 33088 */ 0273,0324,02,017,0263,0101,0,
+ /* 33095 */ 0273,0320,02,017,0253,0101,0,
+ /* 33102 */ 0273,0321,02,017,0253,0101,0,
+ /* 33109 */ 0273,0324,02,017,0253,0101,0,
+ /* 33116 */ 0273,0320,02,017,0261,0101,0,
+ /* 33123 */ 0273,0321,02,017,0261,0101,0,
+ /* 33130 */ 0273,0324,02,017,0261,0101,0,
+ /* 33137 */ 0273,0317,02,017,0307,0201,0,
+ /* 33144 */ 0361,03,017,070,0202,0110,0,
+ /* 33151 */ 0323,0313,03,017,01,0337,0,
+ /* 33158 */ 0320,0323,02,017,02,0110,0,
+ /* 33165 */ 0321,0323,02,017,02,0110,0,
+ /* 33172 */ 0320,0323,02,017,03,0110,0,
+ /* 33179 */ 0321,0323,02,017,03,0110,0,
+ /* 33186 */ 0271,0320,01,0307,0200,031,0,
+ /* 33193 */ 0271,0321,01,0307,0200,041,0,
+ /* 33200 */ 0271,0324,01,0307,0200,0255,0,
+ /* 33207 */ 0360,0324,02,017,0156,0110,0,
+ /* 33214 */ 0360,0324,02,017,0176,0101,0,
+ /* 33221 */ 0273,0320,01,0203,0201,0275,0,
+ /* 33228 */ 0273,0321,01,0203,0201,0275,0,
+ /* 33235 */ 0273,0324,01,0203,0201,0275,0,
+ /* 33242 */ 0273,0320,01,0201,0201,031,0,
+ /* 33249 */ 0273,0321,01,0201,0201,041,0,
+ /* 33256 */ 0273,0324,01,0201,0201,0255,0,
+ /* 33263 */ 0360,0323,02,017,0153,0110,0,
+ /* 33270 */ 0360,0323,02,017,0143,0110,0,
+ /* 33277 */ 0360,0323,02,017,0147,0110,0,
+ /* 33284 */ 0360,0323,02,017,0374,0110,0,
+ /* 33291 */ 0360,0323,02,017,0376,0110,0,
+ /* 33298 */ 0360,0323,02,017,0354,0110,0,
+ /* 33305 */ 0360,0323,02,017,0355,0110,0,
+ /* 33312 */ 0360,0323,02,017,0334,0110,0,
+ /* 33319 */ 0360,0323,02,017,0335,0110,0,
+ /* 33326 */ 0360,0323,02,017,0375,0110,0,
+ /* 33333 */ 0360,0323,02,017,0333,0110,0,
+ /* 33340 */ 0360,0323,02,017,0337,0110,0,
+ /* 33347 */ 0360,0323,02,017,0164,0110,0,
+ /* 33354 */ 0360,0323,02,017,0166,0110,0,
+ /* 33361 */ 0360,0323,02,017,0165,0110,0,
+ /* 33368 */ 0360,0323,02,017,0144,0110,0,
+ /* 33375 */ 0360,0323,02,017,0146,0110,0,
+ /* 33382 */ 0360,0323,02,017,0145,0110,0,
+ /* 33389 */ 0360,0323,02,017,0365,0110,0,
+ /* 33396 */ 0360,0323,02,017,0345,0110,0,
+ /* 33403 */ 0360,0323,02,017,0325,0110,0,
+ /* 33410 */ 0360,0323,02,017,0353,0110,0,
+ /* 33417 */ 0360,0323,02,017,0362,0110,0,
+ /* 33424 */ 0360,02,017,0162,0206,025,0,
+ /* 33431 */ 0360,0323,02,017,0363,0110,0,
+ /* 33438 */ 0360,02,017,0163,0206,025,0,
+ /* 33445 */ 0360,0323,02,017,0361,0110,0,
+ /* 33452 */ 0360,02,017,0161,0206,025,0,
+ /* 33459 */ 0360,0323,02,017,0342,0110,0,
+ /* 33466 */ 0360,02,017,0162,0204,025,0,
+ /* 33473 */ 0360,0323,02,017,0341,0110,0,
+ /* 33480 */ 0360,02,017,0161,0204,025,0,
+ /* 33487 */ 0360,0323,02,017,0322,0110,0,
+ /* 33494 */ 0360,02,017,0162,0202,025,0,
+ /* 33501 */ 0360,0323,02,017,0323,0110,0,
+ /* 33508 */ 0360,02,017,0163,0202,025,0,
+ /* 33515 */ 0360,0323,02,017,0321,0110,0,
+ /* 33522 */ 0360,02,017,0161,0202,025,0,
+ /* 33529 */ 0360,0323,02,017,0370,0110,0,
+ /* 33536 */ 0360,0323,02,017,0372,0110,0,
+ /* 33543 */ 0360,0323,02,017,0350,0110,0,
+ /* 33550 */ 0360,0323,02,017,0351,0110,0,
+ /* 33557 */ 0360,0323,02,017,0330,0110,0,
+ /* 33564 */ 0360,0323,02,017,0331,0110,0,
+ /* 33571 */ 0360,0323,02,017,0371,0110,0,
+ /* 33578 */ 0360,0323,02,017,0150,0110,0,
+ /* 33585 */ 0360,0323,02,017,0152,0110,0,
+ /* 33592 */ 0360,0323,02,017,0151,0110,0,
+ /* 33599 */ 0360,0323,02,017,0140,0110,0,
+ /* 33606 */ 0360,0323,02,017,0142,0110,0,
+ /* 33613 */ 0360,0323,02,017,0141,0110,0,
+ /* 33620 */ 0360,0323,02,017,0357,0110,0,
+ /* 33627 */ 0273,0320,01,0203,0203,0275,0,
+ /* 33634 */ 0273,0321,01,0203,0203,0275,0,
+ /* 33641 */ 0273,0324,01,0203,0203,0275,0,
+ /* 33648 */ 0273,0320,01,0201,0203,031,0,
+ /* 33655 */ 0273,0321,01,0201,0203,041,0,
+ /* 33662 */ 0273,0324,01,0201,0203,0255,0,
+ /* 33669 */ 0320,02,017,0244,0101,026,0,
+ /* 33676 */ 0321,02,017,0244,0101,026,0,
+ /* 33683 */ 0324,02,017,0244,0101,026,0,
+ /* 33690 */ 0320,02,017,0254,0101,026,0,
+ /* 33697 */ 0321,02,017,0254,0101,026,0,
+ /* 33704 */ 0324,02,017,0254,0101,026,0,
+ /* 33711 */ 0273,0320,01,0203,0205,0275,0,
+ /* 33718 */ 0273,0321,01,0203,0205,0275,0,
+ /* 33725 */ 0273,0324,01,0203,0205,0275,0,
+ /* 33732 */ 0273,0320,01,0201,0205,031,0,
+ /* 33739 */ 0273,0321,01,0201,0205,041,0,
+ /* 33746 */ 0273,0324,01,0201,0205,0255,0,
+ /* 33753 */ 0360,0320,02,017,021,0101,0,
+ /* 33760 */ 0360,0321,02,017,021,0101,0,
+ /* 33767 */ 0360,0320,02,017,023,0110,0,
+ /* 33774 */ 0360,0321,02,017,023,0110,0,
+ /* 33781 */ 0273,0320,02,017,0301,0101,0,
+ /* 33788 */ 0273,0321,02,017,0301,0101,0,
+ /* 33795 */ 0273,0324,02,017,0301,0101,0,
+ /* 33802 */ 0273,0320,01,0203,0206,0275,0,
+ /* 33809 */ 0273,0321,01,0203,0206,0275,0,
+ /* 33816 */ 0273,0324,01,0203,0206,0275,0,
+ /* 33823 */ 0273,0320,01,0201,0206,031,0,
+ /* 33830 */ 0273,0321,01,0201,0206,041,0,
+ /* 33837 */ 0273,0324,01,0201,0206,0255,0,
+ /* 33844 */ 01,0166,0373,01,0351,064,0,
+ /* 33851 */ 01,0162,0373,01,0351,064,0,
+ /* 33858 */ 01,0163,0373,01,0351,064,0,
+ /* 33865 */ 01,0167,0373,01,0351,064,0,
+ /* 33872 */ 01,0165,0373,01,0351,064,0,
+ /* 33879 */ 01,0176,0373,01,0351,064,0,
+ /* 33886 */ 01,0174,0373,01,0351,064,0,
+ /* 33893 */ 01,0175,0373,01,0351,064,0,
+ /* 33900 */ 01,0177,0373,01,0351,064,0,
+ /* 33907 */ 01,0164,0373,01,0351,064,0,
+ /* 33914 */ 01,0160,0373,01,0351,064,0,
+ /* 33921 */ 01,0172,0373,01,0351,064,0,
+ /* 33928 */ 01,0170,0373,01,0351,064,0,
+ /* 33935 */ 01,0161,0373,01,0351,064,0,
+ /* 33942 */ 01,0173,0373,01,0351,064,0,
+ /* 33949 */ 01,0171,0373,01,0351,064,0,
+ /* 33956 */ 0360,02,017,0302,0110,026,0,
+ /* 33963 */ 0333,02,017,0302,0110,026,0,
+ /* 33970 */ 0324,0333,02,017,052,0110,0,
+ /* 33977 */ 0324,0333,02,017,055,0110,0,
+ /* 33984 */ 0324,0333,02,017,054,0110,0,
+ /* 33991 */ 0360,0324,02,017,0120,0110,0,
+ /* 33998 */ 0360,02,017,0306,0110,026,0,
+ /* 34005 */ 0324,0360,02,017,0256,0201,0,
+ /* 34012 */ 0324,0360,02,017,0256,0200,0,
+ /* 34019 */ 0324,0360,02,017,0256,0204,0,
+ /* 34026 */ 0324,0360,02,017,0307,0204,0,
+ /* 34033 */ 0324,0360,02,017,0256,0206,0,
+ /* 34040 */ 0324,0360,02,017,0307,0205,0,
+ /* 34047 */ 0324,0360,02,017,0256,0205,0,
+ /* 34054 */ 0324,0360,02,017,0307,0203,0,
+ /* 34061 */ 0360,0323,02,017,0340,0110,0,
+ /* 34068 */ 0360,0323,02,017,0343,0110,0,
+ /* 34075 */ 0360,02,017,0305,0110,026,0,
+ /* 34082 */ 0360,02,017,0304,0110,026,0,
+ /* 34089 */ 0360,0323,02,017,0356,0110,0,
+ /* 34096 */ 0360,0323,02,017,0336,0110,0,
+ /* 34103 */ 0360,0323,02,017,0352,0110,0,
+ /* 34110 */ 0360,0323,02,017,0332,0110,0,
+ /* 34117 */ 0360,0323,02,017,0344,0110,0,
+ /* 34124 */ 0360,0323,02,017,0366,0110,0,
+ /* 34131 */ 0324,0360,02,017,0303,0101,0,
+ /* 34138 */ 0361,0317,02,017,0176,0101,0,
+ /* 34145 */ 0361,0317,02,017,0156,0110,0,
+ /* 34152 */ 0361,0324,02,017,0156,0110,0,
+ /* 34159 */ 0361,0324,02,017,0176,0101,0,
+ /* 34166 */ 0361,02,017,0305,0110,026,0,
+ /* 34173 */ 0361,02,017,0304,0110,026,0,
+ /* 34180 */ 0360,0323,02,017,0364,0110,0,
+ /* 34187 */ 0361,02,017,0160,0110,022,0,
+ /* 34194 */ 0333,02,017,0160,0110,022,0,
+ /* 34201 */ 0332,02,017,0160,0110,022,0,
+ /* 34208 */ 0361,02,017,0163,0207,025,0,
+ /* 34215 */ 0361,02,017,0161,0206,025,0,
+ /* 34222 */ 0361,02,017,0162,0206,025,0,
+ /* 34229 */ 0361,02,017,0163,0206,025,0,
+ /* 34236 */ 0361,02,017,0161,0204,025,0,
+ /* 34243 */ 0361,02,017,0162,0204,025,0,
+ /* 34250 */ 0361,02,017,0163,0203,025,0,
+ /* 34257 */ 0361,02,017,0161,0202,025,0,
+ /* 34264 */ 0361,02,017,0162,0202,025,0,
+ /* 34271 */ 0361,02,017,0163,0202,025,0,
+ /* 34278 */ 0360,0323,02,017,0373,0110,0,
+ /* 34285 */ 0361,02,017,0302,0110,026,0,
+ /* 34292 */ 0332,02,017,0302,0110,026,0,
+ /* 34299 */ 0317,0332,02,017,055,0110,0,
+ /* 34306 */ 0324,0332,02,017,055,0110,0,
+ /* 34313 */ 0317,0332,02,017,052,0110,0,
+ /* 34320 */ 0324,0332,02,017,052,0110,0,
+ /* 34327 */ 0317,0332,02,017,054,0110,0,
+ /* 34334 */ 0324,0332,02,017,054,0110,0,
+ /* 34341 */ 0361,0324,02,017,0120,0110,0,
+ /* 34348 */ 0361,02,017,0306,0110,026,0,
+ /* 34355 */ 0323,0360,02,017,0170,0101,0,
+ /* 34362 */ 0323,0360,02,017,0171,0110,0,
+ /* 34369 */ 0360,03,017,070,034,0110,0,
+ /* 34376 */ 0361,03,017,070,034,0110,0,
+ /* 34383 */ 0360,03,017,070,035,0110,0,
+ /* 34390 */ 0361,03,017,070,035,0110,0,
+ /* 34397 */ 0360,03,017,070,036,0110,0,
+ /* 34404 */ 0361,03,017,070,036,0110,0,
+ /* 34411 */ 0360,03,017,070,01,0110,0,
+ /* 34418 */ 0361,03,017,070,01,0110,0,
+ /* 34425 */ 0360,03,017,070,02,0110,0,
+ /* 34432 */ 0361,03,017,070,02,0110,0,
+ /* 34439 */ 0360,03,017,070,03,0110,0,
+ /* 34446 */ 0361,03,017,070,03,0110,0,
+ /* 34453 */ 0360,03,017,070,05,0110,0,
+ /* 34460 */ 0361,03,017,070,05,0110,0,
+ /* 34467 */ 0360,03,017,070,06,0110,0,
+ /* 34474 */ 0361,03,017,070,06,0110,0,
+ /* 34481 */ 0360,03,017,070,07,0110,0,
+ /* 34488 */ 0361,03,017,070,07,0110,0,
+ /* 34495 */ 0360,03,017,070,04,0110,0,
+ /* 34502 */ 0361,03,017,070,04,0110,0,
+ /* 34509 */ 0360,03,017,070,013,0110,0,
+ /* 34516 */ 0361,03,017,070,013,0110,0,
+ /* 34523 */ 0360,03,017,070,0,0110,0,
+ /* 34530 */ 0361,03,017,070,0,0110,0,
+ /* 34537 */ 0360,03,017,070,010,0110,0,
+ /* 34544 */ 0361,03,017,070,010,0110,0,
+ /* 34551 */ 0360,03,017,070,011,0110,0,
+ /* 34558 */ 0361,03,017,070,011,0110,0,
+ /* 34565 */ 0360,03,017,070,012,0110,0,
+ /* 34572 */ 0361,03,017,070,012,0110,0,
+ /* 34579 */ 0320,0333,02,017,0275,0110,0,
+ /* 34586 */ 0321,0333,02,017,0275,0110,0,
+ /* 34593 */ 0324,0333,02,017,0275,0110,0,
+ /* 34600 */ 0361,03,017,070,025,0110,0,
+ /* 34607 */ 0361,03,017,070,024,0110,0,
+ /* 34614 */ 0361,03,017,070,052,0110,0,
+ /* 34621 */ 0361,03,017,070,053,0110,0,
+ /* 34628 */ 0361,03,017,070,020,0110,0,
+ /* 34635 */ 0361,03,017,070,051,0110,0,
+ /* 34642 */ 0361,03,017,070,0101,0110,0,
+ /* 34649 */ 0361,03,017,070,074,0110,0,
+ /* 34656 */ 0361,03,017,070,075,0110,0,
+ /* 34663 */ 0361,03,017,070,077,0110,0,
+ /* 34670 */ 0361,03,017,070,076,0110,0,
+ /* 34677 */ 0361,03,017,070,070,0110,0,
+ /* 34684 */ 0361,03,017,070,071,0110,0,
+ /* 34691 */ 0361,03,017,070,073,0110,0,
+ /* 34698 */ 0361,03,017,070,072,0110,0,
+ /* 34705 */ 0361,03,017,070,040,0110,0,
+ /* 34712 */ 0361,03,017,070,041,0110,0,
+ /* 34719 */ 0361,03,017,070,042,0110,0,
+ /* 34726 */ 0361,03,017,070,043,0110,0,
+ /* 34733 */ 0361,03,017,070,044,0110,0,
+ /* 34740 */ 0361,03,017,070,045,0110,0,
+ /* 34747 */ 0361,03,017,070,060,0110,0,
+ /* 34754 */ 0361,03,017,070,061,0110,0,
+ /* 34761 */ 0361,03,017,070,062,0110,0,
+ /* 34768 */ 0361,03,017,070,063,0110,0,
+ /* 34775 */ 0361,03,017,070,064,0110,0,
+ /* 34782 */ 0361,03,017,070,065,0110,0,
+ /* 34789 */ 0361,03,017,070,050,0110,0,
+ /* 34796 */ 0361,03,017,070,0100,0110,0,
+ /* 34803 */ 0361,03,017,070,027,0110,0,
+ /* 34810 */ 0361,03,017,070,067,0110,0,
+ /* 34817 */ 0320,0333,02,017,0270,0110,0,
+ /* 34824 */ 0321,0333,02,017,0270,0110,0,
+ /* 34831 */ 0324,0333,02,017,0270,0110,0,
+ /* 34838 */ 0361,03,017,070,0334,0110,0,
+ /* 34845 */ 0361,03,017,070,0335,0110,0,
+ /* 34852 */ 0361,03,017,070,0336,0110,0,
+ /* 34859 */ 0361,03,017,070,0337,0110,0,
+ /* 34866 */ 0361,03,017,070,0333,0110,0,
+ /* 34873 */ 0261,02,041,01,0334,0120,0,
+ /* 34880 */ 0260,02,041,01,0334,0110,0,
+ /* 34887 */ 0261,02,041,01,0335,0120,0,
+ /* 34894 */ 0260,02,041,01,0335,0110,0,
+ /* 34901 */ 0261,02,041,01,0336,0120,0,
+ /* 34908 */ 0260,02,041,01,0336,0110,0,
+ /* 34915 */ 0261,02,041,01,0337,0120,0,
+ /* 34922 */ 0260,02,041,01,0337,0110,0,
+ /* 34929 */ 0270,02,041,01,0333,0110,0,
+ /* 34936 */ 0261,02,045,01,0334,0120,0,
+ /* 34943 */ 0260,02,045,01,0334,0110,0,
+ /* 34950 */ 0261,02,045,01,0335,0120,0,
+ /* 34957 */ 0260,02,045,01,0335,0110,0,
+ /* 34964 */ 0261,02,045,01,0336,0120,0,
+ /* 34971 */ 0260,02,045,01,0336,0110,0,
+ /* 34978 */ 0261,02,045,01,0337,0120,0,
+ /* 34985 */ 0260,02,045,01,0337,0110,0,
+ /* 34992 */ 0261,01,041,01,0130,0120,0,
+ /* 34999 */ 0260,01,041,01,0130,0110,0,
+ /* 35006 */ 0261,01,045,01,0130,0120,0,
+ /* 35013 */ 0260,01,045,01,0130,0110,0,
+ /* 35020 */ 0261,01,040,01,0130,0120,0,
+ /* 35027 */ 0260,01,040,01,0130,0110,0,
+ /* 35034 */ 0261,01,044,01,0130,0120,0,
+ /* 35041 */ 0260,01,044,01,0130,0110,0,
+ /* 35048 */ 0261,01,053,01,0130,0120,0,
+ /* 35055 */ 0260,01,053,01,0130,0110,0,
+ /* 35062 */ 0261,01,052,01,0130,0120,0,
+ /* 35069 */ 0260,01,052,01,0130,0110,0,
+ /* 35076 */ 0261,01,041,01,0320,0120,0,
+ /* 35083 */ 0260,01,041,01,0320,0110,0,
+ /* 35090 */ 0261,01,045,01,0320,0120,0,
+ /* 35097 */ 0260,01,045,01,0320,0110,0,
+ /* 35104 */ 0261,01,043,01,0320,0120,0,
+ /* 35111 */ 0260,01,043,01,0320,0110,0,
+ /* 35118 */ 0261,01,047,01,0320,0120,0,
+ /* 35125 */ 0260,01,047,01,0320,0110,0,
+ /* 35132 */ 0261,01,041,01,0124,0120,0,
+ /* 35139 */ 0260,01,041,01,0124,0110,0,
+ /* 35146 */ 0261,01,045,01,0124,0120,0,
+ /* 35153 */ 0260,01,045,01,0124,0110,0,
+ /* 35160 */ 0261,01,040,01,0124,0120,0,
+ /* 35167 */ 0260,01,040,01,0124,0110,0,
+ /* 35174 */ 0261,01,044,01,0124,0120,0,
+ /* 35181 */ 0260,01,044,01,0124,0110,0,
+ /* 35188 */ 0261,01,041,01,0125,0120,0,
+ /* 35195 */ 0260,01,041,01,0125,0110,0,
+ /* 35202 */ 0261,01,045,01,0125,0120,0,
+ /* 35209 */ 0260,01,045,01,0125,0110,0,
+ /* 35216 */ 0261,01,040,01,0125,0120,0,
+ /* 35223 */ 0260,01,040,01,0125,0110,0,
+ /* 35230 */ 0261,01,044,01,0125,0120,0,
+ /* 35237 */ 0260,01,044,01,0125,0110,0,
+ /* 35244 */ 0270,02,01,01,030,0110,0,
+ /* 35251 */ 0270,02,05,01,030,0110,0,
+ /* 35258 */ 0270,02,05,01,031,0110,0,
+ /* 35265 */ 0270,02,05,01,032,0110,0,
+ /* 35272 */ 0270,01,051,01,057,0110,0,
+ /* 35279 */ 0270,01,050,01,057,0110,0,
+ /* 35286 */ 0270,01,042,01,0346,0110,0,
+ /* 35293 */ 0270,01,046,01,0346,0110,0,
+ /* 35300 */ 0270,01,040,01,0133,0110,0,
+ /* 35307 */ 0270,01,044,01,0133,0110,0,
+ /* 35314 */ 0270,01,043,01,0346,0110,0,
+ /* 35321 */ 0270,01,047,01,0346,0110,0,
+ /* 35328 */ 0270,01,041,01,0132,0110,0,
+ /* 35335 */ 0270,01,045,01,0132,0110,0,
+ /* 35342 */ 0270,01,041,01,0133,0110,0,
+ /* 35349 */ 0270,01,045,01,0133,0110,0,
+ /* 35356 */ 0270,01,040,01,0132,0110,0,
+ /* 35363 */ 0270,01,044,01,0132,0110,0,
+ /* 35370 */ 0270,01,013,01,055,0110,0,
+ /* 35377 */ 0270,01,033,01,055,0110,0,
+ /* 35384 */ 0261,01,053,01,0132,0120,0,
+ /* 35391 */ 0260,01,053,01,0132,0110,0,
+ /* 35398 */ 0261,01,013,01,052,0120,0,
+ /* 35405 */ 0260,01,013,01,052,0110,0,
+ /* 35412 */ 0261,01,033,01,052,0120,0,
+ /* 35419 */ 0260,01,033,01,052,0110,0,
+ /* 35426 */ 0261,01,012,01,052,0120,0,
+ /* 35433 */ 0260,01,012,01,052,0110,0,
+ /* 35440 */ 0261,01,032,01,052,0120,0,
+ /* 35447 */ 0260,01,032,01,052,0110,0,
+ /* 35454 */ 0261,01,052,01,0132,0120,0,
+ /* 35461 */ 0260,01,052,01,0132,0110,0,
+ /* 35468 */ 0270,01,012,01,055,0110,0,
+ /* 35475 */ 0270,01,032,01,055,0110,0,
+ /* 35482 */ 0270,01,041,01,0346,0110,0,
+ /* 35489 */ 0270,01,045,01,0346,0110,0,
+ /* 35496 */ 0270,01,042,01,0133,0110,0,
+ /* 35503 */ 0270,01,046,01,0133,0110,0,
+ /* 35510 */ 0270,01,013,01,054,0110,0,
+ /* 35517 */ 0270,01,033,01,054,0110,0,
+ /* 35524 */ 0270,01,012,01,054,0110,0,
+ /* 35531 */ 0270,01,032,01,054,0110,0,
+ /* 35538 */ 0261,01,041,01,0136,0120,0,
+ /* 35545 */ 0260,01,041,01,0136,0110,0,
+ /* 35552 */ 0261,01,045,01,0136,0120,0,
+ /* 35559 */ 0260,01,045,01,0136,0110,0,
+ /* 35566 */ 0261,01,040,01,0136,0120,0,
+ /* 35573 */ 0260,01,040,01,0136,0110,0,
+ /* 35580 */ 0261,01,044,01,0136,0120,0,
+ /* 35587 */ 0260,01,044,01,0136,0110,0,
+ /* 35594 */ 0261,01,053,01,0136,0120,0,
+ /* 35601 */ 0260,01,053,01,0136,0110,0,
+ /* 35608 */ 0261,01,052,01,0136,0120,0,
+ /* 35615 */ 0260,01,052,01,0136,0110,0,
+ /* 35622 */ 0261,01,041,01,0174,0120,0,
+ /* 35629 */ 0260,01,041,01,0174,0110,0,
+ /* 35636 */ 0261,01,045,01,0174,0120,0,
+ /* 35643 */ 0260,01,045,01,0174,0110,0,
+ /* 35650 */ 0261,01,043,01,0174,0120,0,
+ /* 35657 */ 0260,01,043,01,0174,0110,0,
+ /* 35664 */ 0261,01,047,01,0174,0120,0,
+ /* 35671 */ 0260,01,047,01,0174,0110,0,
+ /* 35678 */ 0261,01,041,01,0175,0120,0,
+ /* 35685 */ 0260,01,041,01,0175,0110,0,
+ /* 35692 */ 0261,01,045,01,0175,0120,0,
+ /* 35699 */ 0260,01,045,01,0175,0110,0,
+ /* 35706 */ 0261,01,043,01,0175,0120,0,
+ /* 35713 */ 0260,01,043,01,0175,0110,0,
+ /* 35720 */ 0261,01,047,01,0175,0120,0,
+ /* 35727 */ 0260,01,047,01,0175,0110,0,
+ /* 35734 */ 0270,01,043,01,0360,0110,0,
+ /* 35741 */ 0270,01,047,01,0360,0110,0,
+ /* 35748 */ 0270,01,040,01,0256,0202,0,
+ /* 35755 */ 0270,01,041,01,0367,0110,0,
+ /* 35762 */ 0261,02,01,01,054,0120,0,
+ /* 35769 */ 0261,02,05,01,054,0120,0,
+ /* 35776 */ 0261,02,01,01,056,0102,0,
+ /* 35783 */ 0261,02,05,01,056,0102,0,
+ /* 35790 */ 0261,02,01,01,055,0120,0,
+ /* 35797 */ 0261,02,05,01,055,0120,0,
+ /* 35804 */ 0261,02,01,01,057,0102,0,
+ /* 35811 */ 0261,02,05,01,057,0102,0,
+ /* 35818 */ 0261,01,041,01,0137,0120,0,
+ /* 35825 */ 0260,01,041,01,0137,0110,0,
+ /* 35832 */ 0261,01,045,01,0137,0120,0,
+ /* 35839 */ 0260,01,045,01,0137,0110,0,
+ /* 35846 */ 0261,01,040,01,0137,0120,0,
+ /* 35853 */ 0260,01,040,01,0137,0110,0,
+ /* 35860 */ 0261,01,044,01,0137,0120,0,
+ /* 35867 */ 0260,01,044,01,0137,0110,0,
+ /* 35874 */ 0261,01,053,01,0137,0120,0,
+ /* 35881 */ 0260,01,053,01,0137,0110,0,
+ /* 35888 */ 0261,01,052,01,0137,0120,0,
+ /* 35895 */ 0260,01,052,01,0137,0110,0,
+ /* 35902 */ 0261,01,041,01,0135,0120,0,
+ /* 35909 */ 0260,01,041,01,0135,0110,0,
+ /* 35916 */ 0261,01,045,01,0135,0120,0,
+ /* 35923 */ 0260,01,045,01,0135,0110,0,
+ /* 35930 */ 0261,01,040,01,0135,0120,0,
+ /* 35937 */ 0260,01,040,01,0135,0110,0,
+ /* 35944 */ 0261,01,044,01,0135,0120,0,
+ /* 35951 */ 0260,01,044,01,0135,0110,0,
+ /* 35958 */ 0261,01,053,01,0135,0120,0,
+ /* 35965 */ 0260,01,053,01,0135,0110,0,
+ /* 35972 */ 0261,01,052,01,0135,0120,0,
+ /* 35979 */ 0260,01,052,01,0135,0110,0,
+ /* 35986 */ 0270,01,041,01,050,0110,0,
+ /* 35993 */ 0270,01,041,01,051,0101,0,
+ /* 36000 */ 0270,01,045,01,050,0110,0,
+ /* 36007 */ 0270,01,045,01,051,0101,0,
+ /* 36014 */ 0270,01,040,01,050,0110,0,
+ /* 36021 */ 0270,01,040,01,051,0101,0,
+ /* 36028 */ 0270,01,044,01,050,0110,0,
+ /* 36035 */ 0270,01,044,01,051,0101,0,
+ /* 36042 */ 0270,01,01,01,0156,0110,0,
+ /* 36049 */ 0270,01,01,01,0176,0101,0,
+ /* 36056 */ 0270,01,042,01,0176,0110,0,
+ /* 36063 */ 0270,01,041,01,0326,0101,0,
+ /* 36070 */ 0270,01,021,01,0156,0110,0,
+ /* 36077 */ 0270,01,021,01,0176,0101,0,
+ /* 36084 */ 0270,01,043,01,022,0110,0,
+ /* 36091 */ 0270,01,047,01,022,0110,0,
+ /* 36098 */ 0270,01,041,01,0157,0110,0,
+ /* 36105 */ 0270,01,041,01,0177,0101,0,
+ /* 36112 */ 0270,01,045,01,0157,0110,0,
+ /* 36119 */ 0270,01,045,01,0177,0101,0,
+ /* 36126 */ 0270,01,042,01,0157,0110,0,
+ /* 36133 */ 0270,01,042,01,0177,0101,0,
+ /* 36140 */ 0270,01,046,01,0157,0110,0,
+ /* 36147 */ 0270,01,046,01,0177,0101,0,
+ /* 36154 */ 0261,01,040,01,022,0120,0,
+ /* 36161 */ 0260,01,040,01,022,0110,0,
+ /* 36168 */ 0261,01,041,01,026,0120,0,
+ /* 36175 */ 0260,01,041,01,026,0110,0,
+ /* 36182 */ 0270,01,041,01,027,0101,0,
+ /* 36189 */ 0261,01,040,01,026,0120,0,
+ /* 36196 */ 0260,01,040,01,026,0110,0,
+ /* 36203 */ 0270,01,040,01,027,0101,0,
+ /* 36210 */ 0261,01,041,01,022,0120,0,
+ /* 36217 */ 0260,01,041,01,022,0110,0,
+ /* 36224 */ 0270,01,041,01,023,0101,0,
+ /* 36231 */ 0270,01,040,01,023,0101,0,
+ /* 36238 */ 0270,01,041,01,0120,0110,0,
+ /* 36245 */ 0270,01,045,01,0120,0110,0,
+ /* 36252 */ 0270,01,040,01,0120,0110,0,
+ /* 36259 */ 0270,01,044,01,0120,0110,0,
+ /* 36266 */ 0270,01,041,01,0347,0101,0,
+ /* 36273 */ 0270,01,045,01,0347,0101,0,
+ /* 36280 */ 0270,02,041,01,052,0110,0,
+ /* 36287 */ 0270,01,041,01,053,0101,0,
+ /* 36294 */ 0270,01,045,01,053,0101,0,
+ /* 36301 */ 0270,01,040,01,053,0101,0,
+ /* 36308 */ 0270,01,044,01,053,0101,0,
+ /* 36315 */ 0261,01,053,01,020,0120,0,
+ /* 36322 */ 0260,01,053,01,020,0110,0,
+ /* 36329 */ 0270,01,053,01,020,0110,0,
+ /* 36336 */ 0261,01,053,01,021,0102,0,
+ /* 36343 */ 0260,01,053,01,021,0101,0,
+ /* 36350 */ 0270,01,053,01,021,0101,0,
+ /* 36357 */ 0270,01,042,01,026,0110,0,
+ /* 36364 */ 0270,01,046,01,026,0110,0,
+ /* 36371 */ 0270,01,042,01,022,0110,0,
+ /* 36378 */ 0270,01,046,01,022,0110,0,
+ /* 36385 */ 0261,01,052,01,020,0120,0,
+ /* 36392 */ 0260,01,052,01,020,0110,0,
+ /* 36399 */ 0270,01,052,01,020,0110,0,
+ /* 36406 */ 0261,01,052,01,021,0102,0,
+ /* 36413 */ 0260,01,052,01,021,0101,0,
+ /* 36420 */ 0270,01,052,01,021,0101,0,
+ /* 36427 */ 0270,01,041,01,020,0110,0,
+ /* 36434 */ 0270,01,041,01,021,0101,0,
+ /* 36441 */ 0270,01,045,01,020,0110,0,
+ /* 36448 */ 0270,01,045,01,021,0101,0,
+ /* 36455 */ 0270,01,040,01,020,0110,0,
+ /* 36462 */ 0270,01,040,01,021,0101,0,
+ /* 36469 */ 0270,01,044,01,020,0110,0,
+ /* 36476 */ 0270,01,044,01,021,0101,0,
+ /* 36483 */ 0261,01,041,01,0131,0120,0,
+ /* 36490 */ 0260,01,041,01,0131,0110,0,
+ /* 36497 */ 0261,01,045,01,0131,0120,0,
+ /* 36504 */ 0260,01,045,01,0131,0110,0,
+ /* 36511 */ 0261,01,040,01,0131,0120,0,
+ /* 36518 */ 0260,01,040,01,0131,0110,0,
+ /* 36525 */ 0261,01,044,01,0131,0120,0,
+ /* 36532 */ 0260,01,044,01,0131,0110,0,
+ /* 36539 */ 0261,01,053,01,0131,0120,0,
+ /* 36546 */ 0260,01,053,01,0131,0110,0,
+ /* 36553 */ 0261,01,052,01,0131,0120,0,
+ /* 36560 */ 0260,01,052,01,0131,0110,0,
+ /* 36567 */ 0261,01,041,01,0126,0120,0,
+ /* 36574 */ 0260,01,041,01,0126,0110,0,
+ /* 36581 */ 0261,01,045,01,0126,0120,0,
+ /* 36588 */ 0260,01,045,01,0126,0110,0,
+ /* 36595 */ 0261,01,040,01,0126,0120,0,
+ /* 36602 */ 0260,01,040,01,0126,0110,0,
+ /* 36609 */ 0261,01,044,01,0126,0120,0,
+ /* 36616 */ 0260,01,044,01,0126,0110,0,
+ /* 36623 */ 0270,02,041,01,034,0110,0,
+ /* 36630 */ 0270,02,041,01,035,0110,0,
+ /* 36637 */ 0270,02,041,01,036,0110,0,
+ /* 36644 */ 0261,01,041,01,0143,0120,0,
+ /* 36651 */ 0260,01,041,01,0143,0110,0,
+ /* 36658 */ 0261,01,041,01,0153,0120,0,
+ /* 36665 */ 0260,01,041,01,0153,0110,0,
+ /* 36672 */ 0261,01,041,01,0147,0120,0,
+ /* 36679 */ 0260,01,041,01,0147,0110,0,
+ /* 36686 */ 0261,02,041,01,053,0120,0,
+ /* 36693 */ 0260,02,041,01,053,0110,0,
+ /* 36700 */ 0261,01,041,01,0374,0120,0,
+ /* 36707 */ 0260,01,041,01,0374,0110,0,
+ /* 36714 */ 0261,01,041,01,0375,0120,0,
+ /* 36721 */ 0260,01,041,01,0375,0110,0,
+ /* 36728 */ 0261,01,041,01,0376,0120,0,
+ /* 36735 */ 0260,01,041,01,0376,0110,0,
+ /* 36742 */ 0261,01,041,01,0324,0120,0,
+ /* 36749 */ 0260,01,041,01,0324,0110,0,
+ /* 36756 */ 0261,01,041,01,0354,0120,0,
+ /* 36763 */ 0260,01,041,01,0354,0110,0,
+ /* 36770 */ 0261,01,041,01,0355,0120,0,
+ /* 36777 */ 0260,01,041,01,0355,0110,0,
+ /* 36784 */ 0261,01,041,01,0334,0120,0,
+ /* 36791 */ 0260,01,041,01,0334,0110,0,
+ /* 36798 */ 0261,01,041,01,0335,0120,0,
+ /* 36805 */ 0260,01,041,01,0335,0110,0,
+ /* 36812 */ 0261,01,041,01,0333,0120,0,
+ /* 36819 */ 0260,01,041,01,0333,0110,0,
+ /* 36826 */ 0261,01,041,01,0337,0120,0,
+ /* 36833 */ 0260,01,041,01,0337,0110,0,
+ /* 36840 */ 0261,01,041,01,0340,0120,0,
+ /* 36847 */ 0260,01,041,01,0340,0110,0,
+ /* 36854 */ 0261,01,041,01,0343,0120,0,
+ /* 36861 */ 0260,01,041,01,0343,0110,0,
+ /* 36868 */ 0261,01,041,01,0164,0120,0,
+ /* 36875 */ 0260,01,041,01,0164,0110,0,
+ /* 36882 */ 0261,01,041,01,0165,0120,0,
+ /* 36889 */ 0260,01,041,01,0165,0110,0,
+ /* 36896 */ 0261,01,041,01,0166,0120,0,
+ /* 36903 */ 0260,01,041,01,0166,0110,0,
+ /* 36910 */ 0261,02,041,01,051,0120,0,
+ /* 36917 */ 0260,02,041,01,051,0110,0,
+ /* 36924 */ 0261,01,041,01,0144,0120,0,
+ /* 36931 */ 0260,01,041,01,0144,0110,0,
+ /* 36938 */ 0261,01,041,01,0145,0120,0,
+ /* 36945 */ 0260,01,041,01,0145,0110,0,
+ /* 36952 */ 0261,01,041,01,0146,0120,0,
+ /* 36959 */ 0260,01,041,01,0146,0110,0,
+ /* 36966 */ 0261,02,041,01,067,0120,0,
+ /* 36973 */ 0260,02,041,01,067,0110,0,
+ /* 36980 */ 0261,02,01,01,015,0120,0,
+ /* 36987 */ 0260,02,01,01,015,0110,0,
+ /* 36994 */ 0261,02,05,01,015,0120,0,
+ /* 37001 */ 0260,02,05,01,015,0110,0,
+ /* 37008 */ 0261,02,01,01,014,0120,0,
+ /* 37015 */ 0260,02,01,01,014,0110,0,
+ /* 37022 */ 0261,02,05,01,014,0120,0,
+ /* 37029 */ 0260,02,05,01,014,0110,0,
+ /* 37036 */ 0261,02,041,01,01,0120,0,
+ /* 37043 */ 0260,02,041,01,01,0110,0,
+ /* 37050 */ 0261,02,041,01,02,0120,0,
+ /* 37057 */ 0260,02,041,01,02,0110,0,
+ /* 37064 */ 0261,02,041,01,03,0120,0,
+ /* 37071 */ 0260,02,041,01,03,0110,0,
+ /* 37078 */ 0270,02,041,01,0101,0110,0,
+ /* 37085 */ 0261,02,041,01,05,0120,0,
+ /* 37092 */ 0260,02,041,01,05,0110,0,
+ /* 37099 */ 0261,02,041,01,06,0120,0,
+ /* 37106 */ 0260,02,041,01,06,0110,0,
+ /* 37113 */ 0261,02,041,01,07,0120,0,
+ /* 37120 */ 0260,02,041,01,07,0110,0,
+ /* 37127 */ 0261,01,041,01,0365,0120,0,
+ /* 37134 */ 0260,01,041,01,0365,0110,0,
+ /* 37141 */ 0261,02,041,01,04,0120,0,
+ /* 37148 */ 0260,02,041,01,04,0110,0,
+ /* 37155 */ 0261,02,041,01,074,0120,0,
+ /* 37162 */ 0260,02,041,01,074,0110,0,
+ /* 37169 */ 0261,01,041,01,0356,0120,0,
+ /* 37176 */ 0260,01,041,01,0356,0110,0,
+ /* 37183 */ 0261,02,041,01,075,0120,0,
+ /* 37190 */ 0260,02,041,01,075,0110,0,
+ /* 37197 */ 0261,01,041,01,0336,0120,0,
+ /* 37204 */ 0260,01,041,01,0336,0110,0,
+ /* 37211 */ 0261,02,041,01,076,0120,0,
+ /* 37218 */ 0260,02,041,01,076,0110,0,
+ /* 37225 */ 0261,02,041,01,077,0120,0,
+ /* 37232 */ 0260,02,041,01,077,0110,0,
+ /* 37239 */ 0261,02,041,01,070,0120,0,
+ /* 37246 */ 0260,02,041,01,070,0110,0,
+ /* 37253 */ 0261,01,041,01,0352,0120,0,
+ /* 37260 */ 0260,01,041,01,0352,0110,0,
+ /* 37267 */ 0261,02,041,01,071,0120,0,
+ /* 37274 */ 0260,02,041,01,071,0110,0,
+ /* 37281 */ 0261,01,041,01,0332,0120,0,
+ /* 37288 */ 0260,01,041,01,0332,0110,0,
+ /* 37295 */ 0261,02,041,01,072,0120,0,
+ /* 37302 */ 0260,02,041,01,072,0110,0,
+ /* 37309 */ 0261,02,041,01,073,0120,0,
+ /* 37316 */ 0260,02,041,01,073,0110,0,
+ /* 37323 */ 0270,01,041,01,0327,0110,0,
+ /* 37330 */ 0270,02,041,01,040,0110,0,
+ /* 37337 */ 0270,02,041,01,041,0110,0,
+ /* 37344 */ 0270,02,041,01,042,0110,0,
+ /* 37351 */ 0270,02,041,01,043,0110,0,
+ /* 37358 */ 0270,02,041,01,044,0110,0,
+ /* 37365 */ 0270,02,041,01,045,0110,0,
+ /* 37372 */ 0270,02,041,01,060,0110,0,
+ /* 37379 */ 0270,02,041,01,061,0110,0,
+ /* 37386 */ 0270,02,041,01,062,0110,0,
+ /* 37393 */ 0270,02,041,01,063,0110,0,
+ /* 37400 */ 0270,02,041,01,064,0110,0,
+ /* 37407 */ 0270,02,041,01,065,0110,0,
+ /* 37414 */ 0261,01,041,01,0344,0120,0,
+ /* 37421 */ 0260,01,041,01,0344,0110,0,
+ /* 37428 */ 0261,02,041,01,013,0120,0,
+ /* 37435 */ 0260,02,041,01,013,0110,0,
+ /* 37442 */ 0261,01,041,01,0345,0120,0,
+ /* 37449 */ 0260,01,041,01,0345,0110,0,
+ /* 37456 */ 0261,01,041,01,0325,0120,0,
+ /* 37463 */ 0260,01,041,01,0325,0110,0,
+ /* 37470 */ 0261,02,041,01,0100,0120,0,
+ /* 37477 */ 0260,02,041,01,0100,0110,0,
+ /* 37484 */ 0261,01,041,01,0364,0120,0,
+ /* 37491 */ 0260,01,041,01,0364,0110,0,
+ /* 37498 */ 0261,02,041,01,050,0120,0,
+ /* 37505 */ 0260,02,041,01,050,0110,0,
+ /* 37512 */ 0261,01,041,01,0353,0120,0,
+ /* 37519 */ 0260,01,041,01,0353,0110,0,
+ /* 37526 */ 0261,01,041,01,0366,0120,0,
+ /* 37533 */ 0260,01,041,01,0366,0110,0,
+ /* 37540 */ 0261,02,041,01,0,0120,0,
+ /* 37547 */ 0260,02,041,01,0,0110,0,
+ /* 37554 */ 0261,02,041,01,010,0120,0,
+ /* 37561 */ 0260,02,041,01,010,0110,0,
+ /* 37568 */ 0261,02,041,01,011,0120,0,
+ /* 37575 */ 0260,02,041,01,011,0110,0,
+ /* 37582 */ 0261,02,041,01,012,0120,0,
+ /* 37589 */ 0260,02,041,01,012,0110,0,
+ /* 37596 */ 0261,01,041,01,0361,0120,0,
+ /* 37603 */ 0260,01,041,01,0361,0110,0,
+ /* 37610 */ 0261,01,041,01,0362,0120,0,
+ /* 37617 */ 0260,01,041,01,0362,0110,0,
+ /* 37624 */ 0261,01,041,01,0363,0120,0,
+ /* 37631 */ 0260,01,041,01,0363,0110,0,
+ /* 37638 */ 0261,01,041,01,0341,0120,0,
+ /* 37645 */ 0260,01,041,01,0341,0110,0,
+ /* 37652 */ 0261,01,041,01,0342,0120,0,
+ /* 37659 */ 0260,01,041,01,0342,0110,0,
+ /* 37666 */ 0261,01,041,01,0321,0120,0,
+ /* 37673 */ 0260,01,041,01,0321,0110,0,
+ /* 37680 */ 0261,01,041,01,0322,0120,0,
+ /* 37687 */ 0260,01,041,01,0322,0110,0,
+ /* 37694 */ 0261,01,041,01,0323,0120,0,
+ /* 37701 */ 0260,01,041,01,0323,0110,0,
+ /* 37708 */ 0270,02,041,01,027,0110,0,
+ /* 37715 */ 0270,02,045,01,027,0110,0,
+ /* 37722 */ 0261,01,041,01,0370,0120,0,
+ /* 37729 */ 0260,01,041,01,0370,0110,0,
+ /* 37736 */ 0261,01,041,01,0371,0120,0,
+ /* 37743 */ 0260,01,041,01,0371,0110,0,
+ /* 37750 */ 0261,01,041,01,0372,0120,0,
+ /* 37757 */ 0260,01,041,01,0372,0110,0,
+ /* 37764 */ 0261,01,041,01,0373,0120,0,
+ /* 37771 */ 0260,01,041,01,0373,0110,0,
+ /* 37778 */ 0261,01,041,01,0350,0120,0,
+ /* 37785 */ 0260,01,041,01,0350,0110,0,
+ /* 37792 */ 0261,01,041,01,0351,0120,0,
+ /* 37799 */ 0260,01,041,01,0351,0110,0,
+ /* 37806 */ 0261,01,041,01,0330,0120,0,
+ /* 37813 */ 0260,01,041,01,0330,0110,0,
+ /* 37820 */ 0261,01,041,01,0331,0120,0,
+ /* 37827 */ 0260,01,041,01,0331,0110,0,
+ /* 37834 */ 0261,01,041,01,0150,0120,0,
+ /* 37841 */ 0260,01,041,01,0150,0110,0,
+ /* 37848 */ 0261,01,041,01,0151,0120,0,
+ /* 37855 */ 0260,01,041,01,0151,0110,0,
+ /* 37862 */ 0261,01,041,01,0152,0120,0,
+ /* 37869 */ 0260,01,041,01,0152,0110,0,
+ /* 37876 */ 0261,01,041,01,0155,0120,0,
+ /* 37883 */ 0260,01,041,01,0155,0110,0,
+ /* 37890 */ 0261,01,041,01,0140,0120,0,
+ /* 37897 */ 0260,01,041,01,0140,0110,0,
+ /* 37904 */ 0261,01,041,01,0141,0120,0,
+ /* 37911 */ 0260,01,041,01,0141,0110,0,
+ /* 37918 */ 0261,01,041,01,0142,0120,0,
+ /* 37925 */ 0260,01,041,01,0142,0110,0,
+ /* 37932 */ 0261,01,041,01,0154,0120,0,
+ /* 37939 */ 0260,01,041,01,0154,0110,0,
+ /* 37946 */ 0261,01,041,01,0357,0120,0,
+ /* 37953 */ 0260,01,041,01,0357,0110,0,
+ /* 37960 */ 0270,01,040,01,0123,0110,0,
+ /* 37967 */ 0270,01,044,01,0123,0110,0,
+ /* 37974 */ 0261,01,052,01,0123,0120,0,
+ /* 37981 */ 0260,01,052,01,0123,0110,0,
+ /* 37988 */ 0270,01,040,01,0122,0110,0,
+ /* 37995 */ 0270,01,044,01,0122,0110,0,
+ /* 38002 */ 0261,01,052,01,0122,0120,0,
+ /* 38009 */ 0260,01,052,01,0122,0110,0,
+ /* 38016 */ 0270,01,041,01,0121,0110,0,
+ /* 38023 */ 0270,01,045,01,0121,0110,0,
+ /* 38030 */ 0270,01,040,01,0121,0110,0,
+ /* 38037 */ 0270,01,044,01,0121,0110,0,
+ /* 38044 */ 0261,01,053,01,0121,0120,0,
+ /* 38051 */ 0260,01,053,01,0121,0110,0,
+ /* 38058 */ 0261,01,052,01,0121,0120,0,
+ /* 38065 */ 0260,01,052,01,0121,0110,0,
+ /* 38072 */ 0270,01,040,01,0256,0203,0,
+ /* 38079 */ 0261,01,041,01,0134,0120,0,
+ /* 38086 */ 0260,01,041,01,0134,0110,0,
+ /* 38093 */ 0261,01,045,01,0134,0120,0,
+ /* 38100 */ 0260,01,045,01,0134,0110,0,
+ /* 38107 */ 0261,01,040,01,0134,0120,0,
+ /* 38114 */ 0260,01,040,01,0134,0110,0,
+ /* 38121 */ 0261,01,044,01,0134,0120,0,
+ /* 38128 */ 0260,01,044,01,0134,0110,0,
+ /* 38135 */ 0261,01,053,01,0134,0120,0,
+ /* 38142 */ 0260,01,053,01,0134,0110,0,
+ /* 38149 */ 0261,01,052,01,0134,0120,0,
+ /* 38156 */ 0260,01,052,01,0134,0110,0,
+ /* 38163 */ 0270,02,01,01,016,0110,0,
+ /* 38170 */ 0270,02,05,01,016,0110,0,
+ /* 38177 */ 0270,02,01,01,017,0110,0,
+ /* 38184 */ 0270,02,05,01,017,0110,0,
+ /* 38191 */ 0270,01,051,01,056,0110,0,
+ /* 38198 */ 0270,01,050,01,056,0110,0,
+ /* 38205 */ 0261,01,041,01,025,0120,0,
+ /* 38212 */ 0260,01,041,01,025,0110,0,
+ /* 38219 */ 0261,01,045,01,025,0120,0,
+ /* 38226 */ 0260,01,045,01,025,0110,0,
+ /* 38233 */ 0261,01,040,01,025,0120,0,
+ /* 38240 */ 0260,01,040,01,025,0110,0,
+ /* 38247 */ 0261,01,044,01,025,0120,0,
+ /* 38254 */ 0260,01,044,01,025,0110,0,
+ /* 38261 */ 0261,01,041,01,024,0120,0,
+ /* 38268 */ 0260,01,041,01,024,0110,0,
+ /* 38275 */ 0261,01,045,01,024,0120,0,
+ /* 38282 */ 0260,01,045,01,024,0110,0,
+ /* 38289 */ 0261,01,040,01,024,0120,0,
+ /* 38296 */ 0260,01,040,01,024,0110,0,
+ /* 38303 */ 0261,01,044,01,024,0120,0,
+ /* 38310 */ 0260,01,044,01,024,0110,0,
+ /* 38317 */ 0261,01,041,01,0127,0120,0,
+ /* 38324 */ 0260,01,041,01,0127,0110,0,
+ /* 38331 */ 0261,01,045,01,0127,0120,0,
+ /* 38338 */ 0260,01,045,01,0127,0110,0,
+ /* 38345 */ 0261,01,040,01,0127,0120,0,
+ /* 38352 */ 0260,01,040,01,0127,0110,0,
+ /* 38359 */ 0261,01,044,01,0127,0120,0,
+ /* 38366 */ 0260,01,044,01,0127,0110,0,
+ /* 38373 */ 0261,02,01,01,0230,0120,0,
+ /* 38380 */ 0261,02,05,01,0230,0120,0,
+ /* 38387 */ 0261,02,021,01,0230,0120,0,
+ /* 38394 */ 0261,02,025,01,0230,0120,0,
+ /* 38401 */ 0261,02,01,01,0250,0120,0,
+ /* 38408 */ 0261,02,05,01,0250,0120,0,
+ /* 38415 */ 0261,02,021,01,0250,0120,0,
+ /* 38422 */ 0261,02,025,01,0250,0120,0,
+ /* 38429 */ 0261,02,01,01,0270,0120,0,
+ /* 38436 */ 0261,02,05,01,0270,0120,0,
+ /* 38443 */ 0261,02,021,01,0270,0120,0,
+ /* 38450 */ 0261,02,025,01,0270,0120,0,
+ /* 38457 */ 0261,02,01,01,0226,0120,0,
+ /* 38464 */ 0261,02,05,01,0226,0120,0,
+ /* 38471 */ 0261,02,021,01,0226,0120,0,
+ /* 38478 */ 0261,02,025,01,0226,0120,0,
+ /* 38485 */ 0261,02,01,01,0246,0120,0,
+ /* 38492 */ 0261,02,05,01,0246,0120,0,
+ /* 38499 */ 0261,02,021,01,0246,0120,0,
+ /* 38506 */ 0261,02,025,01,0246,0120,0,
+ /* 38513 */ 0261,02,01,01,0266,0120,0,
+ /* 38520 */ 0261,02,05,01,0266,0120,0,
+ /* 38527 */ 0261,02,021,01,0266,0120,0,
+ /* 38534 */ 0261,02,025,01,0266,0120,0,
+ /* 38541 */ 0261,02,01,01,0232,0120,0,
+ /* 38548 */ 0261,02,05,01,0232,0120,0,
+ /* 38555 */ 0261,02,021,01,0232,0120,0,
+ /* 38562 */ 0261,02,025,01,0232,0120,0,
+ /* 38569 */ 0261,02,01,01,0252,0120,0,
+ /* 38576 */ 0261,02,05,01,0252,0120,0,
+ /* 38583 */ 0261,02,021,01,0252,0120,0,
+ /* 38590 */ 0261,02,025,01,0252,0120,0,
+ /* 38597 */ 0261,02,01,01,0272,0120,0,
+ /* 38604 */ 0261,02,05,01,0272,0120,0,
+ /* 38611 */ 0261,02,021,01,0272,0120,0,
+ /* 38618 */ 0261,02,025,01,0272,0120,0,
+ /* 38625 */ 0261,02,01,01,0227,0120,0,
+ /* 38632 */ 0261,02,05,01,0227,0120,0,
+ /* 38639 */ 0261,02,021,01,0227,0120,0,
+ /* 38646 */ 0261,02,025,01,0227,0120,0,
+ /* 38653 */ 0261,02,01,01,0247,0120,0,
+ /* 38660 */ 0261,02,05,01,0247,0120,0,
+ /* 38667 */ 0261,02,021,01,0247,0120,0,
+ /* 38674 */ 0261,02,025,01,0247,0120,0,
+ /* 38681 */ 0261,02,01,01,0267,0120,0,
+ /* 38688 */ 0261,02,05,01,0267,0120,0,
+ /* 38695 */ 0261,02,021,01,0267,0120,0,
+ /* 38702 */ 0261,02,025,01,0267,0120,0,
+ /* 38709 */ 0261,02,01,01,0234,0120,0,
+ /* 38716 */ 0261,02,05,01,0234,0120,0,
+ /* 38723 */ 0261,02,021,01,0234,0120,0,
+ /* 38730 */ 0261,02,025,01,0234,0120,0,
+ /* 38737 */ 0261,02,01,01,0254,0120,0,
+ /* 38744 */ 0261,02,05,01,0254,0120,0,
+ /* 38751 */ 0261,02,021,01,0254,0120,0,
+ /* 38758 */ 0261,02,025,01,0254,0120,0,
+ /* 38765 */ 0261,02,01,01,0274,0120,0,
+ /* 38772 */ 0261,02,05,01,0274,0120,0,
+ /* 38779 */ 0261,02,021,01,0274,0120,0,
+ /* 38786 */ 0261,02,025,01,0274,0120,0,
+ /* 38793 */ 0261,02,01,01,0236,0120,0,
+ /* 38800 */ 0261,02,05,01,0236,0120,0,
+ /* 38807 */ 0261,02,021,01,0236,0120,0,
+ /* 38814 */ 0261,02,025,01,0236,0120,0,
+ /* 38821 */ 0261,02,01,01,0256,0120,0,
+ /* 38828 */ 0261,02,05,01,0256,0120,0,
+ /* 38835 */ 0261,02,021,01,0256,0120,0,
+ /* 38842 */ 0261,02,025,01,0256,0120,0,
+ /* 38849 */ 0261,02,01,01,0276,0120,0,
+ /* 38856 */ 0261,02,05,01,0276,0120,0,
+ /* 38863 */ 0261,02,021,01,0276,0120,0,
+ /* 38870 */ 0261,02,025,01,0276,0120,0,
+ /* 38877 */ 0261,02,01,01,0231,0120,0,
+ /* 38884 */ 0261,02,021,01,0231,0120,0,
+ /* 38891 */ 0261,02,01,01,0251,0120,0,
+ /* 38898 */ 0261,02,021,01,0251,0120,0,
+ /* 38905 */ 0261,02,01,01,0271,0120,0,
+ /* 38912 */ 0261,02,021,01,0271,0120,0,
+ /* 38919 */ 0261,02,01,01,0233,0120,0,
+ /* 38926 */ 0261,02,021,01,0233,0120,0,
+ /* 38933 */ 0261,02,01,01,0253,0120,0,
+ /* 38940 */ 0261,02,021,01,0253,0120,0,
+ /* 38947 */ 0261,02,01,01,0273,0120,0,
+ /* 38954 */ 0261,02,021,01,0273,0120,0,
+ /* 38961 */ 0261,02,01,01,0235,0120,0,
+ /* 38968 */ 0261,02,021,01,0235,0120,0,
+ /* 38975 */ 0261,02,01,01,0255,0120,0,
+ /* 38982 */ 0261,02,021,01,0255,0120,0,
+ /* 38989 */ 0261,02,01,01,0275,0120,0,
+ /* 38996 */ 0261,02,021,01,0275,0120,0,
+ /* 39003 */ 0261,02,01,01,0237,0120,0,
+ /* 39010 */ 0261,02,021,01,0237,0120,0,
+ /* 39017 */ 0261,02,01,01,0257,0120,0,
+ /* 39024 */ 0261,02,021,01,0257,0120,0,
+ /* 39031 */ 0261,02,01,01,0277,0120,0,
+ /* 39038 */ 0261,02,021,01,0277,0120,0,
+ /* 39045 */ 0317,0333,02,017,0256,0200,0,
+ /* 39052 */ 0324,0333,02,017,0256,0200,0,
+ /* 39059 */ 0317,0333,02,017,0256,0201,0,
+ /* 39066 */ 0324,0333,02,017,0256,0201,0,
+ /* 39073 */ 0317,0333,02,017,0256,0202,0,
+ /* 39080 */ 0324,0333,02,017,0256,0202,0,
+ /* 39087 */ 0317,0333,02,017,0256,0203,0,
+ /* 39094 */ 0324,0333,02,017,0256,0203,0,
+ /* 39101 */ 0270,02,05,01,023,0110,0,
+ /* 39108 */ 0270,02,01,01,023,0110,0,
+ /* 39115 */ 0270,0111,0,01,022,0200,0,
+ /* 39122 */ 0270,0111,020,01,022,0200,0,
+ /* 39129 */ 0270,0111,0,01,022,0201,0,
+ /* 39136 */ 0270,0111,020,01,022,0201,0,
+ /* 39143 */ 0270,0111,0,01,0201,0110,0,
+ /* 39150 */ 0270,0111,0,01,0201,0100,0,
+ /* 39157 */ 0270,0111,04,01,0201,0110,0,
+ /* 39164 */ 0270,0111,04,01,0201,0100,0,
+ /* 39171 */ 0270,0111,0,01,0200,0110,0,
+ /* 39178 */ 0270,0111,0,01,0200,0100,0,
+ /* 39185 */ 0270,0111,04,01,0200,0110,0,
+ /* 39192 */ 0270,0111,04,01,0200,0100,0,
+ /* 39199 */ 0270,0111,0,01,0203,0110,0,
+ /* 39206 */ 0270,0111,0,01,0203,0100,0,
+ /* 39213 */ 0270,0111,0,01,0202,0110,0,
+ /* 39220 */ 0270,0111,0,01,0202,0100,0,
+ /* 39227 */ 0270,0111,0,01,0302,0110,0,
+ /* 39234 */ 0270,0111,0,01,0302,0100,0,
+ /* 39241 */ 0270,0111,0,01,0303,0110,0,
+ /* 39248 */ 0270,0111,0,01,0303,0100,0,
+ /* 39255 */ 0270,0111,0,01,0301,0110,0,
+ /* 39262 */ 0270,0111,0,01,0301,0100,0,
+ /* 39269 */ 0270,0111,0,01,0313,0110,0,
+ /* 39276 */ 0270,0111,0,01,0313,0100,0,
+ /* 39283 */ 0270,0111,0,01,0322,0110,0,
+ /* 39290 */ 0270,0111,0,01,0322,0100,0,
+ /* 39297 */ 0270,0111,0,01,0323,0110,0,
+ /* 39304 */ 0270,0111,0,01,0323,0100,0,
+ /* 39311 */ 0270,0111,0,01,0321,0110,0,
+ /* 39318 */ 0270,0111,0,01,0321,0100,0,
+ /* 39325 */ 0270,0111,0,01,0333,0110,0,
+ /* 39332 */ 0270,0111,0,01,0333,0100,0,
+ /* 39339 */ 0270,0111,0,01,0326,0110,0,
+ /* 39346 */ 0270,0111,0,01,0326,0100,0,
+ /* 39353 */ 0270,0111,0,01,0327,0110,0,
+ /* 39360 */ 0270,0111,0,01,0327,0100,0,
+ /* 39367 */ 0270,0111,0,01,0306,0110,0,
+ /* 39374 */ 0270,0111,0,01,0306,0100,0,
+ /* 39381 */ 0270,0111,0,01,0307,0110,0,
+ /* 39388 */ 0270,0111,0,01,0307,0100,0,
+ /* 39395 */ 0270,0111,0,01,0341,0110,0,
+ /* 39402 */ 0270,0111,0,01,0341,0100,0,
+ /* 39409 */ 0270,0111,0,01,0343,0110,0,
+ /* 39416 */ 0270,0111,0,01,0343,0100,0,
+ /* 39423 */ 0270,0111,0,01,0342,0110,0,
+ /* 39430 */ 0270,0111,0,01,0342,0100,0,
+ /* 39437 */ 0262,0111,0,01,0220,0110,0,
+ /* 39444 */ 0261,0111,0,01,0220,0100,0,
+ /* 39451 */ 0261,0111,020,01,0220,0120,0,
+ /* 39458 */ 0260,0111,020,01,0220,0110,0,
+ /* 39465 */ 0262,0111,0,01,0222,0110,0,
+ /* 39472 */ 0261,0111,0,01,0222,0100,0,
+ /* 39479 */ 0261,0111,020,01,0222,0120,0,
+ /* 39486 */ 0260,0111,020,01,0222,0110,0,
+ /* 39493 */ 0262,0111,0,01,0223,0110,0,
+ /* 39500 */ 0261,0111,0,01,0223,0100,0,
+ /* 39507 */ 0261,0111,020,01,0223,0120,0,
+ /* 39514 */ 0260,0111,020,01,0223,0110,0,
+ /* 39521 */ 0262,0111,0,01,0221,0110,0,
+ /* 39528 */ 0261,0111,0,01,0221,0100,0,
+ /* 39535 */ 0261,0111,020,01,0221,0120,0,
+ /* 39542 */ 0260,0111,020,01,0221,0110,0,
+ /* 39549 */ 0262,0111,0,01,0230,0110,0,
+ /* 39556 */ 0261,0111,0,01,0230,0100,0,
+ /* 39563 */ 0261,0111,020,01,0230,0120,0,
+ /* 39570 */ 0260,0111,020,01,0230,0110,0,
+ /* 39577 */ 0262,0111,0,01,0232,0110,0,
+ /* 39584 */ 0261,0111,0,01,0232,0100,0,
+ /* 39591 */ 0261,0111,020,01,0232,0120,0,
+ /* 39598 */ 0260,0111,020,01,0232,0110,0,
+ /* 39605 */ 0262,0111,0,01,0233,0110,0,
+ /* 39612 */ 0261,0111,0,01,0233,0100,0,
+ /* 39619 */ 0261,0111,020,01,0233,0120,0,
+ /* 39626 */ 0260,0111,020,01,0233,0110,0,
+ /* 39633 */ 0262,0111,0,01,0231,0110,0,
+ /* 39640 */ 0261,0111,0,01,0231,0100,0,
+ /* 39647 */ 0261,0111,020,01,0231,0120,0,
+ /* 39654 */ 0260,0111,020,01,0231,0110,0,
+ /* 39661 */ 0262,0111,0,01,0224,0110,0,
+ /* 39668 */ 0261,0111,0,01,0224,0100,0,
+ /* 39675 */ 0261,0111,020,01,0224,0120,0,
+ /* 39682 */ 0260,0111,020,01,0224,0110,0,
+ /* 39689 */ 0262,0111,0,01,0226,0110,0,
+ /* 39696 */ 0261,0111,0,01,0226,0100,0,
+ /* 39703 */ 0261,0111,020,01,0226,0120,0,
+ /* 39710 */ 0260,0111,020,01,0226,0110,0,
+ /* 39717 */ 0262,0111,0,01,0227,0110,0,
+ /* 39724 */ 0261,0111,0,01,0227,0100,0,
+ /* 39731 */ 0261,0111,020,01,0227,0120,0,
+ /* 39738 */ 0260,0111,020,01,0227,0110,0,
+ /* 39745 */ 0262,0111,0,01,0225,0110,0,
+ /* 39752 */ 0261,0111,0,01,0225,0100,0,
+ /* 39759 */ 0261,0111,020,01,0225,0120,0,
+ /* 39766 */ 0260,0111,020,01,0225,0110,0,
+ /* 39773 */ 0270,02,045,01,034,0110,0,
+ /* 39780 */ 0270,02,045,01,035,0110,0,
+ /* 39787 */ 0270,02,045,01,036,0110,0,
+ /* 39794 */ 0261,01,045,01,0143,0120,0,
+ /* 39801 */ 0260,01,045,01,0143,0110,0,
+ /* 39808 */ 0261,01,045,01,0153,0120,0,
+ /* 39815 */ 0260,01,045,01,0153,0110,0,
+ /* 39822 */ 0261,02,045,01,053,0120,0,
+ /* 39829 */ 0260,02,045,01,053,0110,0,
+ /* 39836 */ 0261,01,045,01,0147,0120,0,
+ /* 39843 */ 0260,01,045,01,0147,0110,0,
+ /* 39850 */ 0261,01,045,01,0374,0120,0,
+ /* 39857 */ 0260,01,045,01,0374,0110,0,
+ /* 39864 */ 0261,01,045,01,0375,0120,0,
+ /* 39871 */ 0260,01,045,01,0375,0110,0,
+ /* 39878 */ 0261,01,045,01,0376,0120,0,
+ /* 39885 */ 0260,01,045,01,0376,0110,0,
+ /* 39892 */ 0261,01,045,01,0324,0120,0,
+ /* 39899 */ 0260,01,045,01,0324,0110,0,
+ /* 39906 */ 0261,01,045,01,0354,0120,0,
+ /* 39913 */ 0260,01,045,01,0354,0110,0,
+ /* 39920 */ 0261,01,045,01,0355,0120,0,
+ /* 39927 */ 0260,01,045,01,0355,0110,0,
+ /* 39934 */ 0261,01,045,01,0334,0120,0,
+ /* 39941 */ 0260,01,045,01,0334,0110,0,
+ /* 39948 */ 0261,01,045,01,0335,0120,0,
+ /* 39955 */ 0260,01,045,01,0335,0110,0,
+ /* 39962 */ 0261,01,045,01,0333,0120,0,
+ /* 39969 */ 0260,01,045,01,0333,0110,0,
+ /* 39976 */ 0261,01,045,01,0337,0120,0,
+ /* 39983 */ 0260,01,045,01,0337,0110,0,
+ /* 39990 */ 0261,01,045,01,0340,0120,0,
+ /* 39997 */ 0260,01,045,01,0340,0110,0,
+ /* 40004 */ 0261,01,045,01,0343,0120,0,
+ /* 40011 */ 0260,01,045,01,0343,0110,0,
+ /* 40018 */ 0261,01,045,01,0164,0120,0,
+ /* 40025 */ 0260,01,045,01,0164,0110,0,
+ /* 40032 */ 0261,01,045,01,0165,0120,0,
+ /* 40039 */ 0260,01,045,01,0165,0110,0,
+ /* 40046 */ 0261,01,045,01,0166,0120,0,
+ /* 40053 */ 0260,01,045,01,0166,0110,0,
+ /* 40060 */ 0261,02,045,01,051,0120,0,
+ /* 40067 */ 0260,02,045,01,051,0110,0,
+ /* 40074 */ 0261,01,045,01,0144,0120,0,
+ /* 40081 */ 0260,01,045,01,0144,0110,0,
+ /* 40088 */ 0261,01,045,01,0145,0120,0,
+ /* 40095 */ 0260,01,045,01,0145,0110,0,
+ /* 40102 */ 0261,01,045,01,0146,0120,0,
+ /* 40109 */ 0260,01,045,01,0146,0110,0,
+ /* 40116 */ 0261,02,045,01,067,0120,0,
+ /* 40123 */ 0260,02,045,01,067,0110,0,
+ /* 40130 */ 0261,02,045,01,01,0120,0,
+ /* 40137 */ 0260,02,045,01,01,0110,0,
+ /* 40144 */ 0261,02,045,01,02,0120,0,
+ /* 40151 */ 0260,02,045,01,02,0110,0,
+ /* 40158 */ 0261,02,045,01,03,0120,0,
+ /* 40165 */ 0260,02,045,01,03,0110,0,
+ /* 40172 */ 0261,02,045,01,05,0120,0,
+ /* 40179 */ 0260,02,045,01,05,0110,0,
+ /* 40186 */ 0261,02,045,01,06,0120,0,
+ /* 40193 */ 0260,02,045,01,06,0110,0,
+ /* 40200 */ 0261,02,045,01,07,0120,0,
+ /* 40207 */ 0260,02,045,01,07,0110,0,
+ /* 40214 */ 0261,02,045,01,04,0120,0,
+ /* 40221 */ 0260,02,045,01,04,0110,0,
+ /* 40228 */ 0261,01,045,01,0365,0120,0,
+ /* 40235 */ 0260,01,045,01,0365,0110,0,
+ /* 40242 */ 0261,02,045,01,074,0120,0,
+ /* 40249 */ 0260,02,045,01,074,0110,0,
+ /* 40256 */ 0261,01,045,01,0356,0120,0,
+ /* 40263 */ 0260,01,045,01,0356,0110,0,
+ /* 40270 */ 0261,02,045,01,075,0120,0,
+ /* 40277 */ 0260,02,045,01,075,0110,0,
+ /* 40284 */ 0261,01,045,01,0336,0120,0,
+ /* 40291 */ 0260,01,045,01,0336,0110,0,
+ /* 40298 */ 0261,02,045,01,076,0120,0,
+ /* 40305 */ 0260,02,045,01,076,0110,0,
+ /* 40312 */ 0261,02,045,01,077,0120,0,
+ /* 40319 */ 0260,02,045,01,077,0110,0,
+ /* 40326 */ 0261,02,045,01,070,0120,0,
+ /* 40333 */ 0260,02,045,01,070,0110,0,
+ /* 40340 */ 0261,01,045,01,0352,0120,0,
+ /* 40347 */ 0260,01,045,01,0352,0110,0,
+ /* 40354 */ 0261,02,045,01,071,0120,0,
+ /* 40361 */ 0260,02,045,01,071,0110,0,
+ /* 40368 */ 0261,01,045,01,0332,0120,0,
+ /* 40375 */ 0260,01,045,01,0332,0110,0,
+ /* 40382 */ 0261,02,045,01,072,0120,0,
+ /* 40389 */ 0260,02,045,01,072,0110,0,
+ /* 40396 */ 0261,02,045,01,073,0120,0,
+ /* 40403 */ 0260,02,045,01,073,0110,0,
+ /* 40410 */ 0270,01,045,01,0327,0110,0,
+ /* 40417 */ 0270,02,045,01,040,0110,0,
+ /* 40424 */ 0270,02,045,01,041,0110,0,
+ /* 40431 */ 0270,02,045,01,042,0110,0,
+ /* 40438 */ 0270,02,045,01,043,0110,0,
+ /* 40445 */ 0270,02,045,01,044,0110,0,
+ /* 40452 */ 0270,02,045,01,045,0110,0,
+ /* 40459 */ 0270,02,045,01,060,0110,0,
+ /* 40466 */ 0270,02,045,01,061,0110,0,
+ /* 40473 */ 0270,02,045,01,062,0110,0,
+ /* 40480 */ 0270,02,045,01,063,0110,0,
+ /* 40487 */ 0270,02,045,01,064,0110,0,
+ /* 40494 */ 0270,02,045,01,065,0110,0,
+ /* 40501 */ 0261,02,045,01,050,0120,0,
+ /* 40508 */ 0260,02,045,01,050,0110,0,
+ /* 40515 */ 0261,02,045,01,013,0120,0,
+ /* 40522 */ 0260,02,045,01,013,0110,0,
+ /* 40529 */ 0261,01,045,01,0344,0120,0,
+ /* 40536 */ 0260,01,045,01,0344,0110,0,
+ /* 40543 */ 0261,01,045,01,0345,0120,0,
+ /* 40550 */ 0260,01,045,01,0345,0110,0,
+ /* 40557 */ 0261,01,045,01,0325,0120,0,
+ /* 40564 */ 0260,01,045,01,0325,0110,0,
+ /* 40571 */ 0261,02,045,01,0100,0120,0,
+ /* 40578 */ 0260,02,045,01,0100,0110,0,
+ /* 40585 */ 0261,01,045,01,0364,0120,0,
+ /* 40592 */ 0260,01,045,01,0364,0110,0,
+ /* 40599 */ 0261,01,045,01,0353,0120,0,
+ /* 40606 */ 0260,01,045,01,0353,0110,0,
+ /* 40613 */ 0261,01,045,01,0366,0120,0,
+ /* 40620 */ 0260,01,045,01,0366,0110,0,
+ /* 40627 */ 0261,02,045,01,0,0120,0,
+ /* 40634 */ 0260,02,045,01,0,0110,0,
+ /* 40641 */ 0261,02,045,01,010,0120,0,
+ /* 40648 */ 0260,02,045,01,010,0110,0,
+ /* 40655 */ 0261,02,045,01,011,0120,0,
+ /* 40662 */ 0260,02,045,01,011,0110,0,
+ /* 40669 */ 0261,02,045,01,012,0120,0,
+ /* 40676 */ 0260,02,045,01,012,0110,0,
+ /* 40683 */ 0261,01,045,01,0361,0120,0,
+ /* 40690 */ 0260,01,045,01,0361,0110,0,
+ /* 40697 */ 0261,01,045,01,0362,0120,0,
+ /* 40704 */ 0260,01,045,01,0362,0110,0,
+ /* 40711 */ 0261,01,045,01,0363,0120,0,
+ /* 40718 */ 0260,01,045,01,0363,0110,0,
+ /* 40725 */ 0261,01,045,01,0341,0120,0,
+ /* 40732 */ 0260,01,045,01,0341,0110,0,
+ /* 40739 */ 0261,01,045,01,0342,0120,0,
+ /* 40746 */ 0260,01,045,01,0342,0110,0,
+ /* 40753 */ 0261,01,045,01,0321,0120,0,
+ /* 40760 */ 0260,01,045,01,0321,0110,0,
+ /* 40767 */ 0261,01,045,01,0322,0120,0,
+ /* 40774 */ 0260,01,045,01,0322,0110,0,
+ /* 40781 */ 0261,01,045,01,0323,0120,0,
+ /* 40788 */ 0260,01,045,01,0323,0110,0,
+ /* 40795 */ 0261,01,045,01,0370,0120,0,
+ /* 40802 */ 0260,01,045,01,0370,0110,0,
+ /* 40809 */ 0261,01,045,01,0371,0120,0,
+ /* 40816 */ 0260,01,045,01,0371,0110,0,
+ /* 40823 */ 0261,01,045,01,0372,0120,0,
+ /* 40830 */ 0260,01,045,01,0372,0110,0,
+ /* 40837 */ 0261,01,045,01,0373,0120,0,
+ /* 40844 */ 0260,01,045,01,0373,0110,0,
+ /* 40851 */ 0261,01,045,01,0350,0120,0,
+ /* 40858 */ 0260,01,045,01,0350,0110,0,
+ /* 40865 */ 0261,01,045,01,0351,0120,0,
+ /* 40872 */ 0260,01,045,01,0351,0110,0,
+ /* 40879 */ 0261,01,045,01,0330,0120,0,
+ /* 40886 */ 0260,01,045,01,0330,0110,0,
+ /* 40893 */ 0261,01,045,01,0331,0120,0,
+ /* 40900 */ 0260,01,045,01,0331,0110,0,
+ /* 40907 */ 0261,01,045,01,0150,0120,0,
+ /* 40914 */ 0260,01,045,01,0150,0110,0,
+ /* 40921 */ 0261,01,045,01,0151,0120,0,
+ /* 40928 */ 0260,01,045,01,0151,0110,0,
+ /* 40935 */ 0261,01,045,01,0152,0120,0,
+ /* 40942 */ 0260,01,045,01,0152,0110,0,
+ /* 40949 */ 0261,01,045,01,0155,0120,0,
+ /* 40956 */ 0260,01,045,01,0155,0110,0,
+ /* 40963 */ 0261,01,045,01,0140,0120,0,
+ /* 40970 */ 0260,01,045,01,0140,0110,0,
+ /* 40977 */ 0261,01,045,01,0141,0120,0,
+ /* 40984 */ 0260,01,045,01,0141,0110,0,
+ /* 40991 */ 0261,01,045,01,0142,0120,0,
+ /* 40998 */ 0260,01,045,01,0142,0110,0,
+ /* 41005 */ 0261,01,045,01,0154,0120,0,
+ /* 41012 */ 0260,01,045,01,0154,0110,0,
+ /* 41019 */ 0261,01,045,01,0357,0120,0,
+ /* 41026 */ 0260,01,045,01,0357,0110,0,
+ /* 41033 */ 0270,02,045,01,052,0110,0,
+ /* 41040 */ 0270,02,05,01,0132,0110,0,
+ /* 41047 */ 0270,02,01,01,0170,0110,0,
+ /* 41054 */ 0270,02,05,01,0170,0110,0,
+ /* 41061 */ 0270,02,01,01,0171,0110,0,
+ /* 41068 */ 0270,02,05,01,0171,0110,0,
+ /* 41075 */ 0270,02,01,01,0130,0110,0,
+ /* 41082 */ 0270,02,05,01,0130,0110,0,
+ /* 41089 */ 0270,02,01,01,0131,0110,0,
+ /* 41096 */ 0270,02,05,01,0131,0110,0,
+ /* 41103 */ 0261,02,05,01,066,0120,0,
+ /* 41110 */ 0260,02,05,01,066,0110,0,
+ /* 41117 */ 0261,02,05,01,026,0120,0,
+ /* 41124 */ 0260,02,05,01,026,0110,0,
+ /* 41131 */ 0261,02,01,01,0214,0120,0,
+ /* 41138 */ 0260,02,01,01,0214,0110,0,
+ /* 41145 */ 0261,02,05,01,0214,0120,0,
+ /* 41152 */ 0260,02,05,01,0214,0110,0,
+ /* 41159 */ 0261,02,021,01,0214,0120,0,
+ /* 41166 */ 0260,02,021,01,0214,0110,0,
+ /* 41173 */ 0261,02,025,01,0214,0120,0,
+ /* 41180 */ 0260,02,025,01,0214,0110,0,
+ /* 41187 */ 0261,02,01,01,0216,0102,0,
+ /* 41194 */ 0260,02,01,01,0216,0101,0,
+ /* 41201 */ 0261,02,05,01,0216,0102,0,
+ /* 41208 */ 0260,02,05,01,0216,0101,0,
+ /* 41215 */ 0261,02,021,01,0216,0102,0,
+ /* 41222 */ 0260,02,021,01,0216,0101,0,
+ /* 41229 */ 0261,02,025,01,0216,0102,0,
+ /* 41236 */ 0260,02,025,01,0216,0101,0,
+ /* 41243 */ 0261,02,01,01,0107,0120,0,
+ /* 41250 */ 0260,02,01,01,0107,0110,0,
+ /* 41257 */ 0261,02,021,01,0107,0120,0,
+ /* 41264 */ 0260,02,021,01,0107,0110,0,
+ /* 41271 */ 0261,02,05,01,0107,0120,0,
+ /* 41278 */ 0260,02,05,01,0107,0110,0,
+ /* 41285 */ 0261,02,025,01,0107,0120,0,
+ /* 41292 */ 0260,02,025,01,0107,0110,0,
+ /* 41299 */ 0261,02,01,01,0106,0120,0,
+ /* 41306 */ 0260,02,01,01,0106,0110,0,
+ /* 41313 */ 0261,02,05,01,0106,0120,0,
+ /* 41320 */ 0260,02,05,01,0106,0110,0,
+ /* 41327 */ 0261,02,01,01,0105,0120,0,
+ /* 41334 */ 0260,02,01,01,0105,0110,0,
+ /* 41341 */ 0261,02,021,01,0105,0120,0,
+ /* 41348 */ 0260,02,021,01,0105,0110,0,
+ /* 41355 */ 0261,02,05,01,0105,0120,0,
+ /* 41362 */ 0260,02,05,01,0105,0110,0,
+ /* 41369 */ 0261,02,025,01,0105,0120,0,
+ /* 41376 */ 0260,02,025,01,0105,0110,0,
+ /* 41383 */ 0261,02,0,01,0362,0120,0,
+ /* 41390 */ 0261,02,020,01,0362,0120,0,
+ /* 41397 */ 0262,02,0,01,0367,0110,0,
+ /* 41404 */ 0262,02,020,01,0367,0110,0,
+ /* 41411 */ 0260,0111,0,01,02,0216,0,
+ /* 41418 */ 0260,0111,020,01,02,0216,0,
+ /* 41425 */ 0260,0111,0,01,01,0215,0,
+ /* 41432 */ 0260,0111,020,01,01,0215,0,
+ /* 41439 */ 0260,02,0,01,0363,0213,0,
+ /* 41446 */ 0260,02,020,01,0363,0213,0,
+ /* 41453 */ 0260,0111,0,01,01,0216,0,
+ /* 41460 */ 0260,0111,020,01,01,0216,0,
+ /* 41467 */ 0260,0111,0,01,01,0211,0,
+ /* 41474 */ 0260,0111,020,01,01,0211,0,
+ /* 41481 */ 0260,0111,0,01,01,0212,0,
+ /* 41488 */ 0260,0111,020,01,01,0212,0,
+ /* 41495 */ 0260,0111,0,01,02,0211,0,
+ /* 41502 */ 0260,0111,020,01,02,0211,0,
+ /* 41509 */ 0260,02,0,01,0363,0212,0,
+ /* 41516 */ 0260,02,020,01,0363,0212,0,
+ /* 41523 */ 0260,02,0,01,0363,0211,0,
+ /* 41530 */ 0260,02,020,01,0363,0211,0,
+ /* 41537 */ 0260,0111,0,01,01,0213,0,
+ /* 41544 */ 0260,0111,020,01,01,0213,0,
+ /* 41551 */ 0262,02,0,01,0365,0110,0,
+ /* 41558 */ 0262,02,020,01,0365,0110,0,
+ /* 41565 */ 0261,02,03,01,0366,0120,0,
+ /* 41572 */ 0261,02,023,01,0366,0120,0,
+ /* 41579 */ 0261,02,03,01,0365,0120,0,
+ /* 41586 */ 0261,02,023,01,0365,0120,0,
+ /* 41593 */ 0261,02,02,01,0365,0120,0,
+ /* 41600 */ 0261,02,022,01,0365,0120,0,
+ /* 41607 */ 0262,02,02,01,0367,0110,0,
+ /* 41614 */ 0262,02,022,01,0367,0110,0,
+ /* 41621 */ 0262,02,01,01,0367,0110,0,
+ /* 41628 */ 0262,02,021,01,0367,0110,0,
+ /* 41635 */ 0262,02,03,01,0367,0110,0,
+ /* 41642 */ 0262,02,023,01,0367,0110,0,
+ /* 41649 */ 0320,0333,02,017,0274,0110,0,
+ /* 41656 */ 0321,0333,02,017,0274,0110,0,
+ /* 41663 */ 0324,0333,02,017,0274,0110,0,
+ /* 41670 */ 0260,0111,0,01,01,0214,0,
+ /* 41677 */ 0260,0111,020,01,01,0214,0,
+ /* 41684 */ 0260,0111,0,01,01,0217,0,
+ /* 41691 */ 0260,0111,020,01,01,0217,0,
+ /* 41698 */ 0323,0333,02,017,032,0110,0,
+ /* 41705 */ 0323,0332,02,017,032,0110,0,
+ /* 41712 */ 0323,0332,02,017,033,0110,0,
+ /* 41719 */ 03,017,072,0314,0110,022,0,
+ /* 41726 */ 0270,02,02,01,0261,0110,0,
+ /* 41733 */ 0270,02,06,01,0261,0110,0,
+ /* 41740 */ 0270,02,01,01,0261,0110,0,
+ /* 41747 */ 0270,02,05,01,0261,0110,0,
+ /* 41754 */ 0270,02,02,01,0260,0110,0,
+ /* 41761 */ 0270,02,06,01,0260,0110,0,
+ /* 41768 */ 0270,02,01,01,0260,0110,0,
+ /* 41775 */ 0270,02,05,01,0260,0110,0,
+ /* 41782 */ 0270,02,03,01,0260,0110,0,
+ /* 41789 */ 0270,02,07,01,0260,0110,0,
+ /* 41796 */ 0270,02,0,01,0260,0110,0,
+ /* 41803 */ 0270,02,04,01,0260,0110,0,
+ /* 41810 */ 0270,02,02,01,0162,0110,0,
+ /* 41817 */ 0270,02,06,01,0162,0110,0,
+ /* 41824 */ 0261,02,03,01,0120,0120,0,
+ /* 41831 */ 0261,02,07,01,0120,0120,0,
+ /* 41838 */ 0261,02,03,01,0121,0120,0,
+ /* 41845 */ 0261,02,07,01,0121,0120,0,
+ /* 41852 */ 0261,02,02,01,0120,0120,0,
+ /* 41859 */ 0261,02,06,01,0120,0120,0,
+ /* 41866 */ 0261,02,02,01,0121,0120,0,
+ /* 41873 */ 0261,02,06,01,0121,0120,0,
+ /* 41880 */ 0261,02,0,01,0120,0120,0,
+ /* 41887 */ 0261,02,04,01,0120,0120,0,
+ /* 41894 */ 0261,02,0,01,0121,0120,0,
+ /* 41901 */ 0261,02,04,01,0121,0120,0,
+ /* 41908 */ 0261,02,021,01,0265,0120,0,
+ /* 41915 */ 0261,02,025,01,0265,0120,0,
+ /* 41922 */ 0261,02,021,01,0264,0120,0,
+ /* 41929 */ 0261,02,025,01,0264,0120,0,
+ /* 41936 */ 0261,01,05,01,0112,0120,0,
+ /* 41943 */ 0261,01,025,01,0112,0120,0,
+ /* 41950 */ 0261,01,024,01,0112,0120,0,
+ /* 41957 */ 0261,01,04,01,0112,0120,0,
+ /* 41964 */ 0261,01,05,01,0101,0120,0,
+ /* 41971 */ 0261,01,025,01,0101,0120,0,
+ /* 41978 */ 0261,01,05,01,0102,0120,0,
+ /* 41985 */ 0261,01,025,01,0102,0120,0,
+ /* 41992 */ 0261,01,024,01,0102,0120,0,
+ /* 41999 */ 0261,01,04,01,0102,0120,0,
+ /* 42006 */ 0261,01,024,01,0101,0120,0,
+ /* 42013 */ 0261,01,04,01,0101,0120,0,
+ /* 42020 */ 0270,01,01,01,0220,0110,0,
+ /* 42027 */ 0270,01,01,01,0221,0101,0,
+ /* 42034 */ 0270,01,01,01,0222,0110,0,
+ /* 42041 */ 0270,01,01,01,0223,0110,0,
+ /* 42048 */ 0270,01,021,01,0220,0110,0,
+ /* 42055 */ 0270,01,021,01,0221,0101,0,
+ /* 42062 */ 0270,01,03,01,0222,0110,0,
+ /* 42069 */ 0270,01,03,01,0223,0110,0,
+ /* 42076 */ 0270,01,020,01,0220,0110,0,
+ /* 42083 */ 0270,01,020,01,0221,0101,0,
+ /* 42090 */ 0270,01,023,01,0222,0110,0,
+ /* 42097 */ 0270,01,023,01,0223,0110,0,
+ /* 42104 */ 0270,01,0,01,0220,0110,0,
+ /* 42111 */ 0270,01,0,01,0221,0101,0,
+ /* 42118 */ 0270,01,0,01,0222,0110,0,
+ /* 42125 */ 0270,01,0,01,0223,0110,0,
+ /* 42132 */ 0270,01,01,01,0104,0110,0,
+ /* 42139 */ 0270,01,021,01,0104,0110,0,
+ /* 42146 */ 0270,01,020,01,0104,0110,0,
+ /* 42153 */ 0270,01,0,01,0104,0110,0,
+ /* 42160 */ 0261,01,05,01,0105,0120,0,
+ /* 42167 */ 0261,01,025,01,0105,0120,0,
+ /* 42174 */ 0261,01,024,01,0105,0120,0,
+ /* 42181 */ 0261,01,04,01,0105,0120,0,
+ /* 42188 */ 0270,01,01,01,0230,0110,0,
+ /* 42195 */ 0270,01,021,01,0230,0110,0,
+ /* 42202 */ 0270,01,020,01,0230,0110,0,
+ /* 42209 */ 0270,01,0,01,0230,0110,0,
+ /* 42216 */ 0270,01,01,01,0231,0110,0,
+ /* 42223 */ 0270,01,021,01,0231,0110,0,
+ /* 42230 */ 0270,01,020,01,0231,0110,0,
+ /* 42237 */ 0270,01,0,01,0231,0110,0,
+ /* 42244 */ 0261,01,05,01,0113,0120,0,
+ /* 42251 */ 0261,01,024,01,0113,0120,0,
+ /* 42258 */ 0261,01,04,01,0113,0120,0,
+ /* 42265 */ 0261,01,05,01,0106,0120,0,
+ /* 42272 */ 0261,01,025,01,0106,0120,0,
+ /* 42279 */ 0261,01,024,01,0106,0120,0,
+ /* 42286 */ 0261,01,04,01,0106,0120,0,
+ /* 42293 */ 0261,01,05,01,0107,0120,0,
+ /* 42300 */ 0261,01,025,01,0107,0120,0,
+ /* 42307 */ 0261,01,024,01,0107,0120,0,
+ /* 42314 */ 0261,01,04,01,0107,0120,0,
+ /* 42321 */ 0323,0333,02,017,0307,0207,0,
+ /* 42328 */ 0360,03,017,070,0371,0101,0,
+ /* 42335 */ 0324,03,017,070,0371,0101,0,
+ /* 42342 */ 0310,0333,02,017,0256,0206,0,
+ /* 42349 */ 0311,0333,02,017,0256,0206,0,
+ /* 42356 */ 0361,03,017,070,0317,0110,0,
+ /* 42363 */ 0261,02,01,01,0317,0120,0,
+ /* 42370 */ 0260,02,01,01,0317,0110,0,
+ /* 42377 */ 0261,02,05,01,0317,0120,0,
+ /* 42384 */ 0260,02,05,01,0317,0110,0,
+ /* 42391 */ 0321,0333,02,017,0256,0205,0,
+ /* 42398 */ 0324,0333,02,017,0256,0205,0,
+ /* 42405 */ 0321,0333,02,017,036,0201,0,
+ /* 42412 */ 0324,0333,02,017,036,0201,0,
+ /* 42419 */ 0321,03,017,070,0366,0101,0,
+ /* 42426 */ 0324,03,017,070,0366,0101,0,
+ /* 42433 */ 0270,02,0,01,0111,0200,0,
+ /* 42440 */ 0270,02,01,01,0111,0200,0,
+ /* 42447 */ 0262,02,02,01,0134,0110,0,
+ /* 42454 */ 0262,02,03,01,0136,0110,0,
+ /* 42461 */ 0262,02,02,01,0136,0110,0,
+ /* 42468 */ 0262,02,01,01,0136,0110,0,
+ /* 42475 */ 0262,02,0,01,0136,0110,0,
+ /* 42482 */ 0270,02,03,01,0113,0110,0,
+ /* 42489 */ 0270,02,01,01,0113,0110,0,
+ /* 42496 */ 0270,02,0,02,0111,0300,0,
+ /* 42503 */ 0270,02,02,01,0113,0101,0,
+ /* 42510 */ 0323,0333,02,017,0307,0206,0,
+ /* 42517 */ 0262,02,01,01,0347,0101,0,
+ /* 42524 */ 0262,02,01,01,0343,0101,0,
+ /* 42531 */ 0262,02,01,01,0342,0101,0,
+ /* 42538 */ 0262,02,01,01,0346,0101,0,
+ /* 42545 */ 0262,02,01,01,0344,0101,0,
+ /* 42552 */ 0262,02,01,01,0357,0101,0,
+ /* 42559 */ 0262,02,01,01,0355,0101,0,
+ /* 42566 */ 0262,02,01,01,0354,0101,0,
+ /* 42573 */ 0262,02,01,01,0356,0101,0,
+ /* 42580 */ 0262,02,01,01,0345,0101,0,
+ /* 42587 */ 0262,02,01,01,0341,0101,0,
+ /* 42594 */ 0262,02,01,01,0353,0101,0,
+ /* 42601 */ 0262,02,01,01,0351,0101,0,
+ /* 42608 */ 0262,02,01,01,0340,0101,0,
+ /* 42615 */ 0262,02,01,01,0352,0101,0,
+ /* 42622 */ 0262,02,01,01,0350,0101,0,
+ /* 42629 */ 0262,02,021,01,0347,0101,0,
+ /* 42636 */ 0262,02,021,01,0343,0101,0,
+ /* 42643 */ 0262,02,021,01,0342,0101,0,
+ /* 42650 */ 0262,02,021,01,0346,0101,0,
+ /* 42657 */ 0262,02,021,01,0344,0101,0,
+ /* 42664 */ 0262,02,021,01,0357,0101,0,
+ /* 42671 */ 0262,02,021,01,0355,0101,0,
+ /* 42678 */ 0262,02,021,01,0354,0101,0,
+ /* 42685 */ 0262,02,021,01,0356,0101,0,
+ /* 42692 */ 0262,02,021,01,0345,0101,0,
+ /* 42699 */ 0262,02,021,01,0341,0101,0,
+ /* 42706 */ 0262,02,021,01,0353,0101,0,
+ /* 42713 */ 0262,02,021,01,0351,0101,0,
+ /* 42720 */ 0262,02,021,01,0340,0101,0,
+ /* 42727 */ 0262,02,021,01,0352,0101,0,
+ /* 42734 */ 0262,02,021,01,0350,0101,0,
+ /* 42741 */ 0273,0320,01,021,0101,0,
+ /* 42747 */ 0273,0321,01,021,0101,0,
+ /* 42753 */ 0273,0324,01,021,0101,0,
+ /* 42759 */ 0273,01,0200,0202,021,0,
+ /* 42765 */ 0273,01,0202,0202,021,0,
+ /* 42771 */ 0273,0320,01,01,0101,0,
+ /* 42777 */ 0273,0321,01,01,0101,0,
+ /* 42783 */ 0273,0324,01,01,0101,0,
+ /* 42789 */ 0273,01,0200,0200,021,0,
+ /* 42795 */ 0273,01,0202,0200,021,0,
+ /* 42801 */ 0273,0320,01,041,0101,0,
+ /* 42807 */ 0273,0321,01,041,0101,0,
+ /* 42813 */ 0273,0324,01,041,0101,0,
+ /* 42819 */ 0273,01,0200,0204,021,0,
+ /* 42825 */ 0273,01,0202,0204,021,0,
+ /* 42831 */ 0321,01,017,010,0310,0,
+ /* 42837 */ 0324,01,017,010,0310,0,
+ /* 42843 */ 0320,02,017,0243,0101,0,
+ /* 42849 */ 0321,02,017,0243,0101,0,
+ /* 42855 */ 0324,02,017,0243,0101,0,
+ /* 42861 */ 0322,01,0232,034,074,0,
+ /* 42867 */ 0320,01,0232,034,074,0,
+ /* 42873 */ 0321,01,0232,034,074,0,
+ /* 42879 */ 0322,01,0232,035,030,0,
+ /* 42885 */ 0320,01,0232,031,030,0,
+ /* 42891 */ 0321,01,0232,041,030,0,
+ /* 42897 */ 0320,01,0203,0207,0275,0,
+ /* 42903 */ 0321,01,0203,0207,0275,0,
+ /* 42909 */ 0324,01,0203,0207,0275,0,
+ /* 42915 */ 0320,01,0201,0207,031,0,
+ /* 42921 */ 0321,01,0201,0207,041,0,
+ /* 42927 */ 0324,01,0201,0207,0255,0,
+ /* 42933 */ 0273,02,017,0260,0101,0,
+ /* 42939 */ 0320,02,017,0247,0101,0,
+ /* 42945 */ 0321,02,017,0247,0101,0,
+ /* 42951 */ 0324,02,017,0307,0201,0,
+ /* 42957 */ 0273,0320,01,0377,0201,0,
+ /* 42963 */ 0273,0321,01,0377,0201,0,
+ /* 42969 */ 0273,0324,01,0377,0201,0,
+ /* 42975 */ 0320,02,017,0257,0110,0,
+ /* 42981 */ 0321,02,017,0257,0110,0,
+ /* 42987 */ 0324,02,017,0257,0110,0,
+ /* 42993 */ 0320,01,0153,0110,0276,0,
+ /* 42999 */ 0320,01,0151,0110,032,0,
+ /* 43005 */ 0321,01,0153,0110,0276,0,
+ /* 43011 */ 0321,01,0151,0110,042,0,
+ /* 43017 */ 0324,01,0153,0110,0276,0,
+ /* 43023 */ 0324,01,0151,0110,042,0,
+ /* 43029 */ 0324,01,0151,0110,0256,0,
+ /* 43035 */ 0320,01,0153,0100,0275,0,
+ /* 43041 */ 0320,01,0151,0100,031,0,
+ /* 43047 */ 0321,01,0153,0100,0275,0,
+ /* 43053 */ 0321,01,0151,0100,041,0,
+ /* 43059 */ 0324,01,0153,0100,0275,0,
+ /* 43065 */ 0324,01,0151,0100,0255,0,
+ /* 43071 */ 0273,0320,01,0377,0200,0,
+ /* 43077 */ 0273,0321,01,0377,0200,0,
+ /* 43083 */ 0273,0324,01,0377,0200,0,
+ /* 43089 */ 0310,03,017,01,0337,0,
+ /* 43095 */ 0311,03,017,01,0337,0,
+ /* 43101 */ 0323,0313,01,0343,050,0,
+ /* 43107 */ 0322,01,0352,034,074,0,
+ /* 43113 */ 0320,01,0352,034,074,0,
+ /* 43119 */ 0321,01,0352,034,074,0,
+ /* 43125 */ 0322,01,0352,035,030,0,
+ /* 43131 */ 0320,01,0352,031,030,0,
+ /* 43137 */ 0321,01,0352,041,030,0,
+ /* 43143 */ 0322,02,017,0270,064,0,
+ /* 43149 */ 0320,02,017,0270,064,0,
+ /* 43155 */ 0321,02,017,0270,064,0,
+ /* 43161 */ 0320,02,017,0,0206,0,
+ /* 43167 */ 0321,02,017,0,0206,0,
+ /* 43173 */ 0320,02,017,02,0110,0,
+ /* 43179 */ 0321,02,017,02,0110,0,
+ /* 43185 */ 0324,02,017,02,0110,0,
+ /* 43191 */ 0360,03,017,0256,0350,0,
+ /* 43197 */ 0320,02,017,0264,0110,0,
+ /* 43203 */ 0321,02,017,0264,0110,0,
+ /* 43209 */ 0324,02,017,0264,0110,0,
+ /* 43215 */ 0320,02,017,0265,0110,0,
+ /* 43221 */ 0321,02,017,0265,0110,0,
+ /* 43227 */ 0324,02,017,0265,0110,0,
+ /* 43233 */ 0320,02,017,03,0110,0,
+ /* 43239 */ 0321,02,017,03,0110,0,
+ /* 43245 */ 0324,02,017,03,0110,0,
+ /* 43251 */ 0320,02,017,0262,0110,0,
+ /* 43257 */ 0321,02,017,0262,0110,0,
+ /* 43263 */ 0324,02,017,0262,0110,0,
+ /* 43269 */ 0360,03,017,0256,0360,0,
+ /* 43275 */ 0334,02,017,040,0101,0,
+ /* 43281 */ 0323,02,017,040,0101,0,
+ /* 43287 */ 0334,02,017,042,0110,0,
+ /* 43293 */ 0323,02,017,042,0110,0,
+ /* 43299 */ 0323,02,017,041,0101,0,
+ /* 43305 */ 0323,02,017,043,0110,0,
+ /* 43311 */ 0271,0320,01,0211,0101,0,
+ /* 43317 */ 0271,0321,01,0211,0101,0,
+ /* 43323 */ 0271,0324,01,0211,0101,0,
+ /* 43329 */ 0271,01,0306,0200,021,0,
+ /* 43335 */ 0360,02,017,0156,0110,0,
+ /* 43341 */ 0360,02,017,0176,0101,0,
+ /* 43347 */ 0360,02,017,0157,0110,0,
+ /* 43353 */ 0360,02,017,0177,0101,0,
+ /* 43359 */ 0320,02,017,0276,0110,0,
+ /* 43365 */ 0321,02,017,0276,0110,0,
+ /* 43371 */ 0321,02,017,0277,0110,0,
+ /* 43377 */ 0324,02,017,0276,0110,0,
+ /* 43383 */ 0324,02,017,0277,0110,0,
+ /* 43389 */ 0320,02,017,0266,0110,0,
+ /* 43395 */ 0321,02,017,0266,0110,0,
+ /* 43401 */ 0321,02,017,0267,0110,0,
+ /* 43407 */ 0324,02,017,0266,0110,0,
+ /* 43413 */ 0324,02,017,0267,0110,0,
+ /* 43419 */ 0273,0320,01,0367,0203,0,
+ /* 43425 */ 0273,0321,01,0367,0203,0,
+ /* 43431 */ 0273,0324,01,0367,0203,0,
+ /* 43437 */ 0320,02,017,037,0200,0,
+ /* 43443 */ 0321,02,017,037,0200,0,
+ /* 43449 */ 0324,02,017,037,0200,0,
+ /* 43455 */ 0273,0320,01,0367,0202,0,
+ /* 43461 */ 0273,0321,01,0367,0202,0,
+ /* 43467 */ 0273,0324,01,0367,0202,0,
+ /* 43473 */ 0273,0320,01,011,0101,0,
+ /* 43479 */ 0273,0321,01,011,0101,0,
+ /* 43485 */ 0273,0324,01,011,0101,0,
+ /* 43491 */ 0273,01,0200,0201,021,0,
+ /* 43497 */ 0273,01,0202,0201,021,0,
+ /* 43503 */ 0323,02,017,0121,0110,0,
+ /* 43509 */ 0323,02,017,0120,0110,0,
+ /* 43515 */ 0323,02,017,0122,0110,0,
+ /* 43521 */ 0323,02,017,0135,0110,0,
+ /* 43527 */ 0323,02,017,0131,0110,0,
+ /* 43533 */ 0323,02,017,0125,0110,0,
+ /* 43539 */ 0320,01,0301,0202,025,0,
+ /* 43545 */ 0321,01,0301,0202,025,0,
+ /* 43551 */ 0324,01,0301,0202,025,0,
+ /* 43557 */ 0320,01,0301,0203,025,0,
+ /* 43563 */ 0321,01,0301,0203,025,0,
+ /* 43569 */ 0324,01,0301,0203,025,0,
+ /* 43575 */ 0321,02,017,066,0200,0,
+ /* 43581 */ 0320,01,0301,0200,025,0,
+ /* 43587 */ 0321,01,0301,0200,025,0,
+ /* 43593 */ 0324,01,0301,0200,025,0,
+ /* 43599 */ 0320,01,0301,0201,025,0,
+ /* 43605 */ 0321,01,0301,0201,025,0,
+ /* 43611 */ 0324,01,0301,0201,025,0,
+ /* 43617 */ 0320,01,0301,0204,025,0,
+ /* 43623 */ 0321,01,0301,0204,025,0,
+ /* 43629 */ 0324,01,0301,0204,025,0,
+ /* 43635 */ 0320,01,0301,0207,025,0,
+ /* 43641 */ 0321,01,0301,0207,025,0,
+ /* 43647 */ 0324,01,0301,0207,025,0,
+ /* 43653 */ 0273,0320,01,031,0101,0,
+ /* 43659 */ 0273,0321,01,031,0101,0,
+ /* 43665 */ 0273,0324,01,031,0101,0,
+ /* 43671 */ 0273,01,0200,0203,021,0,
+ /* 43677 */ 0273,01,0202,0203,021,0,
+ /* 43683 */ 0360,03,017,0256,0370,0,
+ /* 43689 */ 0320,02,017,0245,0101,0,
+ /* 43695 */ 0321,02,017,0245,0101,0,
+ /* 43701 */ 0324,02,017,0245,0101,0,
+ /* 43707 */ 0320,01,0301,0205,025,0,
+ /* 43713 */ 0321,01,0301,0205,025,0,
+ /* 43719 */ 0324,01,0301,0205,025,0,
+ /* 43725 */ 0320,02,017,0255,0101,0,
+ /* 43731 */ 0321,02,017,0255,0101,0,
+ /* 43737 */ 0324,02,017,0255,0101,0,
+ /* 43743 */ 0320,02,017,0,0200,0,
+ /* 43749 */ 0321,02,017,0,0200,0,
+ /* 43755 */ 0323,02,017,0,0200,0,
+ /* 43761 */ 0324,02,017,0,0200,0,
+ /* 43767 */ 0320,02,017,01,0204,0,
+ /* 43773 */ 0321,02,017,01,0204,0,
+ /* 43779 */ 0324,02,017,01,0204,0,
+ /* 43785 */ 0320,02,017,0,0201,0,
+ /* 43791 */ 0321,02,017,0,0201,0,
+ /* 43797 */ 0324,02,017,0,0201,0,
+ /* 43803 */ 0273,0320,01,051,0101,0,
+ /* 43809 */ 0273,0321,01,051,0101,0,
+ /* 43815 */ 0273,0324,01,051,0101,0,
+ /* 43821 */ 0273,01,0200,0205,021,0,
+ /* 43827 */ 0273,01,0202,0205,021,0,
+ /* 43833 */ 0320,01,0367,0200,031,0,
+ /* 43839 */ 0321,01,0367,0200,041,0,
+ /* 43845 */ 0324,01,0367,0200,0255,0,
+ /* 43851 */ 0320,02,017,0377,0110,0,
+ /* 43857 */ 0321,02,017,0377,0110,0,
+ /* 43863 */ 0324,02,017,0377,0110,0,
+ /* 43869 */ 0320,02,017,0271,0110,0,
+ /* 43875 */ 0321,02,017,0271,0110,0,
+ /* 43881 */ 0324,02,017,0271,0110,0,
+ /* 43887 */ 0360,02,017,020,0101,0,
+ /* 43893 */ 0360,02,017,022,0110,0,
+ /* 43899 */ 0321,02,017,067,0200,0,
+ /* 43905 */ 0273,02,017,0300,0101,0,
+ /* 43911 */ 0320,02,017,0246,0110,0,
+ /* 43917 */ 0321,02,017,0246,0110,0,
+ /* 43923 */ 0272,0320,01,0207,0110,0,
+ /* 43929 */ 0272,0321,01,0207,0110,0,
+ /* 43935 */ 0272,0324,01,0207,0110,0,
+ /* 43941 */ 0272,0320,01,0207,0101,0,
+ /* 43947 */ 0272,0321,01,0207,0101,0,
+ /* 43953 */ 0272,0324,01,0207,0101,0,
+ /* 43959 */ 0273,0320,01,061,0101,0,
+ /* 43965 */ 0273,0321,01,061,0101,0,
+ /* 43971 */ 0273,0324,01,061,0101,0,
+ /* 43977 */ 0273,01,0200,0206,021,0,
+ /* 43983 */ 0273,01,0202,0206,021,0,
+ /* 43989 */ 0320,02,017,0107,0110,0,
+ /* 43995 */ 0320,02,017,0103,0110,0,
+ /* 44001 */ 0320,02,017,0102,0110,0,
+ /* 44007 */ 0320,02,017,0106,0110,0,
+ /* 44013 */ 0320,02,017,0104,0110,0,
+ /* 44019 */ 0320,02,017,0117,0110,0,
+ /* 44025 */ 0320,02,017,0115,0110,0,
+ /* 44031 */ 0320,02,017,0114,0110,0,
+ /* 44037 */ 0320,02,017,0116,0110,0,
+ /* 44043 */ 0320,02,017,0105,0110,0,
+ /* 44049 */ 0320,02,017,0101,0110,0,
+ /* 44055 */ 0320,02,017,0113,0110,0,
+ /* 44061 */ 0320,02,017,0111,0110,0,
+ /* 44067 */ 0320,02,017,0100,0110,0,
+ /* 44073 */ 0320,02,017,0112,0110,0,
+ /* 44079 */ 0320,02,017,0110,0110,0,
+ /* 44085 */ 0321,02,017,0107,0110,0,
+ /* 44091 */ 0321,02,017,0103,0110,0,
+ /* 44097 */ 0321,02,017,0102,0110,0,
+ /* 44103 */ 0321,02,017,0106,0110,0,
+ /* 44109 */ 0321,02,017,0104,0110,0,
+ /* 44115 */ 0321,02,017,0117,0110,0,
+ /* 44121 */ 0321,02,017,0115,0110,0,
+ /* 44127 */ 0321,02,017,0114,0110,0,
+ /* 44133 */ 0321,02,017,0116,0110,0,
+ /* 44139 */ 0321,02,017,0105,0110,0,
+ /* 44145 */ 0321,02,017,0101,0110,0,
+ /* 44151 */ 0321,02,017,0113,0110,0,
+ /* 44157 */ 0321,02,017,0111,0110,0,
+ /* 44163 */ 0321,02,017,0100,0110,0,
+ /* 44169 */ 0321,02,017,0112,0110,0,
+ /* 44175 */ 0321,02,017,0110,0110,0,
+ /* 44181 */ 0324,02,017,0107,0110,0,
+ /* 44187 */ 0324,02,017,0103,0110,0,
+ /* 44193 */ 0324,02,017,0102,0110,0,
+ /* 44199 */ 0324,02,017,0106,0110,0,
+ /* 44205 */ 0324,02,017,0104,0110,0,
+ /* 44211 */ 0324,02,017,0117,0110,0,
+ /* 44217 */ 0324,02,017,0115,0110,0,
+ /* 44223 */ 0324,02,017,0114,0110,0,
+ /* 44229 */ 0324,02,017,0116,0110,0,
+ /* 44235 */ 0324,02,017,0105,0110,0,
+ /* 44241 */ 0324,02,017,0101,0110,0,
+ /* 44247 */ 0324,02,017,0113,0110,0,
+ /* 44253 */ 0324,02,017,0111,0110,0,
+ /* 44259 */ 0324,02,017,0100,0110,0,
+ /* 44265 */ 0324,02,017,0112,0110,0,
+ /* 44271 */ 0324,02,017,0110,0110,0,
+ /* 44277 */ 0322,02,017,0207,064,0,
+ /* 44283 */ 0322,02,017,0203,064,0,
+ /* 44289 */ 0322,02,017,0202,064,0,
+ /* 44295 */ 0322,02,017,0206,064,0,
+ /* 44301 */ 0322,02,017,0204,064,0,
+ /* 44307 */ 0322,02,017,0217,064,0,
+ /* 44313 */ 0322,02,017,0215,064,0,
+ /* 44319 */ 0322,02,017,0214,064,0,
+ /* 44325 */ 0322,02,017,0216,064,0,
+ /* 44331 */ 0322,02,017,0205,064,0,
+ /* 44337 */ 0322,02,017,0201,064,0,
+ /* 44343 */ 0322,02,017,0213,064,0,
+ /* 44349 */ 0322,02,017,0211,064,0,
+ /* 44355 */ 0322,02,017,0200,064,0,
+ /* 44361 */ 0322,02,017,0212,064,0,
+ /* 44367 */ 0322,02,017,0210,064,0,
+ /* 44373 */ 0320,02,017,0207,064,0,
+ /* 44379 */ 0320,02,017,0203,064,0,
+ /* 44385 */ 0320,02,017,0202,064,0,
+ /* 44391 */ 0320,02,017,0206,064,0,
+ /* 44397 */ 0320,02,017,0204,064,0,
+ /* 44403 */ 0320,02,017,0217,064,0,
+ /* 44409 */ 0320,02,017,0215,064,0,
+ /* 44415 */ 0320,02,017,0214,064,0,
+ /* 44421 */ 0320,02,017,0216,064,0,
+ /* 44427 */ 0320,02,017,0205,064,0,
+ /* 44433 */ 0320,02,017,0201,064,0,
+ /* 44439 */ 0320,02,017,0213,064,0,
+ /* 44445 */ 0320,02,017,0211,064,0,
+ /* 44451 */ 0320,02,017,0200,064,0,
+ /* 44457 */ 0320,02,017,0212,064,0,
+ /* 44463 */ 0320,02,017,0210,064,0,
+ /* 44469 */ 0321,02,017,0207,064,0,
+ /* 44475 */ 0321,02,017,0203,064,0,
+ /* 44481 */ 0321,02,017,0202,064,0,
+ /* 44487 */ 0321,02,017,0206,064,0,
+ /* 44493 */ 0321,02,017,0204,064,0,
+ /* 44499 */ 0321,02,017,0217,064,0,
+ /* 44505 */ 0321,02,017,0215,064,0,
+ /* 44511 */ 0321,02,017,0214,064,0,
+ /* 44517 */ 0321,02,017,0216,064,0,
+ /* 44523 */ 0321,02,017,0205,064,0,
+ /* 44529 */ 0321,02,017,0201,064,0,
+ /* 44535 */ 0321,02,017,0213,064,0,
+ /* 44541 */ 0321,02,017,0211,064,0,
+ /* 44547 */ 0321,02,017,0200,064,0,
+ /* 44553 */ 0321,02,017,0212,064,0,
+ /* 44559 */ 0321,02,017,0210,064,0,
+ /* 44565 */ 0323,02,017,0207,064,0,
+ /* 44571 */ 0323,02,017,0203,064,0,
+ /* 44577 */ 0323,02,017,0202,064,0,
+ /* 44583 */ 0323,02,017,0206,064,0,
+ /* 44589 */ 0323,02,017,0204,064,0,
+ /* 44595 */ 0323,02,017,0217,064,0,
+ /* 44601 */ 0323,02,017,0215,064,0,
+ /* 44607 */ 0323,02,017,0214,064,0,
+ /* 44613 */ 0323,02,017,0216,064,0,
+ /* 44619 */ 0323,02,017,0205,064,0,
+ /* 44625 */ 0323,02,017,0201,064,0,
+ /* 44631 */ 0323,02,017,0213,064,0,
+ /* 44637 */ 0323,02,017,0211,064,0,
+ /* 44643 */ 0323,02,017,0200,064,0,
+ /* 44649 */ 0323,02,017,0212,064,0,
+ /* 44655 */ 0323,02,017,0210,064,0,
+ /* 44661 */ 0360,02,017,0130,0110,0,
+ /* 44667 */ 0333,02,017,0130,0110,0,
+ /* 44673 */ 0360,02,017,0125,0110,0,
+ /* 44679 */ 0360,02,017,0124,0110,0,
+ /* 44685 */ 0360,02,017,057,0110,0,
+ /* 44691 */ 0360,02,017,052,0110,0,
+ /* 44697 */ 0360,02,017,055,0110,0,
+ /* 44703 */ 0360,02,017,054,0110,0,
+ /* 44709 */ 0360,02,017,0136,0110,0,
+ /* 44715 */ 0333,02,017,0136,0110,0,
+ /* 44721 */ 0360,02,017,0256,0202,0,
+ /* 44727 */ 0360,02,017,0137,0110,0,
+ /* 44733 */ 0333,02,017,0137,0110,0,
+ /* 44739 */ 0360,02,017,0135,0110,0,
+ /* 44745 */ 0333,02,017,0135,0110,0,
+ /* 44751 */ 0360,02,017,050,0110,0,
+ /* 44757 */ 0360,02,017,051,0101,0,
+ /* 44763 */ 0360,02,017,026,0110,0,
+ /* 44769 */ 0360,02,017,027,0101,0,
+ /* 44775 */ 0360,02,017,023,0101,0,
+ /* 44781 */ 0360,02,017,0120,0110,0,
+ /* 44787 */ 0360,02,017,053,0101,0,
+ /* 44793 */ 0333,02,017,020,0110,0,
+ /* 44799 */ 0333,02,017,021,0101,0,
+ /* 44805 */ 0360,02,017,020,0110,0,
+ /* 44811 */ 0360,02,017,021,0101,0,
+ /* 44817 */ 0360,02,017,0131,0110,0,
+ /* 44823 */ 0333,02,017,0131,0110,0,
+ /* 44829 */ 0360,02,017,0126,0110,0,
+ /* 44835 */ 0360,02,017,0123,0110,0,
+ /* 44841 */ 0333,02,017,0123,0110,0,
+ /* 44847 */ 0360,02,017,0122,0110,0,
+ /* 44853 */ 0333,02,017,0122,0110,0,
+ /* 44859 */ 0360,02,017,0121,0110,0,
+ /* 44865 */ 0333,02,017,0121,0110,0,
+ /* 44871 */ 0360,02,017,0256,0203,0,
+ /* 44877 */ 0360,02,017,0134,0110,0,
+ /* 44883 */ 0333,02,017,0134,0110,0,
+ /* 44889 */ 0360,02,017,056,0110,0,
+ /* 44895 */ 0360,02,017,025,0110,0,
+ /* 44901 */ 0360,02,017,024,0110,0,
+ /* 44907 */ 0360,02,017,0127,0110,0,
+ /* 44913 */ 0360,02,017,0367,0110,0,
+ /* 44919 */ 0360,02,017,0347,0101,0,
+ /* 44925 */ 0360,02,017,0327,0110,0,
+ /* 44931 */ 0361,02,017,0367,0110,0,
+ /* 44937 */ 0360,02,017,0256,0207,0,
+ /* 44943 */ 0361,02,017,0347,0101,0,
+ /* 44949 */ 0361,02,017,053,0101,0,
+ /* 44955 */ 0361,02,017,0157,0110,0,
+ /* 44961 */ 0361,02,017,0177,0101,0,
+ /* 44967 */ 0333,02,017,0157,0110,0,
+ /* 44973 */ 0333,02,017,0177,0101,0,
+ /* 44979 */ 0332,02,017,0326,0110,0,
+ /* 44985 */ 0333,02,017,0176,0110,0,
+ /* 44991 */ 0361,02,017,0326,0101,0,
+ /* 44997 */ 0333,02,017,0326,0110,0,
+ /* 45003 */ 0361,02,017,0143,0110,0,
+ /* 45009 */ 0361,02,017,0153,0110,0,
+ /* 45015 */ 0361,02,017,0147,0110,0,
+ /* 45021 */ 0361,02,017,0374,0110,0,
+ /* 45027 */ 0361,02,017,0375,0110,0,
+ /* 45033 */ 0361,02,017,0376,0110,0,
+ /* 45039 */ 0360,02,017,0324,0110,0,
+ /* 45045 */ 0361,02,017,0324,0110,0,
+ /* 45051 */ 0361,02,017,0354,0110,0,
+ /* 45057 */ 0361,02,017,0355,0110,0,
+ /* 45063 */ 0361,02,017,0334,0110,0,
+ /* 45069 */ 0361,02,017,0335,0110,0,
+ /* 45075 */ 0361,02,017,0333,0110,0,
+ /* 45081 */ 0361,02,017,0337,0110,0,
+ /* 45087 */ 0361,02,017,0340,0110,0,
+ /* 45093 */ 0361,02,017,0343,0110,0,
+ /* 45099 */ 0361,02,017,0164,0110,0,
+ /* 45105 */ 0361,02,017,0165,0110,0,
+ /* 45111 */ 0361,02,017,0166,0110,0,
+ /* 45117 */ 0361,02,017,0144,0110,0,
+ /* 45123 */ 0361,02,017,0145,0110,0,
+ /* 45129 */ 0361,02,017,0146,0110,0,
+ /* 45135 */ 0361,02,017,0365,0110,0,
+ /* 45141 */ 0361,02,017,0356,0110,0,
+ /* 45147 */ 0361,02,017,0336,0110,0,
+ /* 45153 */ 0361,02,017,0352,0110,0,
+ /* 45159 */ 0361,02,017,0332,0110,0,
+ /* 45165 */ 0361,02,017,0327,0110,0,
+ /* 45171 */ 0361,02,017,0344,0110,0,
+ /* 45177 */ 0361,02,017,0345,0110,0,
+ /* 45183 */ 0361,02,017,0325,0110,0,
+ /* 45189 */ 0361,02,017,0364,0110,0,
+ /* 45195 */ 0361,02,017,0353,0110,0,
+ /* 45201 */ 0361,02,017,0366,0110,0,
+ /* 45207 */ 0361,02,017,0361,0110,0,
+ /* 45213 */ 0361,02,017,0362,0110,0,
+ /* 45219 */ 0361,02,017,0363,0110,0,
+ /* 45225 */ 0361,02,017,0341,0110,0,
+ /* 45231 */ 0361,02,017,0342,0110,0,
+ /* 45237 */ 0361,02,017,0321,0110,0,
+ /* 45243 */ 0361,02,017,0322,0110,0,
+ /* 45249 */ 0361,02,017,0323,0110,0,
+ /* 45255 */ 0361,02,017,0370,0110,0,
+ /* 45261 */ 0361,02,017,0371,0110,0,
+ /* 45267 */ 0361,02,017,0372,0110,0,
+ /* 45273 */ 0361,02,017,0373,0110,0,
+ /* 45279 */ 0361,02,017,0350,0110,0,
+ /* 45285 */ 0361,02,017,0351,0110,0,
+ /* 45291 */ 0361,02,017,0330,0110,0,
+ /* 45297 */ 0361,02,017,0331,0110,0,
+ /* 45303 */ 0361,02,017,0150,0110,0,
+ /* 45309 */ 0361,02,017,0151,0110,0,
+ /* 45315 */ 0361,02,017,0152,0110,0,
+ /* 45321 */ 0361,02,017,0155,0110,0,
+ /* 45327 */ 0361,02,017,0140,0110,0,
+ /* 45333 */ 0361,02,017,0141,0110,0,
+ /* 45339 */ 0361,02,017,0142,0110,0,
+ /* 45345 */ 0361,02,017,0154,0110,0,
+ /* 45351 */ 0361,02,017,0357,0110,0,
+ /* 45357 */ 0361,02,017,0130,0110,0,
+ /* 45363 */ 0332,02,017,0130,0110,0,
+ /* 45369 */ 0361,02,017,0125,0110,0,
+ /* 45375 */ 0361,02,017,0124,0110,0,
+ /* 45381 */ 0361,02,017,057,0110,0,
+ /* 45387 */ 0333,02,017,0346,0110,0,
+ /* 45393 */ 0360,02,017,0133,0110,0,
+ /* 45399 */ 0332,02,017,0346,0110,0,
+ /* 45405 */ 0361,02,017,055,0110,0,
+ /* 45411 */ 0361,02,017,0132,0110,0,
+ /* 45417 */ 0361,02,017,052,0110,0,
+ /* 45423 */ 0361,02,017,0133,0110,0,
+ /* 45429 */ 0360,02,017,0132,0110,0,
+ /* 45435 */ 0332,02,017,0132,0110,0,
+ /* 45441 */ 0333,02,017,0132,0110,0,
+ /* 45447 */ 0361,02,017,054,0110,0,
+ /* 45453 */ 0361,02,017,0346,0110,0,
+ /* 45459 */ 0333,02,017,0133,0110,0,
+ /* 45465 */ 0361,02,017,0136,0110,0,
+ /* 45471 */ 0332,02,017,0136,0110,0,
+ /* 45477 */ 0361,02,017,0137,0110,0,
+ /* 45483 */ 0332,02,017,0137,0110,0,
+ /* 45489 */ 0361,02,017,0135,0110,0,
+ /* 45495 */ 0332,02,017,0135,0110,0,
+ /* 45501 */ 0361,02,017,050,0110,0,
+ /* 45507 */ 0361,02,017,051,0101,0,
+ /* 45513 */ 0361,02,017,027,0101,0,
+ /* 45519 */ 0361,02,017,026,0110,0,
+ /* 45525 */ 0361,02,017,023,0101,0,
+ /* 45531 */ 0361,02,017,022,0110,0,
+ /* 45537 */ 0361,02,017,0120,0110,0,
+ /* 45543 */ 0332,02,017,020,0110,0,
+ /* 45549 */ 0332,02,017,021,0101,0,
+ /* 45555 */ 0361,02,017,020,0110,0,
+ /* 45561 */ 0361,02,017,021,0101,0,
+ /* 45567 */ 0361,02,017,0131,0110,0,
+ /* 45573 */ 0332,02,017,0131,0110,0,
+ /* 45579 */ 0361,02,017,0126,0110,0,
+ /* 45585 */ 0361,02,017,0121,0110,0,
+ /* 45591 */ 0332,02,017,0121,0110,0,
+ /* 45597 */ 0361,02,017,0134,0110,0,
+ /* 45603 */ 0332,02,017,0134,0110,0,
+ /* 45609 */ 0361,02,017,056,0110,0,
+ /* 45615 */ 0361,02,017,025,0110,0,
+ /* 45621 */ 0361,02,017,024,0110,0,
+ /* 45627 */ 0361,02,017,0127,0110,0,
+ /* 45633 */ 0361,02,017,0320,0110,0,
+ /* 45639 */ 0332,02,017,0320,0110,0,
+ /* 45645 */ 0361,02,017,0174,0110,0,
+ /* 45651 */ 0332,02,017,0174,0110,0,
+ /* 45657 */ 0361,02,017,0175,0110,0,
+ /* 45663 */ 0332,02,017,0175,0110,0,
+ /* 45669 */ 0332,02,017,0360,0110,0,
+ /* 45675 */ 0332,02,017,022,0110,0,
+ /* 45681 */ 0333,02,017,026,0110,0,
+ /* 45687 */ 0333,02,017,022,0110,0,
+ /* 45693 */ 0361,02,017,0307,0206,0,
+ /* 45699 */ 0360,02,017,0307,0206,0,
+ /* 45705 */ 0360,02,017,0307,0207,0,
+ /* 45711 */ 0332,03,017,01,0377,0,
+ /* 45717 */ 0333,03,017,01,0376,0,
+ /* 45723 */ 0332,03,017,01,0301,0,
+ /* 45729 */ 0333,03,017,01,0301,0,
+ /* 45735 */ 0361,02,017,0171,0110,0,
+ /* 45741 */ 0332,02,017,0171,0110,0,
+ /* 45747 */ 0332,02,017,053,0101,0,
+ /* 45753 */ 0333,02,017,053,0101,0,
+ /* 45759 */ 0270,01,04,01,0167,0,
+ /* 45765 */ 0270,01,0,01,0167,0,
+ /* 45771 */ 0320,02,017,0307,0206,0,
+ /* 45777 */ 0321,02,017,0307,0206,0,
+ /* 45783 */ 0324,02,017,0307,0206,0,
+ /* 45789 */ 0320,02,017,0307,0207,0,
+ /* 45795 */ 0321,02,017,0307,0207,0,
+ /* 45801 */ 0324,02,017,0307,0207,0,
+ /* 45807 */ 0336,03,017,0247,0310,0,
+ /* 45813 */ 0336,03,017,0247,0320,0,
+ /* 45819 */ 0336,03,017,0247,0330,0,
+ /* 45825 */ 0336,03,017,0247,0340,0,
+ /* 45831 */ 0336,03,017,0247,0350,0,
+ /* 45837 */ 0336,03,017,0246,0300,0,
+ /* 45843 */ 0336,03,017,0246,0310,0,
+ /* 45849 */ 0336,03,017,0246,0320,0,
+ /* 45855 */ 0322,02,0307,0370,064,0,
+ /* 45861 */ 0320,02,0307,0370,064,0,
+ /* 45867 */ 0321,02,0307,0370,064,0,
+ /* 45873 */ 0323,02,0307,0370,064,0,
+ /* 45879 */ 0333,02,017,033,0110,0,
+ /* 45885 */ 0361,02,017,032,0110,0,
+ /* 45891 */ 0361,02,017,033,0101,0,
+ /* 45897 */ 02,017,032,016,0110,0,
+ /* 45903 */ 02,017,033,015,0102,0,
+ /* 45909 */ 02,017,033,016,0101,0,
+ /* 45915 */ 03,017,070,0311,0110,0,
+ /* 45921 */ 03,017,070,0312,0110,0,
+ /* 45927 */ 03,017,070,0310,0110,0,
+ /* 45933 */ 03,017,070,0314,0110,0,
+ /* 45939 */ 03,017,070,0315,0110,0,
+ /* 45945 */ 03,017,070,0313,0110,0,
+ /* 45951 */ 0361,02,017,0256,0207,0,
+ /* 45957 */ 0361,02,017,0256,0206,0,
+ /* 45963 */ 0361,03,017,0256,0370,0,
+ /* 45969 */ 0310,03,017,01,0374,0,
+ /* 45975 */ 0311,03,017,01,0374,0,
+ /* 45981 */ 0313,03,017,01,0374,0,
+ /* 45987 */ 0360,02,017,034,0200,0,
+ /* 45993 */ 0360,03,017,01,0305,0,
+ /* 45999 */ 0332,02,017,0256,0206,0,
+ /* 46005 */ 0360,03,017,01,0317,0,
+ /* 46011 */ 0360,03,017,01,0327,0,
+ /* 46017 */ 0360,03,017,01,0300,0,
+ /* 46023 */ 0333,03,017,036,0373,0,
+ /* 46029 */ 0333,03,017,036,0372,0,
+ /* 46035 */ 0333,02,017,01,0205,0,
+ /* 46041 */ 0333,03,017,01,0352,0,
+ /* 46047 */ 0333,03,017,01,0350,0,
+ /* 46053 */ 0360,03,017,01,0350,0,
+ /* 46059 */ 0332,03,017,01,0351,0,
+ /* 46065 */ 0332,03,017,01,0350,0,
+ /* 46071 */ 0333,03,017,01,0356,0,
+ /* 46077 */ 0333,03,017,01,0357,0,
+ /* 46083 */ 0333,03,017,01,0355,0,
+ /* 46089 */ 0333,03,017,01,0354,0,
+ /* 46095 */ 0360,03,017,01,0306,0,
+ /* 46101 */ 0332,03,017,01,0306,0,
+ /* 46107 */ 0333,03,017,01,0306,0,
+ /* 46113 */ 0320,02,017,030,0200,0,
+ /* 46119 */ 0321,02,017,030,0200,0,
+ /* 46125 */ 0324,02,017,030,0200,0,
+ /* 46131 */ 0320,02,017,030,0201,0,
+ /* 46137 */ 0321,02,017,030,0201,0,
+ /* 46143 */ 0324,02,017,030,0201,0,
+ /* 46149 */ 0320,02,017,030,0202,0,
+ /* 46155 */ 0321,02,017,030,0202,0,
+ /* 46161 */ 0324,02,017,030,0202,0,
+ /* 46167 */ 0320,02,017,030,0203,0,
+ /* 46173 */ 0321,02,017,030,0203,0,
+ /* 46179 */ 0324,02,017,030,0203,0,
+ /* 46185 */ 0320,02,017,030,0204,0,
+ /* 46191 */ 0321,02,017,030,0204,0,
+ /* 46197 */ 0324,02,017,030,0204,0,
+ /* 46203 */ 0320,02,017,030,0205,0,
+ /* 46209 */ 0321,02,017,030,0205,0,
+ /* 46215 */ 0324,02,017,030,0205,0,
+ /* 46221 */ 0320,02,017,030,0206,0,
+ /* 46227 */ 0321,02,017,030,0206,0,
+ /* 46233 */ 0324,02,017,030,0206,0,
+ /* 46239 */ 0320,02,017,030,0207,0,
+ /* 46245 */ 0321,02,017,030,0207,0,
+ /* 46251 */ 0324,02,017,030,0207,0,
+ /* 46257 */ 0320,02,017,031,0200,0,
+ /* 46263 */ 0321,02,017,031,0200,0,
+ /* 46269 */ 0324,02,017,031,0200,0,
+ /* 46275 */ 0320,02,017,031,0201,0,
+ /* 46281 */ 0321,02,017,031,0201,0,
+ /* 46287 */ 0324,02,017,031,0201,0,
+ /* 46293 */ 0320,02,017,031,0202,0,
+ /* 46299 */ 0321,02,017,031,0202,0,
+ /* 46305 */ 0324,02,017,031,0202,0,
+ /* 46311 */ 0320,02,017,031,0203,0,
+ /* 46317 */ 0321,02,017,031,0203,0,
+ /* 46323 */ 0324,02,017,031,0203,0,
+ /* 46329 */ 0320,02,017,031,0204,0,
+ /* 46335 */ 0321,02,017,031,0204,0,
+ /* 46341 */ 0324,02,017,031,0204,0,
+ /* 46347 */ 0320,02,017,031,0205,0,
+ /* 46353 */ 0321,02,017,031,0205,0,
+ /* 46359 */ 0324,02,017,031,0205,0,
+ /* 46365 */ 0320,02,017,031,0206,0,
+ /* 46371 */ 0321,02,017,031,0206,0,
+ /* 46377 */ 0324,02,017,031,0206,0,
+ /* 46383 */ 0320,02,017,031,0207,0,
+ /* 46389 */ 0321,02,017,031,0207,0,
+ /* 46395 */ 0324,02,017,031,0207,0,
+ /* 46401 */ 0320,02,017,032,0200,0,
+ /* 46407 */ 0321,02,017,032,0200,0,
+ /* 46413 */ 0324,02,017,032,0200,0,
+ /* 46419 */ 0320,02,017,032,0201,0,
+ /* 46425 */ 0321,02,017,032,0201,0,
+ /* 46431 */ 0324,02,017,032,0201,0,
+ /* 46437 */ 0320,02,017,032,0202,0,
+ /* 46443 */ 0321,02,017,032,0202,0,
+ /* 46449 */ 0324,02,017,032,0202,0,
+ /* 46455 */ 0320,02,017,032,0203,0,
+ /* 46461 */ 0321,02,017,032,0203,0,
+ /* 46467 */ 0324,02,017,032,0203,0,
+ /* 46473 */ 0320,02,017,032,0204,0,
+ /* 46479 */ 0321,02,017,032,0204,0,
+ /* 46485 */ 0324,02,017,032,0204,0,
+ /* 46491 */ 0320,02,017,032,0205,0,
+ /* 46497 */ 0321,02,017,032,0205,0,
+ /* 46503 */ 0324,02,017,032,0205,0,
+ /* 46509 */ 0320,02,017,032,0206,0,
+ /* 46515 */ 0321,02,017,032,0206,0,
+ /* 46521 */ 0324,02,017,032,0206,0,
+ /* 46527 */ 0320,02,017,032,0207,0,
+ /* 46533 */ 0321,02,017,032,0207,0,
+ /* 46539 */ 0324,02,017,032,0207,0,
+ /* 46545 */ 0320,02,017,033,0200,0,
+ /* 46551 */ 0321,02,017,033,0200,0,
+ /* 46557 */ 0324,02,017,033,0200,0,
+ /* 46563 */ 0320,02,017,033,0201,0,
+ /* 46569 */ 0321,02,017,033,0201,0,
+ /* 46575 */ 0324,02,017,033,0201,0,
+ /* 46581 */ 0320,02,017,033,0202,0,
+ /* 46587 */ 0321,02,017,033,0202,0,
+ /* 46593 */ 0324,02,017,033,0202,0,
+ /* 46599 */ 0320,02,017,033,0203,0,
+ /* 46605 */ 0321,02,017,033,0203,0,
+ /* 46611 */ 0324,02,017,033,0203,0,
+ /* 46617 */ 0320,02,017,033,0204,0,
+ /* 46623 */ 0321,02,017,033,0204,0,
+ /* 46629 */ 0324,02,017,033,0204,0,
+ /* 46635 */ 0320,02,017,033,0205,0,
+ /* 46641 */ 0321,02,017,033,0205,0,
+ /* 46647 */ 0324,02,017,033,0205,0,
+ /* 46653 */ 0320,02,017,033,0206,0,
+ /* 46659 */ 0321,02,017,033,0206,0,
+ /* 46665 */ 0324,02,017,033,0206,0,
+ /* 46671 */ 0320,02,017,033,0207,0,
+ /* 46677 */ 0321,02,017,033,0207,0,
+ /* 46683 */ 0324,02,017,033,0207,0,
+ /* 46689 */ 0320,02,017,034,0200,0,
+ /* 46695 */ 0321,02,017,034,0200,0,
+ /* 46701 */ 0324,02,017,034,0200,0,
+ /* 46707 */ 0320,02,017,034,0201,0,
+ /* 46713 */ 0321,02,017,034,0201,0,
+ /* 46719 */ 0324,02,017,034,0201,0,
+ /* 46725 */ 0320,02,017,034,0202,0,
+ /* 46731 */ 0321,02,017,034,0202,0,
+ /* 46737 */ 0324,02,017,034,0202,0,
+ /* 46743 */ 0320,02,017,034,0203,0,
+ /* 46749 */ 0321,02,017,034,0203,0,
+ /* 46755 */ 0324,02,017,034,0203,0,
+ /* 46761 */ 0320,02,017,034,0204,0,
+ /* 46767 */ 0321,02,017,034,0204,0,
+ /* 46773 */ 0324,02,017,034,0204,0,
+ /* 46779 */ 0320,02,017,034,0205,0,
+ /* 46785 */ 0321,02,017,034,0205,0,
+ /* 46791 */ 0324,02,017,034,0205,0,
+ /* 46797 */ 0320,02,017,034,0206,0,
+ /* 46803 */ 0321,02,017,034,0206,0,
+ /* 46809 */ 0324,02,017,034,0206,0,
+ /* 46815 */ 0320,02,017,034,0207,0,
+ /* 46821 */ 0321,02,017,034,0207,0,
+ /* 46827 */ 0324,02,017,034,0207,0,
+ /* 46833 */ 0320,02,017,035,0200,0,
+ /* 46839 */ 0321,02,017,035,0200,0,
+ /* 46845 */ 0324,02,017,035,0200,0,
+ /* 46851 */ 0320,02,017,035,0201,0,
+ /* 46857 */ 0321,02,017,035,0201,0,
+ /* 46863 */ 0324,02,017,035,0201,0,
+ /* 46869 */ 0320,02,017,035,0202,0,
+ /* 46875 */ 0321,02,017,035,0202,0,
+ /* 46881 */ 0324,02,017,035,0202,0,
+ /* 46887 */ 0320,02,017,035,0203,0,
+ /* 46893 */ 0321,02,017,035,0203,0,
+ /* 46899 */ 0324,02,017,035,0203,0,
+ /* 46905 */ 0320,02,017,035,0204,0,
+ /* 46911 */ 0321,02,017,035,0204,0,
+ /* 46917 */ 0324,02,017,035,0204,0,
+ /* 46923 */ 0320,02,017,035,0205,0,
+ /* 46929 */ 0321,02,017,035,0205,0,
+ /* 46935 */ 0324,02,017,035,0205,0,
+ /* 46941 */ 0320,02,017,035,0206,0,
+ /* 46947 */ 0321,02,017,035,0206,0,
+ /* 46953 */ 0324,02,017,035,0206,0,
+ /* 46959 */ 0320,02,017,035,0207,0,
+ /* 46965 */ 0321,02,017,035,0207,0,
+ /* 46971 */ 0324,02,017,035,0207,0,
+ /* 46977 */ 0320,02,017,036,0200,0,
+ /* 46983 */ 0321,02,017,036,0200,0,
+ /* 46989 */ 0324,02,017,036,0200,0,
+ /* 46995 */ 0320,02,017,036,0201,0,
+ /* 47001 */ 0321,02,017,036,0201,0,
+ /* 47007 */ 0324,02,017,036,0201,0,
+ /* 47013 */ 0320,02,017,036,0202,0,
+ /* 47019 */ 0321,02,017,036,0202,0,
+ /* 47025 */ 0324,02,017,036,0202,0,
+ /* 47031 */ 0320,02,017,036,0203,0,
+ /* 47037 */ 0321,02,017,036,0203,0,
+ /* 47043 */ 0324,02,017,036,0203,0,
+ /* 47049 */ 0320,02,017,036,0204,0,
+ /* 47055 */ 0321,02,017,036,0204,0,
+ /* 47061 */ 0324,02,017,036,0204,0,
+ /* 47067 */ 0320,02,017,036,0205,0,
+ /* 47073 */ 0321,02,017,036,0205,0,
+ /* 47079 */ 0324,02,017,036,0205,0,
+ /* 47085 */ 0320,02,017,036,0206,0,
+ /* 47091 */ 0321,02,017,036,0206,0,
+ /* 47097 */ 0324,02,017,036,0206,0,
+ /* 47103 */ 0320,02,017,036,0207,0,
+ /* 47109 */ 0321,02,017,036,0207,0,
+ /* 47115 */ 0324,02,017,036,0207,0,
+ /* 47121 */ 0320,02,017,037,0201,0,
+ /* 47127 */ 0321,02,017,037,0201,0,
+ /* 47133 */ 0324,02,017,037,0201,0,
+ /* 47139 */ 0320,02,017,037,0202,0,
+ /* 47145 */ 0321,02,017,037,0202,0,
+ /* 47151 */ 0324,02,017,037,0202,0,
+ /* 47157 */ 0320,02,017,037,0203,0,
+ /* 47163 */ 0321,02,017,037,0203,0,
+ /* 47169 */ 0324,02,017,037,0203,0,
+ /* 47175 */ 0320,02,017,037,0204,0,
+ /* 47181 */ 0321,02,017,037,0204,0,
+ /* 47187 */ 0324,02,017,037,0204,0,
+ /* 47193 */ 0320,02,017,037,0205,0,
+ /* 47199 */ 0321,02,017,037,0205,0,
+ /* 47205 */ 0324,02,017,037,0205,0,
+ /* 47211 */ 0320,02,017,037,0206,0,
+ /* 47217 */ 0321,02,017,037,0206,0,
+ /* 47223 */ 0324,02,017,037,0206,0,
+ /* 47229 */ 0320,02,017,037,0207,0,
+ /* 47235 */ 0321,02,017,037,0207,0,
+ /* 47241 */ 0324,02,017,037,0207,0,
+ /* 47247 */ 0273,01,020,0101,0,
+ /* 47252 */ 0320,01,023,0110,0,
+ /* 47257 */ 0321,01,023,0110,0,
+ /* 47262 */ 0324,01,023,0110,0,
+ /* 47267 */ 0320,01,025,031,0,
+ /* 47272 */ 0321,01,025,041,0,
+ /* 47277 */ 0324,01,025,0255,0,
+ /* 47282 */ 0273,01,0,0101,0,
+ /* 47287 */ 0320,01,03,0110,0,
+ /* 47292 */ 0321,01,03,0110,0,
+ /* 47297 */ 0324,01,03,0110,0,
+ /* 47302 */ 0320,01,05,031,0,
+ /* 47307 */ 0321,01,05,041,0,
+ /* 47312 */ 0324,01,05,0255,0,
+ /* 47317 */ 0273,01,040,0101,0,
+ /* 47322 */ 0320,01,043,0110,0,
+ /* 47327 */ 0321,01,043,0110,0,
+ /* 47332 */ 0324,01,043,0110,0,
+ /* 47337 */ 0320,01,045,031,0,
+ /* 47342 */ 0321,01,045,041,0,
+ /* 47347 */ 0324,01,045,0255,0,
+ /* 47352 */ 0320,01,0142,0110,0,
+ /* 47357 */ 0321,01,0142,0110,0,
+ /* 47362 */ 0322,01,0350,064,0,
+ /* 47367 */ 0320,01,0350,064,0,
+ /* 47372 */ 0321,01,0350,064,0,
+ /* 47377 */ 0323,01,0350,064,0,
+ /* 47382 */ 0322,01,0377,0203,0,
+ /* 47387 */ 0324,01,0377,0203,0,
+ /* 47392 */ 0320,01,0377,0203,0,
+ /* 47397 */ 0321,01,0377,0203,0,
+ /* 47402 */ 0322,01,0377,0202,0,
+ /* 47407 */ 0320,01,0377,0202,0,
+ /* 47412 */ 0321,01,0377,0202,0,
+ /* 47417 */ 0323,01,0377,0202,0,
+ /* 47422 */ 0320,01,071,0101,0,
+ /* 47427 */ 0321,01,071,0101,0,
+ /* 47432 */ 0324,01,071,0101,0,
+ /* 47437 */ 0320,01,073,0110,0,
+ /* 47442 */ 0321,01,073,0110,0,
+ /* 47447 */ 0324,01,073,0110,0,
+ /* 47452 */ 0320,01,075,031,0,
+ /* 47457 */ 0321,01,075,041,0,
+ /* 47462 */ 0324,01,075,0255,0,
+ /* 47467 */ 01,0200,0207,021,0,
+ /* 47472 */ 01,0202,0207,021,0,
+ /* 47477 */ 0335,0321,01,0247,0,
+ /* 47482 */ 0335,0324,01,0247,0,
+ /* 47487 */ 0335,0320,01,0247,0,
+ /* 47492 */ 02,017,0246,0101,0,
+ /* 47497 */ 0273,01,0376,0201,0,
+ /* 47502 */ 0320,01,0367,0206,0,
+ /* 47507 */ 0321,01,0367,0206,0,
+ /* 47512 */ 0324,01,0367,0206,0,
+ /* 47517 */ 01,0310,030,025,0,
+ /* 47522 */ 01,0334,010,0300,0,
+ /* 47527 */ 01,0330,010,0300,0,
+ /* 47532 */ 01,0330,011,0300,0,
+ /* 47537 */ 01,0336,010,0300,0,
+ /* 47542 */ 0341,02,0333,0342,0,
+ /* 47547 */ 01,0332,010,0300,0,
+ /* 47552 */ 01,0332,011,0300,0,
+ /* 47557 */ 01,0332,010,0320,0,
+ /* 47562 */ 01,0332,011,0320,0,
+ /* 47567 */ 01,0332,010,0310,0,
+ /* 47572 */ 01,0332,011,0310,0,
+ /* 47577 */ 01,0333,010,0300,0,
+ /* 47582 */ 01,0333,011,0300,0,
+ /* 47587 */ 01,0333,010,0320,0,
+ /* 47592 */ 01,0333,011,0320,0,
+ /* 47597 */ 01,0333,010,0310,0,
+ /* 47602 */ 01,0333,011,0310,0,
+ /* 47607 */ 01,0333,010,0330,0,
+ /* 47612 */ 01,0333,011,0330,0,
+ /* 47617 */ 01,0332,010,0330,0,
+ /* 47622 */ 01,0332,011,0330,0,
+ /* 47627 */ 01,0330,010,0320,0,
+ /* 47632 */ 01,0330,011,0320,0,
+ /* 47637 */ 01,0333,010,0360,0,
+ /* 47642 */ 01,0333,011,0360,0,
+ /* 47647 */ 01,0337,010,0360,0,
+ /* 47652 */ 01,0337,011,0360,0,
+ /* 47657 */ 01,0330,010,0330,0,
+ /* 47662 */ 01,0330,011,0330,0,
+ /* 47667 */ 0341,02,0333,0341,0,
+ /* 47672 */ 01,0334,010,0370,0,
+ /* 47677 */ 01,0330,010,0360,0,
+ /* 47682 */ 01,0330,011,0360,0,
+ /* 47687 */ 01,0336,010,0370,0,
+ /* 47692 */ 01,0334,010,0360,0,
+ /* 47697 */ 01,0330,010,0370,0,
+ /* 47702 */ 01,0330,011,0370,0,
+ /* 47707 */ 01,0336,010,0360,0,
+ /* 47712 */ 0341,02,0333,0340,0,
+ /* 47717 */ 01,0335,010,0300,0,
+ /* 47722 */ 01,0337,010,0300,0,
+ /* 47727 */ 0341,02,0333,0343,0,
+ /* 47732 */ 01,0331,010,0300,0,
+ /* 47737 */ 01,0334,010,0310,0,
+ /* 47742 */ 01,0330,010,0310,0,
+ /* 47747 */ 01,0330,011,0310,0,
+ /* 47752 */ 01,0336,010,0310,0,
+ /* 47757 */ 0341,01,0335,0206,0,
+ /* 47762 */ 01,0335,010,0320,0,
+ /* 47767 */ 0341,01,0331,0207,0,
+ /* 47772 */ 0341,01,0331,0206,0,
+ /* 47777 */ 01,0335,010,0330,0,
+ /* 47782 */ 0341,01,0335,0207,0,
+ /* 47787 */ 0341,02,0337,0340,0,
+ /* 47792 */ 01,0334,010,0350,0,
+ /* 47797 */ 01,0330,010,0340,0,
+ /* 47802 */ 01,0330,011,0340,0,
+ /* 47807 */ 01,0336,010,0350,0,
+ /* 47812 */ 01,0334,010,0340,0,
+ /* 47817 */ 01,0330,010,0350,0,
+ /* 47822 */ 01,0330,011,0350,0,
+ /* 47827 */ 01,0336,010,0340,0,
+ /* 47832 */ 01,0335,010,0340,0,
+ /* 47837 */ 01,0335,011,0340,0,
+ /* 47842 */ 01,0333,010,0350,0,
+ /* 47847 */ 01,0333,011,0350,0,
+ /* 47852 */ 01,0337,010,0350,0,
+ /* 47857 */ 01,0337,011,0350,0,
+ /* 47862 */ 01,0335,010,0350,0,
+ /* 47867 */ 01,0335,011,0350,0,
+ /* 47872 */ 01,0331,010,0310,0,
+ /* 47877 */ 01,0331,011,0310,0,
+ /* 47882 */ 0320,01,0367,0207,0,
+ /* 47887 */ 0321,01,0367,0207,0,
+ /* 47892 */ 0324,01,0367,0207,0,
+ /* 47897 */ 0320,01,0367,0205,0,
+ /* 47902 */ 0321,01,0367,0205,0,
+ /* 47907 */ 0324,01,0367,0205,0,
+ /* 47912 */ 0320,01,0345,025,0,
+ /* 47917 */ 0321,01,0345,025,0,
+ /* 47922 */ 0273,01,0376,0200,0,
+ /* 47927 */ 02,017,01,0207,0,
+ /* 47932 */ 0310,01,0343,050,0,
+ /* 47937 */ 0311,01,0343,050,0,
+ /* 47942 */ 0371,01,0353,050,0,
+ /* 47947 */ 0322,01,0351,064,0,
+ /* 47952 */ 0320,01,0351,064,0,
+ /* 47957 */ 0321,01,0351,064,0,
+ /* 47962 */ 0323,01,0351,064,0,
+ /* 47967 */ 0322,01,0377,0205,0,
+ /* 47972 */ 0324,01,0377,0205,0,
+ /* 47977 */ 0320,01,0377,0205,0,
+ /* 47982 */ 0321,01,0377,0205,0,
+ /* 47987 */ 0322,01,0377,0204,0,
+ /* 47992 */ 0320,01,0377,0204,0,
+ /* 47997 */ 0321,01,0377,0204,0,
+ /* 48002 */ 0323,01,0377,0204,0,
+ /* 48007 */ 0320,01,0305,0110,0,
+ /* 48012 */ 0321,01,0305,0110,0,
+ /* 48017 */ 0320,01,0215,0110,0,
+ /* 48022 */ 0321,01,0215,0110,0,
+ /* 48027 */ 0324,01,0215,0110,0,
+ /* 48032 */ 0320,01,0304,0110,0,
+ /* 48037 */ 0321,01,0304,0110,0,
+ /* 48042 */ 02,017,01,0202,0,
+ /* 48047 */ 02,017,01,0203,0,
+ /* 48052 */ 02,017,0,0202,0,
+ /* 48057 */ 02,017,01,0206,0,
+ /* 48062 */ 0312,01,0342,050,0,
+ /* 48067 */ 0310,01,0342,050,0,
+ /* 48072 */ 0311,01,0342,050,0,
+ /* 48077 */ 0313,01,0342,050,0,
+ /* 48082 */ 0312,01,0341,050,0,
+ /* 48087 */ 0310,01,0341,050,0,
+ /* 48092 */ 0311,01,0341,050,0,
+ /* 48097 */ 0313,01,0341,050,0,
+ /* 48102 */ 0312,01,0340,050,0,
+ /* 48107 */ 0310,01,0340,050,0,
+ /* 48112 */ 0311,01,0340,050,0,
+ /* 48117 */ 0313,01,0340,050,0,
+ /* 48122 */ 02,017,0,0203,0,
+ /* 48127 */ 03,017,01,0310,0,
+ /* 48132 */ 03,017,01,0372,0,
+ /* 48137 */ 0320,01,0214,0101,0,
+ /* 48142 */ 0321,01,0214,0101,0,
+ /* 48147 */ 0323,01,0214,0101,0,
+ /* 48152 */ 0324,01,0214,0101,0,
+ /* 48157 */ 0323,01,0216,0110,0,
+ /* 48162 */ 0320,01,0216,0110,0,
+ /* 48167 */ 0321,01,0216,0110,0,
+ /* 48172 */ 0324,01,0216,0110,0,
+ /* 48177 */ 0320,01,0241,045,0,
+ /* 48182 */ 0321,01,0241,045,0,
+ /* 48187 */ 0324,01,0241,045,0,
+ /* 48192 */ 0320,01,0243,044,0,
+ /* 48197 */ 0321,01,0243,044,0,
+ /* 48202 */ 0324,01,0243,044,0,
+ /* 48207 */ 02,017,044,0101,0,
+ /* 48212 */ 02,017,046,0110,0,
+ /* 48217 */ 0271,01,0210,0101,0,
+ /* 48222 */ 0320,01,0213,0110,0,
+ /* 48227 */ 0321,01,0213,0110,0,
+ /* 48232 */ 0324,01,0213,0110,0,
+ /* 48237 */ 0320,010,0270,031,0,
+ /* 48242 */ 0321,010,0270,041,0,
+ /* 48247 */ 0323,010,0270,041,0,
+ /* 48252 */ 0324,010,0270,055,0,
+ /* 48257 */ 0324,01,0143,0110,0,
+ /* 48262 */ 0320,01,0367,0204,0,
+ /* 48267 */ 0321,01,0367,0204,0,
+ /* 48272 */ 0324,01,0367,0204,0,
+ /* 48277 */ 03,017,01,0311,0,
+ /* 48282 */ 03,017,01,0373,0,
+ /* 48287 */ 0273,01,0366,0203,0,
+ /* 48292 */ 0314,0326,01,0220,0,
+ /* 48297 */ 0273,01,0366,0202,0,
+ /* 48302 */ 0273,01,010,0101,0,
+ /* 48307 */ 0320,01,013,0110,0,
+ /* 48312 */ 0321,01,013,0110,0,
+ /* 48317 */ 0324,01,013,0110,0,
+ /* 48322 */ 0320,01,015,031,0,
+ /* 48327 */ 0321,01,015,041,0,
+ /* 48332 */ 0324,01,015,0255,0,
+ /* 48337 */ 0320,01,0347,024,0,
+ /* 48342 */ 0321,01,0347,024,0,
+ /* 48347 */ 0320,01,0217,0200,0,
+ /* 48352 */ 0321,01,0217,0200,0,
+ /* 48357 */ 0323,01,0217,0200,0,
+ /* 48362 */ 02,017,015,0200,0,
+ /* 48367 */ 02,017,015,0201,0,
+ /* 48372 */ 0320,01,0377,0206,0,
+ /* 48377 */ 0321,01,0377,0206,0,
+ /* 48382 */ 0323,01,0377,0206,0,
+ /* 48387 */ 0320,01,0152,0274,0,
+ /* 48392 */ 0320,01,0150,030,0,
+ /* 48397 */ 0321,01,0152,0274,0,
+ /* 48402 */ 0321,01,0150,040,0,
+ /* 48407 */ 0323,01,0152,0274,0,
+ /* 48412 */ 0323,01,0150,0254,0,
+ /* 48417 */ 01,0300,0202,025,0,
+ /* 48422 */ 0320,01,0321,0202,0,
+ /* 48427 */ 0320,01,0323,0202,0,
+ /* 48432 */ 0321,01,0321,0202,0,
+ /* 48437 */ 0321,01,0323,0202,0,
+ /* 48442 */ 0324,01,0321,0202,0,
+ /* 48447 */ 0324,01,0323,0202,0,
+ /* 48452 */ 01,0300,0203,025,0,
+ /* 48457 */ 0320,01,0321,0203,0,
+ /* 48462 */ 0320,01,0323,0203,0,
+ /* 48467 */ 0321,01,0321,0203,0,
+ /* 48472 */ 0321,01,0323,0203,0,
+ /* 48477 */ 0324,01,0321,0203,0,
+ /* 48482 */ 0324,01,0323,0203,0,
+ /* 48487 */ 03,017,01,0371,0,
+ /* 48492 */ 0320,01,0312,030,0,
+ /* 48497 */ 0320,01,0302,030,0,
+ /* 48502 */ 0321,01,0302,030,0,
+ /* 48507 */ 0321,01,0312,030,0,
+ /* 48512 */ 0323,01,0302,030,0,
+ /* 48517 */ 0324,01,0312,030,0,
+ /* 48522 */ 01,0300,0200,025,0,
+ /* 48527 */ 0320,01,0321,0200,0,
+ /* 48532 */ 0320,01,0323,0200,0,
+ /* 48537 */ 0321,01,0321,0200,0,
+ /* 48542 */ 0321,01,0323,0200,0,
+ /* 48547 */ 0324,01,0321,0200,0,
+ /* 48552 */ 0324,01,0323,0200,0,
+ /* 48557 */ 01,0300,0201,025,0,
+ /* 48562 */ 0320,01,0321,0201,0,
+ /* 48567 */ 0320,01,0323,0201,0,
+ /* 48572 */ 0321,01,0321,0201,0,
+ /* 48577 */ 0321,01,0323,0201,0,
+ /* 48582 */ 0324,01,0321,0201,0,
+ /* 48587 */ 0324,01,0323,0201,0,
+ /* 48592 */ 02,017,0173,0200,0,
+ /* 48597 */ 02,017,0175,0200,0,
+ /* 48602 */ 01,0300,0204,025,0,
+ /* 48607 */ 0320,01,0321,0204,0,
+ /* 48612 */ 0320,01,0323,0204,0,
+ /* 48617 */ 0321,01,0321,0204,0,
+ /* 48622 */ 0321,01,0323,0204,0,
+ /* 48627 */ 0324,01,0321,0204,0,
+ /* 48632 */ 0324,01,0323,0204,0,
+ /* 48637 */ 01,0300,0207,025,0,
+ /* 48642 */ 0320,01,0321,0207,0,
+ /* 48647 */ 0320,01,0323,0207,0,
+ /* 48652 */ 0321,01,0321,0207,0,
+ /* 48657 */ 0321,01,0323,0207,0,
+ /* 48662 */ 0324,01,0321,0207,0,
+ /* 48667 */ 0324,01,0323,0207,0,
+ /* 48672 */ 0273,01,030,0101,0,
+ /* 48677 */ 0320,01,033,0110,0,
+ /* 48682 */ 0321,01,033,0110,0,
+ /* 48687 */ 0324,01,033,0110,0,
+ /* 48692 */ 0320,01,035,031,0,
+ /* 48697 */ 0321,01,035,041,0,
+ /* 48702 */ 0324,01,035,0255,0,
+ /* 48707 */ 0335,0321,01,0257,0,
+ /* 48712 */ 0335,0324,01,0257,0,
+ /* 48717 */ 0335,0320,01,0257,0,
+ /* 48722 */ 02,017,01,0200,0,
+ /* 48727 */ 01,0300,0205,025,0,
+ /* 48732 */ 0320,01,0321,0205,0,
+ /* 48737 */ 0320,01,0323,0205,0,
+ /* 48742 */ 0321,01,0321,0205,0,
+ /* 48747 */ 0321,01,0323,0205,0,
+ /* 48752 */ 0324,01,0321,0205,0,
+ /* 48757 */ 0324,01,0323,0205,0,
+ /* 48762 */ 02,017,01,0201,0,
+ /* 48767 */ 03,017,01,0336,0,
+ /* 48772 */ 0273,01,050,0101,0,
+ /* 48777 */ 0320,01,053,0110,0,
+ /* 48782 */ 0321,01,053,0110,0,
+ /* 48787 */ 0324,01,053,0110,0,
+ /* 48792 */ 0320,01,055,031,0,
+ /* 48797 */ 0321,01,055,041,0,
+ /* 48802 */ 0324,01,055,0255,0,
+ /* 48807 */ 02,017,0172,0200,0,
+ /* 48812 */ 02,017,0174,0200,0,
+ /* 48817 */ 03,017,01,0370,0,
+ /* 48822 */ 0320,01,0205,0101,0,
+ /* 48827 */ 0321,01,0205,0101,0,
+ /* 48832 */ 0324,01,0205,0101,0,
+ /* 48837 */ 0320,01,0205,0110,0,
+ /* 48842 */ 0321,01,0205,0110,0,
+ /* 48847 */ 0324,01,0205,0110,0,
+ /* 48852 */ 0320,01,0251,031,0,
+ /* 48857 */ 0321,01,0251,041,0,
+ /* 48862 */ 0324,01,0251,0255,0,
+ /* 48867 */ 01,0366,0200,021,0,
+ /* 48872 */ 02,017,0,0204,0,
+ /* 48877 */ 02,017,0,0205,0,
+ /* 48882 */ 0272,01,0206,0110,0,
+ /* 48887 */ 0272,01,0206,0101,0,
+ /* 48892 */ 0273,01,060,0101,0,
+ /* 48897 */ 0320,01,063,0110,0,
+ /* 48902 */ 0321,01,063,0110,0,
+ /* 48907 */ 0324,01,063,0110,0,
+ /* 48912 */ 0320,01,065,031,0,
+ /* 48917 */ 0321,01,065,041,0,
+ /* 48922 */ 0324,01,065,0255,0,
+ /* 48927 */ 0370,01,0167,050,0,
+ /* 48932 */ 0370,01,0163,050,0,
+ /* 48937 */ 0370,01,0162,050,0,
+ /* 48942 */ 0370,01,0166,050,0,
+ /* 48947 */ 0370,01,0164,050,0,
+ /* 48952 */ 0370,01,0177,050,0,
+ /* 48957 */ 0370,01,0175,050,0,
+ /* 48962 */ 0370,01,0174,050,0,
+ /* 48967 */ 0370,01,0176,050,0,
+ /* 48972 */ 0370,01,0165,050,0,
+ /* 48977 */ 0370,01,0161,050,0,
+ /* 48982 */ 0370,01,0173,050,0,
+ /* 48987 */ 0370,01,0171,050,0,
+ /* 48992 */ 0370,01,0160,050,0,
+ /* 48997 */ 0370,01,0172,050,0,
+ /* 49002 */ 0370,01,0170,050,0,
+ /* 49007 */ 02,017,0227,0200,0,
+ /* 49012 */ 02,017,0223,0200,0,
+ /* 49017 */ 02,017,0222,0200,0,
+ /* 49022 */ 02,017,0226,0200,0,
+ /* 49027 */ 02,017,0224,0200,0,
+ /* 49032 */ 02,017,0237,0200,0,
+ /* 49037 */ 02,017,0235,0200,0,
+ /* 49042 */ 02,017,0234,0200,0,
+ /* 49047 */ 02,017,0236,0200,0,
+ /* 49052 */ 02,017,0225,0200,0,
+ /* 49057 */ 02,017,0221,0200,0,
+ /* 49062 */ 02,017,0233,0200,0,
+ /* 49067 */ 02,017,0231,0200,0,
+ /* 49072 */ 02,017,0220,0200,0,
+ /* 49077 */ 02,017,0232,0200,0,
+ /* 49082 */ 02,017,0230,0200,0,
+ /* 49087 */ 03,017,01,0320,0,
+ /* 49092 */ 03,017,01,0321,0,
+ /* 49097 */ 03,017,01,0335,0,
+ /* 49102 */ 03,017,01,0334,0,
+ /* 49107 */ 03,017,01,0324,0,
+ /* 49112 */ 03,017,01,0302,0,
+ /* 49117 */ 03,017,01,0332,0,
+ /* 49122 */ 03,017,01,0331,0,
+ /* 49127 */ 03,017,01,0303,0,
+ /* 49132 */ 03,017,01,0330,0,
+ /* 49137 */ 03,017,01,0333,0,
+ /* 49142 */ 03,017,01,0304,0,
+ /* 49147 */ 03,017,01,0312,0,
+ /* 49152 */ 03,017,01,0313,0,
+ /* 49157 */ 03,017,0247,0300,0,
+ /* 49162 */ 02,0306,0370,020,0,
+ /* 49167 */ 03,017,01,0325,0,
+ /* 49172 */ 03,017,01,0326,0,
+ /* 49177 */ 02,017,015,0202,0,
+ /* 49182 */ 0333,02,017,011,0,
+ /* 49187 */ 02,0325,012,0,
+ /* 49191 */ 01,0325,024,0,
+ /* 49195 */ 02,0324,012,0,
+ /* 49199 */ 01,0324,024,0,
+ /* 49203 */ 01,024,021,0,
+ /* 49207 */ 01,04,021,0,
+ /* 49211 */ 01,044,021,0,
+ /* 49215 */ 02,017,072,0,
+ /* 49219 */ 02,017,073,0,
+ /* 49223 */ 0320,01,0230,0,
+ /* 49227 */ 0321,01,0231,0,
+ /* 49231 */ 0324,01,0230,0,
+ /* 49235 */ 02,017,06,0,
+ /* 49239 */ 01,070,0101,0,
+ /* 49243 */ 01,074,021,0,
+ /* 49247 */ 0335,01,0246,0,
+ /* 49251 */ 02,017,0242,0,
+ /* 49255 */ 02,017,075,0,
+ /* 49259 */ 02,017,074,0,
+ /* 49263 */ 0324,01,0231,0,
+ /* 49267 */ 0320,01,0231,0,
+ /* 49271 */ 0321,01,0230,0,
+ /* 49275 */ 0320,010,0110,0,
+ /* 49279 */ 0321,010,0110,0,
+ /* 49283 */ 01,0366,0206,0,
+ /* 49287 */ 02,017,071,0,
+ /* 49291 */ 02,017,0167,0,
+ /* 49295 */ 02,0331,0360,0,
+ /* 49299 */ 02,0331,0341,0,
+ /* 49303 */ 01,0330,0200,0,
+ /* 49307 */ 01,0334,0200,0,
+ /* 49311 */ 02,0336,0301,0,
+ /* 49315 */ 01,0337,0204,0,
+ /* 49319 */ 01,0337,0206,0,
+ /* 49323 */ 02,0331,0340,0,
+ /* 49327 */ 02,0332,0301,0,
+ /* 49331 */ 02,0332,0321,0,
+ /* 49335 */ 02,0332,0311,0,
+ /* 49339 */ 02,0333,0301,0,
+ /* 49343 */ 02,0333,0321,0,
+ /* 49347 */ 02,0333,0311,0,
+ /* 49351 */ 02,0333,0331,0,
+ /* 49355 */ 02,0332,0331,0,
+ /* 49359 */ 01,0330,0202,0,
+ /* 49363 */ 01,0334,0202,0,
+ /* 49367 */ 02,0330,0321,0,
+ /* 49371 */ 02,0333,0361,0,
+ /* 49375 */ 02,0337,0361,0,
+ /* 49379 */ 01,0330,0203,0,
+ /* 49383 */ 01,0334,0203,0,
+ /* 49387 */ 02,0330,0331,0,
+ /* 49391 */ 02,0336,0331,0,
+ /* 49395 */ 02,0331,0377,0,
+ /* 49399 */ 02,0331,0366,0,
+ /* 49403 */ 01,0330,0206,0,
+ /* 49407 */ 01,0334,0206,0,
+ /* 49411 */ 02,0336,0371,0,
+ /* 49415 */ 01,0330,0207,0,
+ /* 49419 */ 01,0334,0207,0,
+ /* 49423 */ 02,0336,0361,0,
+ /* 49427 */ 02,017,016,0,
+ /* 49431 */ 02,0335,0301,0,
+ /* 49435 */ 02,0337,0301,0,
+ /* 49439 */ 01,0332,0200,0,
+ /* 49443 */ 01,0336,0200,0,
+ /* 49447 */ 01,0332,0202,0,
+ /* 49451 */ 01,0336,0202,0,
+ /* 49455 */ 01,0332,0203,0,
+ /* 49459 */ 01,0336,0203,0,
+ /* 49463 */ 01,0332,0206,0,
+ /* 49467 */ 01,0336,0206,0,
+ /* 49471 */ 01,0332,0207,0,
+ /* 49475 */ 01,0336,0207,0,
+ /* 49479 */ 01,0333,0200,0,
+ /* 49483 */ 01,0337,0200,0,
+ /* 49487 */ 01,0337,0205,0,
+ /* 49491 */ 01,0332,0201,0,
+ /* 49495 */ 01,0336,0201,0,
+ /* 49499 */ 02,0331,0367,0,
+ /* 49503 */ 01,0333,0202,0,
+ /* 49507 */ 01,0337,0202,0,
+ /* 49511 */ 01,0333,0203,0,
+ /* 49515 */ 01,0337,0203,0,
+ /* 49519 */ 01,0337,0207,0,
+ /* 49523 */ 01,0337,0201,0,
+ /* 49527 */ 01,0333,0201,0,
+ /* 49531 */ 01,0335,0201,0,
+ /* 49535 */ 01,0332,0204,0,
+ /* 49539 */ 01,0336,0204,0,
+ /* 49543 */ 01,0332,0205,0,
+ /* 49547 */ 01,0336,0205,0,
+ /* 49551 */ 01,0331,0200,0,
+ /* 49555 */ 01,0335,0200,0,
+ /* 49559 */ 01,0333,0205,0,
+ /* 49563 */ 02,0331,0301,0,
+ /* 49567 */ 02,0331,0350,0,
+ /* 49571 */ 01,0331,0205,0,
+ /* 49575 */ 01,0331,0204,0,
+ /* 49579 */ 02,0331,0352,0,
+ /* 49583 */ 02,0331,0351,0,
+ /* 49587 */ 02,0331,0354,0,
+ /* 49591 */ 02,0331,0355,0,
+ /* 49595 */ 02,0331,0353,0,
+ /* 49599 */ 02,0331,0356,0,
+ /* 49603 */ 01,0330,0201,0,
+ /* 49607 */ 01,0334,0201,0,
+ /* 49611 */ 02,0336,0311,0,
+ /* 49615 */ 02,0331,0320,0,
+ /* 49619 */ 02,0331,0363,0,
+ /* 49623 */ 02,0331,0370,0,
+ /* 49627 */ 02,0331,0365,0,
+ /* 49631 */ 02,0331,0362,0,
+ /* 49635 */ 02,0331,0374,0,
+ /* 49639 */ 01,0335,0204,0,
+ /* 49643 */ 02,0331,0375,0,
+ /* 49647 */ 02,0333,0344,0,
+ /* 49651 */ 02,0331,0376,0,
+ /* 49655 */ 02,0331,0373,0,
+ /* 49659 */ 02,0331,0372,0,
+ /* 49663 */ 01,0331,0202,0,
+ /* 49667 */ 01,0335,0202,0,
+ /* 49671 */ 02,0335,0321,0,
+ /* 49675 */ 01,0331,0203,0,
+ /* 49679 */ 01,0335,0203,0,
+ /* 49683 */ 01,0333,0207,0,
+ /* 49687 */ 02,0335,0331,0,
+ /* 49691 */ 01,0330,0204,0,
+ /* 49695 */ 01,0334,0204,0,
+ /* 49699 */ 02,0336,0351,0,
+ /* 49703 */ 01,0330,0205,0,
+ /* 49707 */ 01,0334,0205,0,
+ /* 49711 */ 02,0336,0341,0,
+ /* 49715 */ 02,0331,0344,0,
+ /* 49719 */ 02,0335,0341,0,
+ /* 49723 */ 02,0333,0351,0,
+ /* 49727 */ 02,0337,0351,0,
+ /* 49731 */ 02,0335,0351,0,
+ /* 49735 */ 02,0332,0351,0,
+ /* 49739 */ 02,0331,0345,0,
+ /* 49743 */ 02,0331,0311,0,
+ /* 49747 */ 02,0331,0364,0,
+ /* 49751 */ 02,0331,0361,0,
+ /* 49755 */ 02,0331,0371,0,
+ /* 49759 */ 01,0366,0207,0,
+ /* 49763 */ 01,0366,0205,0,
+ /* 49767 */ 01,0344,025,0,
+ /* 49771 */ 0320,01,0355,0,
+ /* 49775 */ 0321,01,0355,0,
+ /* 49779 */ 0320,010,0100,0,
+ /* 49783 */ 0321,010,0100,0,
+ /* 49787 */ 0321,01,0155,0,
+ /* 49791 */ 0320,01,0155,0,
+ /* 49795 */ 01,0315,024,0,
+ /* 49799 */ 02,017,010,0,
+ /* 49803 */ 0322,01,0317,0,
+ /* 49807 */ 0321,01,0317,0,
+ /* 49811 */ 0324,01,0317,0,
+ /* 49815 */ 0320,01,0317,0,
+ /* 49819 */ 02,017,07,0,
+ /* 49823 */ 02,017,05,0,
+ /* 49827 */ 0321,01,0255,0,
+ /* 49831 */ 0324,01,0255,0,
+ /* 49835 */ 0320,01,0255,0,
+ /* 49839 */ 01,0240,045,0,
+ /* 49843 */ 01,0242,044,0,
+ /* 49847 */ 01,0212,0110,0,
+ /* 49851 */ 010,0260,021,0,
+ /* 49855 */ 0321,01,0245,0,
+ /* 49859 */ 0324,01,0245,0,
+ /* 49863 */ 0320,01,0245,0,
+ /* 49867 */ 01,0366,0204,0,
+ /* 49871 */ 01,014,021,0,
+ /* 49875 */ 01,0346,024,0,
+ /* 49879 */ 0320,01,0357,0,
+ /* 49883 */ 0321,01,0357,0,
+ /* 49887 */ 0321,01,0157,0,
+ /* 49891 */ 0320,01,0157,0,
+ /* 49895 */ 0333,01,0220,0,
+ /* 49899 */ 0320,010,0130,0,
+ /* 49903 */ 0321,010,0130,0,
+ /* 49907 */ 0323,010,0130,0,
+ /* 49911 */ 02,017,0241,0,
+ /* 49915 */ 02,017,0251,0,
+ /* 49919 */ 0322,01,0141,0,
+ /* 49923 */ 0321,01,0141,0,
+ /* 49927 */ 0320,01,0141,0,
+ /* 49931 */ 0322,01,0235,0,
+ /* 49935 */ 0321,01,0235,0,
+ /* 49939 */ 0320,01,0235,0,
+ /* 49943 */ 0320,010,0120,0,
+ /* 49947 */ 0321,010,0120,0,
+ /* 49951 */ 0323,010,0120,0,
+ /* 49955 */ 02,017,0240,0,
+ /* 49959 */ 02,017,0250,0,
+ /* 49963 */ 0322,01,0140,0,
+ /* 49967 */ 0321,01,0140,0,
+ /* 49971 */ 0320,01,0140,0,
+ /* 49975 */ 0322,01,0234,0,
+ /* 49979 */ 0321,01,0234,0,
+ /* 49983 */ 0320,01,0234,0,
+ /* 49987 */ 01,0320,0202,0,
+ /* 49991 */ 01,0322,0202,0,
+ /* 49995 */ 01,0320,0203,0,
+ /* 49999 */ 01,0322,0203,0,
+ /* 50003 */ 02,017,062,0,
+ /* 50007 */ 02,017,063,0,
+ /* 50011 */ 02,017,061,0,
+ /* 50015 */ 0320,01,0303,0,
+ /* 50019 */ 0320,01,0313,0,
+ /* 50023 */ 0321,01,0303,0,
+ /* 50027 */ 0321,01,0313,0,
+ /* 50031 */ 0323,01,0303,0,
+ /* 50035 */ 0324,01,0313,0,
+ /* 50039 */ 01,0320,0200,0,
+ /* 50043 */ 01,0322,0200,0,
+ /* 50047 */ 01,0320,0201,0,
+ /* 50051 */ 01,0322,0201,0,
+ /* 50055 */ 02,017,0252,0,
+ /* 50059 */ 01,0320,0204,0,
+ /* 50063 */ 01,0322,0204,0,
+ /* 50067 */ 01,0320,0207,0,
+ /* 50071 */ 01,0322,0207,0,
+ /* 50075 */ 01,034,021,0,
+ /* 50079 */ 0335,01,0256,0,
+ /* 50083 */ 01,0320,0205,0,
+ /* 50087 */ 01,0322,0205,0,
+ /* 50091 */ 02,017,070,0,
+ /* 50095 */ 02,017,0176,0,
+ /* 50099 */ 0321,01,0253,0,
+ /* 50103 */ 0324,01,0253,0,
+ /* 50107 */ 0320,01,0253,0,
+ /* 50111 */ 01,054,021,0,
+ /* 50115 */ 02,017,064,0,
+ /* 50119 */ 02,017,065,0,
+ /* 50123 */ 01,0204,0101,0,
+ /* 50127 */ 01,0204,0110,0,
+ /* 50131 */ 01,0250,021,0,
+ /* 50135 */ 02,017,0377,0,
+ /* 50139 */ 02,017,0271,0,
+ /* 50143 */ 02,017,013,0,
+ /* 50147 */ 02,017,060,0,
+ /* 50151 */ 0320,011,0220,0,
+ /* 50155 */ 0321,011,0220,0,
+ /* 50159 */ 0324,011,0220,0,
+ /* 50163 */ 0320,010,0220,0,
+ /* 50167 */ 0321,010,0220,0,
+ /* 50171 */ 0324,010,0220,0,
+ /* 50175 */ 0321,01,0220,0,
+ /* 50179 */ 01,064,021,0,
+ /* 50183 */ 02,017,067,0,
+ /* 50187 */ 01,067,0,
+ /* 50190 */ 01,077,0,
+ /* 50193 */ 01,0365,0,
+ /* 50196 */ 01,047,0,
+ /* 50199 */ 01,057,0,
+ /* 50202 */ 01,0364,0,
+ /* 50205 */ 01,0361,0,
+ /* 50208 */ 01,0154,0,
+ /* 50211 */ 01,0314,0,
+ /* 50214 */ 01,0316,0,
+ /* 50217 */ 01,0237,0,
+ /* 50220 */ 01,0254,0,
+ /* 50223 */ 01,0156,0,
+ /* 50226 */ 01,0375,0,
+};
+
+/*
+ * Bytecode frequencies (including reuse):
+ *
+ * 0:8285 | 40: 2 | 100: 50 | 140: 0 | 200: 180 | 240: 768 | 300: 1 | 340: 8
+ * 1:7845 | 41: 37 | 101: 645 | 141: 0 | 201: 94 | 241:1569 | 301: 0 | 341: 10
+ * 2:1432 | 42: 12 | 102: 14 | 142: 0 | 202: 110 | 242: 1 | 302: 0 | 342: 0
+ * 3: 242 | 43: 0 | 103: 0 | 143: 0 | 203: 89 | 243: 0 | 303: 0 | 343: 0
+ * 4: 2 | 44: 4 | 104: 0 | 144: 0 | 204: 121 | 244: 0 | 304: 0 | 344: 0
+ * 5: 0 | 45: 4 | 105: 0 | 145: 0 | 205: 88 | 245: 0 | 305: 0 | 345: 0
+ * 6: 0 | 46: 0 | 106: 0 | 146: 0 | 206: 112 | 246: 0 | 306: 0 | 346: 0
+ * 7: 0 | 47: 0 | 107: 0 | 147: 0 | 207: 89 | 247: 0 | 307: 0 | 347: 0
+ * 10: 73 | 50: 115 | 110:3168 | 150: 0 | 210: 8 | 250: 863 | 310: 14 | 350: 0
+ * 11: 26 | 51: 0 | 111: 0 | 151: 0 | 211: 14 | 251: 0 | 311: 12 | 351: 0
+ * 12: 0 | 52: 0 | 112: 0 | 152: 0 | 212: 19 | 252: 0 | 312: 5 | 352: 0
+ * 13: 0 | 53: 0 | 113: 0 | 153: 0 | 213: 9 | 253: 0 | 313: 12 | 353: 0
+ * 14: 0 | 54: 0 | 114: 0 | 154: 0 | 214: 15 | 254: 2 | 314: 1 | 354: 0
+ * 15: 2 | 55: 1 | 115: 0 | 155: 0 | 215: 2 | 255: 23 | 315: 0 | 355: 0
+ * 16: 4 | 56: 0 | 116: 0 | 156: 0 | 216: 19 | 256: 2 | 316: 0 | 356: 0
+ * 17: 0 | 57: 0 | 117: 0 | 157: 0 | 217: 7 | 257: 0 | 317: 21 | 357: 0
+ * 20: 4 | 60: 0 | 120:2566 | 160: 0 | 220: 0 | 260: 800 | 320: 435 | 360: 198
+ * 21: 107 | 61: 0 | 121: 0 | 161: 0 | 221: 0 | 261:1022 | 321: 448 | 361: 255
+ * 22: 408 | 62: 0 | 122: 0 | 162: 0 | 222: 0 | 262: 103 | 322: 52 | 362: 0
+ * 23: 195 | 63: 0 | 123: 0 | 163: 0 | 223: 0 | 263: 0 | 323: 165 | 363: 0
+ * 24: 6 | 64: 207 | 124: 0 | 164: 0 | 224: 0 | 264: 0 | 324: 389 | 364: 0
+ * 25: 67 | 65: 0 | 125: 0 | 165: 0 | 225: 0 | 265: 0 | 325: 2 | 365: 0
+ * 26: 63 | 66: 0 | 126: 0 | 166: 0 | 226: 0 | 266: 0 | 326: 13 | 366: 0
+ * 27: 1 | 67: 0 | 127: 0 | 167: 0 | 227: 0 | 267: 0 | 327: 0 | 367: 0
+ * 30: 24 | 70: 0 | 130: 35 | 170: 0 | 230: 0 | 270: 386 | 330: 0 | 370: 30
+ * 31: 36 | 71: 0 | 131: 0 | 171: 1 | 231: 0 | 271: 12 | 331: 6 | 371: 1
+ * 32: 4 | 72: 0 | 132: 0 | 172: 0 | 232: 0 | 272: 8 | 332: 64 | 372: 0
+ * 33: 0 | 73: 0 | 133: 0 | 173: 0 | 233: 0 | 273: 183 | 333: 101 | 373: 30
+ * 34: 6 | 74: 6 | 134: 0 | 174: 0 | 234: 0 | 274: 6 | 334: 2 | 374: 30
+ * 35: 2 | 75: 0 | 135: 0 | 175: 35 | 235: 0 | 275: 94 | 335: 8 | 375: 26
+ * 36: 0 | 76: 0 | 136: 0 | 176: 88 | 236: 0 | 276: 12 | 336: 8 | 376: 24
+ * 37: 0 | 77: 0 | 137: 0 | 177: 53 | 237: 0 | 277: 0 | 337: 0 | 377: 0
+ */
diff --git a/vere/ext/nasm/x86/insnsd.c b/vere/ext/nasm/x86/insnsd.c
new file mode 100644
index 0000000..53aff50
--- /dev/null
+++ b/vere/ext/nasm/x86/insnsd.c
@@ -0,0 +1,29941 @@
+/* This file auto-generated from insns.dat by insns.pl - don't edit it */
+
+#include "nasm.h"
+#include "insns.h"
+
+static const struct itemplate instrux[] = {
+ /* 0 */ {I_RESB, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 1 */ {I_RESW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 2 */ {I_RESD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 3 */ {I_RESQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 4 */ {I_REST, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 5 */ {I_RESO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 6 */ {I_RESY, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 7 */ {I_RESZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49325, 0},
+ /* 8 */ {I_AAA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50187, 1},
+ /* 9 */ {I_AAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49187, 1},
+ /* 10 */ {I_AAD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49191, 2},
+ /* 11 */ {I_AAM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49195, 1},
+ /* 12 */ {I_AAM, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49199, 2},
+ /* 13 */ {I_AAS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50190, 1},
+ /* 14 */ {I_ADC, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47247, 3},
+ /* 15 */ {I_ADC, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47248, 0},
+ /* 16 */ {I_ADC, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42741, 3},
+ /* 17 */ {I_ADC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42742, 0},
+ /* 18 */ {I_ADC, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42747, 4},
+ /* 19 */ {I_ADC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42748, 5},
+ /* 20 */ {I_ADC, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42753, 6},
+ /* 21 */ {I_ADC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42754, 7},
+ /* 22 */ {I_ADC, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+36381, 8},
+ /* 23 */ {I_ADC, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+36381, 0},
+ /* 24 */ {I_ADC, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47252, 8},
+ /* 25 */ {I_ADC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47252, 0},
+ /* 26 */ {I_ADC, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47257, 9},
+ /* 27 */ {I_ADC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47257, 5},
+ /* 28 */ {I_ADC, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47262, 10},
+ /* 29 */ {I_ADC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47262, 7},
+ /* 30 */ {I_ADC, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32864, 11},
+ /* 31 */ {I_ADC, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32871, 12},
+ /* 32 */ {I_ADC, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32878, 13},
+ /* 33 */ {I_ADC, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49203, 8},
+ /* 34 */ {I_ADC, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47267, 8},
+ /* 35 */ {I_ADC, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47272, 9},
+ /* 36 */ {I_ADC, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47277, 10},
+ /* 37 */ {I_ADC, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42759, 3},
+ /* 38 */ {I_ADC, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32885, 3},
+ /* 39 */ {I_ADC, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32892, 4},
+ /* 40 */ {I_ADC, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32899, 6},
+ /* 41 */ {I_ADC, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32885, 3},
+ /* 42 */ {I_ADC, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32892, 4},
+ /* 43 */ {I_ADD, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47282, 3},
+ /* 44 */ {I_ADD, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47283, 0},
+ /* 45 */ {I_ADD, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42771, 3},
+ /* 46 */ {I_ADD, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42772, 0},
+ /* 47 */ {I_ADD, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42777, 4},
+ /* 48 */ {I_ADD, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42778, 5},
+ /* 49 */ {I_ADD, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42783, 6},
+ /* 50 */ {I_ADD, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42784, 7},
+ /* 51 */ {I_ADD, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40154, 8},
+ /* 52 */ {I_ADD, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40154, 0},
+ /* 53 */ {I_ADD, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47287, 8},
+ /* 54 */ {I_ADD, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47287, 0},
+ /* 55 */ {I_ADD, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47292, 9},
+ /* 56 */ {I_ADD, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47292, 5},
+ /* 57 */ {I_ADD, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47297, 10},
+ /* 58 */ {I_ADD, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47297, 7},
+ /* 59 */ {I_ADD, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32906, 11},
+ /* 60 */ {I_ADD, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32913, 12},
+ /* 61 */ {I_ADD, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32920, 13},
+ /* 62 */ {I_ADD, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49207, 8},
+ /* 63 */ {I_ADD, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47302, 8},
+ /* 64 */ {I_ADD, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47307, 9},
+ /* 65 */ {I_ADD, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47312, 10},
+ /* 66 */ {I_ADD, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42789, 3},
+ /* 67 */ {I_ADD, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32927, 3},
+ /* 68 */ {I_ADD, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32934, 4},
+ /* 69 */ {I_ADD, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32941, 6},
+ /* 70 */ {I_ADD, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42789, 3},
+ /* 71 */ {I_ADD, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32927, 3},
+ /* 72 */ {I_ADD, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32934, 4},
+ /* 73 */ {I_AND, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47317, 3},
+ /* 74 */ {I_AND, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47318, 0},
+ /* 75 */ {I_AND, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42801, 3},
+ /* 76 */ {I_AND, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42802, 0},
+ /* 77 */ {I_AND, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42807, 4},
+ /* 78 */ {I_AND, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42808, 5},
+ /* 79 */ {I_AND, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42813, 6},
+ /* 80 */ {I_AND, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42814, 7},
+ /* 81 */ {I_AND, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40434, 8},
+ /* 82 */ {I_AND, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40434, 0},
+ /* 83 */ {I_AND, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47322, 8},
+ /* 84 */ {I_AND, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47322, 0},
+ /* 85 */ {I_AND, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47327, 9},
+ /* 86 */ {I_AND, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47327, 5},
+ /* 87 */ {I_AND, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47332, 10},
+ /* 88 */ {I_AND, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47332, 7},
+ /* 89 */ {I_AND, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32948, 11},
+ /* 90 */ {I_AND, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32955, 12},
+ /* 91 */ {I_AND, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+32962, 13},
+ /* 92 */ {I_AND, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49211, 8},
+ /* 93 */ {I_AND, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47337, 8},
+ /* 94 */ {I_AND, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47342, 9},
+ /* 95 */ {I_AND, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47347, 10},
+ /* 96 */ {I_AND, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42819, 3},
+ /* 97 */ {I_AND, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32969, 3},
+ /* 98 */ {I_AND, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32976, 4},
+ /* 99 */ {I_AND, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+32983, 6},
+ /* 100 */ {I_AND, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42819, 3},
+ /* 101 */ {I_AND, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32969, 3},
+ /* 102 */ {I_AND, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32976, 4},
+ /* 103 */ {I_ARPL, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29252, 15},
+ /* 104 */ {I_ARPL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+29252, 16},
+ /* 105 */ {I_BOUND, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47352, 18},
+ /* 106 */ {I_BOUND, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47357, 19},
+ /* 107 */ {I_BSF, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+32990, 9},
+ /* 108 */ {I_BSF, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+32990, 5},
+ /* 109 */ {I_BSF, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+32997, 9},
+ /* 110 */ {I_BSF, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32997, 5},
+ /* 111 */ {I_BSF, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33004, 10},
+ /* 112 */ {I_BSF, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33004, 7},
+ /* 113 */ {I_BSR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33011, 9},
+ /* 114 */ {I_BSR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33011, 5},
+ /* 115 */ {I_BSR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33018, 9},
+ /* 116 */ {I_BSR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33018, 5},
+ /* 117 */ {I_BSR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33025, 10},
+ /* 118 */ {I_BSR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33025, 7},
+ /* 119 */ {I_BSWAP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42831, 20},
+ /* 120 */ {I_BSWAP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42837, 7},
+ /* 121 */ {I_BT, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42843, 9},
+ /* 122 */ {I_BT, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42843, 5},
+ /* 123 */ {I_BT, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42849, 9},
+ /* 124 */ {I_BT, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42849, 5},
+ /* 125 */ {I_BT, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42855, 10},
+ /* 126 */ {I_BT, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42855, 7},
+ /* 127 */ {I_BT, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33032, 5},
+ /* 128 */ {I_BT, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33039, 5},
+ /* 129 */ {I_BT, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33046, 7},
+ /* 130 */ {I_BTC, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33053, 4},
+ /* 131 */ {I_BTC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33054, 5},
+ /* 132 */ {I_BTC, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33060, 4},
+ /* 133 */ {I_BTC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33061, 5},
+ /* 134 */ {I_BTC, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33067, 6},
+ /* 135 */ {I_BTC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33068, 7},
+ /* 136 */ {I_BTC, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12304, 12},
+ /* 137 */ {I_BTC, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12312, 12},
+ /* 138 */ {I_BTC, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12320, 13},
+ /* 139 */ {I_BTR, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33074, 4},
+ /* 140 */ {I_BTR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33075, 5},
+ /* 141 */ {I_BTR, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33081, 4},
+ /* 142 */ {I_BTR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33082, 5},
+ /* 143 */ {I_BTR, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33088, 6},
+ /* 144 */ {I_BTR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33089, 7},
+ /* 145 */ {I_BTR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12328, 12},
+ /* 146 */ {I_BTR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12336, 12},
+ /* 147 */ {I_BTR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12344, 13},
+ /* 148 */ {I_BTS, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33095, 4},
+ /* 149 */ {I_BTS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33096, 5},
+ /* 150 */ {I_BTS, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33102, 4},
+ /* 151 */ {I_BTS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33103, 5},
+ /* 152 */ {I_BTS, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33109, 6},
+ /* 153 */ {I_BTS, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33110, 7},
+ /* 154 */ {I_BTS, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12352, 12},
+ /* 155 */ {I_BTS, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12360, 12},
+ /* 156 */ {I_BTS, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12368, 13},
+ /* 157 */ {I_CALL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47362, 21},
+ /* 158 */ {I_CALL, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47367, 22},
+ /* 159 */ {I_CALL, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47372, 23},
+ /* 160 */ {I_CALL, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47377, 24},
+ /* 161 */ {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42879, 1},
+ /* 162 */ {I_CALL, 2, {IMMEDIATE|BITS16|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42885, 1},
+ /* 163 */ {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42885, 1},
+ /* 164 */ {I_CALL, 2, {IMMEDIATE|BITS32|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42891, 19},
+ /* 165 */ {I_CALL, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42891, 19},
+ /* 166 */ {I_CALL, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47382, 1},
+ /* 167 */ {I_CALL, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47387, 7},
+ /* 168 */ {I_CALL, 1, {MEMORY|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47392, 0},
+ /* 169 */ {I_CALL, 1, {MEMORY|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47397, 5},
+ /* 170 */ {I_CALL, 1, {MEMORY|BITS64|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47387, 7},
+ /* 171 */ {I_CALL, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47402, 21},
+ /* 172 */ {I_CALL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47407, 22},
+ /* 173 */ {I_CALL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47412, 23},
+ /* 174 */ {I_CALL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47417, 24},
+ /* 175 */ {I_CBW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49223, 0},
+ /* 176 */ {I_CDQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49227, 5},
+ /* 177 */ {I_CDQE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49231, 7},
+ /* 178 */ {I_CLC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48819, 0},
+ /* 179 */ {I_CLD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45984, 0},
+ /* 180 */ {I_CLI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48134, 0},
+ /* 181 */ {I_CLTS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49235, 25},
+ /* 182 */ {I_CMC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50193, 0},
+ /* 183 */ {I_CMP, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+49239, 8},
+ /* 184 */ {I_CMP, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+49239, 0},
+ /* 185 */ {I_CMP, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47422, 8},
+ /* 186 */ {I_CMP, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47422, 0},
+ /* 187 */ {I_CMP, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47427, 9},
+ /* 188 */ {I_CMP, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47427, 5},
+ /* 189 */ {I_CMP, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47432, 10},
+ /* 190 */ {I_CMP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47432, 7},
+ /* 191 */ {I_CMP, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40392, 8},
+ /* 192 */ {I_CMP, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40392, 0},
+ /* 193 */ {I_CMP, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47437, 8},
+ /* 194 */ {I_CMP, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+47437, 0},
+ /* 195 */ {I_CMP, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47442, 9},
+ /* 196 */ {I_CMP, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+47442, 5},
+ /* 197 */ {I_CMP, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+47447, 10},
+ /* 198 */ {I_CMP, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+47447, 7},
+ /* 199 */ {I_CMP, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42897, 0},
+ /* 200 */ {I_CMP, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42903, 5},
+ /* 201 */ {I_CMP, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42909, 7},
+ /* 202 */ {I_CMP, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49243, 8},
+ /* 203 */ {I_CMP, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47452, 8},
+ /* 204 */ {I_CMP, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47457, 9},
+ /* 205 */ {I_CMP, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47462, 10},
+ /* 206 */ {I_CMP, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47467, 8},
+ /* 207 */ {I_CMP, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42915, 8},
+ /* 208 */ {I_CMP, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42921, 9},
+ /* 209 */ {I_CMP, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+42927, 10},
+ /* 210 */ {I_CMP, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+47467, 8},
+ /* 211 */ {I_CMP, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42915, 8},
+ /* 212 */ {I_CMP, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42921, 9},
+ /* 213 */ {I_CMPSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49247, 0},
+ /* 214 */ {I_CMPSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47477, 5},
+ /* 215 */ {I_CMPSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47482, 7},
+ /* 216 */ {I_CMPSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47487, 0},
+ /* 217 */ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42933, 27},
+ /* 218 */ {I_CMPXCHG, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42934, 28},
+ /* 219 */ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33116, 27},
+ /* 220 */ {I_CMPXCHG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33117, 28},
+ /* 221 */ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33123, 27},
+ /* 222 */ {I_CMPXCHG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33124, 28},
+ /* 223 */ {I_CMPXCHG, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33130, 6},
+ /* 224 */ {I_CMPXCHG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33131, 7},
+ /* 225 */ {I_CMPXCHG8B, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+33137, 31},
+ /* 226 */ {I_CMPXCHG16B, 1, {MEMORY|BITS128,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42951, 13},
+ /* 227 */ {I_CPUID, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49251, 28},
+ /* 228 */ {I_CPU_READ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49255, 32},
+ /* 229 */ {I_CPU_WRITE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49259, 32},
+ /* 230 */ {I_CQO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49263, 7},
+ /* 231 */ {I_CWD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49267, 0},
+ /* 232 */ {I_CWDE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49271, 5},
+ /* 233 */ {I_DAA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50196, 1},
+ /* 234 */ {I_DAS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50199, 1},
+ /* 235 */ {I_DEC, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49275, 1},
+ /* 236 */ {I_DEC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49279, 19},
+ /* 237 */ {I_DEC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47497, 11},
+ /* 238 */ {I_DEC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42957, 11},
+ /* 239 */ {I_DEC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42963, 12},
+ /* 240 */ {I_DEC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42969, 13},
+ /* 241 */ {I_DIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49283, 0},
+ /* 242 */ {I_DIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47502, 0},
+ /* 243 */ {I_DIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47507, 5},
+ /* 244 */ {I_DIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47512, 7},
+ /* 245 */ {I_DMINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49287, 33},
+ /* 246 */ {I_EMMS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49291, 34},
+ /* 247 */ {I_ENTER, 2, {IMMEDIATE,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47517, 35},
+ /* 248 */ {I_EQU, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50228, 0},
+ /* 249 */ {I_EQU, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50228, 0},
+ /* 250 */ {I_F2XM1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49295, 36},
+ /* 251 */ {I_FABS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49299, 36},
+ /* 252 */ {I_FADD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49303, 36},
+ /* 253 */ {I_FADD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49307, 36},
+ /* 254 */ {I_FADD, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47522, 36},
+ /* 255 */ {I_FADD, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47527, 36},
+ /* 256 */ {I_FADD, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47522, 36},
+ /* 257 */ {I_FADD, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47532, 36},
+ /* 258 */ {I_FADDP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47537, 36},
+ /* 259 */ {I_FADDP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47537, 36},
+ /* 260 */ {I_FBLD, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49315, 36},
+ /* 261 */ {I_FBLD, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49315, 36},
+ /* 262 */ {I_FBSTP, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49319, 36},
+ /* 263 */ {I_FBSTP, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49319, 36},
+ /* 264 */ {I_FCHS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49323, 36},
+ /* 265 */ {I_FCLEX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47542, 36},
+ /* 266 */ {I_FCMOVB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47547, 37},
+ /* 267 */ {I_FCMOVB, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47552, 37},
+ /* 268 */ {I_FCMOVBE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47557, 37},
+ /* 269 */ {I_FCMOVBE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47562, 37},
+ /* 270 */ {I_FCMOVE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47567, 37},
+ /* 271 */ {I_FCMOVE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47572, 37},
+ /* 272 */ {I_FCMOVNB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47577, 37},
+ /* 273 */ {I_FCMOVNB, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47582, 37},
+ /* 274 */ {I_FCMOVNBE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47587, 37},
+ /* 275 */ {I_FCMOVNBE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47592, 37},
+ /* 276 */ {I_FCMOVNE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47597, 37},
+ /* 277 */ {I_FCMOVNE, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47602, 37},
+ /* 278 */ {I_FCMOVNU, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47607, 37},
+ /* 279 */ {I_FCMOVNU, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47612, 37},
+ /* 280 */ {I_FCMOVU, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47617, 37},
+ /* 281 */ {I_FCMOVU, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47622, 37},
+ /* 282 */ {I_FCOM, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49359, 36},
+ /* 283 */ {I_FCOM, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49363, 36},
+ /* 284 */ {I_FCOM, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47627, 36},
+ /* 285 */ {I_FCOM, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47632, 36},
+ /* 286 */ {I_FCOMI, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47637, 37},
+ /* 287 */ {I_FCOMI, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47642, 37},
+ /* 288 */ {I_FCOMIP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47647, 37},
+ /* 289 */ {I_FCOMIP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47652, 37},
+ /* 290 */ {I_FCOMP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49379, 36},
+ /* 291 */ {I_FCOMP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49383, 36},
+ /* 292 */ {I_FCOMP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47657, 36},
+ /* 293 */ {I_FCOMP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47662, 36},
+ /* 294 */ {I_FCOMPP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49391, 36},
+ /* 295 */ {I_FCOS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49395, 38},
+ /* 296 */ {I_FDECSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49399, 36},
+ /* 297 */ {I_FDISI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47667, 36},
+ /* 298 */ {I_FDIV, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49403, 36},
+ /* 299 */ {I_FDIV, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49407, 36},
+ /* 300 */ {I_FDIV, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47672, 36},
+ /* 301 */ {I_FDIV, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47677, 36},
+ /* 302 */ {I_FDIV, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47672, 36},
+ /* 303 */ {I_FDIV, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47682, 36},
+ /* 304 */ {I_FDIVP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47687, 36},
+ /* 305 */ {I_FDIVP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47687, 36},
+ /* 306 */ {I_FDIVR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49415, 36},
+ /* 307 */ {I_FDIVR, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49419, 36},
+ /* 308 */ {I_FDIVR, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47692, 36},
+ /* 309 */ {I_FDIVR, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47692, 36},
+ /* 310 */ {I_FDIVR, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47697, 36},
+ /* 311 */ {I_FDIVR, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47702, 36},
+ /* 312 */ {I_FDIVRP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47707, 36},
+ /* 313 */ {I_FDIVRP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47707, 36},
+ /* 314 */ {I_FEMMS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49427, 39},
+ /* 315 */ {I_FENI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47712, 36},
+ /* 316 */ {I_FFREE, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47717, 36},
+ /* 317 */ {I_FFREE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49431, 36},
+ /* 318 */ {I_FFREEP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47722, 40},
+ /* 319 */ {I_FFREEP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49435, 40},
+ /* 320 */ {I_FIADD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49439, 36},
+ /* 321 */ {I_FIADD, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49443, 36},
+ /* 322 */ {I_FICOM, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49447, 36},
+ /* 323 */ {I_FICOM, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49451, 36},
+ /* 324 */ {I_FICOMP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49455, 36},
+ /* 325 */ {I_FICOMP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49459, 36},
+ /* 326 */ {I_FIDIV, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49463, 36},
+ /* 327 */ {I_FIDIV, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49467, 36},
+ /* 328 */ {I_FIDIVR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49471, 36},
+ /* 329 */ {I_FIDIVR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49475, 36},
+ /* 330 */ {I_FILD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49479, 36},
+ /* 331 */ {I_FILD, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49483, 36},
+ /* 332 */ {I_FILD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49487, 36},
+ /* 333 */ {I_FIMUL, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49491, 36},
+ /* 334 */ {I_FIMUL, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49495, 36},
+ /* 335 */ {I_FINCSTP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49499, 36},
+ /* 336 */ {I_FINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47727, 36},
+ /* 337 */ {I_FIST, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49503, 36},
+ /* 338 */ {I_FIST, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49507, 36},
+ /* 339 */ {I_FISTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49511, 36},
+ /* 340 */ {I_FISTP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49515, 36},
+ /* 341 */ {I_FISTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49519, 36},
+ /* 342 */ {I_FISTTP, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49523, 41},
+ /* 343 */ {I_FISTTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49527, 41},
+ /* 344 */ {I_FISTTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49531, 41},
+ /* 345 */ {I_FISUB, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49535, 36},
+ /* 346 */ {I_FISUB, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49539, 36},
+ /* 347 */ {I_FISUBR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49543, 36},
+ /* 348 */ {I_FISUBR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49547, 36},
+ /* 349 */ {I_FLD, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49551, 36},
+ /* 350 */ {I_FLD, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49555, 36},
+ /* 351 */ {I_FLD, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49559, 36},
+ /* 352 */ {I_FLD, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47732, 36},
+ /* 353 */ {I_FLD1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49567, 36},
+ /* 354 */ {I_FLDCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49571, 42},
+ /* 355 */ {I_FLDENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49575, 36},
+ /* 356 */ {I_FLDL2E, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49579, 36},
+ /* 357 */ {I_FLDL2T, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49583, 36},
+ /* 358 */ {I_FLDLG2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49587, 36},
+ /* 359 */ {I_FLDLN2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49591, 36},
+ /* 360 */ {I_FLDPI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49595, 36},
+ /* 361 */ {I_FLDZ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49599, 36},
+ /* 362 */ {I_FMUL, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49603, 36},
+ /* 363 */ {I_FMUL, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49607, 36},
+ /* 364 */ {I_FMUL, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47737, 36},
+ /* 365 */ {I_FMUL, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47737, 36},
+ /* 366 */ {I_FMUL, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47742, 36},
+ /* 367 */ {I_FMUL, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47747, 36},
+ /* 368 */ {I_FMULP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47752, 36},
+ /* 369 */ {I_FMULP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47752, 36},
+ /* 370 */ {I_FNCLEX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47543, 36},
+ /* 371 */ {I_FNDISI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47668, 36},
+ /* 372 */ {I_FNENI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47713, 36},
+ /* 373 */ {I_FNINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47728, 36},
+ /* 374 */ {I_FNOP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49615, 36},
+ /* 375 */ {I_FNSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47758, 36},
+ /* 376 */ {I_FNSTCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47768, 42},
+ /* 377 */ {I_FNSTENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47773, 36},
+ /* 378 */ {I_FNSTSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47783, 42},
+ /* 379 */ {I_FNSTSW, 1, {REG_AX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47788, 43},
+ /* 380 */ {I_FPATAN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49619, 36},
+ /* 381 */ {I_FPREM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49623, 36},
+ /* 382 */ {I_FPREM1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49627, 38},
+ /* 383 */ {I_FPTAN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49631, 36},
+ /* 384 */ {I_FRNDINT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49635, 36},
+ /* 385 */ {I_FRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49639, 36},
+ /* 386 */ {I_FSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47757, 36},
+ /* 387 */ {I_FSCALE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49643, 36},
+ /* 388 */ {I_FSETPM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49647, 43},
+ /* 389 */ {I_FSIN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49651, 38},
+ /* 390 */ {I_FSINCOS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49655, 38},
+ /* 391 */ {I_FSQRT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49659, 36},
+ /* 392 */ {I_FST, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49663, 36},
+ /* 393 */ {I_FST, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49667, 36},
+ /* 394 */ {I_FST, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47762, 36},
+ /* 395 */ {I_FSTCW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47767, 42},
+ /* 396 */ {I_FSTENV, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47772, 36},
+ /* 397 */ {I_FSTP, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49675, 36},
+ /* 398 */ {I_FSTP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49679, 36},
+ /* 399 */ {I_FSTP, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49683, 36},
+ /* 400 */ {I_FSTP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47777, 36},
+ /* 401 */ {I_FSTSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47782, 42},
+ /* 402 */ {I_FSTSW, 1, {REG_AX,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47787, 43},
+ /* 403 */ {I_FSUB, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49691, 36},
+ /* 404 */ {I_FSUB, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49695, 36},
+ /* 405 */ {I_FSUB, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47792, 36},
+ /* 406 */ {I_FSUB, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47792, 36},
+ /* 407 */ {I_FSUB, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47797, 36},
+ /* 408 */ {I_FSUB, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47802, 36},
+ /* 409 */ {I_FSUBP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47807, 36},
+ /* 410 */ {I_FSUBP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47807, 36},
+ /* 411 */ {I_FSUBR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49703, 36},
+ /* 412 */ {I_FSUBR, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49707, 36},
+ /* 413 */ {I_FSUBR, 1, {FPUREG|TO,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47812, 36},
+ /* 414 */ {I_FSUBR, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47812, 36},
+ /* 415 */ {I_FSUBR, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47817, 36},
+ /* 416 */ {I_FSUBR, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47822, 36},
+ /* 417 */ {I_FSUBRP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47827, 36},
+ /* 418 */ {I_FSUBRP, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47827, 36},
+ /* 419 */ {I_FTST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49715, 36},
+ /* 420 */ {I_FUCOM, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47832, 38},
+ /* 421 */ {I_FUCOM, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47837, 38},
+ /* 422 */ {I_FUCOMI, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47842, 37},
+ /* 423 */ {I_FUCOMI, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47847, 37},
+ /* 424 */ {I_FUCOMIP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47852, 37},
+ /* 425 */ {I_FUCOMIP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47857, 37},
+ /* 426 */ {I_FUCOMP, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47862, 38},
+ /* 427 */ {I_FUCOMP, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47867, 38},
+ /* 428 */ {I_FUCOMPP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49735, 38},
+ /* 429 */ {I_FXAM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49739, 36},
+ /* 430 */ {I_FXCH, 1, {FPUREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47872, 36},
+ /* 431 */ {I_FXCH, 2, {FPUREG,FPU0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47872, 36},
+ /* 432 */ {I_FXCH, 2, {FPU0,FPUREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+47877, 36},
+ /* 433 */ {I_FXTRACT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49747, 36},
+ /* 434 */ {I_FYL2X, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49751, 36},
+ /* 435 */ {I_FYL2XP1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49755, 36},
+ /* 436 */ {I_HLT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50202, 44},
+ /* 437 */ {I_IDIV, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49759, 0},
+ /* 438 */ {I_IDIV, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47882, 0},
+ /* 439 */ {I_IDIV, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47887, 5},
+ /* 440 */ {I_IDIV, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47892, 7},
+ /* 441 */ {I_IMUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49763, 0},
+ /* 442 */ {I_IMUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47897, 0},
+ /* 443 */ {I_IMUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47902, 5},
+ /* 444 */ {I_IMUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47907, 7},
+ /* 445 */ {I_IMUL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42975, 9},
+ /* 446 */ {I_IMUL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42975, 5},
+ /* 447 */ {I_IMUL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42981, 9},
+ /* 448 */ {I_IMUL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42981, 5},
+ /* 449 */ {I_IMUL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42987, 10},
+ /* 450 */ {I_IMUL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42987, 7},
+ /* 451 */ {I_IMUL, 3, {REG_GPR|BITS16,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+42993, 48},
+ /* 452 */ {I_IMUL, 3, {REG_GPR|BITS16,MEMORY,IMMEDIATE|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+42999, 49},
+ /* 453 */ {I_IMUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+42993, 35},
+ /* 454 */ {I_IMUL, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE|BITS16,0,0}, NO_DECORATOR, nasm_bytecodes+42999, 35},
+ /* 455 */ {I_IMUL, 3, {REG_GPR|BITS32,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43005, 50},
+ /* 456 */ {I_IMUL, 3, {REG_GPR|BITS32,MEMORY,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43011, 9},
+ /* 457 */ {I_IMUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43005, 5},
+ /* 458 */ {I_IMUL, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43011, 5},
+ /* 459 */ {I_IMUL, 3, {REG_GPR|BITS64,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43017, 51},
+ /* 460 */ {I_IMUL, 3, {REG_GPR|BITS64,MEMORY,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43023, 51},
+ /* 461 */ {I_IMUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+43017, 7},
+ /* 462 */ {I_IMUL, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+43023, 7},
+ /* 463 */ {I_IMUL, 2, {REG_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43035, 35},
+ /* 464 */ {I_IMUL, 2, {REG_GPR|BITS16,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43041, 35},
+ /* 465 */ {I_IMUL, 2, {REG_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43047, 5},
+ /* 466 */ {I_IMUL, 2, {REG_GPR|BITS32,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43053, 5},
+ /* 467 */ {I_IMUL, 2, {REG_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43059, 7},
+ /* 468 */ {I_IMUL, 2, {REG_GPR|BITS64,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43065, 7},
+ /* 469 */ {I_IN, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49767, 52},
+ /* 470 */ {I_IN, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47912, 52},
+ /* 471 */ {I_IN, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+47917, 53},
+ /* 472 */ {I_IN, 2, {REG_AL,REG_DX,0,0,0}, NO_DECORATOR, nasm_bytecodes+46092, 0},
+ /* 473 */ {I_IN, 2, {REG_AX,REG_DX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49771, 0},
+ /* 474 */ {I_IN, 2, {REG_EAX,REG_DX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49775, 5},
+ /* 475 */ {I_INC, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49779, 1},
+ /* 476 */ {I_INC, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49783, 19},
+ /* 477 */ {I_INC, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47922, 11},
+ /* 478 */ {I_INC, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43071, 11},
+ /* 479 */ {I_INC, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43077, 12},
+ /* 480 */ {I_INC, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43083, 13},
+ /* 481 */ {I_INSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50208, 35},
+ /* 482 */ {I_INSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49787, 5},
+ /* 483 */ {I_INSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49791, 35},
+ /* 484 */ {I_INT, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49795, 52},
+ /* 485 */ {I_INT1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50205, 5},
+ /* 486 */ {I_INT3, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50211, 0},
+ /* 487 */ {I_INTO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50214, 1},
+ /* 488 */ {I_INVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49799, 54},
+ /* 489 */ {I_INVPCID, 2, {REG_GPR|BITS32,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+33144, 55},
+ /* 490 */ {I_INVPCID, 2, {REG_GPR|BITS64,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+33144, 56},
+ /* 491 */ {I_INVLPG, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47927, 54},
+ /* 492 */ {I_INVLPGA, 2, {REG_AX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43089, 57},
+ /* 493 */ {I_INVLPGA, 2, {REG_EAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43095, 58},
+ /* 494 */ {I_INVLPGA, 2, {REG_RAX,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33151, 59},
+ /* 495 */ {I_INVLPGA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43096, 58},
+ /* 496 */ {I_IRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49803, 0},
+ /* 497 */ {I_IRETD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49807, 5},
+ /* 498 */ {I_IRETQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49811, 7},
+ /* 499 */ {I_IRETW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49815, 0},
+ /* 500 */ {I_JCXZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47932, 1},
+ /* 501 */ {I_JECXZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47937, 5},
+ /* 502 */ {I_JRCXZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43101, 7},
+ /* 503 */ {I_JMP, 1, {IMMEDIATE|SHORT,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47943, 0},
+ /* 504 */ {I_JMP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47947, 21},
+ /* 505 */ {I_JMP, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47952, 22},
+ /* 506 */ {I_JMP, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47957, 23},
+ /* 507 */ {I_JMP, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47962, 24},
+ /* 508 */ {I_JMP, 2, {IMMEDIATE|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43125, 1},
+ /* 509 */ {I_JMP, 2, {IMMEDIATE|BITS16|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43131, 1},
+ /* 510 */ {I_JMP, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43131, 1},
+ /* 511 */ {I_JMP, 2, {IMMEDIATE|BITS32|COLON,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43137, 19},
+ /* 512 */ {I_JMP, 2, {IMMEDIATE|COLON,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43137, 19},
+ /* 513 */ {I_JMP, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47967, 1},
+ /* 514 */ {I_JMP, 1, {MEMORY|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47972, 7},
+ /* 515 */ {I_JMP, 1, {MEMORY|BITS16|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47977, 0},
+ /* 516 */ {I_JMP, 1, {MEMORY|BITS32|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47982, 5},
+ /* 517 */ {I_JMP, 1, {MEMORY|BITS64|FAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47972, 7},
+ /* 518 */ {I_JMP, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47987, 21},
+ /* 519 */ {I_JMP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47992, 22},
+ /* 520 */ {I_JMP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47997, 23},
+ /* 521 */ {I_JMP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48002, 24},
+ /* 522 */ {I_JMPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43143, 60},
+ /* 523 */ {I_JMPE, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43149, 60},
+ /* 524 */ {I_JMPE, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43155, 60},
+ /* 525 */ {I_JMPE, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43161, 60},
+ /* 526 */ {I_JMPE, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43167, 60},
+ /* 527 */ {I_LAHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50217, 0},
+ /* 528 */ {I_LAR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43173, 61},
+ /* 529 */ {I_LAR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43173, 62},
+ /* 530 */ {I_LAR, 2, {REG_GPR|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43173, 63},
+ /* 531 */ {I_LAR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43179, 65},
+ /* 532 */ {I_LAR, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43179, 63},
+ /* 533 */ {I_LAR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43179, 63},
+ /* 534 */ {I_LAR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 66},
+ /* 535 */ {I_LAR, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 64},
+ /* 536 */ {I_LAR, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 64},
+ /* 537 */ {I_LAR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43185, 64},
+ /* 538 */ {I_LDS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48007, 1},
+ /* 539 */ {I_LDS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48012, 19},
+ /* 540 */ {I_LEA, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48017, 67},
+ /* 541 */ {I_LEA, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48022, 68},
+ /* 542 */ {I_LEA, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48027, 69},
+ /* 543 */ {I_LEAVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48279, 35},
+ /* 544 */ {I_LES, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48032, 1},
+ /* 545 */ {I_LES, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48037, 19},
+ /* 546 */ {I_LFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43191, 59},
+ /* 547 */ {I_LFS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43197, 5},
+ /* 548 */ {I_LFS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43203, 5},
+ /* 549 */ {I_LFS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43209, 7},
+ /* 550 */ {I_LGDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48042, 25},
+ /* 551 */ {I_LGS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43215, 5},
+ /* 552 */ {I_LGS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43221, 5},
+ /* 553 */ {I_LGS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43227, 7},
+ /* 554 */ {I_LIDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48047, 25},
+ /* 555 */ {I_LLDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48052, 70},
+ /* 556 */ {I_LLDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48052, 70},
+ /* 557 */ {I_LLDT, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48052, 70},
+ /* 558 */ {I_LMSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48057, 25},
+ /* 559 */ {I_LMSW, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48057, 25},
+ /* 560 */ {I_LMSW, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48057, 25},
+ /* 561 */ {I_LODSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50220, 0},
+ /* 562 */ {I_LODSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49827, 5},
+ /* 563 */ {I_LODSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49831, 7},
+ /* 564 */ {I_LODSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49835, 0},
+ /* 565 */ {I_LOOP, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48062, 0},
+ /* 566 */ {I_LOOP, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48067, 1},
+ /* 567 */ {I_LOOP, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48072, 5},
+ /* 568 */ {I_LOOP, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48077, 7},
+ /* 569 */ {I_LOOPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48082, 0},
+ /* 570 */ {I_LOOPE, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48087, 1},
+ /* 571 */ {I_LOOPE, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48092, 5},
+ /* 572 */ {I_LOOPE, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48097, 7},
+ /* 573 */ {I_LOOPNE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48102, 0},
+ /* 574 */ {I_LOOPNE, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48107, 1},
+ /* 575 */ {I_LOOPNE, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48112, 5},
+ /* 576 */ {I_LOOPNE, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48117, 7},
+ /* 577 */ {I_LOOPNZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48102, 0},
+ /* 578 */ {I_LOOPNZ, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48107, 1},
+ /* 579 */ {I_LOOPNZ, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48112, 5},
+ /* 580 */ {I_LOOPNZ, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48117, 7},
+ /* 581 */ {I_LOOPZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48082, 0},
+ /* 582 */ {I_LOOPZ, 2, {IMMEDIATE,REG_CX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48087, 1},
+ /* 583 */ {I_LOOPZ, 2, {IMMEDIATE,REG_ECX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48092, 5},
+ /* 584 */ {I_LOOPZ, 2, {IMMEDIATE,REG_RCX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48097, 7},
+ /* 585 */ {I_LSL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43233, 61},
+ /* 586 */ {I_LSL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43233, 62},
+ /* 587 */ {I_LSL, 2, {REG_GPR|BITS16,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43233, 63},
+ /* 588 */ {I_LSL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43239, 65},
+ /* 589 */ {I_LSL, 2, {REG_GPR|BITS32,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43239, 63},
+ /* 590 */ {I_LSL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43239, 63},
+ /* 591 */ {I_LSL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 66},
+ /* 592 */ {I_LSL, 2, {REG_GPR|BITS64,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 64},
+ /* 593 */ {I_LSL, 2, {REG_GPR|BITS64,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 64},
+ /* 594 */ {I_LSL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43245, 64},
+ /* 595 */ {I_LSS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43251, 5},
+ /* 596 */ {I_LSS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43257, 5},
+ /* 597 */ {I_LSS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43263, 7},
+ /* 598 */ {I_LTR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48122, 70},
+ /* 599 */ {I_LTR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48122, 70},
+ /* 600 */ {I_LTR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48122, 70},
+ /* 601 */ {I_MFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43269, 59},
+ /* 602 */ {I_MONITOR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48127, 72},
+ /* 603 */ {I_MONITORX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48132, 74},
+ /* 604 */ {I_MOV, 2, {MEMORY,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48153, 75},
+ /* 605 */ {I_MOV, 2, {REG_GPR|BITS16,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48137, 0},
+ /* 606 */ {I_MOV, 2, {REG_GPR|BITS32,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48142, 5},
+ /* 607 */ {I_MOV, 2, {RM_GPR|BITS64,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+48152, 7},
+ /* 608 */ {I_MOV, 2, {REG_SREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48173, 75},
+ /* 609 */ {I_MOV, 2, {REG_SREG,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48162, 0},
+ /* 610 */ {I_MOV, 2, {REG_SREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48167, 5},
+ /* 611 */ {I_MOV, 2, {REG_SREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48172, 7},
+ /* 612 */ {I_MOV, 2, {REG_AL,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+49839, 8},
+ /* 613 */ {I_MOV, 2, {REG_AX,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+48177, 8},
+ /* 614 */ {I_MOV, 2, {REG_EAX,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+48182, 9},
+ /* 615 */ {I_MOV, 2, {REG_RAX,MEM_OFFS,0,0,0}, NO_DECORATOR, nasm_bytecodes+48187, 10},
+ /* 616 */ {I_MOV, 2, {MEM_OFFS,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49843, 79},
+ /* 617 */ {I_MOV, 2, {MEM_OFFS,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48192, 79},
+ /* 618 */ {I_MOV, 2, {MEM_OFFS,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48197, 80},
+ /* 619 */ {I_MOV, 2, {MEM_OFFS,REG_RAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48202, 81},
+ /* 620 */ {I_MOV, 2, {REG_GPR|BITS32,REG_CREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43275, 82},
+ /* 621 */ {I_MOV, 2, {REG_GPR|BITS64,REG_CREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43281, 83},
+ /* 622 */ {I_MOV, 2, {REG_CREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43287, 82},
+ /* 623 */ {I_MOV, 2, {REG_CREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43293, 83},
+ /* 624 */ {I_MOV, 2, {REG_GPR|BITS32,REG_DREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43300, 82},
+ /* 625 */ {I_MOV, 2, {REG_GPR|BITS64,REG_DREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43299, 83},
+ /* 626 */ {I_MOV, 2, {REG_DREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43306, 82},
+ /* 627 */ {I_MOV, 2, {REG_DREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43305, 83},
+ /* 628 */ {I_MOV, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48217, 8},
+ /* 629 */ {I_MOV, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48218, 0},
+ /* 630 */ {I_MOV, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43311, 8},
+ /* 631 */ {I_MOV, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43312, 0},
+ /* 632 */ {I_MOV, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43317, 9},
+ /* 633 */ {I_MOV, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43318, 5},
+ /* 634 */ {I_MOV, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43323, 10},
+ /* 635 */ {I_MOV, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43324, 7},
+ /* 636 */ {I_MOV, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+49847, 8},
+ /* 637 */ {I_MOV, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+49847, 0},
+ /* 638 */ {I_MOV, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48222, 8},
+ /* 639 */ {I_MOV, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48222, 0},
+ /* 640 */ {I_MOV, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48227, 9},
+ /* 641 */ {I_MOV, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48227, 5},
+ /* 642 */ {I_MOV, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48232, 10},
+ /* 643 */ {I_MOV, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48232, 7},
+ /* 644 */ {I_MOV, 2, {REG_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49851, 8},
+ /* 645 */ {I_MOV, 2, {REG_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48237, 8},
+ /* 646 */ {I_MOV, 2, {REG_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48242, 9},
+ /* 647 */ {I_MOV, 2, {REG_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48252, 10},
+ /* 648 */ {I_MOV, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43329, 8},
+ /* 649 */ {I_MOV, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33186, 8},
+ /* 650 */ {I_MOV, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33193, 9},
+ /* 651 */ {I_MOV, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33200, 10},
+ /* 652 */ {I_MOV, 2, {RM_GPR|BITS64,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33200, 7},
+ /* 653 */ {I_MOV, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43329, 8},
+ /* 654 */ {I_MOV, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33186, 8},
+ /* 655 */ {I_MOV, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33193, 9},
+ /* 656 */ {I_MOVD, 2, {MMXREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43335, 85},
+ /* 657 */ {I_MOVD, 2, {RM_GPR|BITS32,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43341, 85},
+ /* 658 */ {I_MOVQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43347, 87},
+ /* 659 */ {I_MOVQ, 2, {RM_MMX,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+43353, 87},
+ /* 660 */ {I_MOVQ, 2, {MMXREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33207, 88},
+ /* 661 */ {I_MOVQ, 2, {RM_GPR|BITS64,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+33214, 88},
+ /* 662 */ {I_MOVSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12437, 0},
+ /* 663 */ {I_MOVSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49855, 5},
+ /* 664 */ {I_MOVSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49859, 7},
+ /* 665 */ {I_MOVSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49863, 0},
+ /* 666 */ {I_MOVSX, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43359, 53},
+ /* 667 */ {I_MOVSX, 2, {REG_GPR|BITS16,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43359, 5},
+ /* 668 */ {I_MOVSX, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43365, 5},
+ /* 669 */ {I_MOVSX, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43371, 5},
+ /* 670 */ {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43377, 7},
+ /* 671 */ {I_MOVSX, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43383, 7},
+ /* 672 */ {I_MOVSXD, 2, {REG_GPR|BITS64,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48257, 7},
+ /* 673 */ {I_MOVZX, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43389, 53},
+ /* 674 */ {I_MOVZX, 2, {REG_GPR|BITS16,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43389, 5},
+ /* 675 */ {I_MOVZX, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43395, 5},
+ /* 676 */ {I_MOVZX, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43401, 5},
+ /* 677 */ {I_MOVZX, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43407, 7},
+ /* 678 */ {I_MOVZX, 2, {REG_GPR|BITS64,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43413, 7},
+ /* 679 */ {I_MUL, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49867, 0},
+ /* 680 */ {I_MUL, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48262, 0},
+ /* 681 */ {I_MUL, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48267, 5},
+ /* 682 */ {I_MUL, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48272, 7},
+ /* 683 */ {I_MWAIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48277, 72},
+ /* 684 */ {I_MWAITX, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48282, 74},
+ /* 685 */ {I_NEG, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48287, 11},
+ /* 686 */ {I_NEG, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43419, 11},
+ /* 687 */ {I_NEG, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43425, 12},
+ /* 688 */ {I_NEG, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43431, 13},
+ /* 689 */ {I_NOP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48292, 0},
+ /* 690 */ {I_NOP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43437, 89},
+ /* 691 */ {I_NOP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43443, 89},
+ /* 692 */ {I_NOP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43449, 7},
+ /* 693 */ {I_NOT, 1, {RM_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48297, 11},
+ /* 694 */ {I_NOT, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43455, 11},
+ /* 695 */ {I_NOT, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43461, 12},
+ /* 696 */ {I_NOT, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43467, 13},
+ /* 697 */ {I_OR, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48302, 3},
+ /* 698 */ {I_OR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48303, 0},
+ /* 699 */ {I_OR, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43473, 3},
+ /* 700 */ {I_OR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43474, 0},
+ /* 701 */ {I_OR, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43479, 4},
+ /* 702 */ {I_OR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43480, 5},
+ /* 703 */ {I_OR, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43485, 6},
+ /* 704 */ {I_OR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43486, 7},
+ /* 705 */ {I_OR, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40679, 8},
+ /* 706 */ {I_OR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40679, 0},
+ /* 707 */ {I_OR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48307, 8},
+ /* 708 */ {I_OR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48307, 0},
+ /* 709 */ {I_OR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48312, 9},
+ /* 710 */ {I_OR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48312, 5},
+ /* 711 */ {I_OR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48317, 10},
+ /* 712 */ {I_OR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48317, 7},
+ /* 713 */ {I_OR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33221, 11},
+ /* 714 */ {I_OR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33228, 12},
+ /* 715 */ {I_OR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33235, 13},
+ /* 716 */ {I_OR, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+49871, 8},
+ /* 717 */ {I_OR, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48322, 8},
+ /* 718 */ {I_OR, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48327, 9},
+ /* 719 */ {I_OR, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48332, 10},
+ /* 720 */ {I_OR, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43491, 3},
+ /* 721 */ {I_OR, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33242, 3},
+ /* 722 */ {I_OR, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33249, 4},
+ /* 723 */ {I_OR, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33256, 6},
+ /* 724 */ {I_OR, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43491, 3},
+ /* 725 */ {I_OR, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33242, 3},
+ /* 726 */ {I_OR, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33249, 4},
+ /* 727 */ {I_OUT, 2, {IMMEDIATE,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49875, 52},
+ /* 728 */ {I_OUT, 2, {IMMEDIATE,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48337, 52},
+ /* 729 */ {I_OUT, 2, {IMMEDIATE,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+48342, 53},
+ /* 730 */ {I_OUT, 2, {REG_DX,REG_AL,0,0,0}, NO_DECORATOR, nasm_bytecodes+46074, 0},
+ /* 731 */ {I_OUT, 2, {REG_DX,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49879, 0},
+ /* 732 */ {I_OUT, 2, {REG_DX,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+49883, 5},
+ /* 733 */ {I_OUTSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50223, 35},
+ /* 734 */ {I_OUTSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49887, 5},
+ /* 735 */ {I_OUTSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49891, 35},
+ /* 736 */ {I_PACKSSDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33263, 87},
+ /* 737 */ {I_PACKSSWB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33270, 87},
+ /* 738 */ {I_PACKUSWB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33277, 87},
+ /* 739 */ {I_PADDB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33284, 87},
+ /* 740 */ {I_PADDD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33291, 87},
+ /* 741 */ {I_PADDSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33298, 87},
+ /* 742 */ {I_PADDSIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43503, 90},
+ /* 743 */ {I_PADDSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33305, 87},
+ /* 744 */ {I_PADDUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33312, 87},
+ /* 745 */ {I_PADDUSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33319, 87},
+ /* 746 */ {I_PADDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33326, 87},
+ /* 747 */ {I_PAND, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33333, 87},
+ /* 748 */ {I_PANDN, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33340, 87},
+ /* 749 */ {I_PAUSE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49895, 0},
+ /* 750 */ {I_PAVEB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43509, 90},
+ /* 751 */ {I_PAVGUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12376, 91},
+ /* 752 */ {I_PCMPEQB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33347, 87},
+ /* 753 */ {I_PCMPEQD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33354, 87},
+ /* 754 */ {I_PCMPEQW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33361, 87},
+ /* 755 */ {I_PCMPGTB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33368, 87},
+ /* 756 */ {I_PCMPGTD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33375, 87},
+ /* 757 */ {I_PCMPGTW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33382, 87},
+ /* 758 */ {I_PDISTIB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45376, 92},
+ /* 759 */ {I_PF2ID, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12384, 91},
+ /* 760 */ {I_PFACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12392, 91},
+ /* 761 */ {I_PFADD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12400, 91},
+ /* 762 */ {I_PFCMPEQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12408, 91},
+ /* 763 */ {I_PFCMPGE, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12416, 91},
+ /* 764 */ {I_PFCMPGT, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12424, 91},
+ /* 765 */ {I_PFMAX, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12432, 91},
+ /* 766 */ {I_PFMIN, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12440, 91},
+ /* 767 */ {I_PFMUL, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12448, 91},
+ /* 768 */ {I_PFRCP, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12456, 91},
+ /* 769 */ {I_PFRCPIT1, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12464, 91},
+ /* 770 */ {I_PFRCPIT2, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12472, 91},
+ /* 771 */ {I_PFRSQIT1, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12480, 91},
+ /* 772 */ {I_PFRSQRT, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12488, 91},
+ /* 773 */ {I_PFSUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12496, 91},
+ /* 774 */ {I_PFSUBR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12504, 91},
+ /* 775 */ {I_PI2FD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12512, 91},
+ /* 776 */ {I_PMACHRIW, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45472, 92},
+ /* 777 */ {I_PMADDWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33389, 87},
+ /* 778 */ {I_PMAGW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43515, 90},
+ /* 779 */ {I_PMULHRIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43521, 90},
+ /* 780 */ {I_PMULHRWA, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12520, 91},
+ /* 781 */ {I_PMULHRWC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43527, 90},
+ /* 782 */ {I_PMULHW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33396, 87},
+ /* 783 */ {I_PMULLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33403, 87},
+ /* 784 */ {I_PMVGEZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45604, 90},
+ /* 785 */ {I_PMVLZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45460, 90},
+ /* 786 */ {I_PMVNZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45442, 90},
+ /* 787 */ {I_PMVZB, 2, {MMXREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45364, 90},
+ /* 788 */ {I_POP, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49899, 0},
+ /* 789 */ {I_POP, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49903, 19},
+ /* 790 */ {I_POP, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49907, 7},
+ /* 791 */ {I_POP, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48347, 0},
+ /* 792 */ {I_POP, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48352, 19},
+ /* 793 */ {I_POP, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48357, 7},
+ /* 794 */ {I_POP, 1, {REG_ES,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12813, 1},
+ /* 795 */ {I_POP, 1, {REG_SS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7621, 1},
+ /* 796 */ {I_POP, 1, {REG_DS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7765, 1},
+ /* 797 */ {I_POP, 1, {REG_FS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49911, 5},
+ /* 798 */ {I_POP, 1, {REG_GS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49915, 5},
+ /* 799 */ {I_POPA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49919, 18},
+ /* 800 */ {I_POPAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49923, 19},
+ /* 801 */ {I_POPAW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49927, 18},
+ /* 802 */ {I_POPF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49931, 0},
+ /* 803 */ {I_POPFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49935, 19},
+ /* 804 */ {I_POPFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49935, 7},
+ /* 805 */ {I_POPFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49939, 0},
+ /* 806 */ {I_POR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33410, 87},
+ /* 807 */ {I_PREFETCH, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48362, 91},
+ /* 808 */ {I_PREFETCHW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48367, 91},
+ /* 809 */ {I_PSLLD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33417, 87},
+ /* 810 */ {I_PSLLD, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33424, 34},
+ /* 811 */ {I_PSLLQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33431, 87},
+ /* 812 */ {I_PSLLQ, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33438, 34},
+ /* 813 */ {I_PSLLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33445, 87},
+ /* 814 */ {I_PSLLW, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33452, 34},
+ /* 815 */ {I_PSRAD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33459, 87},
+ /* 816 */ {I_PSRAD, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33466, 34},
+ /* 817 */ {I_PSRAW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33473, 87},
+ /* 818 */ {I_PSRAW, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33480, 34},
+ /* 819 */ {I_PSRLD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33487, 87},
+ /* 820 */ {I_PSRLD, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33494, 34},
+ /* 821 */ {I_PSRLQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33501, 87},
+ /* 822 */ {I_PSRLQ, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33508, 34},
+ /* 823 */ {I_PSRLW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33515, 87},
+ /* 824 */ {I_PSRLW, 2, {MMXREG,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33522, 34},
+ /* 825 */ {I_PSUBB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33529, 87},
+ /* 826 */ {I_PSUBD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33536, 87},
+ /* 827 */ {I_PSUBSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33543, 87},
+ /* 828 */ {I_PSUBSIW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+43533, 90},
+ /* 829 */ {I_PSUBSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33550, 87},
+ /* 830 */ {I_PSUBUSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33557, 87},
+ /* 831 */ {I_PSUBUSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33564, 87},
+ /* 832 */ {I_PSUBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33571, 87},
+ /* 833 */ {I_PUNPCKHBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33578, 87},
+ /* 834 */ {I_PUNPCKHDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33585, 87},
+ /* 835 */ {I_PUNPCKHWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33592, 87},
+ /* 836 */ {I_PUNPCKLBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33599, 87},
+ /* 837 */ {I_PUNPCKLDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33606, 87},
+ /* 838 */ {I_PUNPCKLWD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33613, 87},
+ /* 839 */ {I_PUSH, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49943, 0},
+ /* 840 */ {I_PUSH, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49947, 19},
+ /* 841 */ {I_PUSH, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49951, 7},
+ /* 842 */ {I_PUSH, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48372, 0},
+ /* 843 */ {I_PUSH, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48377, 19},
+ /* 844 */ {I_PUSH, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48382, 7},
+ /* 845 */ {I_PUSH, 1, {REG_ES,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12781, 1},
+ /* 846 */ {I_PUSH, 1, {REG_CS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7477, 1},
+ /* 847 */ {I_PUSH, 1, {REG_SS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7603, 1},
+ /* 848 */ {I_PUSH, 1, {REG_DS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+7747, 1},
+ /* 849 */ {I_PUSH, 1, {REG_FS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49955, 5},
+ /* 850 */ {I_PUSH, 1, {REG_GS,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49959, 5},
+ /* 851 */ {I_PUSH, 1, {IMMEDIATE|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48408, 35},
+ /* 852 */ {I_PUSH, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48392, 94},
+ /* 853 */ {I_PUSH, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48402, 95},
+ /* 854 */ {I_PUSH, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48402, 96},
+ /* 855 */ {I_PUSH, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48412, 97},
+ /* 856 */ {I_PUSH, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48412, 97},
+ /* 857 */ {I_PUSHA, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49963, 18},
+ /* 858 */ {I_PUSHAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49967, 19},
+ /* 859 */ {I_PUSHAW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49971, 18},
+ /* 860 */ {I_PUSHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49975, 0},
+ /* 861 */ {I_PUSHFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49979, 19},
+ /* 862 */ {I_PUSHFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49979, 7},
+ /* 863 */ {I_PUSHFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49983, 0},
+ /* 864 */ {I_PXOR, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+33620, 87},
+ /* 865 */ {I_RCL, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+49987, 0},
+ /* 866 */ {I_RCL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49991, 0},
+ /* 867 */ {I_RCL, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48417, 35},
+ /* 868 */ {I_RCL, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48422, 0},
+ /* 869 */ {I_RCL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48427, 0},
+ /* 870 */ {I_RCL, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43539, 35},
+ /* 871 */ {I_RCL, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48432, 5},
+ /* 872 */ {I_RCL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48437, 5},
+ /* 873 */ {I_RCL, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43545, 5},
+ /* 874 */ {I_RCL, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48442, 7},
+ /* 875 */ {I_RCL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48447, 7},
+ /* 876 */ {I_RCL, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43551, 7},
+ /* 877 */ {I_RCR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+49995, 0},
+ /* 878 */ {I_RCR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+49999, 0},
+ /* 879 */ {I_RCR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48452, 35},
+ /* 880 */ {I_RCR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48457, 0},
+ /* 881 */ {I_RCR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48462, 0},
+ /* 882 */ {I_RCR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43557, 35},
+ /* 883 */ {I_RCR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48467, 5},
+ /* 884 */ {I_RCR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48472, 5},
+ /* 885 */ {I_RCR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43563, 5},
+ /* 886 */ {I_RCR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48477, 7},
+ /* 887 */ {I_RCR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48482, 7},
+ /* 888 */ {I_RCR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43569, 7},
+ /* 889 */ {I_RDSHR, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43575, 98},
+ /* 890 */ {I_RDMSR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50003, 99},
+ /* 891 */ {I_RDPMC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50007, 89},
+ /* 892 */ {I_RDTSC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50011, 28},
+ /* 893 */ {I_RDTSCP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48487, 100},
+ /* 894 */ {I_RET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50032, 21},
+ /* 895 */ {I_RET, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48513, 101},
+ /* 896 */ {I_RETF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50036, 0},
+ /* 897 */ {I_RETF, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48518, 75},
+ /* 898 */ {I_RETN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50032, 21},
+ /* 899 */ {I_RETN, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48513, 101},
+ /* 900 */ {I_RETW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50015, 21},
+ /* 901 */ {I_RETW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48513, 101},
+ /* 902 */ {I_RETFW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50019, 0},
+ /* 903 */ {I_RETFW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48492, 75},
+ /* 904 */ {I_RETNW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50015, 21},
+ /* 905 */ {I_RETNW, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48497, 101},
+ /* 906 */ {I_RETD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50023, 22},
+ /* 907 */ {I_RETD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48502, 102},
+ /* 908 */ {I_RETFD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50027, 0},
+ /* 909 */ {I_RETFD, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48507, 75},
+ /* 910 */ {I_RETND, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50023, 22},
+ /* 911 */ {I_RETND, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48502, 102},
+ /* 912 */ {I_RETQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50031, 24},
+ /* 913 */ {I_RETQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48512, 103},
+ /* 914 */ {I_RETFQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50035, 7},
+ /* 915 */ {I_RETFQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48517, 104},
+ /* 916 */ {I_RETNQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50031, 24},
+ /* 917 */ {I_RETNQ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48512, 103},
+ /* 918 */ {I_ROL, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50039, 0},
+ /* 919 */ {I_ROL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50043, 0},
+ /* 920 */ {I_ROL, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48522, 35},
+ /* 921 */ {I_ROL, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48527, 0},
+ /* 922 */ {I_ROL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48532, 0},
+ /* 923 */ {I_ROL, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43581, 35},
+ /* 924 */ {I_ROL, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48537, 5},
+ /* 925 */ {I_ROL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48542, 5},
+ /* 926 */ {I_ROL, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43587, 5},
+ /* 927 */ {I_ROL, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48547, 7},
+ /* 928 */ {I_ROL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48552, 7},
+ /* 929 */ {I_ROL, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43593, 7},
+ /* 930 */ {I_ROR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50047, 0},
+ /* 931 */ {I_ROR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50051, 0},
+ /* 932 */ {I_ROR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48557, 35},
+ /* 933 */ {I_ROR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48562, 0},
+ /* 934 */ {I_ROR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48567, 0},
+ /* 935 */ {I_ROR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43599, 35},
+ /* 936 */ {I_ROR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48572, 5},
+ /* 937 */ {I_ROR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48577, 5},
+ /* 938 */ {I_ROR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43605, 5},
+ /* 939 */ {I_ROR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48582, 7},
+ /* 940 */ {I_ROR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48587, 7},
+ /* 941 */ {I_ROR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43611, 7},
+ /* 942 */ {I_RSDC, 2, {REG_SREG,MEMORY|BITS80,0,0,0}, NO_DECORATOR, nasm_bytecodes+45742, 105},
+ /* 943 */ {I_RSLDT, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48592, 105},
+ /* 944 */ {I_RSM, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50055, 106},
+ /* 945 */ {I_RSTS, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48597, 105},
+ /* 946 */ {I_SAHF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12405, 0},
+ /* 947 */ {I_SALC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49174, 107},
+ /* 948 */ {I_SAR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50067, 0},
+ /* 949 */ {I_SAR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50071, 0},
+ /* 950 */ {I_SAR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48637, 35},
+ /* 951 */ {I_SAR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48642, 0},
+ /* 952 */ {I_SAR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48647, 0},
+ /* 953 */ {I_SAR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43635, 35},
+ /* 954 */ {I_SAR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48652, 5},
+ /* 955 */ {I_SAR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48657, 5},
+ /* 956 */ {I_SAR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43641, 5},
+ /* 957 */ {I_SAR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48662, 7},
+ /* 958 */ {I_SAR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48667, 7},
+ /* 959 */ {I_SAR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43647, 7},
+ /* 960 */ {I_SBB, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48672, 3},
+ /* 961 */ {I_SBB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48673, 0},
+ /* 962 */ {I_SBB, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43653, 3},
+ /* 963 */ {I_SBB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43654, 0},
+ /* 964 */ {I_SBB, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43659, 4},
+ /* 965 */ {I_SBB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43660, 5},
+ /* 966 */ {I_SBB, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43665, 6},
+ /* 967 */ {I_SBB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43666, 7},
+ /* 968 */ {I_SBB, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+35268, 8},
+ /* 969 */ {I_SBB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+35268, 0},
+ /* 970 */ {I_SBB, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48677, 8},
+ /* 971 */ {I_SBB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48677, 0},
+ /* 972 */ {I_SBB, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48682, 9},
+ /* 973 */ {I_SBB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48682, 5},
+ /* 974 */ {I_SBB, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48687, 10},
+ /* 975 */ {I_SBB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48687, 7},
+ /* 976 */ {I_SBB, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33627, 11},
+ /* 977 */ {I_SBB, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33634, 12},
+ /* 978 */ {I_SBB, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33641, 13},
+ /* 979 */ {I_SBB, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50075, 8},
+ /* 980 */ {I_SBB, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48692, 8},
+ /* 981 */ {I_SBB, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48697, 9},
+ /* 982 */ {I_SBB, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48702, 10},
+ /* 983 */ {I_SBB, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43671, 3},
+ /* 984 */ {I_SBB, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33648, 3},
+ /* 985 */ {I_SBB, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33655, 4},
+ /* 986 */ {I_SBB, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33662, 6},
+ /* 987 */ {I_SBB, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43671, 3},
+ /* 988 */ {I_SBB, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33648, 3},
+ /* 989 */ {I_SBB, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33655, 4},
+ /* 990 */ {I_SCASB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50079, 0},
+ /* 991 */ {I_SCASD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48707, 5},
+ /* 992 */ {I_SCASQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48712, 7},
+ /* 993 */ {I_SCASW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48717, 0},
+ /* 994 */ {I_SFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43683, 59},
+ /* 995 */ {I_SGDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48722, 108},
+ /* 996 */ {I_SHL, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50059, 0},
+ /* 997 */ {I_SHL, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50063, 0},
+ /* 998 */ {I_SHL, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48602, 35},
+ /* 999 */ {I_SHL, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48607, 0},
+ /* 1000 */ {I_SHL, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48612, 0},
+ /* 1001 */ {I_SHL, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43617, 35},
+ /* 1002 */ {I_SHL, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48617, 5},
+ /* 1003 */ {I_SHL, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48622, 5},
+ /* 1004 */ {I_SHL, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43623, 5},
+ /* 1005 */ {I_SHL, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48627, 7},
+ /* 1006 */ {I_SHL, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48632, 7},
+ /* 1007 */ {I_SHL, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43629, 7},
+ /* 1008 */ {I_SHLD, 3, {MEMORY,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33669, 109},
+ /* 1009 */ {I_SHLD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33669, 109},
+ /* 1010 */ {I_SHLD, 3, {MEMORY,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33676, 109},
+ /* 1011 */ {I_SHLD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33676, 109},
+ /* 1012 */ {I_SHLD, 3, {MEMORY,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33683, 110},
+ /* 1013 */ {I_SHLD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33683, 110},
+ /* 1014 */ {I_SHLD, 3, {MEMORY,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43689, 9},
+ /* 1015 */ {I_SHLD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43689, 5},
+ /* 1016 */ {I_SHLD, 3, {MEMORY,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43695, 9},
+ /* 1017 */ {I_SHLD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43695, 5},
+ /* 1018 */ {I_SHLD, 3, {MEMORY,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43701, 10},
+ /* 1019 */ {I_SHLD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43701, 7},
+ /* 1020 */ {I_SHR, 2, {RM_GPR|BITS8,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50083, 0},
+ /* 1021 */ {I_SHR, 2, {RM_GPR|BITS8,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+50087, 0},
+ /* 1022 */ {I_SHR, 2, {RM_GPR|BITS8,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48727, 35},
+ /* 1023 */ {I_SHR, 2, {RM_GPR|BITS16,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48732, 0},
+ /* 1024 */ {I_SHR, 2, {RM_GPR|BITS16,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48737, 0},
+ /* 1025 */ {I_SHR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43707, 35},
+ /* 1026 */ {I_SHR, 2, {RM_GPR|BITS32,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48742, 5},
+ /* 1027 */ {I_SHR, 2, {RM_GPR|BITS32,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48747, 5},
+ /* 1028 */ {I_SHR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43713, 5},
+ /* 1029 */ {I_SHR, 2, {RM_GPR|BITS64,UNITY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48752, 7},
+ /* 1030 */ {I_SHR, 2, {RM_GPR|BITS64,REG_CL,0,0,0}, NO_DECORATOR, nasm_bytecodes+48757, 7},
+ /* 1031 */ {I_SHR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43719, 7},
+ /* 1032 */ {I_SHRD, 3, {MEMORY,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33690, 109},
+ /* 1033 */ {I_SHRD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33690, 109},
+ /* 1034 */ {I_SHRD, 3, {MEMORY,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33697, 109},
+ /* 1035 */ {I_SHRD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33697, 109},
+ /* 1036 */ {I_SHRD, 3, {MEMORY,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33704, 110},
+ /* 1037 */ {I_SHRD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+33704, 110},
+ /* 1038 */ {I_SHRD, 3, {MEMORY,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43725, 9},
+ /* 1039 */ {I_SHRD, 3, {REG_GPR|BITS16,REG_GPR|BITS16,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43725, 5},
+ /* 1040 */ {I_SHRD, 3, {MEMORY,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43731, 9},
+ /* 1041 */ {I_SHRD, 3, {REG_GPR|BITS32,REG_GPR|BITS32,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43731, 5},
+ /* 1042 */ {I_SHRD, 3, {MEMORY,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43737, 10},
+ /* 1043 */ {I_SHRD, 3, {REG_GPR|BITS64,REG_GPR|BITS64,REG_CL,0,0}, NO_DECORATOR, nasm_bytecodes+43737, 7},
+ /* 1044 */ {I_SIDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48762, 108},
+ /* 1045 */ {I_SLDT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43762, 108},
+ /* 1046 */ {I_SLDT, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43762, 108},
+ /* 1047 */ {I_SLDT, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43743, 108},
+ /* 1048 */ {I_SLDT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43749, 5},
+ /* 1049 */ {I_SLDT, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43761, 7},
+ /* 1050 */ {I_SKINIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48767, 7},
+ /* 1051 */ {I_SMI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50205, 111},
+ /* 1052 */ {I_SMSW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43780, 108},
+ /* 1053 */ {I_SMSW, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43780, 108},
+ /* 1054 */ {I_SMSW, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43767, 108},
+ /* 1055 */ {I_SMSW, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43773, 5},
+ /* 1056 */ {I_SMSW, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43779, 7},
+ /* 1057 */ {I_STC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48489, 0},
+ /* 1058 */ {I_STD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50226, 0},
+ /* 1059 */ {I_STI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48284, 0},
+ /* 1060 */ {I_STOSB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+12509, 0},
+ /* 1061 */ {I_STOSD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50099, 5},
+ /* 1062 */ {I_STOSQ, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50103, 7},
+ /* 1063 */ {I_STOSW, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50107, 0},
+ /* 1064 */ {I_STR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43798, 62},
+ /* 1065 */ {I_STR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43798, 62},
+ /* 1066 */ {I_STR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43785, 62},
+ /* 1067 */ {I_STR, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43791, 63},
+ /* 1068 */ {I_STR, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43797, 7},
+ /* 1069 */ {I_SUB, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48772, 3},
+ /* 1070 */ {I_SUB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48773, 0},
+ /* 1071 */ {I_SUB, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43803, 3},
+ /* 1072 */ {I_SUB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43804, 0},
+ /* 1073 */ {I_SUB, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43809, 4},
+ /* 1074 */ {I_SUB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43810, 5},
+ /* 1075 */ {I_SUB, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43815, 6},
+ /* 1076 */ {I_SUB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43816, 7},
+ /* 1077 */ {I_SUB, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41036, 8},
+ /* 1078 */ {I_SUB, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+41036, 0},
+ /* 1079 */ {I_SUB, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48777, 8},
+ /* 1080 */ {I_SUB, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48777, 0},
+ /* 1081 */ {I_SUB, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48782, 9},
+ /* 1082 */ {I_SUB, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48782, 5},
+ /* 1083 */ {I_SUB, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48787, 10},
+ /* 1084 */ {I_SUB, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48787, 7},
+ /* 1085 */ {I_SUB, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33711, 11},
+ /* 1086 */ {I_SUB, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33718, 12},
+ /* 1087 */ {I_SUB, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33725, 13},
+ /* 1088 */ {I_SUB, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50111, 8},
+ /* 1089 */ {I_SUB, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48792, 8},
+ /* 1090 */ {I_SUB, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48797, 9},
+ /* 1091 */ {I_SUB, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48802, 10},
+ /* 1092 */ {I_SUB, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43821, 3},
+ /* 1093 */ {I_SUB, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33732, 3},
+ /* 1094 */ {I_SUB, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33739, 4},
+ /* 1095 */ {I_SUB, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33746, 6},
+ /* 1096 */ {I_SUB, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43821, 3},
+ /* 1097 */ {I_SUB, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33732, 3},
+ /* 1098 */ {I_SUB, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33739, 4},
+ /* 1099 */ {I_SVDC, 2, {MEMORY|BITS80,REG_SREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+34357, 105},
+ /* 1100 */ {I_SVTS, 1, {MEMORY|BITS80,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48812, 105},
+ /* 1101 */ {I_SWAPGS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48817, 7},
+ /* 1102 */ {I_SYSCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49823, 113},
+ /* 1103 */ {I_SYSENTER, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50115, 89},
+ /* 1104 */ {I_SYSEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50119, 114},
+ /* 1105 */ {I_SYSRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49819, 115},
+ /* 1106 */ {I_TEST, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+50123, 8},
+ /* 1107 */ {I_TEST, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+50123, 0},
+ /* 1108 */ {I_TEST, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48822, 8},
+ /* 1109 */ {I_TEST, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48822, 0},
+ /* 1110 */ {I_TEST, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48827, 9},
+ /* 1111 */ {I_TEST, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48827, 5},
+ /* 1112 */ {I_TEST, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48832, 10},
+ /* 1113 */ {I_TEST, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48832, 7},
+ /* 1114 */ {I_TEST, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+50127, 8},
+ /* 1115 */ {I_TEST, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48837, 8},
+ /* 1116 */ {I_TEST, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48842, 9},
+ /* 1117 */ {I_TEST, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48847, 10},
+ /* 1118 */ {I_TEST, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50131, 8},
+ /* 1119 */ {I_TEST, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48852, 8},
+ /* 1120 */ {I_TEST, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48857, 9},
+ /* 1121 */ {I_TEST, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48862, 10},
+ /* 1122 */ {I_TEST, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48867, 8},
+ /* 1123 */ {I_TEST, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43833, 8},
+ /* 1124 */ {I_TEST, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43839, 9},
+ /* 1125 */ {I_TEST, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43845, 10},
+ /* 1126 */ {I_TEST, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48867, 8},
+ /* 1127 */ {I_TEST, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43833, 8},
+ /* 1128 */ {I_TEST, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43839, 9},
+ /* 1129 */ {I_UD0, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50135, 116},
+ /* 1130 */ {I_UD0, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43851, 35},
+ /* 1131 */ {I_UD0, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43857, 35},
+ /* 1132 */ {I_UD0, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43863, 35},
+ /* 1133 */ {I_UD1, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43869, 35},
+ /* 1134 */ {I_UD1, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43875, 35},
+ /* 1135 */ {I_UD1, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43881, 35},
+ /* 1136 */ {I_UD2, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50143, 35},
+ /* 1137 */ {I_VERR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48872, 62},
+ /* 1138 */ {I_VERR, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48872, 62},
+ /* 1139 */ {I_VERR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48872, 62},
+ /* 1140 */ {I_VERW, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48877, 62},
+ /* 1141 */ {I_VERW, 1, {MEMORY|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48877, 62},
+ /* 1142 */ {I_VERW, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48877, 62},
+ /* 1143 */ {I_FWAIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49721, 0},
+ /* 1144 */ {I_WBINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49183, 54},
+ /* 1145 */ {I_WRSHR, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43899, 98},
+ /* 1146 */ {I_WRMSR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50147, 99},
+ /* 1147 */ {I_XADD, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43905, 118},
+ /* 1148 */ {I_XADD, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43906, 20},
+ /* 1149 */ {I_XADD, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33781, 118},
+ /* 1150 */ {I_XADD, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33782, 20},
+ /* 1151 */ {I_XADD, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33788, 118},
+ /* 1152 */ {I_XADD, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33789, 20},
+ /* 1153 */ {I_XADD, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33795, 6},
+ /* 1154 */ {I_XADD, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33796, 7},
+ /* 1155 */ {I_XCHG, 2, {REG_AX,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+50151, 0},
+ /* 1156 */ {I_XCHG, 2, {REG_EAX,REG32NA,0,0,0}, NO_DECORATOR, nasm_bytecodes+50155, 5},
+ /* 1157 */ {I_XCHG, 2, {REG_RAX,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+50159, 7},
+ /* 1158 */ {I_XCHG, 2, {REG_GPR|BITS16,REG_AX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50163, 0},
+ /* 1159 */ {I_XCHG, 2, {REG32NA,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50167, 5},
+ /* 1160 */ {I_XCHG, 2, {REG_GPR|BITS64,REG_RAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50171, 7},
+ /* 1161 */ {I_XCHG, 2, {REG_EAX,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+50175, 19},
+ /* 1162 */ {I_XCHG, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48882, 3},
+ /* 1163 */ {I_XCHG, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48883, 0},
+ /* 1164 */ {I_XCHG, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43923, 3},
+ /* 1165 */ {I_XCHG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43924, 0},
+ /* 1166 */ {I_XCHG, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43929, 4},
+ /* 1167 */ {I_XCHG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43930, 5},
+ /* 1168 */ {I_XCHG, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43935, 6},
+ /* 1169 */ {I_XCHG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43936, 7},
+ /* 1170 */ {I_XCHG, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48887, 3},
+ /* 1171 */ {I_XCHG, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48888, 0},
+ /* 1172 */ {I_XCHG, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43941, 3},
+ /* 1173 */ {I_XCHG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43942, 0},
+ /* 1174 */ {I_XCHG, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43947, 4},
+ /* 1175 */ {I_XCHG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43948, 5},
+ /* 1176 */ {I_XCHG, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43953, 6},
+ /* 1177 */ {I_XCHG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43954, 7},
+ /* 1178 */ {I_XLATB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46014, 0},
+ /* 1179 */ {I_XLAT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46014, 0},
+ /* 1180 */ {I_XOR, 2, {MEMORY,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48892, 3},
+ /* 1181 */ {I_XOR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+48893, 0},
+ /* 1182 */ {I_XOR, 2, {MEMORY,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43959, 3},
+ /* 1183 */ {I_XOR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43960, 0},
+ /* 1184 */ {I_XOR, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43965, 4},
+ /* 1185 */ {I_XOR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+43966, 5},
+ /* 1186 */ {I_XOR, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43971, 6},
+ /* 1187 */ {I_XOR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43972, 7},
+ /* 1188 */ {I_XOR, 2, {REG_GPR|BITS8,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+40476, 8},
+ /* 1189 */ {I_XOR, 2, {REG_GPR|BITS8,REG_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+40476, 0},
+ /* 1190 */ {I_XOR, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48897, 8},
+ /* 1191 */ {I_XOR, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+48897, 0},
+ /* 1192 */ {I_XOR, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48902, 9},
+ /* 1193 */ {I_XOR, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+48902, 5},
+ /* 1194 */ {I_XOR, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+48907, 10},
+ /* 1195 */ {I_XOR, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+48907, 7},
+ /* 1196 */ {I_XOR, 2, {RM_GPR|BITS16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33802, 11},
+ /* 1197 */ {I_XOR, 2, {RM_GPR|BITS32,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33809, 12},
+ /* 1198 */ {I_XOR, 2, {RM_GPR|BITS64,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+33816, 13},
+ /* 1199 */ {I_XOR, 2, {REG_AL,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+50179, 8},
+ /* 1200 */ {I_XOR, 2, {REG_AX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48912, 8},
+ /* 1201 */ {I_XOR, 2, {REG_EAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48917, 9},
+ /* 1202 */ {I_XOR, 2, {REG_RAX,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+48922, 10},
+ /* 1203 */ {I_XOR, 2, {RM_GPR|BITS8,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+43977, 3},
+ /* 1204 */ {I_XOR, 2, {RM_GPR|BITS16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33823, 3},
+ /* 1205 */ {I_XOR, 2, {RM_GPR|BITS32,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33830, 4},
+ /* 1206 */ {I_XOR, 2, {RM_GPR|BITS64,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+33837, 6},
+ /* 1207 */ {I_XOR, 2, {MEMORY,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+43977, 3},
+ /* 1208 */ {I_XOR, 2, {MEMORY,IMMEDIATE|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33823, 3},
+ /* 1209 */ {I_XOR, 2, {MEMORY,IMMEDIATE|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33830, 4},
+ /* 1210 */ {I_CMOVA, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43989, 121},
+ /* 1211 */ {I_CMOVC, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 121},
+ /* 1212 */ {I_CMOVG, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44019, 121},
+ /* 1213 */ {I_CMOVL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44031, 121},
+ /* 1214 */ {I_CMOVNA, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44007, 121},
+ /* 1215 */ {I_CMOVNC, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 121},
+ /* 1216 */ {I_CMOVNG, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44037, 121},
+ /* 1217 */ {I_CMOVNL, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44025, 121},
+ /* 1218 */ {I_CMOVNO, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44049, 121},
+ /* 1219 */ {I_CMOVNS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44061, 121},
+ /* 1220 */ {I_CMOVNZ, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44043, 121},
+ /* 1221 */ {I_CMOVO, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44067, 121},
+ /* 1222 */ {I_CMOVPE, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44073, 121},
+ /* 1223 */ {I_CMOVPO, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44055, 121},
+ /* 1224 */ {I_CMOVS, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44079, 121},
+ /* 1225 */ {I_CMOVZ, 2, {REG_GPR|BITS16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44013, 121},
+ /* 1226 */ {I_CMOVA, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43989, 89},
+ /* 1227 */ {I_CMOVC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44001, 89},
+ /* 1228 */ {I_CMOVG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44019, 89},
+ /* 1229 */ {I_CMOVL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44031, 89},
+ /* 1230 */ {I_CMOVNA, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44007, 89},
+ /* 1231 */ {I_CMOVNC, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43995, 89},
+ /* 1232 */ {I_CMOVNG, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44037, 89},
+ /* 1233 */ {I_CMOVNL, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44025, 89},
+ /* 1234 */ {I_CMOVNO, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44049, 89},
+ /* 1235 */ {I_CMOVNS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44061, 89},
+ /* 1236 */ {I_CMOVNZ, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44043, 89},
+ /* 1237 */ {I_CMOVO, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44067, 89},
+ /* 1238 */ {I_CMOVPE, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44073, 89},
+ /* 1239 */ {I_CMOVPO, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44055, 89},
+ /* 1240 */ {I_CMOVS, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44079, 89},
+ /* 1241 */ {I_CMOVZ, 2, {REG_GPR|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44013, 89},
+ /* 1242 */ {I_CMOVA, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44085, 121},
+ /* 1243 */ {I_CMOVC, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 121},
+ /* 1244 */ {I_CMOVG, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44115, 121},
+ /* 1245 */ {I_CMOVL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44127, 121},
+ /* 1246 */ {I_CMOVNA, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44103, 121},
+ /* 1247 */ {I_CMOVNC, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 121},
+ /* 1248 */ {I_CMOVNG, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44133, 121},
+ /* 1249 */ {I_CMOVNL, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44121, 121},
+ /* 1250 */ {I_CMOVNO, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44145, 121},
+ /* 1251 */ {I_CMOVNS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44157, 121},
+ /* 1252 */ {I_CMOVNZ, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44139, 121},
+ /* 1253 */ {I_CMOVO, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44163, 121},
+ /* 1254 */ {I_CMOVPE, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44169, 121},
+ /* 1255 */ {I_CMOVPO, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44151, 121},
+ /* 1256 */ {I_CMOVS, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44175, 121},
+ /* 1257 */ {I_CMOVZ, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44109, 121},
+ /* 1258 */ {I_CMOVA, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44085, 89},
+ /* 1259 */ {I_CMOVC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44097, 89},
+ /* 1260 */ {I_CMOVG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44115, 89},
+ /* 1261 */ {I_CMOVL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44127, 89},
+ /* 1262 */ {I_CMOVNA, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44103, 89},
+ /* 1263 */ {I_CMOVNC, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44091, 89},
+ /* 1264 */ {I_CMOVNG, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44133, 89},
+ /* 1265 */ {I_CMOVNL, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44121, 89},
+ /* 1266 */ {I_CMOVNO, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44145, 89},
+ /* 1267 */ {I_CMOVNS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44157, 89},
+ /* 1268 */ {I_CMOVNZ, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44139, 89},
+ /* 1269 */ {I_CMOVO, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44163, 89},
+ /* 1270 */ {I_CMOVPE, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44169, 89},
+ /* 1271 */ {I_CMOVPO, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44151, 89},
+ /* 1272 */ {I_CMOVS, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44175, 89},
+ /* 1273 */ {I_CMOVZ, 2, {REG_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44109, 89},
+ /* 1274 */ {I_CMOVA, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44181, 10},
+ /* 1275 */ {I_CMOVC, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 10},
+ /* 1276 */ {I_CMOVG, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44211, 10},
+ /* 1277 */ {I_CMOVL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44223, 10},
+ /* 1278 */ {I_CMOVNA, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44199, 10},
+ /* 1279 */ {I_CMOVNC, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 10},
+ /* 1280 */ {I_CMOVNG, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44229, 10},
+ /* 1281 */ {I_CMOVNL, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44217, 10},
+ /* 1282 */ {I_CMOVNO, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44241, 10},
+ /* 1283 */ {I_CMOVNS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44253, 10},
+ /* 1284 */ {I_CMOVNZ, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44235, 10},
+ /* 1285 */ {I_CMOVO, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44259, 10},
+ /* 1286 */ {I_CMOVPE, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44265, 10},
+ /* 1287 */ {I_CMOVPO, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44247, 10},
+ /* 1288 */ {I_CMOVS, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44271, 10},
+ /* 1289 */ {I_CMOVZ, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44205, 10},
+ /* 1290 */ {I_CMOVA, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44181, 7},
+ /* 1291 */ {I_CMOVC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44193, 7},
+ /* 1292 */ {I_CMOVG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44211, 7},
+ /* 1293 */ {I_CMOVL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44223, 7},
+ /* 1294 */ {I_CMOVNA, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44199, 7},
+ /* 1295 */ {I_CMOVNC, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44187, 7},
+ /* 1296 */ {I_CMOVNG, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44229, 7},
+ /* 1297 */ {I_CMOVNL, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44217, 7},
+ /* 1298 */ {I_CMOVNO, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44241, 7},
+ /* 1299 */ {I_CMOVNS, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44253, 7},
+ /* 1300 */ {I_CMOVNZ, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44235, 7},
+ /* 1301 */ {I_CMOVO, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44259, 7},
+ /* 1302 */ {I_CMOVPE, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44265, 7},
+ /* 1303 */ {I_CMOVPO, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44247, 7},
+ /* 1304 */ {I_CMOVS, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44271, 7},
+ /* 1305 */ {I_CMOVZ, 2, {REG_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44205, 7},
+ /* 1306 */ {I_JA, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44277, 122},
+ /* 1307 */ {I_JC, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44289, 122},
+ /* 1308 */ {I_JG, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44307, 122},
+ /* 1309 */ {I_JL, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44319, 122},
+ /* 1310 */ {I_JNA, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44295, 122},
+ /* 1311 */ {I_JNC, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44283, 122},
+ /* 1312 */ {I_JNG, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44325, 122},
+ /* 1313 */ {I_JNL, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44313, 122},
+ /* 1314 */ {I_JNO, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44337, 122},
+ /* 1315 */ {I_JNS, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44349, 122},
+ /* 1316 */ {I_JNZ, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44331, 122},
+ /* 1317 */ {I_JO, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44355, 122},
+ /* 1318 */ {I_JPE, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44361, 122},
+ /* 1319 */ {I_JPO, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44343, 122},
+ /* 1320 */ {I_JS, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44367, 122},
+ /* 1321 */ {I_JZ, 1, {IMMEDIATE|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44301, 122},
+ /* 1322 */ {I_JA, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44373, 23},
+ /* 1323 */ {I_JC, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44385, 23},
+ /* 1324 */ {I_JG, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44403, 23},
+ /* 1325 */ {I_JL, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44415, 23},
+ /* 1326 */ {I_JNA, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44391, 23},
+ /* 1327 */ {I_JNC, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44379, 23},
+ /* 1328 */ {I_JNG, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44421, 23},
+ /* 1329 */ {I_JNL, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44409, 23},
+ /* 1330 */ {I_JNO, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44433, 23},
+ /* 1331 */ {I_JNS, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44445, 23},
+ /* 1332 */ {I_JNZ, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44427, 23},
+ /* 1333 */ {I_JO, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44451, 23},
+ /* 1334 */ {I_JPE, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44457, 23},
+ /* 1335 */ {I_JPO, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44439, 23},
+ /* 1336 */ {I_JS, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44463, 23},
+ /* 1337 */ {I_JZ, 1, {IMMEDIATE|BITS16|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44397, 23},
+ /* 1338 */ {I_JA, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44469, 23},
+ /* 1339 */ {I_JC, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44481, 23},
+ /* 1340 */ {I_JG, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44499, 23},
+ /* 1341 */ {I_JL, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44511, 23},
+ /* 1342 */ {I_JNA, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44487, 23},
+ /* 1343 */ {I_JNC, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44475, 23},
+ /* 1344 */ {I_JNG, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44517, 23},
+ /* 1345 */ {I_JNL, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44505, 23},
+ /* 1346 */ {I_JNO, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44529, 23},
+ /* 1347 */ {I_JNS, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44541, 23},
+ /* 1348 */ {I_JNZ, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44523, 23},
+ /* 1349 */ {I_JO, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44547, 23},
+ /* 1350 */ {I_JPE, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44553, 23},
+ /* 1351 */ {I_JPO, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44535, 23},
+ /* 1352 */ {I_JS, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44559, 23},
+ /* 1353 */ {I_JZ, 1, {IMMEDIATE|BITS32|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44493, 23},
+ /* 1354 */ {I_JA, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44565, 24},
+ /* 1355 */ {I_JC, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44577, 24},
+ /* 1356 */ {I_JG, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44595, 24},
+ /* 1357 */ {I_JL, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44607, 24},
+ /* 1358 */ {I_JNA, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44583, 24},
+ /* 1359 */ {I_JNC, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44571, 24},
+ /* 1360 */ {I_JNG, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44613, 24},
+ /* 1361 */ {I_JNL, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44601, 24},
+ /* 1362 */ {I_JNO, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44625, 24},
+ /* 1363 */ {I_JNS, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44637, 24},
+ /* 1364 */ {I_JNZ, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44619, 24},
+ /* 1365 */ {I_JO, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44643, 24},
+ /* 1366 */ {I_JPE, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44649, 24},
+ /* 1367 */ {I_JPO, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44631, 24},
+ /* 1368 */ {I_JS, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44655, 24},
+ /* 1369 */ {I_JZ, 1, {IMMEDIATE|BITS64|NEAR,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44589, 24},
+ /* 1370 */ {I_JA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48928, 21},
+ /* 1371 */ {I_JC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48938, 21},
+ /* 1372 */ {I_JG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48953, 21},
+ /* 1373 */ {I_JL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48963, 21},
+ /* 1374 */ {I_JNA, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48943, 21},
+ /* 1375 */ {I_JNC, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48933, 21},
+ /* 1376 */ {I_JNG, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48968, 21},
+ /* 1377 */ {I_JNL, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48958, 21},
+ /* 1378 */ {I_JNO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48978, 21},
+ /* 1379 */ {I_JNS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48988, 21},
+ /* 1380 */ {I_JNZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48973, 21},
+ /* 1381 */ {I_JO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48993, 21},
+ /* 1382 */ {I_JPE, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48998, 21},
+ /* 1383 */ {I_JPO, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48983, 21},
+ /* 1384 */ {I_JS, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49003, 21},
+ /* 1385 */ {I_JZ, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+48948, 21},
+ /* 1386 */ {I_SETA, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49007, 53},
+ /* 1387 */ {I_SETC, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 53},
+ /* 1388 */ {I_SETG, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49032, 53},
+ /* 1389 */ {I_SETL, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49042, 53},
+ /* 1390 */ {I_SETNA, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49022, 53},
+ /* 1391 */ {I_SETNC, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 53},
+ /* 1392 */ {I_SETNG, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49047, 53},
+ /* 1393 */ {I_SETNL, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49037, 53},
+ /* 1394 */ {I_SETNO, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49057, 53},
+ /* 1395 */ {I_SETNS, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49067, 53},
+ /* 1396 */ {I_SETNZ, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49052, 53},
+ /* 1397 */ {I_SETO, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49072, 53},
+ /* 1398 */ {I_SETPE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49077, 53},
+ /* 1399 */ {I_SETPO, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49062, 53},
+ /* 1400 */ {I_SETS, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49082, 53},
+ /* 1401 */ {I_SETZ, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49027, 53},
+ /* 1402 */ {I_SETA, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49007, 5},
+ /* 1403 */ {I_SETC, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49017, 5},
+ /* 1404 */ {I_SETG, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49032, 5},
+ /* 1405 */ {I_SETL, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49042, 5},
+ /* 1406 */ {I_SETNA, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49022, 5},
+ /* 1407 */ {I_SETNC, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49012, 5},
+ /* 1408 */ {I_SETNG, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49047, 5},
+ /* 1409 */ {I_SETNL, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49037, 5},
+ /* 1410 */ {I_SETNO, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49057, 5},
+ /* 1411 */ {I_SETNS, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49067, 5},
+ /* 1412 */ {I_SETNZ, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49052, 5},
+ /* 1413 */ {I_SETO, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49072, 5},
+ /* 1414 */ {I_SETPE, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49077, 5},
+ /* 1415 */ {I_SETPO, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49062, 5},
+ /* 1416 */ {I_SETS, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49082, 5},
+ /* 1417 */ {I_SETZ, 1, {REG_GPR|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49027, 5},
+ /* 1418 */ {I_ADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44661, 123},
+ /* 1419 */ {I_ADDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44667, 123},
+ /* 1420 */ {I_ANDNPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44673, 123},
+ /* 1421 */ {I_ANDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44679, 123},
+ /* 1422 */ {I_CMPEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12528, 123},
+ /* 1423 */ {I_CMPEQSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12536, 123},
+ /* 1424 */ {I_CMPLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12544, 123},
+ /* 1425 */ {I_CMPLESS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12552, 123},
+ /* 1426 */ {I_CMPLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12560, 123},
+ /* 1427 */ {I_CMPLTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12568, 123},
+ /* 1428 */ {I_CMPNEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12576, 123},
+ /* 1429 */ {I_CMPNEQSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12584, 123},
+ /* 1430 */ {I_CMPNLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12592, 123},
+ /* 1431 */ {I_CMPNLESS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12600, 123},
+ /* 1432 */ {I_CMPNLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12608, 123},
+ /* 1433 */ {I_CMPNLTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12616, 123},
+ /* 1434 */ {I_CMPORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12624, 123},
+ /* 1435 */ {I_CMPORDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12632, 123},
+ /* 1436 */ {I_CMPUNORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+12640, 123},
+ /* 1437 */ {I_CMPUNORDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12648, 123},
+ /* 1438 */ {I_CMPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+33956, 123},
+ /* 1439 */ {I_CMPSS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+33963, 123},
+ /* 1440 */ {I_COMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44685, 123},
+ /* 1441 */ {I_CVTPI2PS, 2, {XMM_L16,RM_MMX|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44691, 124},
+ /* 1442 */ {I_CVTPS2PI, 2, {MMXREG,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44697, 124},
+ /* 1443 */ {I_CVTSI2SS, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+33971, 125},
+ /* 1444 */ {I_CVTSI2SS, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+33970, 126},
+ /* 1445 */ {I_CVTSS2SI, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33978, 125},
+ /* 1446 */ {I_CVTSS2SI, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33978, 125},
+ /* 1447 */ {I_CVTSS2SI, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33977, 127},
+ /* 1448 */ {I_CVTSS2SI, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+33977, 127},
+ /* 1449 */ {I_CVTTPS2PI, 2, {MMXREG,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44703, 128},
+ /* 1450 */ {I_CVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33985, 125},
+ /* 1451 */ {I_CVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33984, 127},
+ /* 1452 */ {I_DIVPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44709, 123},
+ /* 1453 */ {I_DIVSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44715, 123},
+ /* 1454 */ {I_LDMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44721, 123},
+ /* 1455 */ {I_MAXPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44727, 123},
+ /* 1456 */ {I_MAXSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44733, 123},
+ /* 1457 */ {I_MINPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44739, 123},
+ /* 1458 */ {I_MINSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44745, 123},
+ /* 1459 */ {I_MOVAPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44751, 123},
+ /* 1460 */ {I_MOVAPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44757, 123},
+ /* 1461 */ {I_MOVHPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+44763, 123},
+ /* 1462 */ {I_MOVHPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44769, 123},
+ /* 1463 */ {I_MOVLHPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44763, 123},
+ /* 1464 */ {I_MOVLPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+43893, 123},
+ /* 1465 */ {I_MOVLPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44775, 123},
+ /* 1466 */ {I_MOVHLPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+43893, 123},
+ /* 1467 */ {I_MOVMSKPS, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44781, 123},
+ /* 1468 */ {I_MOVMSKPS, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+33991, 129},
+ /* 1469 */ {I_MOVNTPS, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44787, 123},
+ /* 1470 */ {I_MOVSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44793, 123},
+ /* 1471 */ {I_MOVSS, 2, {RM_XMM_L16|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44799, 123},
+ /* 1472 */ {I_MOVUPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44805, 123},
+ /* 1473 */ {I_MOVUPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44811, 123},
+ /* 1474 */ {I_MULPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44817, 123},
+ /* 1475 */ {I_MULSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44823, 123},
+ /* 1476 */ {I_ORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44829, 123},
+ /* 1477 */ {I_RCPPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44835, 123},
+ /* 1478 */ {I_RCPSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44841, 123},
+ /* 1479 */ {I_RSQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44847, 123},
+ /* 1480 */ {I_RSQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44853, 123},
+ /* 1481 */ {I_SHUFPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+33998, 123},
+ /* 1482 */ {I_SQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44859, 123},
+ /* 1483 */ {I_SQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44865, 123},
+ /* 1484 */ {I_STMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44871, 123},
+ /* 1485 */ {I_SUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44877, 123},
+ /* 1486 */ {I_SUBSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44883, 123},
+ /* 1487 */ {I_UCOMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+44889, 123},
+ /* 1488 */ {I_UNPCKHPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44895, 123},
+ /* 1489 */ {I_UNPCKLPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44901, 123},
+ /* 1490 */ {I_XORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44907, 123},
+ /* 1491 */ {I_FXRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34006, 130},
+ /* 1492 */ {I_FXRSTOR64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34005, 131},
+ /* 1493 */ {I_FXSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34013, 130},
+ /* 1494 */ {I_FXSAVE64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34012, 131},
+ /* 1495 */ {I_XGETBV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49087, 132},
+ /* 1496 */ {I_XSETBV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49092, 133},
+ /* 1497 */ {I_XSAVE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34020, 132},
+ /* 1498 */ {I_XSAVE64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34019, 134},
+ /* 1499 */ {I_XSAVEC, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34027, 135},
+ /* 1500 */ {I_XSAVEC64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34026, 136},
+ /* 1501 */ {I_XSAVEOPT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34034, 135},
+ /* 1502 */ {I_XSAVEOPT64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34033, 136},
+ /* 1503 */ {I_XSAVES, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34041, 135},
+ /* 1504 */ {I_XSAVES64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34040, 136},
+ /* 1505 */ {I_XRSTOR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34048, 132},
+ /* 1506 */ {I_XRSTOR64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34047, 134},
+ /* 1507 */ {I_XRSTORS, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34055, 135},
+ /* 1508 */ {I_XRSTORS64, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34054, 136},
+ /* 1509 */ {I_PREFETCHNTA, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46126, 137},
+ /* 1510 */ {I_PREFETCHT0, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46144, 137},
+ /* 1511 */ {I_PREFETCHT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46162, 137},
+ /* 1512 */ {I_PREFETCHT2, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46180, 137},
+ /* 1513 */ {I_PREFETCHIT0, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46252, 138},
+ /* 1514 */ {I_PREFETCHIT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46234, 138},
+ /* 1515 */ {I_SFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43683, 139},
+ /* 1516 */ {I_MASKMOVQ, 2, {MMXREG,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44913, 140},
+ /* 1517 */ {I_MOVNTQ, 2, {MEMORY,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44919, 141},
+ /* 1518 */ {I_PAVGB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34061, 141},
+ /* 1519 */ {I_PAVGW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34068, 141},
+ /* 1520 */ {I_PEXTRW, 3, {REG_GPR|BITS32,MMXREG,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34075, 142},
+ /* 1521 */ {I_PINSRW, 3, {MMXREG,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34082, 142},
+ /* 1522 */ {I_PINSRW, 3, {MMXREG,RM_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34082, 142},
+ /* 1523 */ {I_PINSRW, 3, {MMXREG,REG_GPR|BITS32,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34082, 142},
+ /* 1524 */ {I_PMAXSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34089, 141},
+ /* 1525 */ {I_PMAXUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34096, 141},
+ /* 1526 */ {I_PMINSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34103, 141},
+ /* 1527 */ {I_PMINUB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34110, 141},
+ /* 1528 */ {I_PMOVMSKB, 2, {REG_GPR|BITS32,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44925, 140},
+ /* 1529 */ {I_PMULHUW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34117, 141},
+ /* 1530 */ {I_PSADBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34124, 141},
+ /* 1531 */ {I_PSHUFW, 3, {MMXREG,RM_MMX,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12656, 143},
+ /* 1532 */ {I_PF2IW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12664, 91},
+ /* 1533 */ {I_PFNACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12672, 91},
+ /* 1534 */ {I_PFPNACC, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12680, 91},
+ /* 1535 */ {I_PI2FW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12688, 91},
+ /* 1536 */ {I_PSWAPD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+12696, 91},
+ /* 1537 */ {I_MASKMOVDQU, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44931, 144},
+ /* 1538 */ {I_CLFLUSH, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+44937, 144},
+ /* 1539 */ {I_MOVNTDQ, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44943, 145},
+ /* 1540 */ {I_MOVNTI, 2, {MEMORY,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34132, 146},
+ /* 1541 */ {I_MOVNTI, 2, {MEMORY,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34131, 147},
+ /* 1542 */ {I_MOVNTPD, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44949, 145},
+ /* 1543 */ {I_LFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43191, 144},
+ /* 1544 */ {I_MFENCE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43269, 144},
+ /* 1545 */ {I_MOVD, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34138, 148},
+ /* 1546 */ {I_MOVD, 2, {XMM_L16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34145, 148},
+ /* 1547 */ {I_MOVD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34145, 144},
+ /* 1548 */ {I_MOVD, 2, {RM_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34138, 144},
+ /* 1549 */ {I_MOVDQA, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44955, 145},
+ /* 1550 */ {I_MOVDQA, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44961, 145},
+ /* 1551 */ {I_MOVDQU, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+44967, 145},
+ /* 1552 */ {I_MOVDQU, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44973, 145},
+ /* 1553 */ {I_MOVDQ2Q, 2, {MMXREG,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44979, 144},
+ /* 1554 */ {I_MOVQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44985, 144},
+ /* 1555 */ {I_MOVQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44991, 144},
+ /* 1556 */ {I_MOVQ, 2, {MEMORY,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+44991, 149},
+ /* 1557 */ {I_MOVQ, 2, {XMM_L16,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+44985, 149},
+ /* 1558 */ {I_MOVQ, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34152, 150},
+ /* 1559 */ {I_MOVQ, 2, {RM_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34159, 150},
+ /* 1560 */ {I_MOVQ2DQ, 2, {XMM_L16,MMXREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+44997, 144},
+ /* 1561 */ {I_PACKSSWB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45003, 145},
+ /* 1562 */ {I_PACKSSDW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45009, 145},
+ /* 1563 */ {I_PACKUSWB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45015, 145},
+ /* 1564 */ {I_PADDB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45021, 145},
+ /* 1565 */ {I_PADDW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45027, 145},
+ /* 1566 */ {I_PADDD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45033, 145},
+ /* 1567 */ {I_PADDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+45039, 151},
+ /* 1568 */ {I_PADDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45045, 145},
+ /* 1569 */ {I_PADDSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45051, 145},
+ /* 1570 */ {I_PADDSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45057, 145},
+ /* 1571 */ {I_PADDUSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45063, 145},
+ /* 1572 */ {I_PADDUSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45069, 145},
+ /* 1573 */ {I_PAND, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45075, 145},
+ /* 1574 */ {I_PANDN, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45081, 145},
+ /* 1575 */ {I_PAVGB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45087, 145},
+ /* 1576 */ {I_PAVGW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45093, 145},
+ /* 1577 */ {I_PCMPEQB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45099, 145},
+ /* 1578 */ {I_PCMPEQW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45105, 145},
+ /* 1579 */ {I_PCMPEQD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45111, 145},
+ /* 1580 */ {I_PCMPGTB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45117, 145},
+ /* 1581 */ {I_PCMPGTW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45123, 145},
+ /* 1582 */ {I_PCMPGTD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45129, 145},
+ /* 1583 */ {I_PEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34166, 152},
+ /* 1584 */ {I_PINSRW, 3, {XMM_L16,REG_GPR|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 152},
+ /* 1585 */ {I_PINSRW, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 152},
+ /* 1586 */ {I_PINSRW, 3, {XMM_L16,MEMORY|BITS16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34173, 152},
+ /* 1587 */ {I_PMADDWD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45135, 145},
+ /* 1588 */ {I_PMAXSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45141, 145},
+ /* 1589 */ {I_PMAXUB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45147, 145},
+ /* 1590 */ {I_PMINSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45153, 145},
+ /* 1591 */ {I_PMINUB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45159, 145},
+ /* 1592 */ {I_PMOVMSKB, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45165, 144},
+ /* 1593 */ {I_PMULHUW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45171, 145},
+ /* 1594 */ {I_PMULHW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45177, 145},
+ /* 1595 */ {I_PMULLW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45183, 145},
+ /* 1596 */ {I_PMULUDQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34180, 145},
+ /* 1597 */ {I_PMULUDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45189, 145},
+ /* 1598 */ {I_POR, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45195, 145},
+ /* 1599 */ {I_PSADBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45201, 145},
+ /* 1600 */ {I_PSHUFD, 3, {XMM_L16,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34187, 152},
+ /* 1601 */ {I_PSHUFD, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34187, 154},
+ /* 1602 */ {I_PSHUFHW, 3, {XMM_L16,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34194, 152},
+ /* 1603 */ {I_PSHUFHW, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34194, 154},
+ /* 1604 */ {I_PSHUFLW, 3, {XMM_L16,XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34201, 152},
+ /* 1605 */ {I_PSHUFLW, 3, {XMM_L16,MEMORY,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+34201, 154},
+ /* 1606 */ {I_PSLLDQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34208, 155},
+ /* 1607 */ {I_PSLLW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45207, 145},
+ /* 1608 */ {I_PSLLW, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34215, 155},
+ /* 1609 */ {I_PSLLD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45213, 145},
+ /* 1610 */ {I_PSLLD, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34222, 155},
+ /* 1611 */ {I_PSLLQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45219, 145},
+ /* 1612 */ {I_PSLLQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34229, 155},
+ /* 1613 */ {I_PSRAW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45225, 145},
+ /* 1614 */ {I_PSRAW, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34236, 155},
+ /* 1615 */ {I_PSRAD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45231, 145},
+ /* 1616 */ {I_PSRAD, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34243, 155},
+ /* 1617 */ {I_PSRLDQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34250, 155},
+ /* 1618 */ {I_PSRLW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45237, 145},
+ /* 1619 */ {I_PSRLW, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34257, 155},
+ /* 1620 */ {I_PSRLD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45243, 145},
+ /* 1621 */ {I_PSRLD, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34264, 155},
+ /* 1622 */ {I_PSRLQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45249, 145},
+ /* 1623 */ {I_PSRLQ, 2, {XMM_L16,IMMEDIATE,0,0,0}, NO_DECORATOR, nasm_bytecodes+34271, 155},
+ /* 1624 */ {I_PSUBB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45255, 145},
+ /* 1625 */ {I_PSUBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45261, 145},
+ /* 1626 */ {I_PSUBD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45267, 145},
+ /* 1627 */ {I_PSUBQ, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34278, 145},
+ /* 1628 */ {I_PSUBQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45273, 145},
+ /* 1629 */ {I_PSUBSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45279, 145},
+ /* 1630 */ {I_PSUBSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45285, 145},
+ /* 1631 */ {I_PSUBUSB, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45291, 145},
+ /* 1632 */ {I_PSUBUSW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45297, 145},
+ /* 1633 */ {I_PUNPCKHBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45303, 145},
+ /* 1634 */ {I_PUNPCKHWD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45309, 145},
+ /* 1635 */ {I_PUNPCKHDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45315, 145},
+ /* 1636 */ {I_PUNPCKHQDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45321, 145},
+ /* 1637 */ {I_PUNPCKLBW, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45327, 145},
+ /* 1638 */ {I_PUNPCKLWD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45333, 145},
+ /* 1639 */ {I_PUNPCKLDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45339, 145},
+ /* 1640 */ {I_PUNPCKLQDQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45345, 145},
+ /* 1641 */ {I_PXOR, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45351, 145},
+ /* 1642 */ {I_ADDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45357, 145},
+ /* 1643 */ {I_ADDSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45363, 149},
+ /* 1644 */ {I_ANDNPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45369, 145},
+ /* 1645 */ {I_ANDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45375, 145},
+ /* 1646 */ {I_CMPEQPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12704, 145},
+ /* 1647 */ {I_CMPEQSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12712, 149},
+ /* 1648 */ {I_CMPLEPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12720, 145},
+ /* 1649 */ {I_CMPLESD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12728, 149},
+ /* 1650 */ {I_CMPLTPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12736, 145},
+ /* 1651 */ {I_CMPLTSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12744, 149},
+ /* 1652 */ {I_CMPNEQPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12752, 145},
+ /* 1653 */ {I_CMPNEQSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12760, 149},
+ /* 1654 */ {I_CMPNLEPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12768, 145},
+ /* 1655 */ {I_CMPNLESD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12776, 149},
+ /* 1656 */ {I_CMPNLTPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12784, 145},
+ /* 1657 */ {I_CMPNLTSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12792, 149},
+ /* 1658 */ {I_CMPORDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12800, 145},
+ /* 1659 */ {I_CMPORDSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12808, 149},
+ /* 1660 */ {I_CMPUNORDPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12816, 145},
+ /* 1661 */ {I_CMPUNORDSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12824, 149},
+ /* 1662 */ {I_CMPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+34285, 144},
+ /* 1663 */ {I_CMPSD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+34292, 144},
+ /* 1664 */ {I_COMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45381, 144},
+ /* 1665 */ {I_CVTDQ2PD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45387, 149},
+ /* 1666 */ {I_CVTDQ2PS, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45393, 145},
+ /* 1667 */ {I_CVTPD2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45399, 145},
+ /* 1668 */ {I_CVTPD2PI, 2, {MMXREG,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45405, 145},
+ /* 1669 */ {I_CVTPD2PS, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45411, 145},
+ /* 1670 */ {I_CVTPI2PD, 2, {XMM_L16,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+45417, 149},
+ /* 1671 */ {I_CVTPS2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45423, 145},
+ /* 1672 */ {I_CVTPS2PD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45429, 149},
+ /* 1673 */ {I_CVTSD2SI, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34299, 156},
+ /* 1674 */ {I_CVTSD2SI, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34299, 156},
+ /* 1675 */ {I_CVTSD2SI, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34306, 157},
+ /* 1676 */ {I_CVTSD2SI, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34306, 157},
+ /* 1677 */ {I_CVTSD2SS, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45435, 149},
+ /* 1678 */ {I_CVTSI2SD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34313, 158},
+ /* 1679 */ {I_CVTSI2SD, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34320, 157},
+ /* 1680 */ {I_CVTSS2SD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45441, 148},
+ /* 1681 */ {I_CVTTPD2PI, 2, {MMXREG,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45447, 145},
+ /* 1682 */ {I_CVTTPD2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45453, 145},
+ /* 1683 */ {I_CVTTPS2DQ, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45459, 145},
+ /* 1684 */ {I_CVTTSD2SI, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34327, 156},
+ /* 1685 */ {I_CVTTSD2SI, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34327, 156},
+ /* 1686 */ {I_CVTTSD2SI, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34334, 157},
+ /* 1687 */ {I_CVTTSD2SI, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+34334, 157},
+ /* 1688 */ {I_DIVPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45465, 145},
+ /* 1689 */ {I_DIVSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45471, 149},
+ /* 1690 */ {I_MAXPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45477, 145},
+ /* 1691 */ {I_MAXSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45483, 149},
+ /* 1692 */ {I_MINPD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45489, 145},
+ /* 1693 */ {I_MINSD, 2, {XMM_L16,RM_XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45495, 149},
+ /* 1694 */ {I_MOVAPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45501, 144},
+ /* 1695 */ {I_MOVAPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45507, 144},
+ /* 1696 */ {I_MOVHPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45513, 144},
+ /* 1697 */ {I_MOVHPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45519, 144},
+ /* 1698 */ {I_MOVLPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45525, 144},
+ /* 1699 */ {I_MOVLPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45531, 144},
+ /* 1700 */ {I_MOVMSKPD, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45537, 144},
+ /* 1701 */ {I_MOVMSKPD, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34341, 150},
+ /* 1702 */ {I_MOVSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45543, 144},
+ /* 1703 */ {I_MOVSD, 2, {RM_XMM_L16|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45549, 144},
+ /* 1704 */ {I_MOVUPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45555, 144},
+ /* 1705 */ {I_MOVUPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45561, 144},
+ /* 1706 */ {I_MULPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45567, 145},
+ /* 1707 */ {I_MULSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45573, 149},
+ /* 1708 */ {I_ORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45579, 145},
+ /* 1709 */ {I_SHUFPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+34348, 144},
+ /* 1710 */ {I_SQRTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45585, 145},
+ /* 1711 */ {I_SQRTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45591, 144},
+ /* 1712 */ {I_SUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45597, 145},
+ /* 1713 */ {I_SUBSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45603, 144},
+ /* 1714 */ {I_UCOMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45609, 144},
+ /* 1715 */ {I_UNPCKHPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45615, 144},
+ /* 1716 */ {I_UNPCKLPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45621, 144},
+ /* 1717 */ {I_XORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45627, 144},
+ /* 1718 */ {I_ADDSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45633, 159},
+ /* 1719 */ {I_ADDSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45639, 159},
+ /* 1720 */ {I_HADDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45645, 159},
+ /* 1721 */ {I_HADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45651, 159},
+ /* 1722 */ {I_HSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45657, 159},
+ /* 1723 */ {I_HSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45663, 159},
+ /* 1724 */ {I_LDDQU, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45669, 159},
+ /* 1725 */ {I_MOVDDUP, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+45675, 160},
+ /* 1726 */ {I_MOVSHDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45681, 161},
+ /* 1727 */ {I_MOVSLDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45687, 161},
+ /* 1728 */ {I_CLGI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49097, 162},
+ /* 1729 */ {I_STGI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49102, 162},
+ /* 1730 */ {I_VMCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45730, 163},
+ /* 1731 */ {I_VMCLEAR, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45693, 163},
+ /* 1732 */ {I_VMFUNC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49107, 163},
+ /* 1733 */ {I_VMLAUNCH, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49112, 163},
+ /* 1734 */ {I_VMLOAD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49117, 162},
+ /* 1735 */ {I_VMMCALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49122, 162},
+ /* 1736 */ {I_VMPTRLD, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45699, 163},
+ /* 1737 */ {I_VMPTRST, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45705, 163},
+ /* 1738 */ {I_VMREAD, 2, {RM_GPR|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34356, 164},
+ /* 1739 */ {I_VMREAD, 2, {RM_GPR|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34355, 165},
+ /* 1740 */ {I_VMRESUME, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49127, 163},
+ /* 1741 */ {I_VMRUN, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49132, 162},
+ /* 1742 */ {I_VMSAVE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49137, 162},
+ /* 1743 */ {I_VMWRITE, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34363, 164},
+ /* 1744 */ {I_VMWRITE, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34362, 165},
+ /* 1745 */ {I_VMXOFF, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49142, 163},
+ /* 1746 */ {I_VMXON, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42511, 163},
+ /* 1747 */ {I_INVEPT, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12833, 166},
+ /* 1748 */ {I_INVEPT, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12832, 167},
+ /* 1749 */ {I_INVVPID, 2, {REG_GPR|BITS32,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12841, 166},
+ /* 1750 */ {I_INVVPID, 2, {REG_GPR|BITS64,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+12840, 167},
+ /* 1751 */ {I_PVALIDATE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45711, 162},
+ /* 1752 */ {I_RMPADJUST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45717, 162},
+ /* 1753 */ {I_VMGEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45723, 162},
+ /* 1754 */ {I_VMGEXIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45729, 162},
+ /* 1755 */ {I_PABSB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34369, 168},
+ /* 1756 */ {I_PABSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34376, 169},
+ /* 1757 */ {I_PABSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34383, 168},
+ /* 1758 */ {I_PABSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34390, 169},
+ /* 1759 */ {I_PABSD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34397, 168},
+ /* 1760 */ {I_PABSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34404, 169},
+ /* 1761 */ {I_PALIGNR, 3, {MMXREG,RM_MMX,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12848, 168},
+ /* 1762 */ {I_PALIGNR, 3, {XMM_L16,RM_XMM_L16,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12856, 169},
+ /* 1763 */ {I_PHADDW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34411, 168},
+ /* 1764 */ {I_PHADDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34418, 169},
+ /* 1765 */ {I_PHADDD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34425, 168},
+ /* 1766 */ {I_PHADDD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34432, 169},
+ /* 1767 */ {I_PHADDSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34439, 168},
+ /* 1768 */ {I_PHADDSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34446, 169},
+ /* 1769 */ {I_PHSUBW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34453, 168},
+ /* 1770 */ {I_PHSUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34460, 169},
+ /* 1771 */ {I_PHSUBD, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34467, 168},
+ /* 1772 */ {I_PHSUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34474, 169},
+ /* 1773 */ {I_PHSUBSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34481, 168},
+ /* 1774 */ {I_PHSUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34488, 169},
+ /* 1775 */ {I_PMADDUBSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34495, 168},
+ /* 1776 */ {I_PMADDUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34502, 169},
+ /* 1777 */ {I_PMULHRSW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34509, 168},
+ /* 1778 */ {I_PMULHRSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34516, 169},
+ /* 1779 */ {I_PSHUFB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34523, 168},
+ /* 1780 */ {I_PSHUFB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34530, 169},
+ /* 1781 */ {I_PSIGNB, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34537, 168},
+ /* 1782 */ {I_PSIGNB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34544, 169},
+ /* 1783 */ {I_PSIGNW, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34551, 168},
+ /* 1784 */ {I_PSIGNW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34558, 169},
+ /* 1785 */ {I_PSIGND, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+34565, 168},
+ /* 1786 */ {I_PSIGND, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34572, 169},
+ /* 1787 */ {I_EXTRQ, 3, {XMM_L16,IMMEDIATE,IMMEDIATE,0,0}, NO_DECORATOR, nasm_bytecodes+12864, 170},
+ /* 1788 */ {I_EXTRQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45735, 170},
+ /* 1789 */ {I_INSERTQ, 4, {XMM_L16,XMM_L16,IMMEDIATE,IMMEDIATE,0}, NO_DECORATOR, nasm_bytecodes+12872, 170},
+ /* 1790 */ {I_INSERTQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45741, 170},
+ /* 1791 */ {I_MOVNTSD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45747, 171},
+ /* 1792 */ {I_MOVNTSS, 2, {MEMORY|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+45753, 172},
+ /* 1793 */ {I_LZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34579, 113},
+ /* 1794 */ {I_LZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34586, 113},
+ /* 1795 */ {I_LZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34593, 59},
+ /* 1796 */ {I_BLENDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12880, 173},
+ /* 1797 */ {I_BLENDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12888, 173},
+ /* 1798 */ {I_BLENDVPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+34600, 173},
+ /* 1799 */ {I_BLENDVPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34600, 173},
+ /* 1800 */ {I_BLENDVPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+34607, 173},
+ /* 1801 */ {I_BLENDVPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34607, 173},
+ /* 1802 */ {I_DPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12896, 173},
+ /* 1803 */ {I_DPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12904, 173},
+ /* 1804 */ {I_EXTRACTPS, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4241, 173},
+ /* 1805 */ {I_EXTRACTPS, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4240, 174},
+ /* 1806 */ {I_INSERTPS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12912, 173},
+ /* 1807 */ {I_MOVNTDQA, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34614, 173},
+ /* 1808 */ {I_MPSADBW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12920, 173},
+ /* 1809 */ {I_PACKUSDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34621, 173},
+ /* 1810 */ {I_PBLENDVB, 3, {XMM_L16,RM_XMM_L16,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+34628, 173},
+ /* 1811 */ {I_PBLENDVB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34628, 173},
+ /* 1812 */ {I_PBLENDW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12928, 173},
+ /* 1813 */ {I_PCMPEQQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34635, 173},
+ /* 1814 */ {I_PEXTRB, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4250, 173},
+ /* 1815 */ {I_PEXTRB, 3, {MEMORY|BITS8,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4250, 173},
+ /* 1816 */ {I_PEXTRB, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4249, 174},
+ /* 1817 */ {I_PEXTRD, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4258, 173},
+ /* 1818 */ {I_PEXTRQ, 3, {RM_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4267, 174},
+ /* 1819 */ {I_PEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4277, 173},
+ /* 1820 */ {I_PEXTRW, 3, {MEMORY|BITS16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4277, 173},
+ /* 1821 */ {I_PEXTRW, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4276, 174},
+ /* 1822 */ {I_PHMINPOSUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34642, 173},
+ /* 1823 */ {I_PINSRB, 3, {XMM_L16,MEMORY,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4286, 175},
+ /* 1824 */ {I_PINSRB, 3, {XMM_L16,RM_GPR|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4285, 175},
+ /* 1825 */ {I_PINSRB, 3, {XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4286, 175},
+ /* 1826 */ {I_PINSRD, 3, {XMM_L16,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4294, 175},
+ /* 1827 */ {I_PINSRQ, 3, {XMM_L16,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+4303, 176},
+ /* 1828 */ {I_PMAXSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34649, 173},
+ /* 1829 */ {I_PMAXSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34656, 173},
+ /* 1830 */ {I_PMAXUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34663, 173},
+ /* 1831 */ {I_PMAXUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34670, 173},
+ /* 1832 */ {I_PMINSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34677, 173},
+ /* 1833 */ {I_PMINSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34684, 173},
+ /* 1834 */ {I_PMINUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34691, 173},
+ /* 1835 */ {I_PMINUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34698, 173},
+ /* 1836 */ {I_PMOVSXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34705, 177},
+ /* 1837 */ {I_PMOVSXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34712, 178},
+ /* 1838 */ {I_PMOVSXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34719, 179},
+ /* 1839 */ {I_PMOVSXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34726, 177},
+ /* 1840 */ {I_PMOVSXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34733, 178},
+ /* 1841 */ {I_PMOVSXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34740, 177},
+ /* 1842 */ {I_PMOVZXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34747, 177},
+ /* 1843 */ {I_PMOVZXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34754, 178},
+ /* 1844 */ {I_PMOVZXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34761, 179},
+ /* 1845 */ {I_PMOVZXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34768, 177},
+ /* 1846 */ {I_PMOVZXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34775, 178},
+ /* 1847 */ {I_PMOVZXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34782, 177},
+ /* 1848 */ {I_PMULDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34789, 173},
+ /* 1849 */ {I_PMULLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34796, 173},
+ /* 1850 */ {I_PTEST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34803, 173},
+ /* 1851 */ {I_ROUNDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12936, 173},
+ /* 1852 */ {I_ROUNDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12944, 173},
+ /* 1853 */ {I_ROUNDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12952, 173},
+ /* 1854 */ {I_ROUNDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+12960, 173},
+ /* 1855 */ {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12985, 180},
+ /* 1856 */ {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+12968, 180},
+ /* 1857 */ {I_CRC32, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+12976, 180},
+ /* 1858 */ {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+12984, 181},
+ /* 1859 */ {I_CRC32, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+12992, 181},
+ /* 1860 */ {I_PCMPESTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13000, 180},
+ /* 1861 */ {I_PCMPESTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13008, 180},
+ /* 1862 */ {I_PCMPISTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13016, 180},
+ /* 1863 */ {I_PCMPISTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13024, 180},
+ /* 1864 */ {I_PCMPGTQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34810, 180},
+ /* 1865 */ {I_POPCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+34817, 182},
+ /* 1866 */ {I_POPCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+34824, 183},
+ /* 1867 */ {I_POPCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+34831, 184},
+ /* 1868 */ {I_GETSEC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+50183, 139},
+ /* 1869 */ {I_PFRCPV, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+13032, 185},
+ /* 1870 */ {I_PFRSQRTV, 2, {MMXREG,RM_MMX,0,0,0}, NO_DECORATOR, nasm_bytecodes+13040, 185},
+ /* 1871 */ {I_MOVBE, 2, {REG_GPR|BITS16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+13048, 186},
+ /* 1872 */ {I_MOVBE, 2, {REG_GPR|BITS32,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13056, 186},
+ /* 1873 */ {I_MOVBE, 2, {REG_GPR|BITS64,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13064, 186},
+ /* 1874 */ {I_MOVBE, 2, {MEMORY|BITS16,REG_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+13072, 186},
+ /* 1875 */ {I_MOVBE, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+13080, 186},
+ /* 1876 */ {I_MOVBE, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+13088, 186},
+ /* 1877 */ {I_AESENC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34838, 187},
+ /* 1878 */ {I_AESENCLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34845, 187},
+ /* 1879 */ {I_AESDEC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34852, 187},
+ /* 1880 */ {I_AESDECLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34859, 187},
+ /* 1881 */ {I_AESIMC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34866, 187},
+ /* 1882 */ {I_AESKEYGENASSIST, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13096, 187},
+ /* 1883 */ {I_VAESENC, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34873, 188},
+ /* 1884 */ {I_VAESENC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34880, 188},
+ /* 1885 */ {I_VAESENCLAST, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34887, 188},
+ /* 1886 */ {I_VAESENCLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34894, 188},
+ /* 1887 */ {I_VAESDEC, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34901, 188},
+ /* 1888 */ {I_VAESDEC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34908, 188},
+ /* 1889 */ {I_VAESDECLAST, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34915, 188},
+ /* 1890 */ {I_VAESDECLAST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34922, 188},
+ /* 1891 */ {I_VAESIMC, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34929, 188},
+ /* 1892 */ {I_VAESKEYGENASSIST, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13104, 188},
+ /* 1893 */ {I_VAESENC, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34936, 189},
+ /* 1894 */ {I_VAESENC, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34943, 189},
+ /* 1895 */ {I_VAESENCLAST, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34950, 189},
+ /* 1896 */ {I_VAESENCLAST, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34957, 189},
+ /* 1897 */ {I_VAESDEC, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34964, 189},
+ /* 1898 */ {I_VAESDEC, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34971, 189},
+ /* 1899 */ {I_VAESDECLAST, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+34978, 189},
+ /* 1900 */ {I_VAESDECLAST, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+34985, 189},
+ /* 1901 */ {I_VAESENC, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13112, 190},
+ /* 1902 */ {I_VAESENC, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13120, 190},
+ /* 1903 */ {I_VAESENC, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13128, 190},
+ /* 1904 */ {I_VAESENC, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13136, 190},
+ /* 1905 */ {I_VAESENCLAST, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13144, 190},
+ /* 1906 */ {I_VAESENCLAST, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13152, 190},
+ /* 1907 */ {I_VAESENCLAST, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13160, 190},
+ /* 1908 */ {I_VAESENCLAST, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13168, 190},
+ /* 1909 */ {I_VAESDEC, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13176, 190},
+ /* 1910 */ {I_VAESDEC, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13184, 190},
+ /* 1911 */ {I_VAESDEC, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13192, 190},
+ /* 1912 */ {I_VAESDEC, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13200, 190},
+ /* 1913 */ {I_VAESDECLAST, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+13208, 190},
+ /* 1914 */ {I_VAESDECLAST, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+13216, 190},
+ /* 1915 */ {I_VAESDECLAST, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+13224, 190},
+ /* 1916 */ {I_VAESDECLAST, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+13232, 190},
+ /* 1917 */ {I_VAESENC, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13240, 191},
+ /* 1918 */ {I_VAESENC, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13248, 191},
+ /* 1919 */ {I_VAESENCLAST, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13256, 191},
+ /* 1920 */ {I_VAESENCLAST, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13264, 191},
+ /* 1921 */ {I_VAESDEC, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13272, 191},
+ /* 1922 */ {I_VAESDEC, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13280, 191},
+ /* 1923 */ {I_VAESDECLAST, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+13288, 191},
+ /* 1924 */ {I_VAESDECLAST, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+13296, 191},
+ /* 1925 */ {I_VADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+34992, 188},
+ /* 1926 */ {I_VADDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+34999, 188},
+ /* 1927 */ {I_VADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35006, 188},
+ /* 1928 */ {I_VADDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35013, 188},
+ /* 1929 */ {I_VADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35020, 188},
+ /* 1930 */ {I_VADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35027, 188},
+ /* 1931 */ {I_VADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35034, 188},
+ /* 1932 */ {I_VADDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35041, 188},
+ /* 1933 */ {I_VADDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35048, 188},
+ /* 1934 */ {I_VADDSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35055, 188},
+ /* 1935 */ {I_VADDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35062, 188},
+ /* 1936 */ {I_VADDSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35069, 188},
+ /* 1937 */ {I_VADDSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35076, 188},
+ /* 1938 */ {I_VADDSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35083, 188},
+ /* 1939 */ {I_VADDSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35090, 188},
+ /* 1940 */ {I_VADDSUBPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35097, 188},
+ /* 1941 */ {I_VADDSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35104, 188},
+ /* 1942 */ {I_VADDSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35111, 188},
+ /* 1943 */ {I_VADDSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35118, 188},
+ /* 1944 */ {I_VADDSUBPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35125, 188},
+ /* 1945 */ {I_VANDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35132, 188},
+ /* 1946 */ {I_VANDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35139, 188},
+ /* 1947 */ {I_VANDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35146, 188},
+ /* 1948 */ {I_VANDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35153, 188},
+ /* 1949 */ {I_VANDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35160, 188},
+ /* 1950 */ {I_VANDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35167, 188},
+ /* 1951 */ {I_VANDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35174, 188},
+ /* 1952 */ {I_VANDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35181, 188},
+ /* 1953 */ {I_VANDNPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35188, 188},
+ /* 1954 */ {I_VANDNPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35195, 188},
+ /* 1955 */ {I_VANDNPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35202, 188},
+ /* 1956 */ {I_VANDNPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35209, 188},
+ /* 1957 */ {I_VANDNPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35216, 188},
+ /* 1958 */ {I_VANDNPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35223, 188},
+ /* 1959 */ {I_VANDNPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35230, 188},
+ /* 1960 */ {I_VANDNPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35237, 188},
+ /* 1961 */ {I_VBLENDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13304, 188},
+ /* 1962 */ {I_VBLENDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13312, 188},
+ /* 1963 */ {I_VBLENDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13320, 188},
+ /* 1964 */ {I_VBLENDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13328, 188},
+ /* 1965 */ {I_VBLENDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13336, 188},
+ /* 1966 */ {I_VBLENDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13344, 188},
+ /* 1967 */ {I_VBLENDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13352, 188},
+ /* 1968 */ {I_VBLENDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13360, 188},
+ /* 1969 */ {I_VBLENDVPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13368, 188},
+ /* 1970 */ {I_VBLENDVPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13376, 188},
+ /* 1971 */ {I_VBLENDVPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13384, 188},
+ /* 1972 */ {I_VBLENDVPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13392, 188},
+ /* 1973 */ {I_VBLENDVPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13400, 188},
+ /* 1974 */ {I_VBLENDVPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13408, 188},
+ /* 1975 */ {I_VBLENDVPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13416, 188},
+ /* 1976 */ {I_VBLENDVPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13424, 188},
+ /* 1977 */ {I_VBROADCASTSS, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35244, 188},
+ /* 1978 */ {I_VBROADCASTSS, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35251, 188},
+ /* 1979 */ {I_VBROADCASTSD, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35258, 188},
+ /* 1980 */ {I_VBROADCASTF128, 2, {YMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35265, 188},
+ /* 1981 */ {I_VCMPEQ_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4312, 188},
+ /* 1982 */ {I_VCMPEQ_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4321, 188},
+ /* 1983 */ {I_VCMPEQ_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4330, 188},
+ /* 1984 */ {I_VCMPEQ_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4339, 188},
+ /* 1985 */ {I_VCMPEQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4348, 188},
+ /* 1986 */ {I_VCMPEQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4357, 188},
+ /* 1987 */ {I_VCMPEQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4366, 188},
+ /* 1988 */ {I_VCMPEQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4375, 188},
+ /* 1989 */ {I_VCMPLT_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4384, 188},
+ /* 1990 */ {I_VCMPLT_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4393, 188},
+ /* 1991 */ {I_VCMPLT_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4402, 188},
+ /* 1992 */ {I_VCMPLT_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4411, 188},
+ /* 1993 */ {I_VCMPLTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4384, 188},
+ /* 1994 */ {I_VCMPLTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4393, 188},
+ /* 1995 */ {I_VCMPLTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4402, 188},
+ /* 1996 */ {I_VCMPLTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4411, 188},
+ /* 1997 */ {I_VCMPLE_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4420, 188},
+ /* 1998 */ {I_VCMPLE_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4429, 188},
+ /* 1999 */ {I_VCMPLE_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4438, 188},
+ /* 2000 */ {I_VCMPLE_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4447, 188},
+ /* 2001 */ {I_VCMPLEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4420, 188},
+ /* 2002 */ {I_VCMPLEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4429, 188},
+ /* 2003 */ {I_VCMPLEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4438, 188},
+ /* 2004 */ {I_VCMPLEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4447, 188},
+ /* 2005 */ {I_VCMPUNORD_QPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4456, 188},
+ /* 2006 */ {I_VCMPUNORD_QPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4465, 188},
+ /* 2007 */ {I_VCMPUNORD_QPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4474, 188},
+ /* 2008 */ {I_VCMPUNORD_QPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4483, 188},
+ /* 2009 */ {I_VCMPUNORDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4456, 188},
+ /* 2010 */ {I_VCMPUNORDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4465, 188},
+ /* 2011 */ {I_VCMPUNORDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4474, 188},
+ /* 2012 */ {I_VCMPUNORDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4483, 188},
+ /* 2013 */ {I_VCMPNEQ_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4492, 188},
+ /* 2014 */ {I_VCMPNEQ_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4501, 188},
+ /* 2015 */ {I_VCMPNEQ_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4510, 188},
+ /* 2016 */ {I_VCMPNEQ_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4519, 188},
+ /* 2017 */ {I_VCMPNEQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4492, 188},
+ /* 2018 */ {I_VCMPNEQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4501, 188},
+ /* 2019 */ {I_VCMPNEQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4510, 188},
+ /* 2020 */ {I_VCMPNEQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4519, 188},
+ /* 2021 */ {I_VCMPNLT_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4528, 188},
+ /* 2022 */ {I_VCMPNLT_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4537, 188},
+ /* 2023 */ {I_VCMPNLT_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4546, 188},
+ /* 2024 */ {I_VCMPNLT_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4555, 188},
+ /* 2025 */ {I_VCMPNLTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4528, 188},
+ /* 2026 */ {I_VCMPNLTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4537, 188},
+ /* 2027 */ {I_VCMPNLTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4546, 188},
+ /* 2028 */ {I_VCMPNLTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4555, 188},
+ /* 2029 */ {I_VCMPNLE_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4564, 188},
+ /* 2030 */ {I_VCMPNLE_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4573, 188},
+ /* 2031 */ {I_VCMPNLE_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4582, 188},
+ /* 2032 */ {I_VCMPNLE_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4591, 188},
+ /* 2033 */ {I_VCMPNLEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4564, 188},
+ /* 2034 */ {I_VCMPNLEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4573, 188},
+ /* 2035 */ {I_VCMPNLEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4582, 188},
+ /* 2036 */ {I_VCMPNLEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4591, 188},
+ /* 2037 */ {I_VCMPORD_QPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4600, 188},
+ /* 2038 */ {I_VCMPORD_QPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4609, 188},
+ /* 2039 */ {I_VCMPORD_QPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4618, 188},
+ /* 2040 */ {I_VCMPORD_QPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4627, 188},
+ /* 2041 */ {I_VCMPORDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4600, 188},
+ /* 2042 */ {I_VCMPORDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4609, 188},
+ /* 2043 */ {I_VCMPORDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4618, 188},
+ /* 2044 */ {I_VCMPORDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4627, 188},
+ /* 2045 */ {I_VCMPEQ_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4636, 188},
+ /* 2046 */ {I_VCMPEQ_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4645, 188},
+ /* 2047 */ {I_VCMPEQ_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4654, 188},
+ /* 2048 */ {I_VCMPEQ_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4663, 188},
+ /* 2049 */ {I_VCMPNGE_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4672, 188},
+ /* 2050 */ {I_VCMPNGE_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4681, 188},
+ /* 2051 */ {I_VCMPNGE_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4690, 188},
+ /* 2052 */ {I_VCMPNGE_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4699, 188},
+ /* 2053 */ {I_VCMPNGEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4672, 188},
+ /* 2054 */ {I_VCMPNGEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4681, 188},
+ /* 2055 */ {I_VCMPNGEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4690, 188},
+ /* 2056 */ {I_VCMPNGEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4699, 188},
+ /* 2057 */ {I_VCMPNGT_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4708, 188},
+ /* 2058 */ {I_VCMPNGT_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4717, 188},
+ /* 2059 */ {I_VCMPNGT_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4726, 188},
+ /* 2060 */ {I_VCMPNGT_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4735, 188},
+ /* 2061 */ {I_VCMPNGTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4708, 188},
+ /* 2062 */ {I_VCMPNGTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4717, 188},
+ /* 2063 */ {I_VCMPNGTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4726, 188},
+ /* 2064 */ {I_VCMPNGTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4735, 188},
+ /* 2065 */ {I_VCMPFALSE_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4744, 188},
+ /* 2066 */ {I_VCMPFALSE_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4753, 188},
+ /* 2067 */ {I_VCMPFALSE_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4762, 188},
+ /* 2068 */ {I_VCMPFALSE_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4771, 188},
+ /* 2069 */ {I_VCMPFALSEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4744, 188},
+ /* 2070 */ {I_VCMPFALSEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4753, 188},
+ /* 2071 */ {I_VCMPFALSEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4762, 188},
+ /* 2072 */ {I_VCMPFALSEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4771, 188},
+ /* 2073 */ {I_VCMPNEQ_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4780, 188},
+ /* 2074 */ {I_VCMPNEQ_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4789, 188},
+ /* 2075 */ {I_VCMPNEQ_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4798, 188},
+ /* 2076 */ {I_VCMPNEQ_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4807, 188},
+ /* 2077 */ {I_VCMPGE_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4816, 188},
+ /* 2078 */ {I_VCMPGE_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4825, 188},
+ /* 2079 */ {I_VCMPGE_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4834, 188},
+ /* 2080 */ {I_VCMPGE_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4843, 188},
+ /* 2081 */ {I_VCMPGEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4816, 188},
+ /* 2082 */ {I_VCMPGEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4825, 188},
+ /* 2083 */ {I_VCMPGEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4834, 188},
+ /* 2084 */ {I_VCMPGEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4843, 188},
+ /* 2085 */ {I_VCMPGT_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4852, 188},
+ /* 2086 */ {I_VCMPGT_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4861, 188},
+ /* 2087 */ {I_VCMPGT_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4870, 188},
+ /* 2088 */ {I_VCMPGT_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4879, 188},
+ /* 2089 */ {I_VCMPGTPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4852, 188},
+ /* 2090 */ {I_VCMPGTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4861, 188},
+ /* 2091 */ {I_VCMPGTPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4870, 188},
+ /* 2092 */ {I_VCMPGTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4879, 188},
+ /* 2093 */ {I_VCMPTRUE_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4888, 188},
+ /* 2094 */ {I_VCMPTRUE_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4897, 188},
+ /* 2095 */ {I_VCMPTRUE_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4906, 188},
+ /* 2096 */ {I_VCMPTRUE_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4915, 188},
+ /* 2097 */ {I_VCMPTRUEPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4888, 188},
+ /* 2098 */ {I_VCMPTRUEPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4897, 188},
+ /* 2099 */ {I_VCMPTRUEPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4906, 188},
+ /* 2100 */ {I_VCMPTRUEPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4915, 188},
+ /* 2101 */ {I_VCMPEQ_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4312, 188},
+ /* 2102 */ {I_VCMPEQ_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4321, 188},
+ /* 2103 */ {I_VCMPEQ_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4330, 188},
+ /* 2104 */ {I_VCMPEQ_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4339, 188},
+ /* 2105 */ {I_VCMPLT_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4924, 188},
+ /* 2106 */ {I_VCMPLT_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4933, 188},
+ /* 2107 */ {I_VCMPLT_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4942, 188},
+ /* 2108 */ {I_VCMPLT_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4951, 188},
+ /* 2109 */ {I_VCMPLE_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4960, 188},
+ /* 2110 */ {I_VCMPLE_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+4969, 188},
+ /* 2111 */ {I_VCMPLE_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+4978, 188},
+ /* 2112 */ {I_VCMPLE_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+4987, 188},
+ /* 2113 */ {I_VCMPUNORD_SPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+4996, 188},
+ /* 2114 */ {I_VCMPUNORD_SPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5005, 188},
+ /* 2115 */ {I_VCMPUNORD_SPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5014, 188},
+ /* 2116 */ {I_VCMPUNORD_SPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5023, 188},
+ /* 2117 */ {I_VCMPNEQ_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5032, 188},
+ /* 2118 */ {I_VCMPNEQ_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5041, 188},
+ /* 2119 */ {I_VCMPNEQ_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5050, 188},
+ /* 2120 */ {I_VCMPNEQ_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5059, 188},
+ /* 2121 */ {I_VCMPNLT_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5068, 188},
+ /* 2122 */ {I_VCMPNLT_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5077, 188},
+ /* 2123 */ {I_VCMPNLT_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5086, 188},
+ /* 2124 */ {I_VCMPNLT_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5095, 188},
+ /* 2125 */ {I_VCMPNLE_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5104, 188},
+ /* 2126 */ {I_VCMPNLE_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5113, 188},
+ /* 2127 */ {I_VCMPNLE_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5122, 188},
+ /* 2128 */ {I_VCMPNLE_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5131, 188},
+ /* 2129 */ {I_VCMPORD_SPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5140, 188},
+ /* 2130 */ {I_VCMPORD_SPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5149, 188},
+ /* 2131 */ {I_VCMPORD_SPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5158, 188},
+ /* 2132 */ {I_VCMPORD_SPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5167, 188},
+ /* 2133 */ {I_VCMPEQ_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5176, 188},
+ /* 2134 */ {I_VCMPEQ_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5185, 188},
+ /* 2135 */ {I_VCMPEQ_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5194, 188},
+ /* 2136 */ {I_VCMPEQ_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5203, 188},
+ /* 2137 */ {I_VCMPNGE_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5212, 188},
+ /* 2138 */ {I_VCMPNGE_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5221, 188},
+ /* 2139 */ {I_VCMPNGE_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5230, 188},
+ /* 2140 */ {I_VCMPNGE_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5239, 188},
+ /* 2141 */ {I_VCMPNGT_UQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5248, 188},
+ /* 2142 */ {I_VCMPNGT_UQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5257, 188},
+ /* 2143 */ {I_VCMPNGT_UQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5266, 188},
+ /* 2144 */ {I_VCMPNGT_UQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5275, 188},
+ /* 2145 */ {I_VCMPFALSE_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5284, 188},
+ /* 2146 */ {I_VCMPFALSE_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5293, 188},
+ /* 2147 */ {I_VCMPFALSE_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5302, 188},
+ /* 2148 */ {I_VCMPFALSE_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5311, 188},
+ /* 2149 */ {I_VCMPNEQ_OSPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5320, 188},
+ /* 2150 */ {I_VCMPNEQ_OSPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5329, 188},
+ /* 2151 */ {I_VCMPNEQ_OSPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5338, 188},
+ /* 2152 */ {I_VCMPNEQ_OSPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5347, 188},
+ /* 2153 */ {I_VCMPGE_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5356, 188},
+ /* 2154 */ {I_VCMPGE_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5365, 188},
+ /* 2155 */ {I_VCMPGE_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5374, 188},
+ /* 2156 */ {I_VCMPGE_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5383, 188},
+ /* 2157 */ {I_VCMPGT_OQPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5392, 188},
+ /* 2158 */ {I_VCMPGT_OQPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5401, 188},
+ /* 2159 */ {I_VCMPGT_OQPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5410, 188},
+ /* 2160 */ {I_VCMPGT_OQPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5419, 188},
+ /* 2161 */ {I_VCMPTRUE_USPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5428, 188},
+ /* 2162 */ {I_VCMPTRUE_USPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5437, 188},
+ /* 2163 */ {I_VCMPTRUE_USPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5446, 188},
+ /* 2164 */ {I_VCMPTRUE_USPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5455, 188},
+ /* 2165 */ {I_VCMPPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13432, 188},
+ /* 2166 */ {I_VCMPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13440, 188},
+ /* 2167 */ {I_VCMPPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13448, 188},
+ /* 2168 */ {I_VCMPPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13456, 188},
+ /* 2169 */ {I_VCMPEQ_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5464, 188},
+ /* 2170 */ {I_VCMPEQ_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5473, 188},
+ /* 2171 */ {I_VCMPEQ_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5482, 188},
+ /* 2172 */ {I_VCMPEQ_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5491, 188},
+ /* 2173 */ {I_VCMPEQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5500, 188},
+ /* 2174 */ {I_VCMPEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5509, 188},
+ /* 2175 */ {I_VCMPEQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5518, 188},
+ /* 2176 */ {I_VCMPEQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5527, 188},
+ /* 2177 */ {I_VCMPLT_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5536, 188},
+ /* 2178 */ {I_VCMPLT_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5545, 188},
+ /* 2179 */ {I_VCMPLT_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5554, 188},
+ /* 2180 */ {I_VCMPLT_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5563, 188},
+ /* 2181 */ {I_VCMPLTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5536, 188},
+ /* 2182 */ {I_VCMPLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5545, 188},
+ /* 2183 */ {I_VCMPLTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5554, 188},
+ /* 2184 */ {I_VCMPLTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5563, 188},
+ /* 2185 */ {I_VCMPLE_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5572, 188},
+ /* 2186 */ {I_VCMPLE_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5581, 188},
+ /* 2187 */ {I_VCMPLE_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5590, 188},
+ /* 2188 */ {I_VCMPLE_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5599, 188},
+ /* 2189 */ {I_VCMPLEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5572, 188},
+ /* 2190 */ {I_VCMPLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5581, 188},
+ /* 2191 */ {I_VCMPLEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5590, 188},
+ /* 2192 */ {I_VCMPLEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5599, 188},
+ /* 2193 */ {I_VCMPUNORD_QPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5608, 188},
+ /* 2194 */ {I_VCMPUNORD_QPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5617, 188},
+ /* 2195 */ {I_VCMPUNORD_QPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5626, 188},
+ /* 2196 */ {I_VCMPUNORD_QPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5635, 188},
+ /* 2197 */ {I_VCMPUNORDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5608, 188},
+ /* 2198 */ {I_VCMPUNORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5617, 188},
+ /* 2199 */ {I_VCMPUNORDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5626, 188},
+ /* 2200 */ {I_VCMPUNORDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5635, 188},
+ /* 2201 */ {I_VCMPNEQ_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5644, 188},
+ /* 2202 */ {I_VCMPNEQ_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5653, 188},
+ /* 2203 */ {I_VCMPNEQ_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5662, 188},
+ /* 2204 */ {I_VCMPNEQ_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5671, 188},
+ /* 2205 */ {I_VCMPNEQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5644, 188},
+ /* 2206 */ {I_VCMPNEQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5653, 188},
+ /* 2207 */ {I_VCMPNEQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5662, 188},
+ /* 2208 */ {I_VCMPNEQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5671, 188},
+ /* 2209 */ {I_VCMPNLT_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5680, 188},
+ /* 2210 */ {I_VCMPNLT_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5689, 188},
+ /* 2211 */ {I_VCMPNLT_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5698, 188},
+ /* 2212 */ {I_VCMPNLT_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5707, 188},
+ /* 2213 */ {I_VCMPNLTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5680, 188},
+ /* 2214 */ {I_VCMPNLTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5689, 188},
+ /* 2215 */ {I_VCMPNLTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5698, 188},
+ /* 2216 */ {I_VCMPNLTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5707, 188},
+ /* 2217 */ {I_VCMPNLE_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5716, 188},
+ /* 2218 */ {I_VCMPNLE_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5725, 188},
+ /* 2219 */ {I_VCMPNLE_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5734, 188},
+ /* 2220 */ {I_VCMPNLE_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5743, 188},
+ /* 2221 */ {I_VCMPNLEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5716, 188},
+ /* 2222 */ {I_VCMPNLEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5725, 188},
+ /* 2223 */ {I_VCMPNLEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5734, 188},
+ /* 2224 */ {I_VCMPNLEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5743, 188},
+ /* 2225 */ {I_VCMPORD_QPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5752, 188},
+ /* 2226 */ {I_VCMPORD_QPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5761, 188},
+ /* 2227 */ {I_VCMPORD_QPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5770, 188},
+ /* 2228 */ {I_VCMPORD_QPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5779, 188},
+ /* 2229 */ {I_VCMPORDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5752, 188},
+ /* 2230 */ {I_VCMPORDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5761, 188},
+ /* 2231 */ {I_VCMPORDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5770, 188},
+ /* 2232 */ {I_VCMPORDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5779, 188},
+ /* 2233 */ {I_VCMPEQ_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5788, 188},
+ /* 2234 */ {I_VCMPEQ_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5797, 188},
+ /* 2235 */ {I_VCMPEQ_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5806, 188},
+ /* 2236 */ {I_VCMPEQ_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5815, 188},
+ /* 2237 */ {I_VCMPNGE_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5824, 188},
+ /* 2238 */ {I_VCMPNGE_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5833, 188},
+ /* 2239 */ {I_VCMPNGE_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5842, 188},
+ /* 2240 */ {I_VCMPNGE_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5851, 188},
+ /* 2241 */ {I_VCMPNGEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5824, 188},
+ /* 2242 */ {I_VCMPNGEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5833, 188},
+ /* 2243 */ {I_VCMPNGEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5842, 188},
+ /* 2244 */ {I_VCMPNGEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5851, 188},
+ /* 2245 */ {I_VCMPNGT_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5860, 188},
+ /* 2246 */ {I_VCMPNGT_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5869, 188},
+ /* 2247 */ {I_VCMPNGT_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5878, 188},
+ /* 2248 */ {I_VCMPNGT_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5887, 188},
+ /* 2249 */ {I_VCMPNGTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5860, 188},
+ /* 2250 */ {I_VCMPNGTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5869, 188},
+ /* 2251 */ {I_VCMPNGTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5878, 188},
+ /* 2252 */ {I_VCMPNGTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5887, 188},
+ /* 2253 */ {I_VCMPFALSE_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5896, 188},
+ /* 2254 */ {I_VCMPFALSE_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5905, 188},
+ /* 2255 */ {I_VCMPFALSE_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5914, 188},
+ /* 2256 */ {I_VCMPFALSE_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5923, 188},
+ /* 2257 */ {I_VCMPFALSEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5896, 188},
+ /* 2258 */ {I_VCMPFALSEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5905, 188},
+ /* 2259 */ {I_VCMPFALSEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5914, 188},
+ /* 2260 */ {I_VCMPFALSEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5923, 188},
+ /* 2261 */ {I_VCMPNEQ_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5932, 188},
+ /* 2262 */ {I_VCMPNEQ_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5941, 188},
+ /* 2263 */ {I_VCMPNEQ_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5950, 188},
+ /* 2264 */ {I_VCMPNEQ_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5959, 188},
+ /* 2265 */ {I_VCMPGE_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5968, 188},
+ /* 2266 */ {I_VCMPGE_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5977, 188},
+ /* 2267 */ {I_VCMPGE_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5986, 188},
+ /* 2268 */ {I_VCMPGE_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5995, 188},
+ /* 2269 */ {I_VCMPGEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5968, 188},
+ /* 2270 */ {I_VCMPGEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5977, 188},
+ /* 2271 */ {I_VCMPGEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5986, 188},
+ /* 2272 */ {I_VCMPGEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5995, 188},
+ /* 2273 */ {I_VCMPGT_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6004, 188},
+ /* 2274 */ {I_VCMPGT_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6013, 188},
+ /* 2275 */ {I_VCMPGT_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6022, 188},
+ /* 2276 */ {I_VCMPGT_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6031, 188},
+ /* 2277 */ {I_VCMPGTPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6004, 188},
+ /* 2278 */ {I_VCMPGTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6013, 188},
+ /* 2279 */ {I_VCMPGTPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6022, 188},
+ /* 2280 */ {I_VCMPGTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6031, 188},
+ /* 2281 */ {I_VCMPTRUE_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6040, 188},
+ /* 2282 */ {I_VCMPTRUE_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6049, 188},
+ /* 2283 */ {I_VCMPTRUE_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6058, 188},
+ /* 2284 */ {I_VCMPTRUE_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6067, 188},
+ /* 2285 */ {I_VCMPTRUEPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6040, 188},
+ /* 2286 */ {I_VCMPTRUEPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6049, 188},
+ /* 2287 */ {I_VCMPTRUEPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6058, 188},
+ /* 2288 */ {I_VCMPTRUEPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6067, 188},
+ /* 2289 */ {I_VCMPEQ_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+5464, 188},
+ /* 2290 */ {I_VCMPEQ_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+5473, 188},
+ /* 2291 */ {I_VCMPEQ_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+5482, 188},
+ /* 2292 */ {I_VCMPEQ_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+5491, 188},
+ /* 2293 */ {I_VCMPLT_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6076, 188},
+ /* 2294 */ {I_VCMPLT_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6085, 188},
+ /* 2295 */ {I_VCMPLT_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6094, 188},
+ /* 2296 */ {I_VCMPLT_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6103, 188},
+ /* 2297 */ {I_VCMPLE_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6112, 188},
+ /* 2298 */ {I_VCMPLE_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6121, 188},
+ /* 2299 */ {I_VCMPLE_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6130, 188},
+ /* 2300 */ {I_VCMPLE_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6139, 188},
+ /* 2301 */ {I_VCMPUNORD_SPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6148, 188},
+ /* 2302 */ {I_VCMPUNORD_SPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6157, 188},
+ /* 2303 */ {I_VCMPUNORD_SPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6166, 188},
+ /* 2304 */ {I_VCMPUNORD_SPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6175, 188},
+ /* 2305 */ {I_VCMPNEQ_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6184, 188},
+ /* 2306 */ {I_VCMPNEQ_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6193, 188},
+ /* 2307 */ {I_VCMPNEQ_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6202, 188},
+ /* 2308 */ {I_VCMPNEQ_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6211, 188},
+ /* 2309 */ {I_VCMPNLT_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6220, 188},
+ /* 2310 */ {I_VCMPNLT_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6229, 188},
+ /* 2311 */ {I_VCMPNLT_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6238, 188},
+ /* 2312 */ {I_VCMPNLT_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6247, 188},
+ /* 2313 */ {I_VCMPNLE_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6256, 188},
+ /* 2314 */ {I_VCMPNLE_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6265, 188},
+ /* 2315 */ {I_VCMPNLE_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6274, 188},
+ /* 2316 */ {I_VCMPNLE_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6283, 188},
+ /* 2317 */ {I_VCMPORD_SPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6292, 188},
+ /* 2318 */ {I_VCMPORD_SPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6301, 188},
+ /* 2319 */ {I_VCMPORD_SPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6310, 188},
+ /* 2320 */ {I_VCMPORD_SPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6319, 188},
+ /* 2321 */ {I_VCMPEQ_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6328, 188},
+ /* 2322 */ {I_VCMPEQ_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6337, 188},
+ /* 2323 */ {I_VCMPEQ_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6346, 188},
+ /* 2324 */ {I_VCMPEQ_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6355, 188},
+ /* 2325 */ {I_VCMPNGE_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6364, 188},
+ /* 2326 */ {I_VCMPNGE_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6373, 188},
+ /* 2327 */ {I_VCMPNGE_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6382, 188},
+ /* 2328 */ {I_VCMPNGE_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6391, 188},
+ /* 2329 */ {I_VCMPNGT_UQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6400, 188},
+ /* 2330 */ {I_VCMPNGT_UQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6409, 188},
+ /* 2331 */ {I_VCMPNGT_UQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6418, 188},
+ /* 2332 */ {I_VCMPNGT_UQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6427, 188},
+ /* 2333 */ {I_VCMPFALSE_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6436, 188},
+ /* 2334 */ {I_VCMPFALSE_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6445, 188},
+ /* 2335 */ {I_VCMPFALSE_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6454, 188},
+ /* 2336 */ {I_VCMPFALSE_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6463, 188},
+ /* 2337 */ {I_VCMPNEQ_OSPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6472, 188},
+ /* 2338 */ {I_VCMPNEQ_OSPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6481, 188},
+ /* 2339 */ {I_VCMPNEQ_OSPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6490, 188},
+ /* 2340 */ {I_VCMPNEQ_OSPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6499, 188},
+ /* 2341 */ {I_VCMPGE_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6508, 188},
+ /* 2342 */ {I_VCMPGE_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6517, 188},
+ /* 2343 */ {I_VCMPGE_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6526, 188},
+ /* 2344 */ {I_VCMPGE_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6535, 188},
+ /* 2345 */ {I_VCMPGT_OQPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6544, 188},
+ /* 2346 */ {I_VCMPGT_OQPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6553, 188},
+ /* 2347 */ {I_VCMPGT_OQPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6562, 188},
+ /* 2348 */ {I_VCMPGT_OQPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6571, 188},
+ /* 2349 */ {I_VCMPTRUE_USPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+6580, 188},
+ /* 2350 */ {I_VCMPTRUE_USPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+6589, 188},
+ /* 2351 */ {I_VCMPTRUE_USPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+6598, 188},
+ /* 2352 */ {I_VCMPTRUE_USPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+6607, 188},
+ /* 2353 */ {I_VCMPPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13464, 188},
+ /* 2354 */ {I_VCMPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13472, 188},
+ /* 2355 */ {I_VCMPPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13480, 188},
+ /* 2356 */ {I_VCMPPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13488, 188},
+ /* 2357 */ {I_VCMPEQ_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6616, 188},
+ /* 2358 */ {I_VCMPEQ_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6625, 188},
+ /* 2359 */ {I_VCMPEQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6634, 188},
+ /* 2360 */ {I_VCMPEQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6643, 188},
+ /* 2361 */ {I_VCMPLT_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6652, 188},
+ /* 2362 */ {I_VCMPLT_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6661, 188},
+ /* 2363 */ {I_VCMPLTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6652, 188},
+ /* 2364 */ {I_VCMPLTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6661, 188},
+ /* 2365 */ {I_VCMPLE_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6670, 188},
+ /* 2366 */ {I_VCMPLE_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6679, 188},
+ /* 2367 */ {I_VCMPLESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6670, 188},
+ /* 2368 */ {I_VCMPLESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6679, 188},
+ /* 2369 */ {I_VCMPUNORD_QSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6688, 188},
+ /* 2370 */ {I_VCMPUNORD_QSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6697, 188},
+ /* 2371 */ {I_VCMPUNORDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6688, 188},
+ /* 2372 */ {I_VCMPUNORDSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6697, 188},
+ /* 2373 */ {I_VCMPNEQ_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6706, 188},
+ /* 2374 */ {I_VCMPNEQ_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6715, 188},
+ /* 2375 */ {I_VCMPNEQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6706, 188},
+ /* 2376 */ {I_VCMPNEQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6715, 188},
+ /* 2377 */ {I_VCMPNLT_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6724, 188},
+ /* 2378 */ {I_VCMPNLT_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6733, 188},
+ /* 2379 */ {I_VCMPNLTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6724, 188},
+ /* 2380 */ {I_VCMPNLTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6733, 188},
+ /* 2381 */ {I_VCMPNLE_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6742, 188},
+ /* 2382 */ {I_VCMPNLE_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6751, 188},
+ /* 2383 */ {I_VCMPNLESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6742, 188},
+ /* 2384 */ {I_VCMPNLESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6751, 188},
+ /* 2385 */ {I_VCMPORD_QSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6760, 188},
+ /* 2386 */ {I_VCMPORD_QSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6769, 188},
+ /* 2387 */ {I_VCMPORDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6760, 188},
+ /* 2388 */ {I_VCMPORDSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6769, 188},
+ /* 2389 */ {I_VCMPEQ_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6778, 188},
+ /* 2390 */ {I_VCMPEQ_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6787, 188},
+ /* 2391 */ {I_VCMPNGE_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6796, 188},
+ /* 2392 */ {I_VCMPNGE_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6805, 188},
+ /* 2393 */ {I_VCMPNGESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6796, 188},
+ /* 2394 */ {I_VCMPNGESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6805, 188},
+ /* 2395 */ {I_VCMPNGT_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6814, 188},
+ /* 2396 */ {I_VCMPNGT_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6823, 188},
+ /* 2397 */ {I_VCMPNGTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6814, 188},
+ /* 2398 */ {I_VCMPNGTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6823, 188},
+ /* 2399 */ {I_VCMPFALSE_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6832, 188},
+ /* 2400 */ {I_VCMPFALSE_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6841, 188},
+ /* 2401 */ {I_VCMPFALSESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6832, 188},
+ /* 2402 */ {I_VCMPFALSESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6841, 188},
+ /* 2403 */ {I_VCMPNEQ_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6850, 188},
+ /* 2404 */ {I_VCMPNEQ_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6859, 188},
+ /* 2405 */ {I_VCMPGE_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6868, 188},
+ /* 2406 */ {I_VCMPGE_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6877, 188},
+ /* 2407 */ {I_VCMPGESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6868, 188},
+ /* 2408 */ {I_VCMPGESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6877, 188},
+ /* 2409 */ {I_VCMPGT_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6886, 188},
+ /* 2410 */ {I_VCMPGT_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6895, 188},
+ /* 2411 */ {I_VCMPGTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6886, 188},
+ /* 2412 */ {I_VCMPGTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6895, 188},
+ /* 2413 */ {I_VCMPTRUE_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6904, 188},
+ /* 2414 */ {I_VCMPTRUE_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6913, 188},
+ /* 2415 */ {I_VCMPTRUESD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6904, 188},
+ /* 2416 */ {I_VCMPTRUESD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6913, 188},
+ /* 2417 */ {I_VCMPEQ_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6616, 188},
+ /* 2418 */ {I_VCMPEQ_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6625, 188},
+ /* 2419 */ {I_VCMPLT_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6922, 188},
+ /* 2420 */ {I_VCMPLT_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6931, 188},
+ /* 2421 */ {I_VCMPLE_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6940, 188},
+ /* 2422 */ {I_VCMPLE_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6949, 188},
+ /* 2423 */ {I_VCMPUNORD_SSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6958, 188},
+ /* 2424 */ {I_VCMPUNORD_SSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6967, 188},
+ /* 2425 */ {I_VCMPNEQ_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6976, 188},
+ /* 2426 */ {I_VCMPNEQ_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+6985, 188},
+ /* 2427 */ {I_VCMPNLT_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+6994, 188},
+ /* 2428 */ {I_VCMPNLT_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7003, 188},
+ /* 2429 */ {I_VCMPNLE_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7012, 188},
+ /* 2430 */ {I_VCMPNLE_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7021, 188},
+ /* 2431 */ {I_VCMPORD_SSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7030, 188},
+ /* 2432 */ {I_VCMPORD_SSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7039, 188},
+ /* 2433 */ {I_VCMPEQ_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7048, 188},
+ /* 2434 */ {I_VCMPEQ_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7057, 188},
+ /* 2435 */ {I_VCMPNGE_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7066, 188},
+ /* 2436 */ {I_VCMPNGE_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7075, 188},
+ /* 2437 */ {I_VCMPNGT_UQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7084, 188},
+ /* 2438 */ {I_VCMPNGT_UQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7093, 188},
+ /* 2439 */ {I_VCMPFALSE_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7102, 188},
+ /* 2440 */ {I_VCMPFALSE_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7111, 188},
+ /* 2441 */ {I_VCMPNEQ_OSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7120, 188},
+ /* 2442 */ {I_VCMPNEQ_OSSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7129, 188},
+ /* 2443 */ {I_VCMPGE_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7138, 188},
+ /* 2444 */ {I_VCMPGE_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7147, 188},
+ /* 2445 */ {I_VCMPGT_OQSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7156, 188},
+ /* 2446 */ {I_VCMPGT_OQSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7165, 188},
+ /* 2447 */ {I_VCMPTRUE_USSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7174, 188},
+ /* 2448 */ {I_VCMPTRUE_USSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7183, 188},
+ /* 2449 */ {I_VCMPSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13496, 188},
+ /* 2450 */ {I_VCMPSD, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13504, 188},
+ /* 2451 */ {I_VCMPEQ_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7192, 188},
+ /* 2452 */ {I_VCMPEQ_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7201, 188},
+ /* 2453 */ {I_VCMPEQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7210, 188},
+ /* 2454 */ {I_VCMPEQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7219, 188},
+ /* 2455 */ {I_VCMPLT_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7228, 188},
+ /* 2456 */ {I_VCMPLT_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7237, 188},
+ /* 2457 */ {I_VCMPLTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7228, 188},
+ /* 2458 */ {I_VCMPLTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7237, 188},
+ /* 2459 */ {I_VCMPLE_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7246, 188},
+ /* 2460 */ {I_VCMPLE_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7255, 188},
+ /* 2461 */ {I_VCMPLESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7246, 188},
+ /* 2462 */ {I_VCMPLESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7255, 188},
+ /* 2463 */ {I_VCMPUNORD_QSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7264, 188},
+ /* 2464 */ {I_VCMPUNORD_QSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7273, 188},
+ /* 2465 */ {I_VCMPUNORDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7264, 188},
+ /* 2466 */ {I_VCMPUNORDSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7273, 188},
+ /* 2467 */ {I_VCMPNEQ_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7282, 188},
+ /* 2468 */ {I_VCMPNEQ_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7291, 188},
+ /* 2469 */ {I_VCMPNEQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7282, 188},
+ /* 2470 */ {I_VCMPNEQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7291, 188},
+ /* 2471 */ {I_VCMPNLT_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7300, 188},
+ /* 2472 */ {I_VCMPNLT_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7309, 188},
+ /* 2473 */ {I_VCMPNLTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7300, 188},
+ /* 2474 */ {I_VCMPNLTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7309, 188},
+ /* 2475 */ {I_VCMPNLE_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7318, 188},
+ /* 2476 */ {I_VCMPNLE_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7327, 188},
+ /* 2477 */ {I_VCMPNLESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7318, 188},
+ /* 2478 */ {I_VCMPNLESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7327, 188},
+ /* 2479 */ {I_VCMPORD_QSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7336, 188},
+ /* 2480 */ {I_VCMPORD_QSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7345, 188},
+ /* 2481 */ {I_VCMPORDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7336, 188},
+ /* 2482 */ {I_VCMPORDSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7345, 188},
+ /* 2483 */ {I_VCMPEQ_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7354, 188},
+ /* 2484 */ {I_VCMPEQ_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7363, 188},
+ /* 2485 */ {I_VCMPNGE_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7372, 188},
+ /* 2486 */ {I_VCMPNGE_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7381, 188},
+ /* 2487 */ {I_VCMPNGESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7372, 188},
+ /* 2488 */ {I_VCMPNGESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7381, 188},
+ /* 2489 */ {I_VCMPNGT_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7390, 188},
+ /* 2490 */ {I_VCMPNGT_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7399, 188},
+ /* 2491 */ {I_VCMPNGTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7390, 188},
+ /* 2492 */ {I_VCMPNGTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7399, 188},
+ /* 2493 */ {I_VCMPFALSE_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7408, 188},
+ /* 2494 */ {I_VCMPFALSE_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7417, 188},
+ /* 2495 */ {I_VCMPFALSESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7408, 188},
+ /* 2496 */ {I_VCMPFALSESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7417, 188},
+ /* 2497 */ {I_VCMPNEQ_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7426, 188},
+ /* 2498 */ {I_VCMPNEQ_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7435, 188},
+ /* 2499 */ {I_VCMPGE_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7444, 188},
+ /* 2500 */ {I_VCMPGE_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7453, 188},
+ /* 2501 */ {I_VCMPGESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7444, 188},
+ /* 2502 */ {I_VCMPGESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7453, 188},
+ /* 2503 */ {I_VCMPGT_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7462, 188},
+ /* 2504 */ {I_VCMPGT_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7471, 188},
+ /* 2505 */ {I_VCMPGTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7462, 188},
+ /* 2506 */ {I_VCMPGTSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7471, 188},
+ /* 2507 */ {I_VCMPTRUE_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7480, 188},
+ /* 2508 */ {I_VCMPTRUE_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7489, 188},
+ /* 2509 */ {I_VCMPTRUESS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7480, 188},
+ /* 2510 */ {I_VCMPTRUESS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7489, 188},
+ /* 2511 */ {I_VCMPEQ_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7192, 188},
+ /* 2512 */ {I_VCMPEQ_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7201, 188},
+ /* 2513 */ {I_VCMPLT_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7498, 188},
+ /* 2514 */ {I_VCMPLT_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7507, 188},
+ /* 2515 */ {I_VCMPLE_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7516, 188},
+ /* 2516 */ {I_VCMPLE_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7525, 188},
+ /* 2517 */ {I_VCMPUNORD_SSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7534, 188},
+ /* 2518 */ {I_VCMPUNORD_SSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7543, 188},
+ /* 2519 */ {I_VCMPNEQ_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7552, 188},
+ /* 2520 */ {I_VCMPNEQ_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7561, 188},
+ /* 2521 */ {I_VCMPNLT_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7570, 188},
+ /* 2522 */ {I_VCMPNLT_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7579, 188},
+ /* 2523 */ {I_VCMPNLE_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7588, 188},
+ /* 2524 */ {I_VCMPNLE_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7597, 188},
+ /* 2525 */ {I_VCMPORD_SSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7606, 188},
+ /* 2526 */ {I_VCMPORD_SSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7615, 188},
+ /* 2527 */ {I_VCMPEQ_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7624, 188},
+ /* 2528 */ {I_VCMPEQ_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7633, 188},
+ /* 2529 */ {I_VCMPNGE_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7642, 188},
+ /* 2530 */ {I_VCMPNGE_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7651, 188},
+ /* 2531 */ {I_VCMPNGT_UQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7660, 188},
+ /* 2532 */ {I_VCMPNGT_UQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7669, 188},
+ /* 2533 */ {I_VCMPFALSE_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7678, 188},
+ /* 2534 */ {I_VCMPFALSE_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7687, 188},
+ /* 2535 */ {I_VCMPNEQ_OSSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7696, 188},
+ /* 2536 */ {I_VCMPNEQ_OSSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7705, 188},
+ /* 2537 */ {I_VCMPGE_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7714, 188},
+ /* 2538 */ {I_VCMPGE_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7723, 188},
+ /* 2539 */ {I_VCMPGT_OQSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7732, 188},
+ /* 2540 */ {I_VCMPGT_OQSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7741, 188},
+ /* 2541 */ {I_VCMPTRUE_USSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+7750, 188},
+ /* 2542 */ {I_VCMPTRUE_USSS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+7759, 188},
+ /* 2543 */ {I_VCMPSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13512, 188},
+ /* 2544 */ {I_VCMPSS, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13520, 188},
+ /* 2545 */ {I_VCOMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35272, 188},
+ /* 2546 */ {I_VCOMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35279, 188},
+ /* 2547 */ {I_VCVTDQ2PD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35286, 188},
+ /* 2548 */ {I_VCVTDQ2PD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35293, 188},
+ /* 2549 */ {I_VCVTDQ2PS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35300, 188},
+ /* 2550 */ {I_VCVTDQ2PS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35307, 188},
+ /* 2551 */ {I_VCVTPD2DQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35314, 188},
+ /* 2552 */ {I_VCVTPD2DQ, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35314, 192},
+ /* 2553 */ {I_VCVTPD2DQ, 2, {XMM_L16,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35321, 188},
+ /* 2554 */ {I_VCVTPD2DQ, 2, {XMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35321, 193},
+ /* 2555 */ {I_VCVTPD2PS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35328, 188},
+ /* 2556 */ {I_VCVTPD2PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35328, 192},
+ /* 2557 */ {I_VCVTPD2PS, 2, {XMM_L16,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35335, 188},
+ /* 2558 */ {I_VCVTPD2PS, 2, {XMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35335, 193},
+ /* 2559 */ {I_VCVTPS2DQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35342, 188},
+ /* 2560 */ {I_VCVTPS2DQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35349, 188},
+ /* 2561 */ {I_VCVTPS2PD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35356, 188},
+ /* 2562 */ {I_VCVTPS2PD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35363, 188},
+ /* 2563 */ {I_VCVTSD2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35370, 188},
+ /* 2564 */ {I_VCVTSD2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35377, 194},
+ /* 2565 */ {I_VCVTSD2SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35384, 188},
+ /* 2566 */ {I_VCVTSD2SS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35391, 188},
+ /* 2567 */ {I_VCVTSI2SD, 3, {XMM_L16,XMM_L16,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35398, 195},
+ /* 2568 */ {I_VCVTSI2SD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35405, 195},
+ /* 2569 */ {I_VCVTSI2SD, 3, {XMM_L16,XMM_L16,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35412, 196},
+ /* 2570 */ {I_VCVTSI2SD, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35419, 196},
+ /* 2571 */ {I_VCVTSI2SS, 3, {XMM_L16,XMM_L16,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35426, 195},
+ /* 2572 */ {I_VCVTSI2SS, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35433, 195},
+ /* 2573 */ {I_VCVTSI2SS, 3, {XMM_L16,XMM_L16,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35440, 196},
+ /* 2574 */ {I_VCVTSI2SS, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35447, 196},
+ /* 2575 */ {I_VCVTSS2SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35454, 188},
+ /* 2576 */ {I_VCVTSS2SD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35461, 188},
+ /* 2577 */ {I_VCVTSS2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35468, 188},
+ /* 2578 */ {I_VCVTSS2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35475, 194},
+ /* 2579 */ {I_VCVTTPD2DQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35482, 188},
+ /* 2580 */ {I_VCVTTPD2DQ, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35482, 192},
+ /* 2581 */ {I_VCVTTPD2DQ, 2, {XMM_L16,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35489, 188},
+ /* 2582 */ {I_VCVTTPD2DQ, 2, {XMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35489, 193},
+ /* 2583 */ {I_VCVTTPS2DQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35496, 188},
+ /* 2584 */ {I_VCVTTPS2DQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35503, 188},
+ /* 2585 */ {I_VCVTTSD2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35510, 188},
+ /* 2586 */ {I_VCVTTSD2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35517, 194},
+ /* 2587 */ {I_VCVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35524, 188},
+ /* 2588 */ {I_VCVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35531, 194},
+ /* 2589 */ {I_VDIVPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35538, 188},
+ /* 2590 */ {I_VDIVPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35545, 188},
+ /* 2591 */ {I_VDIVPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35552, 188},
+ /* 2592 */ {I_VDIVPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35559, 188},
+ /* 2593 */ {I_VDIVPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35566, 188},
+ /* 2594 */ {I_VDIVPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35573, 188},
+ /* 2595 */ {I_VDIVPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35580, 188},
+ /* 2596 */ {I_VDIVPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35587, 188},
+ /* 2597 */ {I_VDIVSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35594, 188},
+ /* 2598 */ {I_VDIVSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35601, 188},
+ /* 2599 */ {I_VDIVSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35608, 188},
+ /* 2600 */ {I_VDIVSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35615, 188},
+ /* 2601 */ {I_VDPPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13528, 188},
+ /* 2602 */ {I_VDPPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13536, 188},
+ /* 2603 */ {I_VDPPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13544, 188},
+ /* 2604 */ {I_VDPPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13552, 188},
+ /* 2605 */ {I_VDPPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13560, 188},
+ /* 2606 */ {I_VDPPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13568, 188},
+ /* 2607 */ {I_VEXTRACTF128, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13576, 188},
+ /* 2608 */ {I_VEXTRACTPS, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13584, 188},
+ /* 2609 */ {I_VHADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35622, 188},
+ /* 2610 */ {I_VHADDPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35629, 188},
+ /* 2611 */ {I_VHADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35636, 188},
+ /* 2612 */ {I_VHADDPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35643, 188},
+ /* 2613 */ {I_VHADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35650, 188},
+ /* 2614 */ {I_VHADDPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35657, 188},
+ /* 2615 */ {I_VHADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35664, 188},
+ /* 2616 */ {I_VHADDPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35671, 188},
+ /* 2617 */ {I_VHSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35678, 188},
+ /* 2618 */ {I_VHSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35685, 188},
+ /* 2619 */ {I_VHSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35692, 188},
+ /* 2620 */ {I_VHSUBPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35699, 188},
+ /* 2621 */ {I_VHSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35706, 188},
+ /* 2622 */ {I_VHSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35713, 188},
+ /* 2623 */ {I_VHSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35720, 188},
+ /* 2624 */ {I_VHSUBPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35727, 188},
+ /* 2625 */ {I_VINSERTF128, 4, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13592, 188},
+ /* 2626 */ {I_VINSERTF128, 3, {YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13600, 188},
+ /* 2627 */ {I_VINSERTPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13608, 188},
+ /* 2628 */ {I_VINSERTPS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13616, 188},
+ /* 2629 */ {I_VLDDQU, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35734, 188},
+ /* 2630 */ {I_VLDQQU, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35741, 188},
+ /* 2631 */ {I_VLDDQU, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35741, 188},
+ /* 2632 */ {I_VLDMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+35748, 188},
+ /* 2633 */ {I_VMASKMOVDQU, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35755, 188},
+ /* 2634 */ {I_VMASKMOVPS, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35762, 188},
+ /* 2635 */ {I_VMASKMOVPS, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35769, 188},
+ /* 2636 */ {I_VMASKMOVPS, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35776, 192},
+ /* 2637 */ {I_VMASKMOVPS, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35783, 193},
+ /* 2638 */ {I_VMASKMOVPD, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35790, 188},
+ /* 2639 */ {I_VMASKMOVPD, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35797, 188},
+ /* 2640 */ {I_VMASKMOVPD, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35804, 188},
+ /* 2641 */ {I_VMASKMOVPD, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+35811, 188},
+ /* 2642 */ {I_VMAXPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35818, 188},
+ /* 2643 */ {I_VMAXPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35825, 188},
+ /* 2644 */ {I_VMAXPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35832, 188},
+ /* 2645 */ {I_VMAXPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35839, 188},
+ /* 2646 */ {I_VMAXPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35846, 188},
+ /* 2647 */ {I_VMAXPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35853, 188},
+ /* 2648 */ {I_VMAXPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35860, 188},
+ /* 2649 */ {I_VMAXPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35867, 188},
+ /* 2650 */ {I_VMAXSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35874, 188},
+ /* 2651 */ {I_VMAXSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35881, 188},
+ /* 2652 */ {I_VMAXSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35888, 188},
+ /* 2653 */ {I_VMAXSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35895, 188},
+ /* 2654 */ {I_VMINPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35902, 188},
+ /* 2655 */ {I_VMINPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35909, 188},
+ /* 2656 */ {I_VMINPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35916, 188},
+ /* 2657 */ {I_VMINPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35923, 188},
+ /* 2658 */ {I_VMINPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+35930, 188},
+ /* 2659 */ {I_VMINPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35937, 188},
+ /* 2660 */ {I_VMINPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+35944, 188},
+ /* 2661 */ {I_VMINPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+35951, 188},
+ /* 2662 */ {I_VMINSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+35958, 188},
+ /* 2663 */ {I_VMINSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+35965, 188},
+ /* 2664 */ {I_VMINSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+35972, 188},
+ /* 2665 */ {I_VMINSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+35979, 188},
+ /* 2666 */ {I_VMOVAPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+35986, 188},
+ /* 2667 */ {I_VMOVAPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35993, 188},
+ /* 2668 */ {I_VMOVAPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36000, 188},
+ /* 2669 */ {I_VMOVAPD, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36007, 188},
+ /* 2670 */ {I_VMOVAPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36014, 188},
+ /* 2671 */ {I_VMOVAPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36021, 188},
+ /* 2672 */ {I_VMOVAPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36028, 188},
+ /* 2673 */ {I_VMOVAPS, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36035, 188},
+ /* 2674 */ {I_VMOVD, 2, {XMM_L16,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+36042, 188},
+ /* 2675 */ {I_VMOVD, 2, {RM_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36049, 188},
+ /* 2676 */ {I_VMOVQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36056, 197},
+ /* 2677 */ {I_VMOVQ, 2, {RM_XMM_L16|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36063, 197},
+ /* 2678 */ {I_VMOVQ, 2, {XMM_L16,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36070, 196},
+ /* 2679 */ {I_VMOVQ, 2, {RM_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36077, 196},
+ /* 2680 */ {I_VMOVDDUP, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36084, 188},
+ /* 2681 */ {I_VMOVDDUP, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36091, 188},
+ /* 2682 */ {I_VMOVDQA, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36098, 188},
+ /* 2683 */ {I_VMOVDQA, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36105, 188},
+ /* 2684 */ {I_VMOVQQA, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36112, 188},
+ /* 2685 */ {I_VMOVQQA, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36119, 188},
+ /* 2686 */ {I_VMOVDQA, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36112, 188},
+ /* 2687 */ {I_VMOVDQA, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36119, 188},
+ /* 2688 */ {I_VMOVDQU, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36126, 188},
+ /* 2689 */ {I_VMOVDQU, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36133, 188},
+ /* 2690 */ {I_VMOVQQU, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36140, 188},
+ /* 2691 */ {I_VMOVQQU, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36147, 188},
+ /* 2692 */ {I_VMOVDQU, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36140, 188},
+ /* 2693 */ {I_VMOVDQU, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36147, 188},
+ /* 2694 */ {I_VMOVHLPS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36154, 188},
+ /* 2695 */ {I_VMOVHLPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36161, 188},
+ /* 2696 */ {I_VMOVHPD, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36168, 188},
+ /* 2697 */ {I_VMOVHPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36175, 188},
+ /* 2698 */ {I_VMOVHPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36182, 188},
+ /* 2699 */ {I_VMOVHPS, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36189, 188},
+ /* 2700 */ {I_VMOVHPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36196, 188},
+ /* 2701 */ {I_VMOVHPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36203, 188},
+ /* 2702 */ {I_VMOVLHPS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36189, 188},
+ /* 2703 */ {I_VMOVLHPS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36196, 188},
+ /* 2704 */ {I_VMOVLPD, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36210, 188},
+ /* 2705 */ {I_VMOVLPD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36217, 188},
+ /* 2706 */ {I_VMOVLPD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36224, 188},
+ /* 2707 */ {I_VMOVLPS, 3, {XMM_L16,XMM_L16,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36154, 188},
+ /* 2708 */ {I_VMOVLPS, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36161, 188},
+ /* 2709 */ {I_VMOVLPS, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36231, 188},
+ /* 2710 */ {I_VMOVMSKPD, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36238, 194},
+ /* 2711 */ {I_VMOVMSKPD, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36238, 188},
+ /* 2712 */ {I_VMOVMSKPD, 2, {REG_GPR|BITS64,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36245, 194},
+ /* 2713 */ {I_VMOVMSKPD, 2, {REG_GPR|BITS32,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36245, 188},
+ /* 2714 */ {I_VMOVMSKPS, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36252, 194},
+ /* 2715 */ {I_VMOVMSKPS, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36252, 188},
+ /* 2716 */ {I_VMOVMSKPS, 2, {REG_GPR|BITS64,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36259, 194},
+ /* 2717 */ {I_VMOVMSKPS, 2, {REG_GPR|BITS32,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36259, 188},
+ /* 2718 */ {I_VMOVNTDQ, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36266, 188},
+ /* 2719 */ {I_VMOVNTQQ, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36273, 188},
+ /* 2720 */ {I_VMOVNTDQ, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36273, 188},
+ /* 2721 */ {I_VMOVNTDQA, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36280, 188},
+ /* 2722 */ {I_VMOVNTPD, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36287, 188},
+ /* 2723 */ {I_VMOVNTPD, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36294, 188},
+ /* 2724 */ {I_VMOVNTPS, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36301, 188},
+ /* 2725 */ {I_VMOVNTPS, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36308, 188},
+ /* 2726 */ {I_VMOVSD, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36315, 188},
+ /* 2727 */ {I_VMOVSD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36322, 188},
+ /* 2728 */ {I_VMOVSD, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36329, 188},
+ /* 2729 */ {I_VMOVSD, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36336, 188},
+ /* 2730 */ {I_VMOVSD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36343, 188},
+ /* 2731 */ {I_VMOVSD, 2, {MEMORY|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36350, 188},
+ /* 2732 */ {I_VMOVSHDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36357, 188},
+ /* 2733 */ {I_VMOVSHDUP, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36364, 188},
+ /* 2734 */ {I_VMOVSLDUP, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36371, 188},
+ /* 2735 */ {I_VMOVSLDUP, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36378, 188},
+ /* 2736 */ {I_VMOVSS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36385, 188},
+ /* 2737 */ {I_VMOVSS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36392, 188},
+ /* 2738 */ {I_VMOVSS, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+36399, 188},
+ /* 2739 */ {I_VMOVSS, 3, {XMM_L16,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+36406, 188},
+ /* 2740 */ {I_VMOVSS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36413, 188},
+ /* 2741 */ {I_VMOVSS, 2, {MEMORY|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36420, 188},
+ /* 2742 */ {I_VMOVUPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36427, 188},
+ /* 2743 */ {I_VMOVUPD, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36434, 188},
+ /* 2744 */ {I_VMOVUPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36441, 188},
+ /* 2745 */ {I_VMOVUPD, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36448, 188},
+ /* 2746 */ {I_VMOVUPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36455, 188},
+ /* 2747 */ {I_VMOVUPS, 2, {RM_XMM_L16|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36462, 188},
+ /* 2748 */ {I_VMOVUPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36469, 188},
+ /* 2749 */ {I_VMOVUPS, 2, {RM_YMM_L16|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+36476, 188},
+ /* 2750 */ {I_VMPSADBW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13624, 188},
+ /* 2751 */ {I_VMPSADBW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13632, 188},
+ /* 2752 */ {I_VMULPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36483, 188},
+ /* 2753 */ {I_VMULPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36490, 188},
+ /* 2754 */ {I_VMULPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36497, 188},
+ /* 2755 */ {I_VMULPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36504, 188},
+ /* 2756 */ {I_VMULPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36511, 188},
+ /* 2757 */ {I_VMULPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36518, 188},
+ /* 2758 */ {I_VMULPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36525, 188},
+ /* 2759 */ {I_VMULPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36532, 188},
+ /* 2760 */ {I_VMULSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+36539, 188},
+ /* 2761 */ {I_VMULSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+36546, 188},
+ /* 2762 */ {I_VMULSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+36553, 188},
+ /* 2763 */ {I_VMULSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+36560, 188},
+ /* 2764 */ {I_VORPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36567, 188},
+ /* 2765 */ {I_VORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36574, 188},
+ /* 2766 */ {I_VORPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36581, 188},
+ /* 2767 */ {I_VORPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36588, 188},
+ /* 2768 */ {I_VORPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36595, 188},
+ /* 2769 */ {I_VORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36602, 188},
+ /* 2770 */ {I_VORPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36609, 188},
+ /* 2771 */ {I_VORPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+36616, 188},
+ /* 2772 */ {I_VPABSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36623, 188},
+ /* 2773 */ {I_VPABSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36630, 188},
+ /* 2774 */ {I_VPABSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36637, 188},
+ /* 2775 */ {I_VPACKSSWB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36644, 188},
+ /* 2776 */ {I_VPACKSSWB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36651, 188},
+ /* 2777 */ {I_VPACKSSDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36658, 188},
+ /* 2778 */ {I_VPACKSSDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36665, 188},
+ /* 2779 */ {I_VPACKUSWB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36672, 188},
+ /* 2780 */ {I_VPACKUSWB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36679, 188},
+ /* 2781 */ {I_VPACKUSDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36686, 188},
+ /* 2782 */ {I_VPACKUSDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36693, 188},
+ /* 2783 */ {I_VPADDB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36700, 188},
+ /* 2784 */ {I_VPADDB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36707, 188},
+ /* 2785 */ {I_VPADDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36714, 188},
+ /* 2786 */ {I_VPADDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36721, 188},
+ /* 2787 */ {I_VPADDD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36728, 188},
+ /* 2788 */ {I_VPADDD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36735, 188},
+ /* 2789 */ {I_VPADDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36742, 188},
+ /* 2790 */ {I_VPADDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36749, 188},
+ /* 2791 */ {I_VPADDSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36756, 188},
+ /* 2792 */ {I_VPADDSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36763, 188},
+ /* 2793 */ {I_VPADDSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36770, 188},
+ /* 2794 */ {I_VPADDSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36777, 188},
+ /* 2795 */ {I_VPADDUSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36784, 188},
+ /* 2796 */ {I_VPADDUSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36791, 188},
+ /* 2797 */ {I_VPADDUSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36798, 188},
+ /* 2798 */ {I_VPADDUSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36805, 188},
+ /* 2799 */ {I_VPALIGNR, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13640, 188},
+ /* 2800 */ {I_VPALIGNR, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13648, 188},
+ /* 2801 */ {I_VPAND, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36812, 188},
+ /* 2802 */ {I_VPAND, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36819, 188},
+ /* 2803 */ {I_VPANDN, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36826, 188},
+ /* 2804 */ {I_VPANDN, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36833, 188},
+ /* 2805 */ {I_VPAVGB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36840, 188},
+ /* 2806 */ {I_VPAVGB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36847, 188},
+ /* 2807 */ {I_VPAVGW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36854, 188},
+ /* 2808 */ {I_VPAVGW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36861, 188},
+ /* 2809 */ {I_VPBLENDVB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+13656, 188},
+ /* 2810 */ {I_VPBLENDVB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+13664, 188},
+ /* 2811 */ {I_VPBLENDW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13672, 188},
+ /* 2812 */ {I_VPBLENDW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13680, 188},
+ /* 2813 */ {I_VPCMPESTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13688, 188},
+ /* 2814 */ {I_VPCMPESTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13696, 188},
+ /* 2815 */ {I_VPCMPISTRI, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13704, 188},
+ /* 2816 */ {I_VPCMPISTRM, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13712, 188},
+ /* 2817 */ {I_VPCMPEQB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36868, 188},
+ /* 2818 */ {I_VPCMPEQB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36875, 188},
+ /* 2819 */ {I_VPCMPEQW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36882, 188},
+ /* 2820 */ {I_VPCMPEQW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36889, 188},
+ /* 2821 */ {I_VPCMPEQD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36896, 188},
+ /* 2822 */ {I_VPCMPEQD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36903, 188},
+ /* 2823 */ {I_VPCMPEQQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36910, 188},
+ /* 2824 */ {I_VPCMPEQQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36917, 188},
+ /* 2825 */ {I_VPCMPGTB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36924, 188},
+ /* 2826 */ {I_VPCMPGTB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36931, 188},
+ /* 2827 */ {I_VPCMPGTW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36938, 188},
+ /* 2828 */ {I_VPCMPGTW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36945, 188},
+ /* 2829 */ {I_VPCMPGTD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36952, 188},
+ /* 2830 */ {I_VPCMPGTD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36959, 188},
+ /* 2831 */ {I_VPCMPGTQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36966, 188},
+ /* 2832 */ {I_VPCMPGTQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36973, 188},
+ /* 2833 */ {I_VPERMILPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+36980, 188},
+ /* 2834 */ {I_VPERMILPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+36987, 188},
+ /* 2835 */ {I_VPERMILPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+36994, 188},
+ /* 2836 */ {I_VPERMILPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37001, 188},
+ /* 2837 */ {I_VPERMILPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13720, 188},
+ /* 2838 */ {I_VPERMILPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13728, 188},
+ /* 2839 */ {I_VPERMILPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37008, 188},
+ /* 2840 */ {I_VPERMILPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37015, 188},
+ /* 2841 */ {I_VPERMILPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+37022, 188},
+ /* 2842 */ {I_VPERMILPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37029, 188},
+ /* 2843 */ {I_VPERMILPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13736, 188},
+ /* 2844 */ {I_VPERMILPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13744, 188},
+ /* 2845 */ {I_VPERM2F128, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13752, 188},
+ /* 2846 */ {I_VPERM2F128, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13760, 188},
+ /* 2847 */ {I_VPEXTRB, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13768, 194},
+ /* 2848 */ {I_VPEXTRB, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13768, 188},
+ /* 2849 */ {I_VPEXTRB, 3, {MEMORY|BITS8,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13768, 188},
+ /* 2850 */ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13776, 194},
+ /* 2851 */ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13776, 188},
+ /* 2852 */ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13784, 194},
+ /* 2853 */ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13784, 188},
+ /* 2854 */ {I_VPEXTRW, 3, {MEMORY|BITS16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13784, 188},
+ /* 2855 */ {I_VPEXTRD, 3, {REG_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13792, 194},
+ /* 2856 */ {I_VPEXTRD, 3, {RM_GPR|BITS32,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13792, 188},
+ /* 2857 */ {I_VPEXTRQ, 3, {RM_GPR|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13800, 194},
+ /* 2858 */ {I_VPHADDW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37036, 188},
+ /* 2859 */ {I_VPHADDW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37043, 188},
+ /* 2860 */ {I_VPHADDD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37050, 188},
+ /* 2861 */ {I_VPHADDD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37057, 188},
+ /* 2862 */ {I_VPHADDSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37064, 188},
+ /* 2863 */ {I_VPHADDSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37071, 188},
+ /* 2864 */ {I_VPHMINPOSUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37078, 188},
+ /* 2865 */ {I_VPHSUBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37085, 188},
+ /* 2866 */ {I_VPHSUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37092, 188},
+ /* 2867 */ {I_VPHSUBD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37099, 188},
+ /* 2868 */ {I_VPHSUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37106, 188},
+ /* 2869 */ {I_VPHSUBSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37113, 188},
+ /* 2870 */ {I_VPHSUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37120, 188},
+ /* 2871 */ {I_VPINSRB, 4, {XMM_L16,XMM_L16,MEMORY|BITS8,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13808, 188},
+ /* 2872 */ {I_VPINSRB, 3, {XMM_L16,MEMORY|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13816, 188},
+ /* 2873 */ {I_VPINSRB, 4, {XMM_L16,XMM_L16,RM_GPR|BITS8,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13808, 188},
+ /* 2874 */ {I_VPINSRB, 3, {XMM_L16,RM_GPR|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13816, 188},
+ /* 2875 */ {I_VPINSRB, 4, {XMM_L16,XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13808, 188},
+ /* 2876 */ {I_VPINSRB, 3, {XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13816, 188},
+ /* 2877 */ {I_VPINSRW, 4, {XMM_L16,XMM_L16,MEMORY|BITS16,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13824, 188},
+ /* 2878 */ {I_VPINSRW, 3, {XMM_L16,MEMORY|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13832, 188},
+ /* 2879 */ {I_VPINSRW, 4, {XMM_L16,XMM_L16,RM_GPR|BITS16,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13824, 188},
+ /* 2880 */ {I_VPINSRW, 3, {XMM_L16,RM_GPR|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13832, 188},
+ /* 2881 */ {I_VPINSRW, 4, {XMM_L16,XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13824, 188},
+ /* 2882 */ {I_VPINSRW, 3, {XMM_L16,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13832, 188},
+ /* 2883 */ {I_VPINSRD, 4, {XMM_L16,XMM_L16,MEMORY|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13840, 188},
+ /* 2884 */ {I_VPINSRD, 3, {XMM_L16,MEMORY|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13848, 188},
+ /* 2885 */ {I_VPINSRD, 4, {XMM_L16,XMM_L16,RM_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13840, 188},
+ /* 2886 */ {I_VPINSRD, 3, {XMM_L16,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13848, 188},
+ /* 2887 */ {I_VPINSRQ, 4, {XMM_L16,XMM_L16,MEMORY|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13856, 194},
+ /* 2888 */ {I_VPINSRQ, 3, {XMM_L16,MEMORY|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13864, 194},
+ /* 2889 */ {I_VPINSRQ, 4, {XMM_L16,XMM_L16,RM_GPR|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+13856, 194},
+ /* 2890 */ {I_VPINSRQ, 3, {XMM_L16,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13864, 194},
+ /* 2891 */ {I_VPMADDWD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37127, 188},
+ /* 2892 */ {I_VPMADDWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37134, 188},
+ /* 2893 */ {I_VPMADDUBSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37141, 188},
+ /* 2894 */ {I_VPMADDUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37148, 188},
+ /* 2895 */ {I_VPMAXSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37155, 188},
+ /* 2896 */ {I_VPMAXSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37162, 188},
+ /* 2897 */ {I_VPMAXSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37169, 188},
+ /* 2898 */ {I_VPMAXSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37176, 188},
+ /* 2899 */ {I_VPMAXSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37183, 188},
+ /* 2900 */ {I_VPMAXSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37190, 188},
+ /* 2901 */ {I_VPMAXUB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37197, 188},
+ /* 2902 */ {I_VPMAXUB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37204, 188},
+ /* 2903 */ {I_VPMAXUW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37211, 188},
+ /* 2904 */ {I_VPMAXUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37218, 188},
+ /* 2905 */ {I_VPMAXUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37225, 188},
+ /* 2906 */ {I_VPMAXUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37232, 188},
+ /* 2907 */ {I_VPMINSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37239, 188},
+ /* 2908 */ {I_VPMINSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37246, 188},
+ /* 2909 */ {I_VPMINSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37253, 188},
+ /* 2910 */ {I_VPMINSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37260, 188},
+ /* 2911 */ {I_VPMINSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37267, 188},
+ /* 2912 */ {I_VPMINSD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37274, 188},
+ /* 2913 */ {I_VPMINUB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37281, 188},
+ /* 2914 */ {I_VPMINUB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37288, 188},
+ /* 2915 */ {I_VPMINUW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37295, 188},
+ /* 2916 */ {I_VPMINUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37302, 188},
+ /* 2917 */ {I_VPMINUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37309, 188},
+ /* 2918 */ {I_VPMINUD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37316, 188},
+ /* 2919 */ {I_VPMOVMSKB, 2, {REG_GPR|BITS64,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37323, 194},
+ /* 2920 */ {I_VPMOVMSKB, 2, {REG_GPR|BITS32,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37323, 188},
+ /* 2921 */ {I_VPMOVSXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37330, 188},
+ /* 2922 */ {I_VPMOVSXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37337, 188},
+ /* 2923 */ {I_VPMOVSXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37344, 188},
+ /* 2924 */ {I_VPMOVSXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37351, 188},
+ /* 2925 */ {I_VPMOVSXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37358, 188},
+ /* 2926 */ {I_VPMOVSXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37365, 188},
+ /* 2927 */ {I_VPMOVZXBW, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37372, 188},
+ /* 2928 */ {I_VPMOVZXBD, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37379, 188},
+ /* 2929 */ {I_VPMOVZXBQ, 2, {XMM_L16,RM_XMM_L16|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+37386, 188},
+ /* 2930 */ {I_VPMOVZXWD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37393, 188},
+ /* 2931 */ {I_VPMOVZXWQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37400, 188},
+ /* 2932 */ {I_VPMOVZXDQ, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+37407, 188},
+ /* 2933 */ {I_VPMULHUW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37414, 188},
+ /* 2934 */ {I_VPMULHUW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37421, 188},
+ /* 2935 */ {I_VPMULHRSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37428, 188},
+ /* 2936 */ {I_VPMULHRSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37435, 188},
+ /* 2937 */ {I_VPMULHW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37442, 188},
+ /* 2938 */ {I_VPMULHW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37449, 188},
+ /* 2939 */ {I_VPMULLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37456, 188},
+ /* 2940 */ {I_VPMULLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37463, 188},
+ /* 2941 */ {I_VPMULLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37470, 188},
+ /* 2942 */ {I_VPMULLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37477, 188},
+ /* 2943 */ {I_VPMULUDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37484, 188},
+ /* 2944 */ {I_VPMULUDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37491, 188},
+ /* 2945 */ {I_VPMULDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37498, 188},
+ /* 2946 */ {I_VPMULDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37505, 188},
+ /* 2947 */ {I_VPOR, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37512, 188},
+ /* 2948 */ {I_VPOR, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37519, 188},
+ /* 2949 */ {I_VPSADBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37526, 188},
+ /* 2950 */ {I_VPSADBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37533, 188},
+ /* 2951 */ {I_VPSHUFB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37540, 188},
+ /* 2952 */ {I_VPSHUFB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37547, 188},
+ /* 2953 */ {I_VPSHUFD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13872, 188},
+ /* 2954 */ {I_VPSHUFHW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13880, 188},
+ /* 2955 */ {I_VPSHUFLW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13888, 188},
+ /* 2956 */ {I_VPSIGNB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37554, 188},
+ /* 2957 */ {I_VPSIGNB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37561, 188},
+ /* 2958 */ {I_VPSIGNW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37568, 188},
+ /* 2959 */ {I_VPSIGNW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37575, 188},
+ /* 2960 */ {I_VPSIGND, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37582, 188},
+ /* 2961 */ {I_VPSIGND, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37589, 188},
+ /* 2962 */ {I_VPSLLDQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13896, 188},
+ /* 2963 */ {I_VPSLLDQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13904, 188},
+ /* 2964 */ {I_VPSRLDQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13912, 188},
+ /* 2965 */ {I_VPSRLDQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13920, 188},
+ /* 2966 */ {I_VPSLLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37596, 188},
+ /* 2967 */ {I_VPSLLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37603, 188},
+ /* 2968 */ {I_VPSLLW, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13928, 188},
+ /* 2969 */ {I_VPSLLW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13936, 188},
+ /* 2970 */ {I_VPSLLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37610, 188},
+ /* 2971 */ {I_VPSLLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37617, 188},
+ /* 2972 */ {I_VPSLLD, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13944, 188},
+ /* 2973 */ {I_VPSLLD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13952, 188},
+ /* 2974 */ {I_VPSLLQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37624, 188},
+ /* 2975 */ {I_VPSLLQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37631, 188},
+ /* 2976 */ {I_VPSLLQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13960, 188},
+ /* 2977 */ {I_VPSLLQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13968, 188},
+ /* 2978 */ {I_VPSRAW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37638, 188},
+ /* 2979 */ {I_VPSRAW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37645, 188},
+ /* 2980 */ {I_VPSRAW, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13976, 188},
+ /* 2981 */ {I_VPSRAW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+13984, 188},
+ /* 2982 */ {I_VPSRAD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37652, 188},
+ /* 2983 */ {I_VPSRAD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37659, 188},
+ /* 2984 */ {I_VPSRAD, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+13992, 188},
+ /* 2985 */ {I_VPSRAD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14000, 188},
+ /* 2986 */ {I_VPSRLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37666, 188},
+ /* 2987 */ {I_VPSRLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37673, 188},
+ /* 2988 */ {I_VPSRLW, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14008, 188},
+ /* 2989 */ {I_VPSRLW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14016, 188},
+ /* 2990 */ {I_VPSRLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37680, 188},
+ /* 2991 */ {I_VPSRLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37687, 188},
+ /* 2992 */ {I_VPSRLD, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14024, 188},
+ /* 2993 */ {I_VPSRLD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14032, 188},
+ /* 2994 */ {I_VPSRLQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37694, 188},
+ /* 2995 */ {I_VPSRLQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37701, 188},
+ /* 2996 */ {I_VPSRLQ, 3, {XMM_L16,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14040, 188},
+ /* 2997 */ {I_VPSRLQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+14048, 188},
+ /* 2998 */ {I_VPTEST, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37708, 188},
+ /* 2999 */ {I_VPTEST, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37715, 188},
+ /* 3000 */ {I_VPSUBB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37722, 188},
+ /* 3001 */ {I_VPSUBB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37729, 188},
+ /* 3002 */ {I_VPSUBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37736, 188},
+ /* 3003 */ {I_VPSUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37743, 188},
+ /* 3004 */ {I_VPSUBD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37750, 188},
+ /* 3005 */ {I_VPSUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37757, 188},
+ /* 3006 */ {I_VPSUBQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37764, 188},
+ /* 3007 */ {I_VPSUBQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37771, 188},
+ /* 3008 */ {I_VPSUBSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37778, 188},
+ /* 3009 */ {I_VPSUBSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37785, 188},
+ /* 3010 */ {I_VPSUBSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37792, 188},
+ /* 3011 */ {I_VPSUBSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37799, 188},
+ /* 3012 */ {I_VPSUBUSB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37806, 188},
+ /* 3013 */ {I_VPSUBUSB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37813, 188},
+ /* 3014 */ {I_VPSUBUSW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37820, 188},
+ /* 3015 */ {I_VPSUBUSW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37827, 188},
+ /* 3016 */ {I_VPUNPCKHBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37834, 188},
+ /* 3017 */ {I_VPUNPCKHBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37841, 188},
+ /* 3018 */ {I_VPUNPCKHWD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37848, 188},
+ /* 3019 */ {I_VPUNPCKHWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37855, 188},
+ /* 3020 */ {I_VPUNPCKHDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37862, 188},
+ /* 3021 */ {I_VPUNPCKHDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37869, 188},
+ /* 3022 */ {I_VPUNPCKHQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37876, 188},
+ /* 3023 */ {I_VPUNPCKHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37883, 188},
+ /* 3024 */ {I_VPUNPCKLBW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37890, 188},
+ /* 3025 */ {I_VPUNPCKLBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37897, 188},
+ /* 3026 */ {I_VPUNPCKLWD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37904, 188},
+ /* 3027 */ {I_VPUNPCKLWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37911, 188},
+ /* 3028 */ {I_VPUNPCKLDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37918, 188},
+ /* 3029 */ {I_VPUNPCKLDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37925, 188},
+ /* 3030 */ {I_VPUNPCKLQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37932, 188},
+ /* 3031 */ {I_VPUNPCKLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37939, 188},
+ /* 3032 */ {I_VPXOR, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+37946, 188},
+ /* 3033 */ {I_VPXOR, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37953, 188},
+ /* 3034 */ {I_VRCPPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37960, 188},
+ /* 3035 */ {I_VRCPPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37967, 188},
+ /* 3036 */ {I_VRCPSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+37974, 188},
+ /* 3037 */ {I_VRCPSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+37981, 188},
+ /* 3038 */ {I_VRSQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+37988, 188},
+ /* 3039 */ {I_VRSQRTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+37995, 188},
+ /* 3040 */ {I_VRSQRTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38002, 188},
+ /* 3041 */ {I_VRSQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38009, 188},
+ /* 3042 */ {I_VROUNDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14056, 188},
+ /* 3043 */ {I_VROUNDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14064, 188},
+ /* 3044 */ {I_VROUNDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14072, 188},
+ /* 3045 */ {I_VROUNDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14080, 188},
+ /* 3046 */ {I_VROUNDSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14088, 188},
+ /* 3047 */ {I_VROUNDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14096, 188},
+ /* 3048 */ {I_VROUNDSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14104, 188},
+ /* 3049 */ {I_VROUNDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14112, 188},
+ /* 3050 */ {I_VSHUFPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14120, 188},
+ /* 3051 */ {I_VSHUFPD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14128, 188},
+ /* 3052 */ {I_VSHUFPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14136, 188},
+ /* 3053 */ {I_VSHUFPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14144, 188},
+ /* 3054 */ {I_VSHUFPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14152, 188},
+ /* 3055 */ {I_VSHUFPS, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14160, 188},
+ /* 3056 */ {I_VSHUFPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14168, 188},
+ /* 3057 */ {I_VSHUFPS, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14176, 188},
+ /* 3058 */ {I_VSQRTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38016, 188},
+ /* 3059 */ {I_VSQRTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38023, 188},
+ /* 3060 */ {I_VSQRTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38030, 188},
+ /* 3061 */ {I_VSQRTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38037, 188},
+ /* 3062 */ {I_VSQRTSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38044, 188},
+ /* 3063 */ {I_VSQRTSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+38051, 188},
+ /* 3064 */ {I_VSQRTSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38058, 188},
+ /* 3065 */ {I_VSQRTSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38065, 188},
+ /* 3066 */ {I_VSTMXCSR, 1, {MEMORY|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+38072, 188},
+ /* 3067 */ {I_VSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38079, 188},
+ /* 3068 */ {I_VSUBPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38086, 188},
+ /* 3069 */ {I_VSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38093, 188},
+ /* 3070 */ {I_VSUBPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38100, 188},
+ /* 3071 */ {I_VSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38107, 188},
+ /* 3072 */ {I_VSUBPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38114, 188},
+ /* 3073 */ {I_VSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38121, 188},
+ /* 3074 */ {I_VSUBPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38128, 188},
+ /* 3075 */ {I_VSUBSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38135, 188},
+ /* 3076 */ {I_VSUBSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+38142, 188},
+ /* 3077 */ {I_VSUBSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38149, 188},
+ /* 3078 */ {I_VSUBSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38156, 188},
+ /* 3079 */ {I_VTESTPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38163, 188},
+ /* 3080 */ {I_VTESTPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38170, 188},
+ /* 3081 */ {I_VTESTPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38177, 188},
+ /* 3082 */ {I_VTESTPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38184, 188},
+ /* 3083 */ {I_VUCOMISD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+38191, 188},
+ /* 3084 */ {I_VUCOMISS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+38198, 188},
+ /* 3085 */ {I_VUNPCKHPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38205, 188},
+ /* 3086 */ {I_VUNPCKHPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38212, 188},
+ /* 3087 */ {I_VUNPCKHPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38219, 188},
+ /* 3088 */ {I_VUNPCKHPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38226, 188},
+ /* 3089 */ {I_VUNPCKHPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38233, 188},
+ /* 3090 */ {I_VUNPCKHPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38240, 188},
+ /* 3091 */ {I_VUNPCKHPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38247, 188},
+ /* 3092 */ {I_VUNPCKHPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38254, 188},
+ /* 3093 */ {I_VUNPCKLPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38261, 188},
+ /* 3094 */ {I_VUNPCKLPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38268, 188},
+ /* 3095 */ {I_VUNPCKLPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38275, 188},
+ /* 3096 */ {I_VUNPCKLPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38282, 188},
+ /* 3097 */ {I_VUNPCKLPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38289, 188},
+ /* 3098 */ {I_VUNPCKLPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38296, 188},
+ /* 3099 */ {I_VUNPCKLPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38303, 188},
+ /* 3100 */ {I_VUNPCKLPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38310, 188},
+ /* 3101 */ {I_VXORPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38317, 188},
+ /* 3102 */ {I_VXORPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38324, 188},
+ /* 3103 */ {I_VXORPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38331, 188},
+ /* 3104 */ {I_VXORPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38338, 188},
+ /* 3105 */ {I_VXORPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38345, 188},
+ /* 3106 */ {I_VXORPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+38352, 188},
+ /* 3107 */ {I_VXORPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38359, 188},
+ /* 3108 */ {I_VXORPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+38366, 188},
+ /* 3109 */ {I_VZEROALL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45759, 188},
+ /* 3110 */ {I_VZEROUPPER, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45765, 188},
+ /* 3111 */ {I_PCLMULLQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7768, 187},
+ /* 3112 */ {I_PCLMULHQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7777, 187},
+ /* 3113 */ {I_PCLMULLQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7786, 187},
+ /* 3114 */ {I_PCLMULHQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7795, 187},
+ /* 3115 */ {I_PCLMULQDQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14184, 187},
+ /* 3116 */ {I_VPCLMULLQLQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7804, 188},
+ /* 3117 */ {I_VPCLMULLQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7813, 188},
+ /* 3118 */ {I_VPCLMULHQLQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7822, 188},
+ /* 3119 */ {I_VPCLMULHQLQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7831, 188},
+ /* 3120 */ {I_VPCLMULLQHQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7840, 188},
+ /* 3121 */ {I_VPCLMULLQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7849, 188},
+ /* 3122 */ {I_VPCLMULHQHQDQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+7858, 188},
+ /* 3123 */ {I_VPCLMULHQHQDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+7867, 188},
+ /* 3124 */ {I_VPCLMULQDQ, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14192, 188},
+ /* 3125 */ {I_VPCLMULQDQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14200, 188},
+ /* 3126 */ {I_VPCLMULLQLQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7876, 198},
+ /* 3127 */ {I_VPCLMULLQLQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7885, 198},
+ /* 3128 */ {I_VPCLMULHQLQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7894, 198},
+ /* 3129 */ {I_VPCLMULHQLQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7903, 198},
+ /* 3130 */ {I_VPCLMULLQHQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7912, 198},
+ /* 3131 */ {I_VPCLMULLQHQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7921, 198},
+ /* 3132 */ {I_VPCLMULHQHQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+7930, 198},
+ /* 3133 */ {I_VPCLMULHQHQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+7939, 198},
+ /* 3134 */ {I_VPCLMULQDQ, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+14208, 198},
+ /* 3135 */ {I_VPCLMULQDQ, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14216, 198},
+ /* 3136 */ {I_VPCLMULLQLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+0, 199},
+ /* 3137 */ {I_VPCLMULLQLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+10, 199},
+ /* 3138 */ {I_VPCLMULHQLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+20, 199},
+ /* 3139 */ {I_VPCLMULHQLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+30, 199},
+ /* 3140 */ {I_VPCLMULLQHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40, 199},
+ /* 3141 */ {I_VPCLMULLQHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+50, 199},
+ /* 3142 */ {I_VPCLMULHQHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+60, 199},
+ /* 3143 */ {I_VPCLMULHQHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+70, 199},
+ /* 3144 */ {I_VPCLMULQDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+7948, 199},
+ /* 3145 */ {I_VPCLMULQDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+7957, 199},
+ /* 3146 */ {I_VPCLMULLQLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+80, 199},
+ /* 3147 */ {I_VPCLMULLQLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+90, 199},
+ /* 3148 */ {I_VPCLMULHQLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+100, 199},
+ /* 3149 */ {I_VPCLMULHQLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+110, 199},
+ /* 3150 */ {I_VPCLMULLQHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+120, 199},
+ /* 3151 */ {I_VPCLMULLQHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+130, 199},
+ /* 3152 */ {I_VPCLMULHQHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+140, 199},
+ /* 3153 */ {I_VPCLMULHQHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+150, 199},
+ /* 3154 */ {I_VPCLMULQDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+7966, 199},
+ /* 3155 */ {I_VPCLMULQDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+7975, 199},
+ /* 3156 */ {I_VPCLMULLQLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+160, 200},
+ /* 3157 */ {I_VPCLMULLQLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+170, 200},
+ /* 3158 */ {I_VPCLMULHQLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+180, 200},
+ /* 3159 */ {I_VPCLMULHQLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+190, 200},
+ /* 3160 */ {I_VPCLMULLQHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+200, 200},
+ /* 3161 */ {I_VPCLMULLQHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+210, 200},
+ /* 3162 */ {I_VPCLMULHQHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+220, 200},
+ /* 3163 */ {I_VPCLMULHQHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+230, 200},
+ /* 3164 */ {I_VPCLMULQDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+7984, 200},
+ /* 3165 */ {I_VPCLMULQDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+7993, 200},
+ /* 3166 */ {I_VFMADD132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38373, 201},
+ /* 3167 */ {I_VFMADD132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38380, 201},
+ /* 3168 */ {I_VFMADD132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38387, 201},
+ /* 3169 */ {I_VFMADD132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38394, 201},
+ /* 3170 */ {I_VFMADD312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38373, 201},
+ /* 3171 */ {I_VFMADD312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38380, 201},
+ /* 3172 */ {I_VFMADD312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38387, 201},
+ /* 3173 */ {I_VFMADD312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38394, 201},
+ /* 3174 */ {I_VFMADD213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38401, 201},
+ /* 3175 */ {I_VFMADD213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38408, 201},
+ /* 3176 */ {I_VFMADD213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38415, 201},
+ /* 3177 */ {I_VFMADD213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38422, 201},
+ /* 3178 */ {I_VFMADD123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38401, 201},
+ /* 3179 */ {I_VFMADD123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38408, 201},
+ /* 3180 */ {I_VFMADD123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38415, 201},
+ /* 3181 */ {I_VFMADD123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38422, 201},
+ /* 3182 */ {I_VFMADD231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38429, 201},
+ /* 3183 */ {I_VFMADD231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38436, 201},
+ /* 3184 */ {I_VFMADD231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38443, 201},
+ /* 3185 */ {I_VFMADD231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38450, 201},
+ /* 3186 */ {I_VFMADD321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38429, 201},
+ /* 3187 */ {I_VFMADD321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38436, 201},
+ /* 3188 */ {I_VFMADD321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38443, 201},
+ /* 3189 */ {I_VFMADD321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38450, 201},
+ /* 3190 */ {I_VFMADDSUB132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38457, 201},
+ /* 3191 */ {I_VFMADDSUB132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38464, 201},
+ /* 3192 */ {I_VFMADDSUB132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38471, 201},
+ /* 3193 */ {I_VFMADDSUB132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38478, 201},
+ /* 3194 */ {I_VFMADDSUB312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38457, 201},
+ /* 3195 */ {I_VFMADDSUB312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38464, 201},
+ /* 3196 */ {I_VFMADDSUB312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38471, 201},
+ /* 3197 */ {I_VFMADDSUB312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38478, 201},
+ /* 3198 */ {I_VFMADDSUB213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38485, 201},
+ /* 3199 */ {I_VFMADDSUB213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38492, 201},
+ /* 3200 */ {I_VFMADDSUB213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38499, 201},
+ /* 3201 */ {I_VFMADDSUB213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38506, 201},
+ /* 3202 */ {I_VFMADDSUB123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38485, 201},
+ /* 3203 */ {I_VFMADDSUB123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38492, 201},
+ /* 3204 */ {I_VFMADDSUB123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38499, 201},
+ /* 3205 */ {I_VFMADDSUB123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38506, 201},
+ /* 3206 */ {I_VFMADDSUB231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38513, 201},
+ /* 3207 */ {I_VFMADDSUB231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38520, 201},
+ /* 3208 */ {I_VFMADDSUB231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38527, 201},
+ /* 3209 */ {I_VFMADDSUB231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38534, 201},
+ /* 3210 */ {I_VFMADDSUB321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38513, 201},
+ /* 3211 */ {I_VFMADDSUB321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38520, 201},
+ /* 3212 */ {I_VFMADDSUB321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38527, 201},
+ /* 3213 */ {I_VFMADDSUB321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38534, 201},
+ /* 3214 */ {I_VFMSUB132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38541, 201},
+ /* 3215 */ {I_VFMSUB132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38548, 201},
+ /* 3216 */ {I_VFMSUB132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38555, 201},
+ /* 3217 */ {I_VFMSUB132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38562, 201},
+ /* 3218 */ {I_VFMSUB312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38541, 201},
+ /* 3219 */ {I_VFMSUB312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38548, 201},
+ /* 3220 */ {I_VFMSUB312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38555, 201},
+ /* 3221 */ {I_VFMSUB312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38562, 201},
+ /* 3222 */ {I_VFMSUB213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38569, 201},
+ /* 3223 */ {I_VFMSUB213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38576, 201},
+ /* 3224 */ {I_VFMSUB213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38583, 201},
+ /* 3225 */ {I_VFMSUB213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38590, 201},
+ /* 3226 */ {I_VFMSUB123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38569, 201},
+ /* 3227 */ {I_VFMSUB123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38576, 201},
+ /* 3228 */ {I_VFMSUB123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38583, 201},
+ /* 3229 */ {I_VFMSUB123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38590, 201},
+ /* 3230 */ {I_VFMSUB231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38597, 201},
+ /* 3231 */ {I_VFMSUB231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38604, 201},
+ /* 3232 */ {I_VFMSUB231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38611, 201},
+ /* 3233 */ {I_VFMSUB231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38618, 201},
+ /* 3234 */ {I_VFMSUB321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38597, 201},
+ /* 3235 */ {I_VFMSUB321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38604, 201},
+ /* 3236 */ {I_VFMSUB321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38611, 201},
+ /* 3237 */ {I_VFMSUB321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38618, 201},
+ /* 3238 */ {I_VFMSUBADD132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38625, 201},
+ /* 3239 */ {I_VFMSUBADD132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38632, 201},
+ /* 3240 */ {I_VFMSUBADD132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38639, 201},
+ /* 3241 */ {I_VFMSUBADD132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38646, 201},
+ /* 3242 */ {I_VFMSUBADD312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38625, 201},
+ /* 3243 */ {I_VFMSUBADD312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38632, 201},
+ /* 3244 */ {I_VFMSUBADD312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38639, 201},
+ /* 3245 */ {I_VFMSUBADD312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38646, 201},
+ /* 3246 */ {I_VFMSUBADD213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38653, 201},
+ /* 3247 */ {I_VFMSUBADD213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38660, 201},
+ /* 3248 */ {I_VFMSUBADD213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38667, 201},
+ /* 3249 */ {I_VFMSUBADD213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38674, 201},
+ /* 3250 */ {I_VFMSUBADD123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38653, 201},
+ /* 3251 */ {I_VFMSUBADD123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38660, 201},
+ /* 3252 */ {I_VFMSUBADD123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38667, 201},
+ /* 3253 */ {I_VFMSUBADD123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38674, 201},
+ /* 3254 */ {I_VFMSUBADD231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38681, 201},
+ /* 3255 */ {I_VFMSUBADD231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38688, 201},
+ /* 3256 */ {I_VFMSUBADD231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38695, 201},
+ /* 3257 */ {I_VFMSUBADD231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38702, 201},
+ /* 3258 */ {I_VFMSUBADD321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38681, 201},
+ /* 3259 */ {I_VFMSUBADD321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38688, 201},
+ /* 3260 */ {I_VFMSUBADD321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38695, 201},
+ /* 3261 */ {I_VFMSUBADD321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38702, 201},
+ /* 3262 */ {I_VFNMADD132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38709, 201},
+ /* 3263 */ {I_VFNMADD132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38716, 201},
+ /* 3264 */ {I_VFNMADD132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38723, 201},
+ /* 3265 */ {I_VFNMADD132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38730, 201},
+ /* 3266 */ {I_VFNMADD312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38709, 201},
+ /* 3267 */ {I_VFNMADD312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38716, 201},
+ /* 3268 */ {I_VFNMADD312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38723, 201},
+ /* 3269 */ {I_VFNMADD312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38730, 201},
+ /* 3270 */ {I_VFNMADD213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38737, 201},
+ /* 3271 */ {I_VFNMADD213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38744, 201},
+ /* 3272 */ {I_VFNMADD213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38751, 201},
+ /* 3273 */ {I_VFNMADD213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38758, 201},
+ /* 3274 */ {I_VFNMADD123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38737, 201},
+ /* 3275 */ {I_VFNMADD123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38744, 201},
+ /* 3276 */ {I_VFNMADD123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38751, 201},
+ /* 3277 */ {I_VFNMADD123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38758, 201},
+ /* 3278 */ {I_VFNMADD231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38765, 201},
+ /* 3279 */ {I_VFNMADD231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38772, 201},
+ /* 3280 */ {I_VFNMADD231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38779, 201},
+ /* 3281 */ {I_VFNMADD231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38786, 201},
+ /* 3282 */ {I_VFNMADD321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38765, 201},
+ /* 3283 */ {I_VFNMADD321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38772, 201},
+ /* 3284 */ {I_VFNMADD321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38779, 201},
+ /* 3285 */ {I_VFNMADD321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38786, 201},
+ /* 3286 */ {I_VFNMSUB132PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38793, 201},
+ /* 3287 */ {I_VFNMSUB132PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38800, 201},
+ /* 3288 */ {I_VFNMSUB132PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38807, 201},
+ /* 3289 */ {I_VFNMSUB132PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38814, 201},
+ /* 3290 */ {I_VFNMSUB312PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38793, 201},
+ /* 3291 */ {I_VFNMSUB312PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38800, 201},
+ /* 3292 */ {I_VFNMSUB312PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38807, 201},
+ /* 3293 */ {I_VFNMSUB312PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38814, 201},
+ /* 3294 */ {I_VFNMSUB213PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38821, 201},
+ /* 3295 */ {I_VFNMSUB213PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38828, 201},
+ /* 3296 */ {I_VFNMSUB213PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38835, 201},
+ /* 3297 */ {I_VFNMSUB213PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38842, 201},
+ /* 3298 */ {I_VFNMSUB123PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38821, 201},
+ /* 3299 */ {I_VFNMSUB123PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38828, 201},
+ /* 3300 */ {I_VFNMSUB123PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38835, 201},
+ /* 3301 */ {I_VFNMSUB123PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38842, 201},
+ /* 3302 */ {I_VFNMSUB231PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38849, 201},
+ /* 3303 */ {I_VFNMSUB231PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38856, 201},
+ /* 3304 */ {I_VFNMSUB231PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38863, 201},
+ /* 3305 */ {I_VFNMSUB231PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38870, 201},
+ /* 3306 */ {I_VFNMSUB321PS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38849, 201},
+ /* 3307 */ {I_VFNMSUB321PS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38856, 201},
+ /* 3308 */ {I_VFNMSUB321PD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+38863, 201},
+ /* 3309 */ {I_VFNMSUB321PD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+38870, 201},
+ /* 3310 */ {I_VFMADD132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38877, 201},
+ /* 3311 */ {I_VFMADD132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38884, 201},
+ /* 3312 */ {I_VFMADD312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38877, 201},
+ /* 3313 */ {I_VFMADD312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38884, 201},
+ /* 3314 */ {I_VFMADD213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38891, 201},
+ /* 3315 */ {I_VFMADD213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38898, 201},
+ /* 3316 */ {I_VFMADD123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38891, 201},
+ /* 3317 */ {I_VFMADD123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38898, 201},
+ /* 3318 */ {I_VFMADD231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38905, 201},
+ /* 3319 */ {I_VFMADD231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38912, 201},
+ /* 3320 */ {I_VFMADD321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38905, 201},
+ /* 3321 */ {I_VFMADD321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38912, 201},
+ /* 3322 */ {I_VFMSUB132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38919, 201},
+ /* 3323 */ {I_VFMSUB132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38926, 201},
+ /* 3324 */ {I_VFMSUB312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38919, 201},
+ /* 3325 */ {I_VFMSUB312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38926, 201},
+ /* 3326 */ {I_VFMSUB213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38933, 201},
+ /* 3327 */ {I_VFMSUB213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38940, 201},
+ /* 3328 */ {I_VFMSUB123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38933, 201},
+ /* 3329 */ {I_VFMSUB123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38940, 201},
+ /* 3330 */ {I_VFMSUB231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38947, 201},
+ /* 3331 */ {I_VFMSUB231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38954, 201},
+ /* 3332 */ {I_VFMSUB321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38947, 201},
+ /* 3333 */ {I_VFMSUB321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38954, 201},
+ /* 3334 */ {I_VFNMADD132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38961, 201},
+ /* 3335 */ {I_VFNMADD132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38968, 201},
+ /* 3336 */ {I_VFNMADD312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38961, 201},
+ /* 3337 */ {I_VFNMADD312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38968, 201},
+ /* 3338 */ {I_VFNMADD213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38975, 201},
+ /* 3339 */ {I_VFNMADD213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38982, 201},
+ /* 3340 */ {I_VFNMADD123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38975, 201},
+ /* 3341 */ {I_VFNMADD123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38982, 201},
+ /* 3342 */ {I_VFNMADD231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38989, 201},
+ /* 3343 */ {I_VFNMADD231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38996, 201},
+ /* 3344 */ {I_VFNMADD321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+38989, 201},
+ /* 3345 */ {I_VFNMADD321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+38996, 201},
+ /* 3346 */ {I_VFNMSUB132SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39003, 201},
+ /* 3347 */ {I_VFNMSUB132SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39010, 201},
+ /* 3348 */ {I_VFNMSUB312SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39003, 201},
+ /* 3349 */ {I_VFNMSUB312SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39010, 201},
+ /* 3350 */ {I_VFNMSUB213SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39017, 201},
+ /* 3351 */ {I_VFNMSUB213SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39024, 201},
+ /* 3352 */ {I_VFNMSUB123SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39017, 201},
+ /* 3353 */ {I_VFNMSUB123SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39024, 201},
+ /* 3354 */ {I_VFNMSUB231SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39031, 201},
+ /* 3355 */ {I_VFNMSUB231SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39038, 201},
+ /* 3356 */ {I_VFNMSUB321SS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+39031, 201},
+ /* 3357 */ {I_VFNMSUB321SD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+39038, 201},
+ /* 3358 */ {I_RDFSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39045, 136},
+ /* 3359 */ {I_RDFSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39052, 136},
+ /* 3360 */ {I_RDGSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39059, 136},
+ /* 3361 */ {I_RDGSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39066, 136},
+ /* 3362 */ {I_RDRAND, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45771, 135},
+ /* 3363 */ {I_RDRAND, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45777, 135},
+ /* 3364 */ {I_RDRAND, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45783, 136},
+ /* 3365 */ {I_WRFSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39073, 136},
+ /* 3366 */ {I_WRFSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39080, 136},
+ /* 3367 */ {I_WRGSBASE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39087, 136},
+ /* 3368 */ {I_WRGSBASE, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39094, 136},
+ /* 3369 */ {I_VCVTPH2PS, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39101, 202},
+ /* 3370 */ {I_VCVTPH2PS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+39108, 202},
+ /* 3371 */ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14224, 202},
+ /* 3372 */ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14232, 202},
+ /* 3373 */ {I_ADCX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+14240, 135},
+ /* 3374 */ {I_ADCX, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+14248, 136},
+ /* 3375 */ {I_ADOX, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+14256, 135},
+ /* 3376 */ {I_ADOX, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+14264, 136},
+ /* 3377 */ {I_RDSEED, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45789, 135},
+ /* 3378 */ {I_RDSEED, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45795, 135},
+ /* 3379 */ {I_RDSEED, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45801, 136},
+ /* 3380 */ {I_CLAC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49147, 203},
+ /* 3381 */ {I_STAC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49152, 203},
+ /* 3382 */ {I_XSTORE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49157, 32},
+ /* 3383 */ {I_XCRYPTECB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45807, 32},
+ /* 3384 */ {I_XCRYPTCBC, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45813, 32},
+ /* 3385 */ {I_XCRYPTCTR, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45819, 32},
+ /* 3386 */ {I_XCRYPTCFB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45825, 32},
+ /* 3387 */ {I_XCRYPTOFB, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45831, 32},
+ /* 3388 */ {I_MONTMUL, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45837, 32},
+ /* 3389 */ {I_XSHA1, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45843, 32},
+ /* 3390 */ {I_XSHA256, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45849, 32},
+ /* 3391 */ {I_LLWPCB, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39115, 204},
+ /* 3392 */ {I_LLWPCB, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39122, 205},
+ /* 3393 */ {I_SLWPCB, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39129, 204},
+ /* 3394 */ {I_SLWPCB, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39136, 205},
+ /* 3395 */ {I_LWPVAL, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14272, 204},
+ /* 3396 */ {I_LWPVAL, 3, {REG_GPR|BITS64,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14280, 205},
+ /* 3397 */ {I_LWPINS, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14288, 204},
+ /* 3398 */ {I_LWPINS, 3, {REG_GPR|BITS64,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14296, 205},
+ /* 3399 */ {I_VFMADDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14304, 206},
+ /* 3400 */ {I_VFMADDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14312, 206},
+ /* 3401 */ {I_VFMADDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14320, 206},
+ /* 3402 */ {I_VFMADDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14328, 206},
+ /* 3403 */ {I_VFMADDPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14336, 206},
+ /* 3404 */ {I_VFMADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14344, 206},
+ /* 3405 */ {I_VFMADDPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14352, 206},
+ /* 3406 */ {I_VFMADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14360, 206},
+ /* 3407 */ {I_VFMADDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14368, 206},
+ /* 3408 */ {I_VFMADDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14376, 206},
+ /* 3409 */ {I_VFMADDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14384, 206},
+ /* 3410 */ {I_VFMADDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14392, 206},
+ /* 3411 */ {I_VFMADDPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14400, 206},
+ /* 3412 */ {I_VFMADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14408, 206},
+ /* 3413 */ {I_VFMADDPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14416, 206},
+ /* 3414 */ {I_VFMADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14424, 206},
+ /* 3415 */ {I_VFMADDSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14432, 206},
+ /* 3416 */ {I_VFMADDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14440, 206},
+ /* 3417 */ {I_VFMADDSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+14448, 206},
+ /* 3418 */ {I_VFMADDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14456, 206},
+ /* 3419 */ {I_VFMADDSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14464, 206},
+ /* 3420 */ {I_VFMADDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14472, 206},
+ /* 3421 */ {I_VFMADDSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+14480, 206},
+ /* 3422 */ {I_VFMADDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14488, 206},
+ /* 3423 */ {I_VFMADDSUBPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14496, 206},
+ /* 3424 */ {I_VFMADDSUBPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14504, 206},
+ /* 3425 */ {I_VFMADDSUBPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14512, 206},
+ /* 3426 */ {I_VFMADDSUBPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14520, 206},
+ /* 3427 */ {I_VFMADDSUBPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14528, 206},
+ /* 3428 */ {I_VFMADDSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14536, 206},
+ /* 3429 */ {I_VFMADDSUBPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14544, 206},
+ /* 3430 */ {I_VFMADDSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14552, 206},
+ /* 3431 */ {I_VFMADDSUBPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14560, 206},
+ /* 3432 */ {I_VFMADDSUBPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14568, 206},
+ /* 3433 */ {I_VFMADDSUBPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14576, 206},
+ /* 3434 */ {I_VFMADDSUBPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14584, 206},
+ /* 3435 */ {I_VFMADDSUBPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14592, 206},
+ /* 3436 */ {I_VFMADDSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14600, 206},
+ /* 3437 */ {I_VFMADDSUBPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14608, 206},
+ /* 3438 */ {I_VFMADDSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14616, 206},
+ /* 3439 */ {I_VFMSUBADDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14624, 206},
+ /* 3440 */ {I_VFMSUBADDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14632, 206},
+ /* 3441 */ {I_VFMSUBADDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14640, 206},
+ /* 3442 */ {I_VFMSUBADDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14648, 206},
+ /* 3443 */ {I_VFMSUBADDPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14656, 206},
+ /* 3444 */ {I_VFMSUBADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14664, 206},
+ /* 3445 */ {I_VFMSUBADDPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14672, 206},
+ /* 3446 */ {I_VFMSUBADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14680, 206},
+ /* 3447 */ {I_VFMSUBADDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14688, 206},
+ /* 3448 */ {I_VFMSUBADDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14696, 206},
+ /* 3449 */ {I_VFMSUBADDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14704, 206},
+ /* 3450 */ {I_VFMSUBADDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14712, 206},
+ /* 3451 */ {I_VFMSUBADDPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14720, 206},
+ /* 3452 */ {I_VFMSUBADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14728, 206},
+ /* 3453 */ {I_VFMSUBADDPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14736, 206},
+ /* 3454 */ {I_VFMSUBADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14744, 206},
+ /* 3455 */ {I_VFMSUBPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14752, 206},
+ /* 3456 */ {I_VFMSUBPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14760, 206},
+ /* 3457 */ {I_VFMSUBPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14768, 206},
+ /* 3458 */ {I_VFMSUBPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14776, 206},
+ /* 3459 */ {I_VFMSUBPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14784, 206},
+ /* 3460 */ {I_VFMSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14792, 206},
+ /* 3461 */ {I_VFMSUBPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14800, 206},
+ /* 3462 */ {I_VFMSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14808, 206},
+ /* 3463 */ {I_VFMSUBPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14816, 206},
+ /* 3464 */ {I_VFMSUBPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14824, 206},
+ /* 3465 */ {I_VFMSUBPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14832, 206},
+ /* 3466 */ {I_VFMSUBPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14840, 206},
+ /* 3467 */ {I_VFMSUBPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14848, 206},
+ /* 3468 */ {I_VFMSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14856, 206},
+ /* 3469 */ {I_VFMSUBPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14864, 206},
+ /* 3470 */ {I_VFMSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+14872, 206},
+ /* 3471 */ {I_VFMSUBSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14880, 206},
+ /* 3472 */ {I_VFMSUBSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14888, 206},
+ /* 3473 */ {I_VFMSUBSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+14896, 206},
+ /* 3474 */ {I_VFMSUBSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+14904, 206},
+ /* 3475 */ {I_VFMSUBSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14912, 206},
+ /* 3476 */ {I_VFMSUBSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14920, 206},
+ /* 3477 */ {I_VFMSUBSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+14928, 206},
+ /* 3478 */ {I_VFMSUBSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+14936, 206},
+ /* 3479 */ {I_VFNMADDPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14944, 206},
+ /* 3480 */ {I_VFNMADDPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14952, 206},
+ /* 3481 */ {I_VFNMADDPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+14960, 206},
+ /* 3482 */ {I_VFNMADDPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+14968, 206},
+ /* 3483 */ {I_VFNMADDPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+14976, 206},
+ /* 3484 */ {I_VFNMADDPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+14984, 206},
+ /* 3485 */ {I_VFNMADDPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+14992, 206},
+ /* 3486 */ {I_VFNMADDPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15000, 206},
+ /* 3487 */ {I_VFNMADDPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15008, 206},
+ /* 3488 */ {I_VFNMADDPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15016, 206},
+ /* 3489 */ {I_VFNMADDPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15024, 206},
+ /* 3490 */ {I_VFNMADDPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15032, 206},
+ /* 3491 */ {I_VFNMADDPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15040, 206},
+ /* 3492 */ {I_VFNMADDPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15048, 206},
+ /* 3493 */ {I_VFNMADDPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15056, 206},
+ /* 3494 */ {I_VFNMADDPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15064, 206},
+ /* 3495 */ {I_VFNMADDSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15072, 206},
+ /* 3496 */ {I_VFNMADDSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15080, 206},
+ /* 3497 */ {I_VFNMADDSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+15088, 206},
+ /* 3498 */ {I_VFNMADDSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15096, 206},
+ /* 3499 */ {I_VFNMADDSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15104, 206},
+ /* 3500 */ {I_VFNMADDSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15112, 206},
+ /* 3501 */ {I_VFNMADDSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+15120, 206},
+ /* 3502 */ {I_VFNMADDSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15128, 206},
+ /* 3503 */ {I_VFNMSUBPD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15136, 206},
+ /* 3504 */ {I_VFNMSUBPD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15144, 206},
+ /* 3505 */ {I_VFNMSUBPD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15152, 206},
+ /* 3506 */ {I_VFNMSUBPD, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15160, 206},
+ /* 3507 */ {I_VFNMSUBPD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15168, 206},
+ /* 3508 */ {I_VFNMSUBPD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15176, 206},
+ /* 3509 */ {I_VFNMSUBPD, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15184, 206},
+ /* 3510 */ {I_VFNMSUBPD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15192, 206},
+ /* 3511 */ {I_VFNMSUBPS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15200, 206},
+ /* 3512 */ {I_VFNMSUBPS, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15208, 206},
+ /* 3513 */ {I_VFNMSUBPS, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15216, 206},
+ /* 3514 */ {I_VFNMSUBPS, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15224, 206},
+ /* 3515 */ {I_VFNMSUBPS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15232, 206},
+ /* 3516 */ {I_VFNMSUBPS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15240, 206},
+ /* 3517 */ {I_VFNMSUBPS, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15248, 206},
+ /* 3518 */ {I_VFNMSUBPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15256, 206},
+ /* 3519 */ {I_VFNMSUBSD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15264, 206},
+ /* 3520 */ {I_VFNMSUBSD, 3, {XMM_L16,RM_XMM_L16|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15272, 206},
+ /* 3521 */ {I_VFNMSUBSD, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0}, NO_DECORATOR, nasm_bytecodes+15280, 206},
+ /* 3522 */ {I_VFNMSUBSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+15288, 206},
+ /* 3523 */ {I_VFNMSUBSS, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15296, 206},
+ /* 3524 */ {I_VFNMSUBSS, 3, {XMM_L16,RM_XMM_L16|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15304, 206},
+ /* 3525 */ {I_VFNMSUBSS, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0}, NO_DECORATOR, nasm_bytecodes+15312, 206},
+ /* 3526 */ {I_VFNMSUBSS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+15320, 206},
+ /* 3527 */ {I_VFRCZPD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39143, 206},
+ /* 3528 */ {I_VFRCZPD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39150, 206},
+ /* 3529 */ {I_VFRCZPD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39157, 206},
+ /* 3530 */ {I_VFRCZPD, 1, {YMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39164, 206},
+ /* 3531 */ {I_VFRCZPS, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39171, 206},
+ /* 3532 */ {I_VFRCZPS, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39178, 206},
+ /* 3533 */ {I_VFRCZPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39185, 206},
+ /* 3534 */ {I_VFRCZPS, 1, {YMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39192, 206},
+ /* 3535 */ {I_VFRCZSD, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+39199, 206},
+ /* 3536 */ {I_VFRCZSD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39206, 206},
+ /* 3537 */ {I_VFRCZSS, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+39213, 206},
+ /* 3538 */ {I_VFRCZSS, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39220, 206},
+ /* 3539 */ {I_VPCMOV, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15328, 206},
+ /* 3540 */ {I_VPCMOV, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15336, 206},
+ /* 3541 */ {I_VPCMOV, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15344, 206},
+ /* 3542 */ {I_VPCMOV, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15352, 206},
+ /* 3543 */ {I_VPCMOV, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15360, 206},
+ /* 3544 */ {I_VPCMOV, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15368, 206},
+ /* 3545 */ {I_VPCMOV, 4, {YMM_L16,YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0}, NO_DECORATOR, nasm_bytecodes+15376, 206},
+ /* 3546 */ {I_VPCMOV, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+15384, 206},
+ /* 3547 */ {I_VPCOMB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15392, 206},
+ /* 3548 */ {I_VPCOMB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15400, 206},
+ /* 3549 */ {I_VPCOMD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15408, 206},
+ /* 3550 */ {I_VPCOMD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15416, 206},
+ /* 3551 */ {I_VPCOMQ, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15424, 206},
+ /* 3552 */ {I_VPCOMQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15432, 206},
+ /* 3553 */ {I_VPCOMUB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15440, 206},
+ /* 3554 */ {I_VPCOMUB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15448, 206},
+ /* 3555 */ {I_VPCOMUD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15456, 206},
+ /* 3556 */ {I_VPCOMUD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15464, 206},
+ /* 3557 */ {I_VPCOMUQ, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15472, 206},
+ /* 3558 */ {I_VPCOMUQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15480, 206},
+ /* 3559 */ {I_VPCOMUW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15488, 206},
+ /* 3560 */ {I_VPCOMUW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15496, 206},
+ /* 3561 */ {I_VPCOMW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15504, 206},
+ /* 3562 */ {I_VPCOMW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15512, 206},
+ /* 3563 */ {I_VPHADDBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39227, 206},
+ /* 3564 */ {I_VPHADDBD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39234, 206},
+ /* 3565 */ {I_VPHADDBQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39241, 206},
+ /* 3566 */ {I_VPHADDBQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39248, 206},
+ /* 3567 */ {I_VPHADDBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39255, 206},
+ /* 3568 */ {I_VPHADDBW, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39262, 206},
+ /* 3569 */ {I_VPHADDDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39269, 206},
+ /* 3570 */ {I_VPHADDDQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39276, 206},
+ /* 3571 */ {I_VPHADDUBD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39283, 206},
+ /* 3572 */ {I_VPHADDUBD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39290, 206},
+ /* 3573 */ {I_VPHADDUBQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39297, 206},
+ /* 3574 */ {I_VPHADDUBQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39304, 206},
+ /* 3575 */ {I_VPHADDUBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39311, 206},
+ /* 3576 */ {I_VPHADDUBW, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39318, 206},
+ /* 3577 */ {I_VPHADDUDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39325, 206},
+ /* 3578 */ {I_VPHADDUDQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39332, 206},
+ /* 3579 */ {I_VPHADDUWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39339, 206},
+ /* 3580 */ {I_VPHADDUWD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39346, 206},
+ /* 3581 */ {I_VPHADDUWQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39353, 206},
+ /* 3582 */ {I_VPHADDUWQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39360, 206},
+ /* 3583 */ {I_VPHADDWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39367, 206},
+ /* 3584 */ {I_VPHADDWD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39374, 206},
+ /* 3585 */ {I_VPHADDWQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39381, 206},
+ /* 3586 */ {I_VPHADDWQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39388, 206},
+ /* 3587 */ {I_VPHSUBBW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39395, 206},
+ /* 3588 */ {I_VPHSUBBW, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39402, 206},
+ /* 3589 */ {I_VPHSUBDQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39409, 206},
+ /* 3590 */ {I_VPHSUBDQ, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39416, 206},
+ /* 3591 */ {I_VPHSUBWD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39423, 206},
+ /* 3592 */ {I_VPHSUBWD, 1, {XMM_L16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+39430, 206},
+ /* 3593 */ {I_VPMACSDD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15520, 206},
+ /* 3594 */ {I_VPMACSDD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15528, 206},
+ /* 3595 */ {I_VPMACSDQH, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15536, 206},
+ /* 3596 */ {I_VPMACSDQH, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15544, 206},
+ /* 3597 */ {I_VPMACSDQL, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15552, 206},
+ /* 3598 */ {I_VPMACSDQL, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15560, 206},
+ /* 3599 */ {I_VPMACSSDD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15568, 206},
+ /* 3600 */ {I_VPMACSSDD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15576, 206},
+ /* 3601 */ {I_VPMACSSDQH, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15584, 206},
+ /* 3602 */ {I_VPMACSSDQH, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15592, 206},
+ /* 3603 */ {I_VPMACSSDQL, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15600, 206},
+ /* 3604 */ {I_VPMACSSDQL, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15608, 206},
+ /* 3605 */ {I_VPMACSSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15616, 206},
+ /* 3606 */ {I_VPMACSSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15624, 206},
+ /* 3607 */ {I_VPMACSSWW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15632, 206},
+ /* 3608 */ {I_VPMACSSWW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15640, 206},
+ /* 3609 */ {I_VPMACSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15648, 206},
+ /* 3610 */ {I_VPMACSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15656, 206},
+ /* 3611 */ {I_VPMACSWW, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15664, 206},
+ /* 3612 */ {I_VPMACSWW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15672, 206},
+ /* 3613 */ {I_VPMADCSSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15680, 206},
+ /* 3614 */ {I_VPMADCSSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15688, 206},
+ /* 3615 */ {I_VPMADCSWD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15696, 206},
+ /* 3616 */ {I_VPMADCSWD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15704, 206},
+ /* 3617 */ {I_VPPERM, 4, {XMM_L16,XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0}, NO_DECORATOR, nasm_bytecodes+15712, 206},
+ /* 3618 */ {I_VPPERM, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+15720, 206},
+ /* 3619 */ {I_VPPERM, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15728, 206},
+ /* 3620 */ {I_VPPERM, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15736, 206},
+ /* 3621 */ {I_VPROTB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39437, 206},
+ /* 3622 */ {I_VPROTB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39444, 206},
+ /* 3623 */ {I_VPROTB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39451, 206},
+ /* 3624 */ {I_VPROTB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39458, 206},
+ /* 3625 */ {I_VPROTB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15744, 206},
+ /* 3626 */ {I_VPROTB, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15752, 206},
+ /* 3627 */ {I_VPROTD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39465, 206},
+ /* 3628 */ {I_VPROTD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39472, 206},
+ /* 3629 */ {I_VPROTD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39479, 206},
+ /* 3630 */ {I_VPROTD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39486, 206},
+ /* 3631 */ {I_VPROTD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15760, 206},
+ /* 3632 */ {I_VPROTD, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15768, 206},
+ /* 3633 */ {I_VPROTQ, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39493, 206},
+ /* 3634 */ {I_VPROTQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39500, 206},
+ /* 3635 */ {I_VPROTQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39507, 206},
+ /* 3636 */ {I_VPROTQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39514, 206},
+ /* 3637 */ {I_VPROTQ, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15776, 206},
+ /* 3638 */ {I_VPROTQ, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15784, 206},
+ /* 3639 */ {I_VPROTW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39521, 206},
+ /* 3640 */ {I_VPROTW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39528, 206},
+ /* 3641 */ {I_VPROTW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39535, 206},
+ /* 3642 */ {I_VPROTW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39542, 206},
+ /* 3643 */ {I_VPROTW, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15792, 206},
+ /* 3644 */ {I_VPROTW, 2, {XMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15800, 206},
+ /* 3645 */ {I_VPSHAB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39549, 206},
+ /* 3646 */ {I_VPSHAB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39556, 206},
+ /* 3647 */ {I_VPSHAB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39563, 206},
+ /* 3648 */ {I_VPSHAB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39570, 206},
+ /* 3649 */ {I_VPSHAD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39577, 206},
+ /* 3650 */ {I_VPSHAD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39584, 206},
+ /* 3651 */ {I_VPSHAD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39591, 206},
+ /* 3652 */ {I_VPSHAD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39598, 206},
+ /* 3653 */ {I_VPSHAQ, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39605, 206},
+ /* 3654 */ {I_VPSHAQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39612, 206},
+ /* 3655 */ {I_VPSHAQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39619, 206},
+ /* 3656 */ {I_VPSHAQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39626, 206},
+ /* 3657 */ {I_VPSHAW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39633, 206},
+ /* 3658 */ {I_VPSHAW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39640, 206},
+ /* 3659 */ {I_VPSHAW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39647, 206},
+ /* 3660 */ {I_VPSHAW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39654, 206},
+ /* 3661 */ {I_VPSHLB, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39661, 206},
+ /* 3662 */ {I_VPSHLB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39668, 206},
+ /* 3663 */ {I_VPSHLB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39675, 206},
+ /* 3664 */ {I_VPSHLB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39682, 206},
+ /* 3665 */ {I_VPSHLD, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39689, 206},
+ /* 3666 */ {I_VPSHLD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39696, 206},
+ /* 3667 */ {I_VPSHLD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39703, 206},
+ /* 3668 */ {I_VPSHLD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39710, 206},
+ /* 3669 */ {I_VPSHLQ, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39717, 206},
+ /* 3670 */ {I_VPSHLQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39724, 206},
+ /* 3671 */ {I_VPSHLQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39731, 206},
+ /* 3672 */ {I_VPSHLQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39738, 206},
+ /* 3673 */ {I_VPSHLW, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+39745, 206},
+ /* 3674 */ {I_VPSHLW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+39752, 206},
+ /* 3675 */ {I_VPSHLW, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+39759, 206},
+ /* 3676 */ {I_VPSHLW, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39766, 206},
+ /* 3677 */ {I_VMPSADBW, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15808, 207},
+ /* 3678 */ {I_VMPSADBW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15816, 207},
+ /* 3679 */ {I_VPABSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39773, 207},
+ /* 3680 */ {I_VPABSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39780, 207},
+ /* 3681 */ {I_VPABSD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39787, 207},
+ /* 3682 */ {I_VPACKSSWB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39794, 207},
+ /* 3683 */ {I_VPACKSSWB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39801, 207},
+ /* 3684 */ {I_VPACKSSDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39808, 207},
+ /* 3685 */ {I_VPACKSSDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39815, 207},
+ /* 3686 */ {I_VPACKUSDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39822, 207},
+ /* 3687 */ {I_VPACKUSDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39829, 207},
+ /* 3688 */ {I_VPACKUSWB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39836, 207},
+ /* 3689 */ {I_VPACKUSWB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39843, 207},
+ /* 3690 */ {I_VPADDB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39850, 207},
+ /* 3691 */ {I_VPADDB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39857, 207},
+ /* 3692 */ {I_VPADDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39864, 207},
+ /* 3693 */ {I_VPADDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39871, 207},
+ /* 3694 */ {I_VPADDD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39878, 207},
+ /* 3695 */ {I_VPADDD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39885, 207},
+ /* 3696 */ {I_VPADDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39892, 207},
+ /* 3697 */ {I_VPADDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39899, 207},
+ /* 3698 */ {I_VPADDSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39906, 207},
+ /* 3699 */ {I_VPADDSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39913, 207},
+ /* 3700 */ {I_VPADDSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39920, 207},
+ /* 3701 */ {I_VPADDSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39927, 207},
+ /* 3702 */ {I_VPADDUSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39934, 207},
+ /* 3703 */ {I_VPADDUSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39941, 207},
+ /* 3704 */ {I_VPADDUSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39948, 207},
+ /* 3705 */ {I_VPADDUSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39955, 207},
+ /* 3706 */ {I_VPALIGNR, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15824, 207},
+ /* 3707 */ {I_VPALIGNR, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15832, 207},
+ /* 3708 */ {I_VPAND, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39962, 207},
+ /* 3709 */ {I_VPAND, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39969, 207},
+ /* 3710 */ {I_VPANDN, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39976, 207},
+ /* 3711 */ {I_VPANDN, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39983, 207},
+ /* 3712 */ {I_VPAVGB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+39990, 207},
+ /* 3713 */ {I_VPAVGB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+39997, 207},
+ /* 3714 */ {I_VPAVGW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40004, 207},
+ /* 3715 */ {I_VPAVGW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40011, 207},
+ /* 3716 */ {I_VPBLENDVB, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0}, NO_DECORATOR, nasm_bytecodes+15840, 207},
+ /* 3717 */ {I_VPBLENDVB, 3, {YMM_L16,RM_YMM_L16|BITS256,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+15848, 207},
+ /* 3718 */ {I_VPBLENDW, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+15856, 207},
+ /* 3719 */ {I_VPBLENDW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15864, 207},
+ /* 3720 */ {I_VPCMPEQB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40018, 207},
+ /* 3721 */ {I_VPCMPEQB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40025, 207},
+ /* 3722 */ {I_VPCMPEQW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40032, 207},
+ /* 3723 */ {I_VPCMPEQW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40039, 207},
+ /* 3724 */ {I_VPCMPEQD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40046, 207},
+ /* 3725 */ {I_VPCMPEQD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40053, 207},
+ /* 3726 */ {I_VPCMPEQQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40060, 207},
+ /* 3727 */ {I_VPCMPEQQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40067, 207},
+ /* 3728 */ {I_VPCMPGTB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40074, 207},
+ /* 3729 */ {I_VPCMPGTB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40081, 207},
+ /* 3730 */ {I_VPCMPGTW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40088, 207},
+ /* 3731 */ {I_VPCMPGTW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40095, 207},
+ /* 3732 */ {I_VPCMPGTD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40102, 207},
+ /* 3733 */ {I_VPCMPGTD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40109, 207},
+ /* 3734 */ {I_VPCMPGTQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40116, 207},
+ /* 3735 */ {I_VPCMPGTQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40123, 207},
+ /* 3736 */ {I_VPHADDW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40130, 207},
+ /* 3737 */ {I_VPHADDW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40137, 207},
+ /* 3738 */ {I_VPHADDD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40144, 207},
+ /* 3739 */ {I_VPHADDD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40151, 207},
+ /* 3740 */ {I_VPHADDSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40158, 207},
+ /* 3741 */ {I_VPHADDSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40165, 207},
+ /* 3742 */ {I_VPHSUBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40172, 207},
+ /* 3743 */ {I_VPHSUBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40179, 207},
+ /* 3744 */ {I_VPHSUBD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40186, 207},
+ /* 3745 */ {I_VPHSUBD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40193, 207},
+ /* 3746 */ {I_VPHSUBSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40200, 207},
+ /* 3747 */ {I_VPHSUBSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40207, 207},
+ /* 3748 */ {I_VPMADDUBSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40214, 207},
+ /* 3749 */ {I_VPMADDUBSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40221, 207},
+ /* 3750 */ {I_VPMADDWD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40228, 207},
+ /* 3751 */ {I_VPMADDWD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40235, 207},
+ /* 3752 */ {I_VPMAXSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40242, 207},
+ /* 3753 */ {I_VPMAXSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40249, 207},
+ /* 3754 */ {I_VPMAXSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40256, 207},
+ /* 3755 */ {I_VPMAXSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40263, 207},
+ /* 3756 */ {I_VPMAXSD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40270, 207},
+ /* 3757 */ {I_VPMAXSD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40277, 207},
+ /* 3758 */ {I_VPMAXUB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40284, 207},
+ /* 3759 */ {I_VPMAXUB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40291, 207},
+ /* 3760 */ {I_VPMAXUW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40298, 207},
+ /* 3761 */ {I_VPMAXUW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40305, 207},
+ /* 3762 */ {I_VPMAXUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40312, 207},
+ /* 3763 */ {I_VPMAXUD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40319, 207},
+ /* 3764 */ {I_VPMINSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40326, 207},
+ /* 3765 */ {I_VPMINSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40333, 207},
+ /* 3766 */ {I_VPMINSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40340, 207},
+ /* 3767 */ {I_VPMINSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40347, 207},
+ /* 3768 */ {I_VPMINSD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40354, 207},
+ /* 3769 */ {I_VPMINSD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40361, 207},
+ /* 3770 */ {I_VPMINUB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40368, 207},
+ /* 3771 */ {I_VPMINUB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40375, 207},
+ /* 3772 */ {I_VPMINUW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40382, 207},
+ /* 3773 */ {I_VPMINUW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40389, 207},
+ /* 3774 */ {I_VPMINUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40396, 207},
+ /* 3775 */ {I_VPMINUD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40403, 207},
+ /* 3776 */ {I_VPMOVMSKB, 2, {REG_GPR|BITS32,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40410, 207},
+ /* 3777 */ {I_VPMOVMSKB, 2, {REG_GPR|BITS64,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40410, 207},
+ /* 3778 */ {I_VPMOVSXBW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40417, 207},
+ /* 3779 */ {I_VPMOVSXBD, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40424, 207},
+ /* 3780 */ {I_VPMOVSXBD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40424, 207},
+ /* 3781 */ {I_VPMOVSXBQ, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+40431, 207},
+ /* 3782 */ {I_VPMOVSXBQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40431, 207},
+ /* 3783 */ {I_VPMOVSXWD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40438, 207},
+ /* 3784 */ {I_VPMOVSXWQ, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40445, 207},
+ /* 3785 */ {I_VPMOVSXWQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40445, 207},
+ /* 3786 */ {I_VPMOVSXDQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40452, 207},
+ /* 3787 */ {I_VPMOVZXBW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40459, 207},
+ /* 3788 */ {I_VPMOVZXBD, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40466, 207},
+ /* 3789 */ {I_VPMOVZXBD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40466, 207},
+ /* 3790 */ {I_VPMOVZXBQ, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+40473, 207},
+ /* 3791 */ {I_VPMOVZXBQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40473, 207},
+ /* 3792 */ {I_VPMOVZXWD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40480, 207},
+ /* 3793 */ {I_VPMOVZXWQ, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+40487, 207},
+ /* 3794 */ {I_VPMOVZXWQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+40487, 207},
+ /* 3795 */ {I_VPMOVZXDQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40494, 207},
+ /* 3796 */ {I_VPMULDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40501, 207},
+ /* 3797 */ {I_VPMULDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40508, 207},
+ /* 3798 */ {I_VPMULHRSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40515, 207},
+ /* 3799 */ {I_VPMULHRSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40522, 207},
+ /* 3800 */ {I_VPMULHUW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40529, 207},
+ /* 3801 */ {I_VPMULHUW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40536, 207},
+ /* 3802 */ {I_VPMULHW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40543, 207},
+ /* 3803 */ {I_VPMULHW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40550, 207},
+ /* 3804 */ {I_VPMULLW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40557, 207},
+ /* 3805 */ {I_VPMULLW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40564, 207},
+ /* 3806 */ {I_VPMULLD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40571, 207},
+ /* 3807 */ {I_VPMULLD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40578, 207},
+ /* 3808 */ {I_VPMULUDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40585, 207},
+ /* 3809 */ {I_VPMULUDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40592, 207},
+ /* 3810 */ {I_VPOR, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40599, 207},
+ /* 3811 */ {I_VPOR, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40606, 207},
+ /* 3812 */ {I_VPSADBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40613, 207},
+ /* 3813 */ {I_VPSADBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40620, 207},
+ /* 3814 */ {I_VPSHUFB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40627, 207},
+ /* 3815 */ {I_VPSHUFB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40634, 207},
+ /* 3816 */ {I_VPSHUFD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15872, 207},
+ /* 3817 */ {I_VPSHUFHW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15880, 207},
+ /* 3818 */ {I_VPSHUFLW, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15888, 207},
+ /* 3819 */ {I_VPSIGNB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40641, 207},
+ /* 3820 */ {I_VPSIGNB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40648, 207},
+ /* 3821 */ {I_VPSIGNW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40655, 207},
+ /* 3822 */ {I_VPSIGNW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40662, 207},
+ /* 3823 */ {I_VPSIGND, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40669, 207},
+ /* 3824 */ {I_VPSIGND, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40676, 207},
+ /* 3825 */ {I_VPSLLDQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15896, 207},
+ /* 3826 */ {I_VPSLLDQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15904, 207},
+ /* 3827 */ {I_VPSLLW, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40683, 207},
+ /* 3828 */ {I_VPSLLW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40690, 207},
+ /* 3829 */ {I_VPSLLW, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15912, 207},
+ /* 3830 */ {I_VPSLLW, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15920, 207},
+ /* 3831 */ {I_VPSLLD, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40697, 207},
+ /* 3832 */ {I_VPSLLD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40704, 207},
+ /* 3833 */ {I_VPSLLD, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15928, 207},
+ /* 3834 */ {I_VPSLLD, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15936, 207},
+ /* 3835 */ {I_VPSLLQ, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40711, 207},
+ /* 3836 */ {I_VPSLLQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40718, 207},
+ /* 3837 */ {I_VPSLLQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15944, 207},
+ /* 3838 */ {I_VPSLLQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15952, 207},
+ /* 3839 */ {I_VPSRAW, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40725, 207},
+ /* 3840 */ {I_VPSRAW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40732, 207},
+ /* 3841 */ {I_VPSRAW, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15960, 207},
+ /* 3842 */ {I_VPSRAW, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15968, 207},
+ /* 3843 */ {I_VPSRAD, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40739, 207},
+ /* 3844 */ {I_VPSRAD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40746, 207},
+ /* 3845 */ {I_VPSRAD, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15976, 207},
+ /* 3846 */ {I_VPSRAD, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+15984, 207},
+ /* 3847 */ {I_VPSRLDQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+15992, 207},
+ /* 3848 */ {I_VPSRLDQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16000, 207},
+ /* 3849 */ {I_VPSRLW, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40753, 207},
+ /* 3850 */ {I_VPSRLW, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40760, 207},
+ /* 3851 */ {I_VPSRLW, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16008, 207},
+ /* 3852 */ {I_VPSRLW, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16016, 207},
+ /* 3853 */ {I_VPSRLD, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40767, 207},
+ /* 3854 */ {I_VPSRLD, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40774, 207},
+ /* 3855 */ {I_VPSRLD, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16024, 207},
+ /* 3856 */ {I_VPSRLD, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16032, 207},
+ /* 3857 */ {I_VPSRLQ, 3, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+40781, 207},
+ /* 3858 */ {I_VPSRLQ, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+40788, 207},
+ /* 3859 */ {I_VPSRLQ, 3, {YMM_L16,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16040, 207},
+ /* 3860 */ {I_VPSRLQ, 2, {YMM_L16,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+16048, 207},
+ /* 3861 */ {I_VPSUBB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40795, 207},
+ /* 3862 */ {I_VPSUBB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40802, 207},
+ /* 3863 */ {I_VPSUBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40809, 207},
+ /* 3864 */ {I_VPSUBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40816, 207},
+ /* 3865 */ {I_VPSUBD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40823, 207},
+ /* 3866 */ {I_VPSUBD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40830, 207},
+ /* 3867 */ {I_VPSUBQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40837, 207},
+ /* 3868 */ {I_VPSUBQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40844, 207},
+ /* 3869 */ {I_VPSUBSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40851, 207},
+ /* 3870 */ {I_VPSUBSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40858, 207},
+ /* 3871 */ {I_VPSUBSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40865, 207},
+ /* 3872 */ {I_VPSUBSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40872, 207},
+ /* 3873 */ {I_VPSUBUSB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40879, 207},
+ /* 3874 */ {I_VPSUBUSB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40886, 207},
+ /* 3875 */ {I_VPSUBUSW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40893, 207},
+ /* 3876 */ {I_VPSUBUSW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40900, 207},
+ /* 3877 */ {I_VPUNPCKHBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40907, 207},
+ /* 3878 */ {I_VPUNPCKHBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40914, 207},
+ /* 3879 */ {I_VPUNPCKHWD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40921, 207},
+ /* 3880 */ {I_VPUNPCKHWD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40928, 207},
+ /* 3881 */ {I_VPUNPCKHDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40935, 207},
+ /* 3882 */ {I_VPUNPCKHDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40942, 207},
+ /* 3883 */ {I_VPUNPCKHQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40949, 207},
+ /* 3884 */ {I_VPUNPCKHQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40956, 207},
+ /* 3885 */ {I_VPUNPCKLBW, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40963, 207},
+ /* 3886 */ {I_VPUNPCKLBW, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40970, 207},
+ /* 3887 */ {I_VPUNPCKLWD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40977, 207},
+ /* 3888 */ {I_VPUNPCKLWD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40984, 207},
+ /* 3889 */ {I_VPUNPCKLDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+40991, 207},
+ /* 3890 */ {I_VPUNPCKLDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+40998, 207},
+ /* 3891 */ {I_VPUNPCKLQDQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41005, 207},
+ /* 3892 */ {I_VPUNPCKLQDQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41012, 207},
+ /* 3893 */ {I_VPXOR, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41019, 207},
+ /* 3894 */ {I_VPXOR, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41026, 207},
+ /* 3895 */ {I_VMOVNTDQA, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41033, 207},
+ /* 3896 */ {I_VBROADCASTSS, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35244, 207},
+ /* 3897 */ {I_VBROADCASTSS, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35251, 207},
+ /* 3898 */ {I_VBROADCASTSD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+35258, 207},
+ /* 3899 */ {I_VBROADCASTI128, 2, {YMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41040, 207},
+ /* 3900 */ {I_VPBLENDD, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16056, 207},
+ /* 3901 */ {I_VPBLENDD, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16064, 207},
+ /* 3902 */ {I_VPBLENDD, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16072, 207},
+ /* 3903 */ {I_VPBLENDD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16080, 207},
+ /* 3904 */ {I_VPBROADCASTB, 2, {XMM_L16,MEMORY|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+41047, 207},
+ /* 3905 */ {I_VPBROADCASTB, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41047, 207},
+ /* 3906 */ {I_VPBROADCASTB, 2, {YMM_L16,MEMORY|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+41054, 207},
+ /* 3907 */ {I_VPBROADCASTB, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41054, 207},
+ /* 3908 */ {I_VPBROADCASTW, 2, {XMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41061, 207},
+ /* 3909 */ {I_VPBROADCASTW, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41061, 207},
+ /* 3910 */ {I_VPBROADCASTW, 2, {YMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41068, 207},
+ /* 3911 */ {I_VPBROADCASTW, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41068, 207},
+ /* 3912 */ {I_VPBROADCASTD, 2, {XMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41075, 207},
+ /* 3913 */ {I_VPBROADCASTD, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41075, 207},
+ /* 3914 */ {I_VPBROADCASTD, 2, {YMM_L16,MEMORY|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41082, 207},
+ /* 3915 */ {I_VPBROADCASTD, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41082, 207},
+ /* 3916 */ {I_VPBROADCASTQ, 2, {XMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41089, 207},
+ /* 3917 */ {I_VPBROADCASTQ, 2, {XMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41089, 207},
+ /* 3918 */ {I_VPBROADCASTQ, 2, {YMM_L16,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41096, 207},
+ /* 3919 */ {I_VPBROADCASTQ, 2, {YMM_L16,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41096, 207},
+ /* 3920 */ {I_VPERMD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41103, 207},
+ /* 3921 */ {I_VPERMD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41110, 207},
+ /* 3922 */ {I_VPERMPD, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16088, 207},
+ /* 3923 */ {I_VPERMPS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41117, 207},
+ /* 3924 */ {I_VPERMPS, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41124, 207},
+ /* 3925 */ {I_VPERMQ, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16096, 207},
+ /* 3926 */ {I_VPERM2I128, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16104, 207},
+ /* 3927 */ {I_VPERM2I128, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16112, 207},
+ /* 3928 */ {I_VEXTRACTI128, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16120, 207},
+ /* 3929 */ {I_VINSERTI128, 4, {YMM_L16,YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+16128, 207},
+ /* 3930 */ {I_VINSERTI128, 3, {YMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16136, 207},
+ /* 3931 */ {I_VPMASKMOVD, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41131, 207},
+ /* 3932 */ {I_VPMASKMOVD, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41138, 207},
+ /* 3933 */ {I_VPMASKMOVD, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41145, 207},
+ /* 3934 */ {I_VPMASKMOVD, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41152, 207},
+ /* 3935 */ {I_VPMASKMOVQ, 3, {XMM_L16,XMM_L16,MEMORY|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41159, 207},
+ /* 3936 */ {I_VPMASKMOVQ, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41166, 207},
+ /* 3937 */ {I_VPMASKMOVQ, 3, {YMM_L16,YMM_L16,MEMORY|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41173, 207},
+ /* 3938 */ {I_VPMASKMOVQ, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41180, 207},
+ /* 3939 */ {I_VPMASKMOVD, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41187, 207},
+ /* 3940 */ {I_VPMASKMOVD, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41194, 207},
+ /* 3941 */ {I_VPMASKMOVD, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41201, 207},
+ /* 3942 */ {I_VPMASKMOVD, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41208, 207},
+ /* 3943 */ {I_VPMASKMOVQ, 3, {MEMORY|BITS128,XMM_L16,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41215, 207},
+ /* 3944 */ {I_VPMASKMOVQ, 2, {MEMORY|BITS128,XMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41222, 207},
+ /* 3945 */ {I_VPMASKMOVQ, 3, {MEMORY|BITS256,YMM_L16,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+41229, 207},
+ /* 3946 */ {I_VPMASKMOVQ, 2, {MEMORY|BITS256,YMM_L16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41236, 207},
+ /* 3947 */ {I_VPSLLVD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41243, 207},
+ /* 3948 */ {I_VPSLLVD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41250, 207},
+ /* 3949 */ {I_VPSLLVQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41257, 207},
+ /* 3950 */ {I_VPSLLVQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41264, 207},
+ /* 3951 */ {I_VPSLLVD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41271, 207},
+ /* 3952 */ {I_VPSLLVD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41278, 207},
+ /* 3953 */ {I_VPSLLVQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41285, 207},
+ /* 3954 */ {I_VPSLLVQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41292, 207},
+ /* 3955 */ {I_VPSRAVD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41299, 207},
+ /* 3956 */ {I_VPSRAVD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41306, 207},
+ /* 3957 */ {I_VPSRAVD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41313, 207},
+ /* 3958 */ {I_VPSRAVD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41320, 207},
+ /* 3959 */ {I_VPSRLVD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41327, 207},
+ /* 3960 */ {I_VPSRLVD, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41334, 207},
+ /* 3961 */ {I_VPSRLVQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41341, 207},
+ /* 3962 */ {I_VPSRLVQ, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41348, 207},
+ /* 3963 */ {I_VPSRLVD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41355, 207},
+ /* 3964 */ {I_VPSRLVD, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41362, 207},
+ /* 3965 */ {I_VPSRLVQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41369, 207},
+ /* 3966 */ {I_VPSRLVQ, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41376, 207},
+ /* 3967 */ {I_VGATHERDPD, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16144, 207},
+ /* 3968 */ {I_VGATHERQPD, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16152, 207},
+ /* 3969 */ {I_VGATHERDPD, 3, {YMM_L16,XMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16160, 207},
+ /* 3970 */ {I_VGATHERQPD, 3, {YMM_L16,YMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16168, 207},
+ /* 3971 */ {I_VGATHERDPS, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16176, 207},
+ /* 3972 */ {I_VGATHERQPS, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16184, 207},
+ /* 3973 */ {I_VGATHERDPS, 3, {YMM_L16,YMEM|BITS32,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16192, 207},
+ /* 3974 */ {I_VGATHERQPS, 3, {XMM_L16,YMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16200, 207},
+ /* 3975 */ {I_VPGATHERDD, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16208, 207},
+ /* 3976 */ {I_VPGATHERQD, 3, {XMM_L16,XMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16216, 207},
+ /* 3977 */ {I_VPGATHERDD, 3, {YMM_L16,YMEM|BITS32,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16224, 207},
+ /* 3978 */ {I_VPGATHERQD, 3, {XMM_L16,YMEM|BITS32,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16232, 207},
+ /* 3979 */ {I_VPGATHERDQ, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16240, 207},
+ /* 3980 */ {I_VPGATHERQQ, 3, {XMM_L16,XMEM|BITS64,XMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16248, 207},
+ /* 3981 */ {I_VPGATHERDQ, 3, {YMM_L16,XMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16256, 207},
+ /* 3982 */ {I_VPGATHERQQ, 3, {YMM_L16,YMEM|BITS64,YMM_L16,0,0}, NO_DECORATOR, nasm_bytecodes+16264, 207},
+ /* 3983 */ {I_XABORT, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49162, 208},
+ /* 3984 */ {I_XABORT, 1, {IMMEDIATE|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49162, 208},
+ /* 3985 */ {I_XBEGIN, 1, {IMMEDIATE,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45855, 208},
+ /* 3986 */ {I_XBEGIN, 1, {IMMEDIATE|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45861, 209},
+ /* 3987 */ {I_XBEGIN, 1, {IMMEDIATE|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45867, 209},
+ /* 3988 */ {I_XBEGIN, 1, {IMMEDIATE|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45873, 210},
+ /* 3989 */ {I_XEND, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49167, 208},
+ /* 3990 */ {I_XTEST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49172, 211},
+ /* 3991 */ {I_ANDN, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41383, 212},
+ /* 3992 */ {I_ANDN, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41390, 213},
+ /* 3993 */ {I_BEXTR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41397, 212},
+ /* 3994 */ {I_BEXTR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41404, 213},
+ /* 3995 */ {I_BEXTR, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16272, 214},
+ /* 3996 */ {I_BEXTR, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMMEDIATE|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+16280, 215},
+ /* 3997 */ {I_BLCI, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41411, 214},
+ /* 3998 */ {I_BLCI, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41418, 215},
+ /* 3999 */ {I_BLCIC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41425, 214},
+ /* 4000 */ {I_BLCIC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41432, 215},
+ /* 4001 */ {I_BLSI, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41439, 212},
+ /* 4002 */ {I_BLSI, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41446, 213},
+ /* 4003 */ {I_BLSIC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41453, 214},
+ /* 4004 */ {I_BLSIC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41460, 215},
+ /* 4005 */ {I_BLCFILL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41467, 214},
+ /* 4006 */ {I_BLCFILL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41474, 215},
+ /* 4007 */ {I_BLSFILL, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41481, 214},
+ /* 4008 */ {I_BLSFILL, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41488, 215},
+ /* 4009 */ {I_BLCMSK, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41495, 214},
+ /* 4010 */ {I_BLCMSK, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41502, 215},
+ /* 4011 */ {I_BLSMSK, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41509, 212},
+ /* 4012 */ {I_BLSMSK, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41516, 213},
+ /* 4013 */ {I_BLSR, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41523, 212},
+ /* 4014 */ {I_BLSR, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41530, 213},
+ /* 4015 */ {I_BLCS, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41537, 214},
+ /* 4016 */ {I_BLCS, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41544, 215},
+ /* 4017 */ {I_BZHI, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41551, 216},
+ /* 4018 */ {I_BZHI, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41558, 217},
+ /* 4019 */ {I_MULX, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41565, 216},
+ /* 4020 */ {I_MULX, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41572, 217},
+ /* 4021 */ {I_PDEP, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41579, 216},
+ /* 4022 */ {I_PDEP, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41586, 217},
+ /* 4023 */ {I_PEXT, 3, {REG_GPR|BITS32,REG_GPR|BITS32,RM_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41593, 216},
+ /* 4024 */ {I_PEXT, 3, {REG_GPR|BITS64,REG_GPR|BITS64,RM_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41600, 217},
+ /* 4025 */ {I_RORX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16288, 216},
+ /* 4026 */ {I_RORX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16296, 217},
+ /* 4027 */ {I_SARX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41607, 216},
+ /* 4028 */ {I_SARX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41614, 217},
+ /* 4029 */ {I_SHLX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41621, 216},
+ /* 4030 */ {I_SHLX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41628, 217},
+ /* 4031 */ {I_SHRX, 3, {REG_GPR|BITS32,RM_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+41635, 216},
+ /* 4032 */ {I_SHRX, 3, {REG_GPR|BITS64,RM_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+41642, 217},
+ /* 4033 */ {I_TZCNT, 2, {REG_GPR|BITS16,RM_GPR|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41649, 218},
+ /* 4034 */ {I_TZCNT, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41656, 218},
+ /* 4035 */ {I_TZCNT, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41663, 219},
+ /* 4036 */ {I_TZMSK, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41670, 214},
+ /* 4037 */ {I_TZMSK, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41677, 215},
+ /* 4038 */ {I_T1MSKC, 2, {REG_GPR|BITS32,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41684, 214},
+ /* 4039 */ {I_T1MSKC, 2, {REG_GPR|BITS64,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41691, 215},
+ /* 4040 */ {I_PREFETCHWT1, 1, {MEMORY|BITS8,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49177, 220},
+ /* 4041 */ {I_BNDMK, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45879, 221},
+ /* 4042 */ {I_BNDCL, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41699, 222},
+ /* 4043 */ {I_BNDCL, 2, {BNDREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41699, 223},
+ /* 4044 */ {I_BNDCL, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41698, 224},
+ /* 4045 */ {I_BNDCU, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41706, 222},
+ /* 4046 */ {I_BNDCU, 2, {BNDREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41706, 223},
+ /* 4047 */ {I_BNDCU, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41705, 224},
+ /* 4048 */ {I_BNDCN, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+41713, 222},
+ /* 4049 */ {I_BNDCN, 2, {BNDREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+41713, 223},
+ /* 4050 */ {I_BNDCN, 2, {BNDREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+41712, 224},
+ /* 4051 */ {I_BNDMOV, 2, {BNDREG,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45885, 222},
+ /* 4052 */ {I_BNDMOV, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45885, 222},
+ /* 4053 */ {I_BNDMOV, 2, {BNDREG,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45891, 222},
+ /* 4054 */ {I_BNDMOV, 2, {MEMORY,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45891, 222},
+ /* 4055 */ {I_BNDLDX, 2, {BNDREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+45886, 221},
+ /* 4056 */ {I_BNDLDX, 3, {BNDREG,MEMORY,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+45897, 225},
+ /* 4057 */ {I_BNDLDX, 3, {BNDREG,MEMORY,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+45897, 226},
+ /* 4058 */ {I_BNDSTX, 2, {MEMORY,BNDREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+45892, 221},
+ /* 4059 */ {I_BNDSTX, 3, {MEMORY,REG_GPR|BITS32,BNDREG,0,0}, NO_DECORATOR, nasm_bytecodes+45903, 225},
+ /* 4060 */ {I_BNDSTX, 3, {MEMORY,REG_GPR|BITS64,BNDREG,0,0}, NO_DECORATOR, nasm_bytecodes+45903, 226},
+ /* 4061 */ {I_BNDSTX, 3, {MEMORY,BNDREG,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+45909, 225},
+ /* 4062 */ {I_BNDSTX, 3, {MEMORY,BNDREG,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+45909, 226},
+ /* 4063 */ {I_SHA1MSG1, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45915, 227},
+ /* 4064 */ {I_SHA1MSG2, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45921, 227},
+ /* 4065 */ {I_SHA1NEXTE, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45927, 227},
+ /* 4066 */ {I_SHA1RNDS4, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+41719, 227},
+ /* 4067 */ {I_SHA256MSG1, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45933, 227},
+ /* 4068 */ {I_SHA256MSG2, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45939, 227},
+ /* 4069 */ {I_SHA256RNDS2, 3, {XMM_L16,RM_XMM_L16|BITS128,XMM0,0,0}, NO_DECORATOR, nasm_bytecodes+45945, 227},
+ /* 4070 */ {I_SHA256RNDS2, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+45945, 227},
+ /* 4071 */ {I_VBCSTNEBF16PS, 2, {XMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41726, 228},
+ /* 4072 */ {I_VBCSTNEBF16PS, 2, {YMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41733, 228},
+ /* 4073 */ {I_VBCSTNESH2PS, 2, {XMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41740, 228},
+ /* 4074 */ {I_VBCSTNESH2PS, 2, {YMM_L16,MEMORY|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+41747, 228},
+ /* 4075 */ {I_VCVTNEEBF162PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41754, 229},
+ /* 4076 */ {I_VCVTNEEBF162PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41761, 230},
+ /* 4077 */ {I_VCVTNEEPH2PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41768, 229},
+ /* 4078 */ {I_VCVTNEEPH2PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41775, 230},
+ /* 4079 */ {I_VCVTNEOBF162PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41782, 229},
+ /* 4080 */ {I_VCVTNEOBF162PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41789, 230},
+ /* 4081 */ {I_VCVTNEOPH2PS, 2, {XMM_L16,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41796, 229},
+ /* 4082 */ {I_VCVTNEOPH2PS, 2, {YMM_L16,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41803, 230},
+ /* 4083 */ {I_VCVTNEPS2BF16, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+41810, 229},
+ /* 4084 */ {I_VCVTNEPS2BF16, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+41817, 230},
+ /* 4085 */ {I_VPDPBSSD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41824, 231},
+ /* 4086 */ {I_VPDPBSSD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41831, 232},
+ /* 4087 */ {I_VPDPBSSDS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41838, 231},
+ /* 4088 */ {I_VPDPBSSDS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41845, 232},
+ /* 4089 */ {I_VPDPBSUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41852, 231},
+ /* 4090 */ {I_VPDPBSUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41859, 232},
+ /* 4091 */ {I_VPDPBSUDS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41866, 231},
+ /* 4092 */ {I_VPDPBSUDS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41873, 232},
+ /* 4093 */ {I_VPDPBUUD, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41880, 231},
+ /* 4094 */ {I_VPDPBUUD, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41887, 232},
+ /* 4095 */ {I_VPDPBUUDS, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41894, 231},
+ /* 4096 */ {I_VPDPBUUDS, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41901, 232},
+ /* 4097 */ {I_VPMADD52HUQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41908, 233},
+ /* 4098 */ {I_VPMADD52HUQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41915, 234},
+ /* 4099 */ {I_VPMADD52LUQ, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+41922, 233},
+ /* 4100 */ {I_VPMADD52LUQ, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+41929, 234},
+ /* 4101 */ {I_KADDB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41936, 235},
+ /* 4102 */ {I_KADDD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41943, 235},
+ /* 4103 */ {I_KADDQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41950, 235},
+ /* 4104 */ {I_KADDW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41957, 235},
+ /* 4105 */ {I_KANDB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41964, 235},
+ /* 4106 */ {I_KANDD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41971, 235},
+ /* 4107 */ {I_KANDNB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41978, 235},
+ /* 4108 */ {I_KANDND, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41985, 235},
+ /* 4109 */ {I_KANDNQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41992, 235},
+ /* 4110 */ {I_KANDNW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+41999, 235},
+ /* 4111 */ {I_KANDQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42006, 235},
+ /* 4112 */ {I_KANDW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42013, 235},
+ /* 4113 */ {I_KMOVB, 2, {KREG,RM_K|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+42020, 235},
+ /* 4114 */ {I_KMOVB, 2, {MEMORY|BITS8,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42027, 235},
+ /* 4115 */ {I_KMOVB, 2, {KREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42034, 235},
+ /* 4116 */ {I_KMOVB, 2, {REG_GPR|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42041, 235},
+ /* 4117 */ {I_KMOVD, 2, {KREG,RM_K|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42048, 235},
+ /* 4118 */ {I_KMOVD, 2, {MEMORY|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42055, 235},
+ /* 4119 */ {I_KMOVD, 2, {KREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42062, 235},
+ /* 4120 */ {I_KMOVD, 2, {REG_GPR|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42069, 235},
+ /* 4121 */ {I_KMOVQ, 2, {KREG,RM_K|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42076, 235},
+ /* 4122 */ {I_KMOVQ, 2, {MEMORY|BITS64,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42083, 235},
+ /* 4123 */ {I_KMOVQ, 2, {KREG,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42090, 235},
+ /* 4124 */ {I_KMOVQ, 2, {REG_GPR|BITS64,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42097, 235},
+ /* 4125 */ {I_KMOVW, 2, {KREG,RM_K|BITS16,0,0,0}, NO_DECORATOR, nasm_bytecodes+42104, 235},
+ /* 4126 */ {I_KMOVW, 2, {MEMORY|BITS16,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42111, 235},
+ /* 4127 */ {I_KMOVW, 2, {KREG,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42118, 235},
+ /* 4128 */ {I_KMOVW, 2, {REG_GPR|BITS32,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42125, 235},
+ /* 4129 */ {I_KNOTB, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42132, 235},
+ /* 4130 */ {I_KNOTD, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42139, 235},
+ /* 4131 */ {I_KNOTQ, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42146, 235},
+ /* 4132 */ {I_KNOTW, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42153, 235},
+ /* 4133 */ {I_KORB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42160, 235},
+ /* 4134 */ {I_KORD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42167, 235},
+ /* 4135 */ {I_KORQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42174, 235},
+ /* 4136 */ {I_KORW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42181, 235},
+ /* 4137 */ {I_KORTESTB, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42188, 235},
+ /* 4138 */ {I_KORTESTD, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42195, 235},
+ /* 4139 */ {I_KORTESTQ, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42202, 235},
+ /* 4140 */ {I_KORTESTW, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42209, 235},
+ /* 4141 */ {I_KSHIFTLB, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16312, 235},
+ /* 4142 */ {I_KSHIFTLD, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16320, 235},
+ /* 4143 */ {I_KSHIFTLQ, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16328, 235},
+ /* 4144 */ {I_KSHIFTLW, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16336, 235},
+ /* 4145 */ {I_KSHIFTRB, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16344, 235},
+ /* 4146 */ {I_KSHIFTRD, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16352, 235},
+ /* 4147 */ {I_KSHIFTRQ, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16360, 235},
+ /* 4148 */ {I_KSHIFTRW, 3, {KREG,KREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+16368, 235},
+ /* 4149 */ {I_KTESTB, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42216, 235},
+ /* 4150 */ {I_KTESTD, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42223, 235},
+ /* 4151 */ {I_KTESTQ, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42230, 235},
+ /* 4152 */ {I_KTESTW, 2, {KREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42237, 235},
+ /* 4153 */ {I_KUNPCKBW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42244, 235},
+ /* 4154 */ {I_KUNPCKDQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42251, 235},
+ /* 4155 */ {I_KUNPCKWD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42258, 235},
+ /* 4156 */ {I_KXNORB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42265, 235},
+ /* 4157 */ {I_KXNORD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42272, 235},
+ /* 4158 */ {I_KXNORQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42279, 235},
+ /* 4159 */ {I_KXNORW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42286, 235},
+ /* 4160 */ {I_KXORB, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42293, 235},
+ /* 4161 */ {I_KXORD, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42300, 235},
+ /* 4162 */ {I_KXORQ, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42307, 235},
+ /* 4163 */ {I_KXORW, 3, {KREG,KREG,KREG,0,0}, NO_DECORATOR, nasm_bytecodes+42314, 235},
+ /* 4164 */ {I_VADDPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16376, 240},
+ /* 4165 */ {I_VADDPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16384, 240},
+ /* 4166 */ {I_VADDPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16392, 240},
+ /* 4167 */ {I_VADDPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16400, 240},
+ /* 4168 */ {I_VADDPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+16408, 241},
+ /* 4169 */ {I_VADDPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+16416, 241},
+ /* 4170 */ {I_VADDPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16424, 240},
+ /* 4171 */ {I_VADDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16432, 240},
+ /* 4172 */ {I_VADDPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16440, 240},
+ /* 4173 */ {I_VADDPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16448, 240},
+ /* 4174 */ {I_VADDPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+16456, 241},
+ /* 4175 */ {I_VADDPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+16464, 241},
+ /* 4176 */ {I_VADDSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+16472, 241},
+ /* 4177 */ {I_VADDSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+16480, 241},
+ /* 4178 */ {I_VADDSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+16488, 241},
+ /* 4179 */ {I_VADDSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+16496, 241},
+ /* 4180 */ {I_VALIGND, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8002, 240},
+ /* 4181 */ {I_VALIGND, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8011, 240},
+ /* 4182 */ {I_VALIGND, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8020, 240},
+ /* 4183 */ {I_VALIGND, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8029, 240},
+ /* 4184 */ {I_VALIGND, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8038, 241},
+ /* 4185 */ {I_VALIGND, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8047, 241},
+ /* 4186 */ {I_VALIGNQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8056, 240},
+ /* 4187 */ {I_VALIGNQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8065, 240},
+ /* 4188 */ {I_VALIGNQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8074, 240},
+ /* 4189 */ {I_VALIGNQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8083, 240},
+ /* 4190 */ {I_VALIGNQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8092, 241},
+ /* 4191 */ {I_VALIGNQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8101, 241},
+ /* 4192 */ {I_VANDNPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16504, 242},
+ /* 4193 */ {I_VANDNPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16512, 242},
+ /* 4194 */ {I_VANDNPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16520, 242},
+ /* 4195 */ {I_VANDNPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16528, 242},
+ /* 4196 */ {I_VANDNPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16536, 243},
+ /* 4197 */ {I_VANDNPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16544, 243},
+ /* 4198 */ {I_VANDNPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16552, 242},
+ /* 4199 */ {I_VANDNPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16560, 242},
+ /* 4200 */ {I_VANDNPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16568, 242},
+ /* 4201 */ {I_VANDNPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16576, 242},
+ /* 4202 */ {I_VANDNPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16584, 243},
+ /* 4203 */ {I_VANDNPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16592, 243},
+ /* 4204 */ {I_VANDPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16600, 242},
+ /* 4205 */ {I_VANDPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16608, 242},
+ /* 4206 */ {I_VANDPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16616, 242},
+ /* 4207 */ {I_VANDPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16624, 242},
+ /* 4208 */ {I_VANDPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16632, 243},
+ /* 4209 */ {I_VANDPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+16640, 243},
+ /* 4210 */ {I_VANDPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16648, 242},
+ /* 4211 */ {I_VANDPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16656, 242},
+ /* 4212 */ {I_VANDPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16664, 242},
+ /* 4213 */ {I_VANDPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16672, 242},
+ /* 4214 */ {I_VANDPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16680, 243},
+ /* 4215 */ {I_VANDPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+16688, 243},
+ /* 4216 */ {I_VBLENDMPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16696, 240},
+ /* 4217 */ {I_VBLENDMPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16704, 240},
+ /* 4218 */ {I_VBLENDMPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+16712, 241},
+ /* 4219 */ {I_VBLENDMPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16720, 240},
+ /* 4220 */ {I_VBLENDMPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16728, 240},
+ /* 4221 */ {I_VBLENDMPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+16736, 241},
+ /* 4222 */ {I_VBROADCASTF32X2, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16744, 242},
+ /* 4223 */ {I_VBROADCASTF32X2, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16752, 243},
+ /* 4224 */ {I_VBROADCASTF32X4, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16760, 240},
+ /* 4225 */ {I_VBROADCASTF32X4, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16768, 241},
+ /* 4226 */ {I_VBROADCASTF32X8, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16776, 243},
+ /* 4227 */ {I_VBROADCASTF64X2, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16784, 242},
+ /* 4228 */ {I_VBROADCASTF64X2, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16792, 243},
+ /* 4229 */ {I_VBROADCASTF64X4, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16800, 241},
+ /* 4230 */ {I_VBROADCASTI32X2, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16808, 242},
+ /* 4231 */ {I_VBROADCASTI32X2, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16816, 242},
+ /* 4232 */ {I_VBROADCASTI32X2, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16824, 243},
+ /* 4233 */ {I_VBROADCASTI32X4, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16832, 240},
+ /* 4234 */ {I_VBROADCASTI32X4, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16840, 241},
+ /* 4235 */ {I_VBROADCASTI32X8, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16848, 243},
+ /* 4236 */ {I_VBROADCASTI64X2, 2, {YMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16856, 242},
+ /* 4237 */ {I_VBROADCASTI64X2, 2, {ZMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16864, 243},
+ /* 4238 */ {I_VBROADCASTI64X4, 2, {ZMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16872, 241},
+ /* 4239 */ {I_VBROADCASTSD, 2, {YMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16880, 240},
+ /* 4240 */ {I_VBROADCASTSD, 2, {ZMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16888, 241},
+ /* 4241 */ {I_VBROADCASTSD, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16896, 240},
+ /* 4242 */ {I_VBROADCASTSD, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16904, 241},
+ /* 4243 */ {I_VBROADCASTSS, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16912, 240},
+ /* 4244 */ {I_VBROADCASTSS, 2, {YMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16920, 240},
+ /* 4245 */ {I_VBROADCASTSS, 2, {ZMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16928, 241},
+ /* 4246 */ {I_VBROADCASTSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16936, 240},
+ /* 4247 */ {I_VBROADCASTSS, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16944, 240},
+ /* 4248 */ {I_VBROADCASTSS, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+16952, 241},
+ /* 4249 */ {I_VCMPEQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+240, 240},
+ /* 4250 */ {I_VCMPEQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+250, 240},
+ /* 4251 */ {I_VCMPEQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+260, 241},
+ /* 4252 */ {I_VCMPEQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+270, 240},
+ /* 4253 */ {I_VCMPEQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+280, 240},
+ /* 4254 */ {I_VCMPEQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+290, 241},
+ /* 4255 */ {I_VCMPEQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+300, 241},
+ /* 4256 */ {I_VCMPEQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+310, 241},
+ /* 4257 */ {I_VCMPEQ_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+240, 240},
+ /* 4258 */ {I_VCMPEQ_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+250, 240},
+ /* 4259 */ {I_VCMPEQ_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+260, 241},
+ /* 4260 */ {I_VCMPEQ_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+270, 240},
+ /* 4261 */ {I_VCMPEQ_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+280, 240},
+ /* 4262 */ {I_VCMPEQ_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+290, 241},
+ /* 4263 */ {I_VCMPEQ_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+300, 241},
+ /* 4264 */ {I_VCMPEQ_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+310, 241},
+ /* 4265 */ {I_VCMPLTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+320, 240},
+ /* 4266 */ {I_VCMPLTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+330, 240},
+ /* 4267 */ {I_VCMPLTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+340, 241},
+ /* 4268 */ {I_VCMPLTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+350, 240},
+ /* 4269 */ {I_VCMPLTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+360, 240},
+ /* 4270 */ {I_VCMPLTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+370, 241},
+ /* 4271 */ {I_VCMPLTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+380, 241},
+ /* 4272 */ {I_VCMPLTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+390, 241},
+ /* 4273 */ {I_VCMPLT_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+320, 240},
+ /* 4274 */ {I_VCMPLT_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+330, 240},
+ /* 4275 */ {I_VCMPLT_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+340, 241},
+ /* 4276 */ {I_VCMPLT_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+350, 240},
+ /* 4277 */ {I_VCMPLT_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+360, 240},
+ /* 4278 */ {I_VCMPLT_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+370, 241},
+ /* 4279 */ {I_VCMPLT_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+380, 241},
+ /* 4280 */ {I_VCMPLT_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+390, 241},
+ /* 4281 */ {I_VCMPLEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+400, 240},
+ /* 4282 */ {I_VCMPLEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+410, 240},
+ /* 4283 */ {I_VCMPLEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+420, 241},
+ /* 4284 */ {I_VCMPLEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+430, 240},
+ /* 4285 */ {I_VCMPLEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+440, 240},
+ /* 4286 */ {I_VCMPLEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+450, 241},
+ /* 4287 */ {I_VCMPLESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+460, 241},
+ /* 4288 */ {I_VCMPLESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+470, 241},
+ /* 4289 */ {I_VCMPLE_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+400, 240},
+ /* 4290 */ {I_VCMPLE_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+410, 240},
+ /* 4291 */ {I_VCMPLE_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+420, 241},
+ /* 4292 */ {I_VCMPLE_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+430, 240},
+ /* 4293 */ {I_VCMPLE_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+440, 240},
+ /* 4294 */ {I_VCMPLE_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+450, 241},
+ /* 4295 */ {I_VCMPLE_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+460, 241},
+ /* 4296 */ {I_VCMPLE_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+470, 241},
+ /* 4297 */ {I_VCMPUNORDPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+480, 240},
+ /* 4298 */ {I_VCMPUNORDPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+490, 240},
+ /* 4299 */ {I_VCMPUNORDPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+500, 241},
+ /* 4300 */ {I_VCMPUNORDPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+510, 240},
+ /* 4301 */ {I_VCMPUNORDPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+520, 240},
+ /* 4302 */ {I_VCMPUNORDPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+530, 241},
+ /* 4303 */ {I_VCMPUNORDSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+540, 241},
+ /* 4304 */ {I_VCMPUNORDSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+550, 241},
+ /* 4305 */ {I_VCMPUNORD_QPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+480, 240},
+ /* 4306 */ {I_VCMPUNORD_QPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+490, 240},
+ /* 4307 */ {I_VCMPUNORD_QPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+500, 241},
+ /* 4308 */ {I_VCMPUNORD_QPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+510, 240},
+ /* 4309 */ {I_VCMPUNORD_QPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+520, 240},
+ /* 4310 */ {I_VCMPUNORD_QPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+530, 241},
+ /* 4311 */ {I_VCMPUNORD_QSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+540, 241},
+ /* 4312 */ {I_VCMPUNORD_QSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+550, 241},
+ /* 4313 */ {I_VCMPNEQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+560, 240},
+ /* 4314 */ {I_VCMPNEQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+570, 240},
+ /* 4315 */ {I_VCMPNEQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+580, 241},
+ /* 4316 */ {I_VCMPNEQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+590, 240},
+ /* 4317 */ {I_VCMPNEQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+600, 240},
+ /* 4318 */ {I_VCMPNEQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+610, 241},
+ /* 4319 */ {I_VCMPNEQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+620, 241},
+ /* 4320 */ {I_VCMPNEQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+630, 241},
+ /* 4321 */ {I_VCMPNEQ_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+560, 240},
+ /* 4322 */ {I_VCMPNEQ_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+570, 240},
+ /* 4323 */ {I_VCMPNEQ_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+580, 241},
+ /* 4324 */ {I_VCMPNEQ_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+590, 240},
+ /* 4325 */ {I_VCMPNEQ_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+600, 240},
+ /* 4326 */ {I_VCMPNEQ_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+610, 241},
+ /* 4327 */ {I_VCMPNEQ_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+620, 241},
+ /* 4328 */ {I_VCMPNEQ_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+630, 241},
+ /* 4329 */ {I_VCMPNLTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+640, 240},
+ /* 4330 */ {I_VCMPNLTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+650, 240},
+ /* 4331 */ {I_VCMPNLTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+660, 241},
+ /* 4332 */ {I_VCMPNLTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+670, 240},
+ /* 4333 */ {I_VCMPNLTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+680, 240},
+ /* 4334 */ {I_VCMPNLTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+690, 241},
+ /* 4335 */ {I_VCMPNLTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+700, 241},
+ /* 4336 */ {I_VCMPNLTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+710, 241},
+ /* 4337 */ {I_VCMPNLT_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+640, 240},
+ /* 4338 */ {I_VCMPNLT_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+650, 240},
+ /* 4339 */ {I_VCMPNLT_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+660, 241},
+ /* 4340 */ {I_VCMPNLT_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+670, 240},
+ /* 4341 */ {I_VCMPNLT_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+680, 240},
+ /* 4342 */ {I_VCMPNLT_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+690, 241},
+ /* 4343 */ {I_VCMPNLT_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+700, 241},
+ /* 4344 */ {I_VCMPNLT_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+710, 241},
+ /* 4345 */ {I_VCMPNLEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+720, 240},
+ /* 4346 */ {I_VCMPNLEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+730, 240},
+ /* 4347 */ {I_VCMPNLEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+740, 241},
+ /* 4348 */ {I_VCMPNLEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+750, 240},
+ /* 4349 */ {I_VCMPNLEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+760, 240},
+ /* 4350 */ {I_VCMPNLEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+770, 241},
+ /* 4351 */ {I_VCMPNLESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+780, 241},
+ /* 4352 */ {I_VCMPNLESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+790, 241},
+ /* 4353 */ {I_VCMPNLE_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+720, 240},
+ /* 4354 */ {I_VCMPNLE_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+730, 240},
+ /* 4355 */ {I_VCMPNLE_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+740, 241},
+ /* 4356 */ {I_VCMPNLE_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+750, 240},
+ /* 4357 */ {I_VCMPNLE_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+760, 240},
+ /* 4358 */ {I_VCMPNLE_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+770, 241},
+ /* 4359 */ {I_VCMPNLE_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+780, 241},
+ /* 4360 */ {I_VCMPNLE_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+790, 241},
+ /* 4361 */ {I_VCMPORDPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+800, 240},
+ /* 4362 */ {I_VCMPORDPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+810, 240},
+ /* 4363 */ {I_VCMPORDPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+820, 241},
+ /* 4364 */ {I_VCMPORDPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+830, 240},
+ /* 4365 */ {I_VCMPORDPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+840, 240},
+ /* 4366 */ {I_VCMPORDPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+850, 241},
+ /* 4367 */ {I_VCMPORDSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+860, 241},
+ /* 4368 */ {I_VCMPORDSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+870, 241},
+ /* 4369 */ {I_VCMPORD_QPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+800, 240},
+ /* 4370 */ {I_VCMPORD_QPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+810, 240},
+ /* 4371 */ {I_VCMPORD_QPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+820, 241},
+ /* 4372 */ {I_VCMPORD_QPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+830, 240},
+ /* 4373 */ {I_VCMPORD_QPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+840, 240},
+ /* 4374 */ {I_VCMPORD_QPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+850, 241},
+ /* 4375 */ {I_VCMPORD_QSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+860, 241},
+ /* 4376 */ {I_VCMPORD_QSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+870, 241},
+ /* 4377 */ {I_VCMPEQ_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+880, 240},
+ /* 4378 */ {I_VCMPEQ_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+890, 240},
+ /* 4379 */ {I_VCMPEQ_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+900, 241},
+ /* 4380 */ {I_VCMPEQ_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+910, 240},
+ /* 4381 */ {I_VCMPEQ_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+920, 240},
+ /* 4382 */ {I_VCMPEQ_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+930, 241},
+ /* 4383 */ {I_VCMPEQ_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+940, 241},
+ /* 4384 */ {I_VCMPEQ_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+950, 241},
+ /* 4385 */ {I_VCMPNGEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+960, 240},
+ /* 4386 */ {I_VCMPNGEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+970, 240},
+ /* 4387 */ {I_VCMPNGEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+980, 241},
+ /* 4388 */ {I_VCMPNGEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+990, 240},
+ /* 4389 */ {I_VCMPNGEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1000, 240},
+ /* 4390 */ {I_VCMPNGEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1010, 241},
+ /* 4391 */ {I_VCMPNGESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1020, 241},
+ /* 4392 */ {I_VCMPNGESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1030, 241},
+ /* 4393 */ {I_VCMPNGE_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+960, 240},
+ /* 4394 */ {I_VCMPNGE_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+970, 240},
+ /* 4395 */ {I_VCMPNGE_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+980, 241},
+ /* 4396 */ {I_VCMPNGE_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+990, 240},
+ /* 4397 */ {I_VCMPNGE_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1000, 240},
+ /* 4398 */ {I_VCMPNGE_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1010, 241},
+ /* 4399 */ {I_VCMPNGE_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1020, 241},
+ /* 4400 */ {I_VCMPNGE_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1030, 241},
+ /* 4401 */ {I_VCMPNGTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1040, 240},
+ /* 4402 */ {I_VCMPNGTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1050, 240},
+ /* 4403 */ {I_VCMPNGTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1060, 241},
+ /* 4404 */ {I_VCMPNGTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1070, 240},
+ /* 4405 */ {I_VCMPNGTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1080, 240},
+ /* 4406 */ {I_VCMPNGTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1090, 241},
+ /* 4407 */ {I_VCMPNGTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1100, 241},
+ /* 4408 */ {I_VCMPNGTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1110, 241},
+ /* 4409 */ {I_VCMPNGT_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1040, 240},
+ /* 4410 */ {I_VCMPNGT_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1050, 240},
+ /* 4411 */ {I_VCMPNGT_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1060, 241},
+ /* 4412 */ {I_VCMPNGT_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1070, 240},
+ /* 4413 */ {I_VCMPNGT_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1080, 240},
+ /* 4414 */ {I_VCMPNGT_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1090, 241},
+ /* 4415 */ {I_VCMPNGT_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1100, 241},
+ /* 4416 */ {I_VCMPNGT_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1110, 241},
+ /* 4417 */ {I_VCMPFALSEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1120, 240},
+ /* 4418 */ {I_VCMPFALSEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1130, 240},
+ /* 4419 */ {I_VCMPFALSEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1140, 241},
+ /* 4420 */ {I_VCMPFALSEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1150, 240},
+ /* 4421 */ {I_VCMPFALSEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1160, 240},
+ /* 4422 */ {I_VCMPFALSEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1170, 241},
+ /* 4423 */ {I_VCMPFALSESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1180, 241},
+ /* 4424 */ {I_VCMPFALSESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1190, 241},
+ /* 4425 */ {I_VCMPFALSE_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1120, 240},
+ /* 4426 */ {I_VCMPFALSE_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1130, 240},
+ /* 4427 */ {I_VCMPFALSE_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1140, 241},
+ /* 4428 */ {I_VCMPFALSE_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1150, 240},
+ /* 4429 */ {I_VCMPFALSE_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1160, 240},
+ /* 4430 */ {I_VCMPFALSE_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1170, 241},
+ /* 4431 */ {I_VCMPFALSE_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1180, 241},
+ /* 4432 */ {I_VCMPFALSE_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1190, 241},
+ /* 4433 */ {I_VCMPNEQ_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1200, 240},
+ /* 4434 */ {I_VCMPNEQ_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1210, 240},
+ /* 4435 */ {I_VCMPNEQ_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1220, 241},
+ /* 4436 */ {I_VCMPNEQ_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1230, 240},
+ /* 4437 */ {I_VCMPNEQ_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1240, 240},
+ /* 4438 */ {I_VCMPNEQ_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1250, 241},
+ /* 4439 */ {I_VCMPNEQ_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1260, 241},
+ /* 4440 */ {I_VCMPNEQ_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1270, 241},
+ /* 4441 */ {I_VCMPGEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1280, 240},
+ /* 4442 */ {I_VCMPGEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1290, 240},
+ /* 4443 */ {I_VCMPGEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1300, 241},
+ /* 4444 */ {I_VCMPGEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1310, 240},
+ /* 4445 */ {I_VCMPGEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1320, 240},
+ /* 4446 */ {I_VCMPGEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1330, 241},
+ /* 4447 */ {I_VCMPGESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1340, 241},
+ /* 4448 */ {I_VCMPGESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1350, 241},
+ /* 4449 */ {I_VCMPGE_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1280, 240},
+ /* 4450 */ {I_VCMPGE_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1290, 240},
+ /* 4451 */ {I_VCMPGE_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1300, 241},
+ /* 4452 */ {I_VCMPGE_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1310, 240},
+ /* 4453 */ {I_VCMPGE_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1320, 240},
+ /* 4454 */ {I_VCMPGE_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1330, 241},
+ /* 4455 */ {I_VCMPGE_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1340, 241},
+ /* 4456 */ {I_VCMPGE_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1350, 241},
+ /* 4457 */ {I_VCMPGTPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1360, 240},
+ /* 4458 */ {I_VCMPGTPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1370, 240},
+ /* 4459 */ {I_VCMPGTPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1380, 241},
+ /* 4460 */ {I_VCMPGTPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1390, 240},
+ /* 4461 */ {I_VCMPGTPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1400, 240},
+ /* 4462 */ {I_VCMPGTPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1410, 241},
+ /* 4463 */ {I_VCMPGTSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1420, 241},
+ /* 4464 */ {I_VCMPGTSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1430, 241},
+ /* 4465 */ {I_VCMPGT_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1360, 240},
+ /* 4466 */ {I_VCMPGT_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1370, 240},
+ /* 4467 */ {I_VCMPGT_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1380, 241},
+ /* 4468 */ {I_VCMPGT_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1390, 240},
+ /* 4469 */ {I_VCMPGT_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1400, 240},
+ /* 4470 */ {I_VCMPGT_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1410, 241},
+ /* 4471 */ {I_VCMPGT_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1420, 241},
+ /* 4472 */ {I_VCMPGT_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1430, 241},
+ /* 4473 */ {I_VCMPTRUEPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1440, 240},
+ /* 4474 */ {I_VCMPTRUEPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1450, 240},
+ /* 4475 */ {I_VCMPTRUEPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1460, 241},
+ /* 4476 */ {I_VCMPTRUEPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1470, 240},
+ /* 4477 */ {I_VCMPTRUEPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1480, 240},
+ /* 4478 */ {I_VCMPTRUEPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1490, 241},
+ /* 4479 */ {I_VCMPTRUESD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1500, 241},
+ /* 4480 */ {I_VCMPTRUESS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1510, 241},
+ /* 4481 */ {I_VCMPTRUE_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1440, 240},
+ /* 4482 */ {I_VCMPTRUE_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1450, 240},
+ /* 4483 */ {I_VCMPTRUE_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1460, 241},
+ /* 4484 */ {I_VCMPTRUE_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1470, 240},
+ /* 4485 */ {I_VCMPTRUE_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1480, 240},
+ /* 4486 */ {I_VCMPTRUE_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1490, 241},
+ /* 4487 */ {I_VCMPTRUE_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1500, 241},
+ /* 4488 */ {I_VCMPTRUE_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1510, 241},
+ /* 4489 */ {I_VCMPEQ_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1520, 240},
+ /* 4490 */ {I_VCMPEQ_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1530, 240},
+ /* 4491 */ {I_VCMPEQ_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1540, 241},
+ /* 4492 */ {I_VCMPEQ_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1550, 240},
+ /* 4493 */ {I_VCMPEQ_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1560, 240},
+ /* 4494 */ {I_VCMPEQ_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1570, 241},
+ /* 4495 */ {I_VCMPEQ_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1580, 241},
+ /* 4496 */ {I_VCMPEQ_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1590, 241},
+ /* 4497 */ {I_VCMPLT_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1600, 240},
+ /* 4498 */ {I_VCMPLT_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1610, 240},
+ /* 4499 */ {I_VCMPLT_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1620, 241},
+ /* 4500 */ {I_VCMPLT_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1630, 240},
+ /* 4501 */ {I_VCMPLT_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1640, 240},
+ /* 4502 */ {I_VCMPLT_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1650, 241},
+ /* 4503 */ {I_VCMPLT_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1660, 241},
+ /* 4504 */ {I_VCMPLT_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1670, 241},
+ /* 4505 */ {I_VCMPLE_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1680, 240},
+ /* 4506 */ {I_VCMPLE_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1690, 240},
+ /* 4507 */ {I_VCMPLE_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1700, 241},
+ /* 4508 */ {I_VCMPLE_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1710, 240},
+ /* 4509 */ {I_VCMPLE_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1720, 240},
+ /* 4510 */ {I_VCMPLE_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1730, 241},
+ /* 4511 */ {I_VCMPLE_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1740, 241},
+ /* 4512 */ {I_VCMPLE_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1750, 241},
+ /* 4513 */ {I_VCMPUNORD_SPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1760, 240},
+ /* 4514 */ {I_VCMPUNORD_SPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1770, 240},
+ /* 4515 */ {I_VCMPUNORD_SPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1780, 241},
+ /* 4516 */ {I_VCMPUNORD_SPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1790, 240},
+ /* 4517 */ {I_VCMPUNORD_SPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1800, 240},
+ /* 4518 */ {I_VCMPUNORD_SPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1810, 241},
+ /* 4519 */ {I_VCMPUNORD_SSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1820, 241},
+ /* 4520 */ {I_VCMPUNORD_SSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1830, 241},
+ /* 4521 */ {I_VCMPNEQ_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1840, 240},
+ /* 4522 */ {I_VCMPNEQ_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1850, 240},
+ /* 4523 */ {I_VCMPNEQ_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1860, 241},
+ /* 4524 */ {I_VCMPNEQ_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1870, 240},
+ /* 4525 */ {I_VCMPNEQ_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1880, 240},
+ /* 4526 */ {I_VCMPNEQ_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1890, 241},
+ /* 4527 */ {I_VCMPNEQ_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1900, 241},
+ /* 4528 */ {I_VCMPNEQ_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1910, 241},
+ /* 4529 */ {I_VCMPNLT_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1920, 240},
+ /* 4530 */ {I_VCMPNLT_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+1930, 240},
+ /* 4531 */ {I_VCMPNLT_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+1940, 241},
+ /* 4532 */ {I_VCMPNLT_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1950, 240},
+ /* 4533 */ {I_VCMPNLT_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+1960, 240},
+ /* 4534 */ {I_VCMPNLT_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+1970, 241},
+ /* 4535 */ {I_VCMPNLT_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1980, 241},
+ /* 4536 */ {I_VCMPNLT_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+1990, 241},
+ /* 4537 */ {I_VCMPNLE_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2000, 240},
+ /* 4538 */ {I_VCMPNLE_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2010, 240},
+ /* 4539 */ {I_VCMPNLE_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2020, 241},
+ /* 4540 */ {I_VCMPNLE_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2030, 240},
+ /* 4541 */ {I_VCMPNLE_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2040, 240},
+ /* 4542 */ {I_VCMPNLE_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2050, 241},
+ /* 4543 */ {I_VCMPNLE_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2060, 241},
+ /* 4544 */ {I_VCMPNLE_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2070, 241},
+ /* 4545 */ {I_VCMPORD_SPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2080, 240},
+ /* 4546 */ {I_VCMPORD_SPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2090, 240},
+ /* 4547 */ {I_VCMPORD_SPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2100, 241},
+ /* 4548 */ {I_VCMPORD_SPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2110, 240},
+ /* 4549 */ {I_VCMPORD_SPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2120, 240},
+ /* 4550 */ {I_VCMPORD_SPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2130, 241},
+ /* 4551 */ {I_VCMPORD_SSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2140, 241},
+ /* 4552 */ {I_VCMPORD_SSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2150, 241},
+ /* 4553 */ {I_VCMPEQ_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2160, 240},
+ /* 4554 */ {I_VCMPEQ_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2170, 240},
+ /* 4555 */ {I_VCMPEQ_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2180, 241},
+ /* 4556 */ {I_VCMPEQ_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2190, 240},
+ /* 4557 */ {I_VCMPEQ_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2200, 240},
+ /* 4558 */ {I_VCMPEQ_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2210, 241},
+ /* 4559 */ {I_VCMPEQ_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2220, 241},
+ /* 4560 */ {I_VCMPEQ_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2230, 241},
+ /* 4561 */ {I_VCMPNGE_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2240, 240},
+ /* 4562 */ {I_VCMPNGE_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2250, 240},
+ /* 4563 */ {I_VCMPNGE_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2260, 241},
+ /* 4564 */ {I_VCMPNGE_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2270, 240},
+ /* 4565 */ {I_VCMPNGE_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2280, 240},
+ /* 4566 */ {I_VCMPNGE_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2290, 241},
+ /* 4567 */ {I_VCMPNGE_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2300, 241},
+ /* 4568 */ {I_VCMPNGE_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2310, 241},
+ /* 4569 */ {I_VCMPNGT_UQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2320, 240},
+ /* 4570 */ {I_VCMPNGT_UQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2330, 240},
+ /* 4571 */ {I_VCMPNGT_UQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2340, 241},
+ /* 4572 */ {I_VCMPNGT_UQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2350, 240},
+ /* 4573 */ {I_VCMPNGT_UQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2360, 240},
+ /* 4574 */ {I_VCMPNGT_UQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2370, 241},
+ /* 4575 */ {I_VCMPNGT_UQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2380, 241},
+ /* 4576 */ {I_VCMPNGT_UQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2390, 241},
+ /* 4577 */ {I_VCMPFALSE_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2400, 240},
+ /* 4578 */ {I_VCMPFALSE_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2410, 240},
+ /* 4579 */ {I_VCMPFALSE_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2420, 241},
+ /* 4580 */ {I_VCMPFALSE_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2430, 240},
+ /* 4581 */ {I_VCMPFALSE_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2440, 240},
+ /* 4582 */ {I_VCMPFALSE_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2450, 241},
+ /* 4583 */ {I_VCMPFALSE_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2460, 241},
+ /* 4584 */ {I_VCMPFALSE_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2470, 241},
+ /* 4585 */ {I_VCMPNEQ_OSPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2480, 240},
+ /* 4586 */ {I_VCMPNEQ_OSPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2490, 240},
+ /* 4587 */ {I_VCMPNEQ_OSPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2500, 241},
+ /* 4588 */ {I_VCMPNEQ_OSPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2510, 240},
+ /* 4589 */ {I_VCMPNEQ_OSPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2520, 240},
+ /* 4590 */ {I_VCMPNEQ_OSPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2530, 241},
+ /* 4591 */ {I_VCMPNEQ_OSSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2540, 241},
+ /* 4592 */ {I_VCMPNEQ_OSSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2550, 241},
+ /* 4593 */ {I_VCMPGE_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2560, 240},
+ /* 4594 */ {I_VCMPGE_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2570, 240},
+ /* 4595 */ {I_VCMPGE_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2580, 241},
+ /* 4596 */ {I_VCMPGE_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2590, 240},
+ /* 4597 */ {I_VCMPGE_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2600, 240},
+ /* 4598 */ {I_VCMPGE_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2610, 241},
+ /* 4599 */ {I_VCMPGE_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2620, 241},
+ /* 4600 */ {I_VCMPGE_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2630, 241},
+ /* 4601 */ {I_VCMPGT_OQPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2640, 240},
+ /* 4602 */ {I_VCMPGT_OQPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2650, 240},
+ /* 4603 */ {I_VCMPGT_OQPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2660, 241},
+ /* 4604 */ {I_VCMPGT_OQPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2670, 240},
+ /* 4605 */ {I_VCMPGT_OQPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2680, 240},
+ /* 4606 */ {I_VCMPGT_OQPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2690, 241},
+ /* 4607 */ {I_VCMPGT_OQSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2700, 241},
+ /* 4608 */ {I_VCMPGT_OQSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2710, 241},
+ /* 4609 */ {I_VCMPTRUE_USPD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2720, 240},
+ /* 4610 */ {I_VCMPTRUE_USPD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2730, 240},
+ /* 4611 */ {I_VCMPTRUE_USPD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+2740, 241},
+ /* 4612 */ {I_VCMPTRUE_USPS, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2750, 240},
+ /* 4613 */ {I_VCMPTRUE_USPS, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2760, 240},
+ /* 4614 */ {I_VCMPTRUE_USPS, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+2770, 241},
+ /* 4615 */ {I_VCMPTRUE_USSD, 3, {KREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2780, 241},
+ /* 4616 */ {I_VCMPTRUE_USSS, 3, {KREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+2790, 241},
+ /* 4617 */ {I_VCMPPD, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8110, 240},
+ /* 4618 */ {I_VCMPPD, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+8119, 240},
+ /* 4619 */ {I_VCMPPD, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B64|SAE,0,0}, nasm_bytecodes+8128, 241},
+ /* 4620 */ {I_VCMPPS, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8137, 240},
+ /* 4621 */ {I_VCMPPS, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+8146, 240},
+ /* 4622 */ {I_VCMPPS, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B32|SAE,0,0}, nasm_bytecodes+8155, 241},
+ /* 4623 */ {I_VCMPSD, 4, {KREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+8164, 241},
+ /* 4624 */ {I_VCMPSS, 4, {KREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+8173, 241},
+ /* 4625 */ {I_VCOMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+16960, 241},
+ /* 4626 */ {I_VCOMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+16968, 241},
+ /* 4627 */ {I_VCOMPRESSPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+16976, 240},
+ /* 4628 */ {I_VCOMPRESSPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+16984, 240},
+ /* 4629 */ {I_VCOMPRESSPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+16992, 241},
+ /* 4630 */ {I_VCOMPRESSPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17000, 240},
+ /* 4631 */ {I_VCOMPRESSPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17008, 240},
+ /* 4632 */ {I_VCOMPRESSPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17016, 241},
+ /* 4633 */ {I_VCOMPRESSPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+17024, 240},
+ /* 4634 */ {I_VCOMPRESSPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+17032, 240},
+ /* 4635 */ {I_VCOMPRESSPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+17040, 241},
+ /* 4636 */ {I_VCOMPRESSPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17048, 240},
+ /* 4637 */ {I_VCOMPRESSPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17056, 240},
+ /* 4638 */ {I_VCOMPRESSPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17064, 241},
+ /* 4639 */ {I_VCVTDQ2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17072, 240},
+ /* 4640 */ {I_VCVTDQ2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17080, 240},
+ /* 4641 */ {I_VCVTDQ2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17088, 241},
+ /* 4642 */ {I_VCVTDQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17096, 240},
+ /* 4643 */ {I_VCVTDQ2PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17104, 240},
+ /* 4644 */ {I_VCVTDQ2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17112, 241},
+ /* 4645 */ {I_VCVTPD2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17120, 240},
+ /* 4646 */ {I_VCVTPD2DQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17128, 240},
+ /* 4647 */ {I_VCVTPD2DQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17136, 241},
+ /* 4648 */ {I_VCVTPD2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17144, 240},
+ /* 4649 */ {I_VCVTPD2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17152, 240},
+ /* 4650 */ {I_VCVTPD2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17160, 241},
+ /* 4651 */ {I_VCVTPD2QQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17168, 242},
+ /* 4652 */ {I_VCVTPD2QQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17176, 242},
+ /* 4653 */ {I_VCVTPD2QQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17184, 243},
+ /* 4654 */ {I_VCVTPD2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17192, 240},
+ /* 4655 */ {I_VCVTPD2UDQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17200, 240},
+ /* 4656 */ {I_VCVTPD2UDQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17208, 241},
+ /* 4657 */ {I_VCVTPD2UQQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17216, 242},
+ /* 4658 */ {I_VCVTPD2UQQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17224, 242},
+ /* 4659 */ {I_VCVTPD2UQQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17232, 243},
+ /* 4660 */ {I_VCVTPH2PS, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17240, 240},
+ /* 4661 */ {I_VCVTPH2PS, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17248, 240},
+ /* 4662 */ {I_VCVTPH2PS, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+17256, 241},
+ /* 4663 */ {I_VCVTPS2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17264, 240},
+ /* 4664 */ {I_VCVTPS2DQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17272, 240},
+ /* 4665 */ {I_VCVTPS2DQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17280, 241},
+ /* 4666 */ {I_VCVTPS2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17288, 240},
+ /* 4667 */ {I_VCVTPS2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17296, 240},
+ /* 4668 */ {I_VCVTPS2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17304, 241},
+ /* 4669 */ {I_VCVTPS2PH, 3, {XMMREG,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8182, 240},
+ /* 4670 */ {I_VCVTPS2PH, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8191, 240},
+ /* 4671 */ {I_VCVTPS2PH, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ /* 4672 */ {I_VCVTPS2PH, 3, {MEMORY|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8182, 240},
+ /* 4673 */ {I_VCVTPS2PH, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8191, 240},
+ /* 4674 */ {I_VCVTPS2PH, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ /* 4675 */ {I_VCVTPS2QQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17312, 242},
+ /* 4676 */ {I_VCVTPS2QQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17320, 242},
+ /* 4677 */ {I_VCVTPS2QQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17328, 243},
+ /* 4678 */ {I_VCVTPS2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17336, 240},
+ /* 4679 */ {I_VCVTPS2UDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17344, 240},
+ /* 4680 */ {I_VCVTPS2UDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17352, 241},
+ /* 4681 */ {I_VCVTPS2UQQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17360, 242},
+ /* 4682 */ {I_VCVTPS2UQQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17368, 242},
+ /* 4683 */ {I_VCVTPS2UQQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17376, 243},
+ /* 4684 */ {I_VCVTQQ2PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17384, 242},
+ /* 4685 */ {I_VCVTQQ2PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17392, 242},
+ /* 4686 */ {I_VCVTQQ2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17400, 243},
+ /* 4687 */ {I_VCVTQQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17408, 242},
+ /* 4688 */ {I_VCVTQQ2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17416, 242},
+ /* 4689 */ {I_VCVTQQ2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17424, 243},
+ /* 4690 */ {I_VCVTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17432, 241},
+ /* 4691 */ {I_VCVTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17440, 241},
+ /* 4692 */ {I_VCVTSD2SS, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+17448, 241},
+ /* 4693 */ {I_VCVTSD2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17456, 241},
+ /* 4694 */ {I_VCVTSD2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17464, 241},
+ /* 4695 */ {I_VCVTSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17472, 241},
+ /* 4696 */ {I_VCVTSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17480, 241},
+ /* 4697 */ {I_VCVTSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17488, 241},
+ /* 4698 */ {I_VCVTSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17496, 241},
+ /* 4699 */ {I_VCVTSS2SD, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+17504, 241},
+ /* 4700 */ {I_VCVTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17512, 241},
+ /* 4701 */ {I_VCVTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17520, 241},
+ /* 4702 */ {I_VCVTSS2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17528, 241},
+ /* 4703 */ {I_VCVTSS2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17536, 241},
+ /* 4704 */ {I_VCVTTPD2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17544, 240},
+ /* 4705 */ {I_VCVTTPD2DQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17552, 240},
+ /* 4706 */ {I_VCVTTPD2DQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17560, 241},
+ /* 4707 */ {I_VCVTTPD2QQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17568, 242},
+ /* 4708 */ {I_VCVTTPD2QQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17576, 242},
+ /* 4709 */ {I_VCVTTPD2QQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17584, 243},
+ /* 4710 */ {I_VCVTTPD2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17592, 240},
+ /* 4711 */ {I_VCVTTPD2UDQ, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17600, 240},
+ /* 4712 */ {I_VCVTTPD2UDQ, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17608, 241},
+ /* 4713 */ {I_VCVTTPD2UQQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17616, 242},
+ /* 4714 */ {I_VCVTTPD2UQQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17624, 242},
+ /* 4715 */ {I_VCVTTPD2UQQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+17632, 243},
+ /* 4716 */ {I_VCVTTPS2DQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17640, 240},
+ /* 4717 */ {I_VCVTTPS2DQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17648, 240},
+ /* 4718 */ {I_VCVTTPS2DQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17656, 241},
+ /* 4719 */ {I_VCVTTPS2QQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17664, 242},
+ /* 4720 */ {I_VCVTTPS2QQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17672, 242},
+ /* 4721 */ {I_VCVTTPS2QQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17680, 243},
+ /* 4722 */ {I_VCVTTPS2UDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17688, 240},
+ /* 4723 */ {I_VCVTTPS2UDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17696, 240},
+ /* 4724 */ {I_VCVTTPS2UDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17704, 241},
+ /* 4725 */ {I_VCVTTPS2UQQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17712, 242},
+ /* 4726 */ {I_VCVTTPS2UQQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17720, 242},
+ /* 4727 */ {I_VCVTTPS2UQQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+17728, 243},
+ /* 4728 */ {I_VCVTTSD2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17736, 241},
+ /* 4729 */ {I_VCVTTSD2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17744, 241},
+ /* 4730 */ {I_VCVTTSD2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17752, 241},
+ /* 4731 */ {I_VCVTTSD2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17760, 241},
+ /* 4732 */ {I_VCVTTSS2SI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17768, 241},
+ /* 4733 */ {I_VCVTTSS2SI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17776, 241},
+ /* 4734 */ {I_VCVTTSS2USI, 2, {REG_GPR|BITS32,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17784, 241},
+ /* 4735 */ {I_VCVTTSS2USI, 2, {REG_GPR|BITS64,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+17792, 241},
+ /* 4736 */ {I_VCVTUDQ2PD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17800, 240},
+ /* 4737 */ {I_VCVTUDQ2PD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17808, 240},
+ /* 4738 */ {I_VCVTUDQ2PD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17816, 241},
+ /* 4739 */ {I_VCVTUDQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17824, 240},
+ /* 4740 */ {I_VCVTUDQ2PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17832, 240},
+ /* 4741 */ {I_VCVTUDQ2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+17840, 241},
+ /* 4742 */ {I_VCVTUQQ2PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17848, 242},
+ /* 4743 */ {I_VCVTUQQ2PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17856, 242},
+ /* 4744 */ {I_VCVTUQQ2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17864, 243},
+ /* 4745 */ {I_VCVTUQQ2PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17872, 242},
+ /* 4746 */ {I_VCVTUQQ2PS, 2, {XMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17880, 242},
+ /* 4747 */ {I_VCVTUQQ2PS, 2, {YMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17888, 243},
+ /* 4748 */ {I_VCVTUSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17896, 241},
+ /* 4749 */ {I_VCVTUSI2SD, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17904, 241},
+ /* 4750 */ {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17912, 241},
+ /* 4751 */ {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,0,0,0}, nasm_bytecodes+17920, 241},
+ /* 4752 */ {I_VDBPSADBW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8209, 244},
+ /* 4753 */ {I_VDBPSADBW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8218, 244},
+ /* 4754 */ {I_VDBPSADBW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8227, 244},
+ /* 4755 */ {I_VDBPSADBW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8236, 244},
+ /* 4756 */ {I_VDBPSADBW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8245, 245},
+ /* 4757 */ {I_VDBPSADBW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8254, 245},
+ /* 4758 */ {I_VDIVPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+17928, 240},
+ /* 4759 */ {I_VDIVPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17936, 240},
+ /* 4760 */ {I_VDIVPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+17944, 240},
+ /* 4761 */ {I_VDIVPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+17952, 240},
+ /* 4762 */ {I_VDIVPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+17960, 241},
+ /* 4763 */ {I_VDIVPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+17968, 241},
+ /* 4764 */ {I_VDIVPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+17976, 240},
+ /* 4765 */ {I_VDIVPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+17984, 240},
+ /* 4766 */ {I_VDIVPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+17992, 240},
+ /* 4767 */ {I_VDIVPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+18000, 240},
+ /* 4768 */ {I_VDIVPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18008, 241},
+ /* 4769 */ {I_VDIVPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+18016, 241},
+ /* 4770 */ {I_VDIVSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18024, 241},
+ /* 4771 */ {I_VDIVSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+18032, 241},
+ /* 4772 */ {I_VDIVSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18040, 241},
+ /* 4773 */ {I_VDIVSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+18048, 241},
+ /* 4774 */ {I_VEXP2PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+18056, 246},
+ /* 4775 */ {I_VEXP2PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+18064, 246},
+ /* 4776 */ {I_VEXPANDPD, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18072, 240},
+ /* 4777 */ {I_VEXPANDPD, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18080, 240},
+ /* 4778 */ {I_VEXPANDPD, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18088, 241},
+ /* 4779 */ {I_VEXPANDPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18072, 240},
+ /* 4780 */ {I_VEXPANDPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18080, 240},
+ /* 4781 */ {I_VEXPANDPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18088, 241},
+ /* 4782 */ {I_VEXPANDPS, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18096, 240},
+ /* 4783 */ {I_VEXPANDPS, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18104, 240},
+ /* 4784 */ {I_VEXPANDPS, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18112, 241},
+ /* 4785 */ {I_VEXPANDPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18096, 240},
+ /* 4786 */ {I_VEXPANDPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18104, 240},
+ /* 4787 */ {I_VEXPANDPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+18112, 241},
+ /* 4788 */ {I_VEXTRACTF32X4, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8263, 240},
+ /* 4789 */ {I_VEXTRACTF32X4, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8272, 241},
+ /* 4790 */ {I_VEXTRACTF32X4, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8281, 240},
+ /* 4791 */ {I_VEXTRACTF32X4, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8290, 241},
+ /* 4792 */ {I_VEXTRACTF32X8, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8299, 243},
+ /* 4793 */ {I_VEXTRACTF32X8, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8308, 243},
+ /* 4794 */ {I_VEXTRACTF64X2, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8317, 242},
+ /* 4795 */ {I_VEXTRACTF64X2, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8326, 243},
+ /* 4796 */ {I_VEXTRACTF64X2, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8335, 242},
+ /* 4797 */ {I_VEXTRACTF64X2, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8344, 243},
+ /* 4798 */ {I_VEXTRACTF64X4, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8353, 241},
+ /* 4799 */ {I_VEXTRACTF64X4, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8362, 241},
+ /* 4800 */ {I_VEXTRACTI32X4, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8371, 240},
+ /* 4801 */ {I_VEXTRACTI32X4, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8380, 241},
+ /* 4802 */ {I_VEXTRACTI32X4, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8389, 240},
+ /* 4803 */ {I_VEXTRACTI32X4, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8398, 241},
+ /* 4804 */ {I_VEXTRACTI32X8, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8407, 243},
+ /* 4805 */ {I_VEXTRACTI32X8, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8416, 243},
+ /* 4806 */ {I_VEXTRACTI64X2, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8425, 242},
+ /* 4807 */ {I_VEXTRACTI64X2, 3, {XMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8434, 243},
+ /* 4808 */ {I_VEXTRACTI64X2, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8443, 242},
+ /* 4809 */ {I_VEXTRACTI64X2, 3, {MEMORY|BITS128,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8452, 243},
+ /* 4810 */ {I_VEXTRACTI64X4, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8461, 241},
+ /* 4811 */ {I_VEXTRACTI64X4, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8470, 241},
+ /* 4812 */ {I_VEXTRACTPS, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+8479, 241},
+ /* 4813 */ {I_VEXTRACTPS, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+8479, 241},
+ /* 4814 */ {I_VEXTRACTPS, 3, {MEMORY|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+8479, 241},
+ /* 4815 */ {I_VFIXUPIMMPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8488, 240},
+ /* 4816 */ {I_VFIXUPIMMPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8497, 240},
+ /* 4817 */ {I_VFIXUPIMMPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+8506, 240},
+ /* 4818 */ {I_VFIXUPIMMPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8515, 240},
+ /* 4819 */ {I_VFIXUPIMMPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+8524, 241},
+ /* 4820 */ {I_VFIXUPIMMPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+8533, 241},
+ /* 4821 */ {I_VFIXUPIMMPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8542, 240},
+ /* 4822 */ {I_VFIXUPIMMPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8551, 240},
+ /* 4823 */ {I_VFIXUPIMMPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+8560, 240},
+ /* 4824 */ {I_VFIXUPIMMPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8569, 240},
+ /* 4825 */ {I_VFIXUPIMMPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+8578, 241},
+ /* 4826 */ {I_VFIXUPIMMPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+8587, 241},
+ /* 4827 */ {I_VFIXUPIMMSD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8596, 241},
+ /* 4828 */ {I_VFIXUPIMMSD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8605, 241},
+ /* 4829 */ {I_VFIXUPIMMSS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8614, 241},
+ /* 4830 */ {I_VFIXUPIMMSS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8623, 241},
+ /* 4831 */ {I_VFMADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18120, 240},
+ /* 4832 */ {I_VFMADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18128, 240},
+ /* 4833 */ {I_VFMADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18136, 241},
+ /* 4834 */ {I_VFMADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18144, 240},
+ /* 4835 */ {I_VFMADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18152, 240},
+ /* 4836 */ {I_VFMADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18160, 241},
+ /* 4837 */ {I_VFMADD132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18168, 241},
+ /* 4838 */ {I_VFMADD132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18176, 241},
+ /* 4839 */ {I_VFMADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18184, 240},
+ /* 4840 */ {I_VFMADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18192, 240},
+ /* 4841 */ {I_VFMADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18200, 241},
+ /* 4842 */ {I_VFMADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18208, 240},
+ /* 4843 */ {I_VFMADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18216, 240},
+ /* 4844 */ {I_VFMADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18224, 241},
+ /* 4845 */ {I_VFMADD213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18232, 241},
+ /* 4846 */ {I_VFMADD213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18240, 241},
+ /* 4847 */ {I_VFMADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18248, 240},
+ /* 4848 */ {I_VFMADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18256, 240},
+ /* 4849 */ {I_VFMADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18264, 241},
+ /* 4850 */ {I_VFMADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18272, 240},
+ /* 4851 */ {I_VFMADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18280, 240},
+ /* 4852 */ {I_VFMADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18288, 241},
+ /* 4853 */ {I_VFMADD231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18296, 241},
+ /* 4854 */ {I_VFMADD231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18304, 241},
+ /* 4855 */ {I_VFMADDSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18312, 240},
+ /* 4856 */ {I_VFMADDSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18320, 240},
+ /* 4857 */ {I_VFMADDSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18328, 241},
+ /* 4858 */ {I_VFMADDSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18336, 240},
+ /* 4859 */ {I_VFMADDSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18344, 240},
+ /* 4860 */ {I_VFMADDSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18352, 241},
+ /* 4861 */ {I_VFMADDSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18360, 240},
+ /* 4862 */ {I_VFMADDSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18368, 240},
+ /* 4863 */ {I_VFMADDSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18376, 241},
+ /* 4864 */ {I_VFMADDSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18384, 240},
+ /* 4865 */ {I_VFMADDSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18392, 240},
+ /* 4866 */ {I_VFMADDSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18400, 241},
+ /* 4867 */ {I_VFMADDSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18408, 240},
+ /* 4868 */ {I_VFMADDSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18416, 240},
+ /* 4869 */ {I_VFMADDSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18424, 241},
+ /* 4870 */ {I_VFMADDSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18432, 240},
+ /* 4871 */ {I_VFMADDSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18440, 240},
+ /* 4872 */ {I_VFMADDSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18448, 241},
+ /* 4873 */ {I_VFMSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18456, 240},
+ /* 4874 */ {I_VFMSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18464, 240},
+ /* 4875 */ {I_VFMSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18472, 241},
+ /* 4876 */ {I_VFMSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18480, 240},
+ /* 4877 */ {I_VFMSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18488, 240},
+ /* 4878 */ {I_VFMSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18496, 241},
+ /* 4879 */ {I_VFMSUB132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18504, 241},
+ /* 4880 */ {I_VFMSUB132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18512, 241},
+ /* 4881 */ {I_VFMSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18520, 240},
+ /* 4882 */ {I_VFMSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18528, 240},
+ /* 4883 */ {I_VFMSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18536, 241},
+ /* 4884 */ {I_VFMSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18544, 240},
+ /* 4885 */ {I_VFMSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18552, 240},
+ /* 4886 */ {I_VFMSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18560, 241},
+ /* 4887 */ {I_VFMSUB213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18568, 241},
+ /* 4888 */ {I_VFMSUB213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18576, 241},
+ /* 4889 */ {I_VFMSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18584, 240},
+ /* 4890 */ {I_VFMSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18592, 240},
+ /* 4891 */ {I_VFMSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18600, 241},
+ /* 4892 */ {I_VFMSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18608, 240},
+ /* 4893 */ {I_VFMSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18616, 240},
+ /* 4894 */ {I_VFMSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18624, 241},
+ /* 4895 */ {I_VFMSUB231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18632, 241},
+ /* 4896 */ {I_VFMSUB231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18640, 241},
+ /* 4897 */ {I_VFMSUBADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18648, 240},
+ /* 4898 */ {I_VFMSUBADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18656, 240},
+ /* 4899 */ {I_VFMSUBADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18664, 241},
+ /* 4900 */ {I_VFMSUBADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18672, 240},
+ /* 4901 */ {I_VFMSUBADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18680, 240},
+ /* 4902 */ {I_VFMSUBADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18688, 241},
+ /* 4903 */ {I_VFMSUBADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18696, 240},
+ /* 4904 */ {I_VFMSUBADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18704, 240},
+ /* 4905 */ {I_VFMSUBADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18712, 241},
+ /* 4906 */ {I_VFMSUBADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18720, 240},
+ /* 4907 */ {I_VFMSUBADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18728, 240},
+ /* 4908 */ {I_VFMSUBADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18736, 241},
+ /* 4909 */ {I_VFMSUBADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18744, 240},
+ /* 4910 */ {I_VFMSUBADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18752, 240},
+ /* 4911 */ {I_VFMSUBADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18760, 241},
+ /* 4912 */ {I_VFMSUBADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18768, 240},
+ /* 4913 */ {I_VFMSUBADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18776, 240},
+ /* 4914 */ {I_VFMSUBADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18784, 241},
+ /* 4915 */ {I_VFNMADD132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18792, 240},
+ /* 4916 */ {I_VFNMADD132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18800, 240},
+ /* 4917 */ {I_VFNMADD132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18808, 241},
+ /* 4918 */ {I_VFNMADD132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18816, 240},
+ /* 4919 */ {I_VFNMADD132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18824, 240},
+ /* 4920 */ {I_VFNMADD132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18832, 241},
+ /* 4921 */ {I_VFNMADD132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18840, 241},
+ /* 4922 */ {I_VFNMADD132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18848, 241},
+ /* 4923 */ {I_VFNMADD213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18856, 240},
+ /* 4924 */ {I_VFNMADD213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18864, 240},
+ /* 4925 */ {I_VFNMADD213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18872, 241},
+ /* 4926 */ {I_VFNMADD213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18880, 240},
+ /* 4927 */ {I_VFNMADD213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18888, 240},
+ /* 4928 */ {I_VFNMADD213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18896, 241},
+ /* 4929 */ {I_VFNMADD213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18904, 241},
+ /* 4930 */ {I_VFNMADD213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18912, 241},
+ /* 4931 */ {I_VFNMADD231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18920, 240},
+ /* 4932 */ {I_VFNMADD231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18928, 240},
+ /* 4933 */ {I_VFNMADD231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+18936, 241},
+ /* 4934 */ {I_VFNMADD231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18944, 240},
+ /* 4935 */ {I_VFNMADD231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+18952, 240},
+ /* 4936 */ {I_VFNMADD231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+18960, 241},
+ /* 4937 */ {I_VFNMADD231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18968, 241},
+ /* 4938 */ {I_VFNMADD231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+18976, 241},
+ /* 4939 */ {I_VFNMSUB132PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18984, 240},
+ /* 4940 */ {I_VFNMSUB132PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+18992, 240},
+ /* 4941 */ {I_VFNMSUB132PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+19000, 241},
+ /* 4942 */ {I_VFNMSUB132PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19008, 240},
+ /* 4943 */ {I_VFNMSUB132PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19016, 240},
+ /* 4944 */ {I_VFNMSUB132PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+19024, 241},
+ /* 4945 */ {I_VFNMSUB132SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19032, 241},
+ /* 4946 */ {I_VFNMSUB132SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19040, 241},
+ /* 4947 */ {I_VFNMSUB213PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19048, 240},
+ /* 4948 */ {I_VFNMSUB213PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19056, 240},
+ /* 4949 */ {I_VFNMSUB213PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+19064, 241},
+ /* 4950 */ {I_VFNMSUB213PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19072, 240},
+ /* 4951 */ {I_VFNMSUB213PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19080, 240},
+ /* 4952 */ {I_VFNMSUB213PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+19088, 241},
+ /* 4953 */ {I_VFNMSUB213SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19096, 241},
+ /* 4954 */ {I_VFNMSUB213SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19104, 241},
+ /* 4955 */ {I_VFNMSUB231PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19112, 240},
+ /* 4956 */ {I_VFNMSUB231PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19120, 240},
+ /* 4957 */ {I_VFNMSUB231PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+19128, 241},
+ /* 4958 */ {I_VFNMSUB231PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19136, 240},
+ /* 4959 */ {I_VFNMSUB231PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19144, 240},
+ /* 4960 */ {I_VFNMSUB231PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+19152, 241},
+ /* 4961 */ {I_VFNMSUB231SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19160, 241},
+ /* 4962 */ {I_VFNMSUB231SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+19168, 241},
+ /* 4963 */ {I_VFPCLASSPD, 3, {KREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+8632, 242},
+ /* 4964 */ {I_VFPCLASSPD, 3, {KREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+8641, 242},
+ /* 4965 */ {I_VFPCLASSPD, 3, {KREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK,B64,0,0,0}, nasm_bytecodes+8650, 243},
+ /* 4966 */ {I_VFPCLASSPS, 3, {KREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+8659, 242},
+ /* 4967 */ {I_VFPCLASSPS, 3, {KREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+8668, 242},
+ /* 4968 */ {I_VFPCLASSPS, 3, {KREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK,B32,0,0,0}, nasm_bytecodes+8677, 243},
+ /* 4969 */ {I_VFPCLASSSD, 3, {KREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8686, 243},
+ /* 4970 */ {I_VFPCLASSSS, 3, {KREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8695, 243},
+ /* 4971 */ {I_VGATHERDPD, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8704, 240},
+ /* 4972 */ {I_VGATHERDPD, 2, {YMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8713, 240},
+ /* 4973 */ {I_VGATHERDPD, 2, {ZMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8722, 241},
+ /* 4974 */ {I_VGATHERDPS, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8731, 240},
+ /* 4975 */ {I_VGATHERDPS, 2, {YMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8740, 240},
+ /* 4976 */ {I_VGATHERDPS, 2, {ZMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8749, 241},
+ /* 4977 */ {I_VGATHERPF0DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8758, 247},
+ /* 4978 */ {I_VGATHERPF0DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8767, 247},
+ /* 4979 */ {I_VGATHERPF0QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8776, 247},
+ /* 4980 */ {I_VGATHERPF0QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8785, 247},
+ /* 4981 */ {I_VGATHERPF1DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8794, 247},
+ /* 4982 */ {I_VGATHERPF1DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8803, 247},
+ /* 4983 */ {I_VGATHERPF1QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8812, 247},
+ /* 4984 */ {I_VGATHERPF1QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8821, 247},
+ /* 4985 */ {I_VGATHERQPD, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8830, 240},
+ /* 4986 */ {I_VGATHERQPD, 2, {YMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8839, 240},
+ /* 4987 */ {I_VGATHERQPD, 2, {ZMMREG,ZMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8848, 241},
+ /* 4988 */ {I_VGATHERQPS, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8857, 240},
+ /* 4989 */ {I_VGATHERQPS, 2, {XMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8866, 240},
+ /* 4990 */ {I_VGATHERQPS, 2, {YMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8875, 241},
+ /* 4991 */ {I_VGETEXPPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19176, 240},
+ /* 4992 */ {I_VGETEXPPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19184, 240},
+ /* 4993 */ {I_VGETEXPPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+19192, 241},
+ /* 4994 */ {I_VGETEXPPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19200, 240},
+ /* 4995 */ {I_VGETEXPPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19208, 240},
+ /* 4996 */ {I_VGETEXPPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+19216, 241},
+ /* 4997 */ {I_VGETEXPSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19224, 241},
+ /* 4998 */ {I_VGETEXPSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19232, 241},
+ /* 4999 */ {I_VGETMANTPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8884, 240},
+ /* 5000 */ {I_VGETMANTPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+8893, 240},
+ /* 5001 */ {I_VGETMANTPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+8902, 241},
+ /* 5002 */ {I_VGETMANTPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8911, 240},
+ /* 5003 */ {I_VGETMANTPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+8920, 240},
+ /* 5004 */ {I_VGETMANTPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+8929, 241},
+ /* 5005 */ {I_VGETMANTSD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8938, 241},
+ /* 5006 */ {I_VGETMANTSS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+8947, 241},
+ /* 5007 */ {I_VINSERTF32X4, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8956, 240},
+ /* 5008 */ {I_VINSERTF32X4, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8965, 240},
+ /* 5009 */ {I_VINSERTF32X4, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8974, 241},
+ /* 5010 */ {I_VINSERTF32X4, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8983, 241},
+ /* 5011 */ {I_VINSERTF32X8, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8992, 243},
+ /* 5012 */ {I_VINSERTF32X8, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9001, 243},
+ /* 5013 */ {I_VINSERTF64X2, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9010, 242},
+ /* 5014 */ {I_VINSERTF64X2, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9019, 242},
+ /* 5015 */ {I_VINSERTF64X2, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9028, 243},
+ /* 5016 */ {I_VINSERTF64X2, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9037, 243},
+ /* 5017 */ {I_VINSERTF64X4, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9046, 241},
+ /* 5018 */ {I_VINSERTF64X4, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9055, 241},
+ /* 5019 */ {I_VINSERTI32X4, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9064, 240},
+ /* 5020 */ {I_VINSERTI32X4, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9073, 240},
+ /* 5021 */ {I_VINSERTI32X4, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9082, 241},
+ /* 5022 */ {I_VINSERTI32X4, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9091, 241},
+ /* 5023 */ {I_VINSERTI32X8, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9100, 243},
+ /* 5024 */ {I_VINSERTI32X8, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9109, 243},
+ /* 5025 */ {I_VINSERTI64X2, 4, {YMMREG,YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9118, 242},
+ /* 5026 */ {I_VINSERTI64X2, 3, {YMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9127, 242},
+ /* 5027 */ {I_VINSERTI64X2, 4, {ZMMREG,ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9136, 243},
+ /* 5028 */ {I_VINSERTI64X2, 3, {ZMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9145, 243},
+ /* 5029 */ {I_VINSERTI64X4, 4, {ZMMREG,ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9154, 241},
+ /* 5030 */ {I_VINSERTI64X4, 3, {ZMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9163, 241},
+ /* 5031 */ {I_VINSERTPS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9172, 241},
+ /* 5032 */ {I_VINSERTPS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9181, 241},
+ /* 5033 */ {I_VMAXPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19240, 240},
+ /* 5034 */ {I_VMAXPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19248, 240},
+ /* 5035 */ {I_VMAXPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19256, 240},
+ /* 5036 */ {I_VMAXPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19264, 240},
+ /* 5037 */ {I_VMAXPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+19272, 241},
+ /* 5038 */ {I_VMAXPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+19280, 241},
+ /* 5039 */ {I_VMAXPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19288, 240},
+ /* 5040 */ {I_VMAXPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19296, 240},
+ /* 5041 */ {I_VMAXPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19304, 240},
+ /* 5042 */ {I_VMAXPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19312, 240},
+ /* 5043 */ {I_VMAXPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+19320, 241},
+ /* 5044 */ {I_VMAXPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+19328, 241},
+ /* 5045 */ {I_VMAXSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19336, 241},
+ /* 5046 */ {I_VMAXSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19344, 241},
+ /* 5047 */ {I_VMAXSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19352, 241},
+ /* 5048 */ {I_VMAXSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19360, 241},
+ /* 5049 */ {I_VMINPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19368, 240},
+ /* 5050 */ {I_VMINPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19376, 240},
+ /* 5051 */ {I_VMINPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+19384, 240},
+ /* 5052 */ {I_VMINPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+19392, 240},
+ /* 5053 */ {I_VMINPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+19400, 241},
+ /* 5054 */ {I_VMINPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+19408, 241},
+ /* 5055 */ {I_VMINPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19416, 240},
+ /* 5056 */ {I_VMINPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19424, 240},
+ /* 5057 */ {I_VMINPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+19432, 240},
+ /* 5058 */ {I_VMINPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+19440, 240},
+ /* 5059 */ {I_VMINPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+19448, 241},
+ /* 5060 */ {I_VMINPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+19456, 241},
+ /* 5061 */ {I_VMINSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19464, 241},
+ /* 5062 */ {I_VMINSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19472, 241},
+ /* 5063 */ {I_VMINSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+19480, 241},
+ /* 5064 */ {I_VMINSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+19488, 241},
+ /* 5065 */ {I_VMOVAPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19496, 240},
+ /* 5066 */ {I_VMOVAPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19504, 240},
+ /* 5067 */ {I_VMOVAPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19512, 241},
+ /* 5068 */ {I_VMOVAPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19520, 240},
+ /* 5069 */ {I_VMOVAPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19528, 240},
+ /* 5070 */ {I_VMOVAPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19536, 241},
+ /* 5071 */ {I_VMOVAPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19544, 240},
+ /* 5072 */ {I_VMOVAPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19552, 240},
+ /* 5073 */ {I_VMOVAPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19560, 241},
+ /* 5074 */ {I_VMOVAPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19568, 240},
+ /* 5075 */ {I_VMOVAPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19576, 240},
+ /* 5076 */ {I_VMOVAPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19584, 241},
+ /* 5077 */ {I_VMOVAPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19592, 240},
+ /* 5078 */ {I_VMOVAPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19600, 240},
+ /* 5079 */ {I_VMOVAPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19608, 241},
+ /* 5080 */ {I_VMOVAPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19616, 240},
+ /* 5081 */ {I_VMOVAPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19624, 240},
+ /* 5082 */ {I_VMOVAPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+19632, 241},
+ /* 5083 */ {I_VMOVD, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+19640, 241},
+ /* 5084 */ {I_VMOVD, 2, {RM_GPR|BITS32,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+19648, 241},
+ /* 5085 */ {I_VMOVDDUP, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19656, 240},
+ /* 5086 */ {I_VMOVDDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19664, 240},
+ /* 5087 */ {I_VMOVDDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19672, 241},
+ /* 5088 */ {I_VMOVDQA32, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19680, 240},
+ /* 5089 */ {I_VMOVDQA32, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19688, 240},
+ /* 5090 */ {I_VMOVDQA32, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19696, 241},
+ /* 5091 */ {I_VMOVDQA32, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19704, 240},
+ /* 5092 */ {I_VMOVDQA32, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19712, 240},
+ /* 5093 */ {I_VMOVDQA32, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19720, 241},
+ /* 5094 */ {I_VMOVDQA64, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19728, 240},
+ /* 5095 */ {I_VMOVDQA64, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19736, 240},
+ /* 5096 */ {I_VMOVDQA64, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19744, 241},
+ /* 5097 */ {I_VMOVDQA64, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19752, 240},
+ /* 5098 */ {I_VMOVDQA64, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19760, 240},
+ /* 5099 */ {I_VMOVDQA64, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19768, 241},
+ /* 5100 */ {I_VMOVDQU16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19776, 244},
+ /* 5101 */ {I_VMOVDQU16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19784, 244},
+ /* 5102 */ {I_VMOVDQU16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19792, 245},
+ /* 5103 */ {I_VMOVDQU16, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19800, 244},
+ /* 5104 */ {I_VMOVDQU16, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19808, 244},
+ /* 5105 */ {I_VMOVDQU16, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19816, 245},
+ /* 5106 */ {I_VMOVDQU32, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19824, 240},
+ /* 5107 */ {I_VMOVDQU32, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19832, 240},
+ /* 5108 */ {I_VMOVDQU32, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19840, 241},
+ /* 5109 */ {I_VMOVDQU32, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19848, 240},
+ /* 5110 */ {I_VMOVDQU32, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19856, 240},
+ /* 5111 */ {I_VMOVDQU32, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19864, 241},
+ /* 5112 */ {I_VMOVDQU64, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19872, 240},
+ /* 5113 */ {I_VMOVDQU64, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19880, 240},
+ /* 5114 */ {I_VMOVDQU64, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19888, 241},
+ /* 5115 */ {I_VMOVDQU64, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19896, 240},
+ /* 5116 */ {I_VMOVDQU64, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19904, 240},
+ /* 5117 */ {I_VMOVDQU64, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19912, 241},
+ /* 5118 */ {I_VMOVDQU8, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19920, 244},
+ /* 5119 */ {I_VMOVDQU8, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19928, 244},
+ /* 5120 */ {I_VMOVDQU8, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19936, 245},
+ /* 5121 */ {I_VMOVDQU8, 2, {RM_XMM|BITS128,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19944, 244},
+ /* 5122 */ {I_VMOVDQU8, 2, {RM_YMM|BITS256,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19952, 244},
+ /* 5123 */ {I_VMOVDQU8, 2, {RM_ZMM|BITS512,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+19960, 245},
+ /* 5124 */ {I_VMOVHLPS, 3, {XMMREG,XMMREG,XMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+19968, 241},
+ /* 5125 */ {I_VMOVHLPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+19976, 241},
+ /* 5126 */ {I_VMOVHPD, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+19984, 241},
+ /* 5127 */ {I_VMOVHPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+19992, 241},
+ /* 5128 */ {I_VMOVHPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20000, 241},
+ /* 5129 */ {I_VMOVHPS, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+20008, 241},
+ /* 5130 */ {I_VMOVHPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20016, 241},
+ /* 5131 */ {I_VMOVHPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20024, 241},
+ /* 5132 */ {I_VMOVLHPS, 3, {XMMREG,XMMREG,XMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+20032, 241},
+ /* 5133 */ {I_VMOVLHPS, 2, {XMMREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20040, 241},
+ /* 5134 */ {I_VMOVLPD, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+20048, 241},
+ /* 5135 */ {I_VMOVLPD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20056, 241},
+ /* 5136 */ {I_VMOVLPD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20064, 241},
+ /* 5137 */ {I_VMOVLPS, 3, {XMMREG,XMMREG,MEMORY|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+20072, 241},
+ /* 5138 */ {I_VMOVLPS, 2, {XMMREG,MEMORY|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20080, 241},
+ /* 5139 */ {I_VMOVLPS, 2, {MEMORY|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20088, 241},
+ /* 5140 */ {I_VMOVNTDQ, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20096, 240},
+ /* 5141 */ {I_VMOVNTDQ, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20104, 240},
+ /* 5142 */ {I_VMOVNTDQ, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20112, 241},
+ /* 5143 */ {I_VMOVNTDQA, 2, {XMMREG,MEMORY|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+20120, 240},
+ /* 5144 */ {I_VMOVNTDQA, 2, {YMMREG,MEMORY|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+20128, 240},
+ /* 5145 */ {I_VMOVNTDQA, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+20136, 241},
+ /* 5146 */ {I_VMOVNTPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20144, 240},
+ /* 5147 */ {I_VMOVNTPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20152, 240},
+ /* 5148 */ {I_VMOVNTPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20160, 241},
+ /* 5149 */ {I_VMOVNTPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20168, 240},
+ /* 5150 */ {I_VMOVNTPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20176, 240},
+ /* 5151 */ {I_VMOVNTPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20184, 241},
+ /* 5152 */ {I_VMOVQ, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20192, 241},
+ /* 5153 */ {I_VMOVQ, 2, {RM_GPR|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20200, 241},
+ /* 5154 */ {I_VMOVQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+20208, 241},
+ /* 5155 */ {I_VMOVQ, 2, {RM_XMM|BITS64,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+20216, 241},
+ /* 5156 */ {I_VMOVSD, 2, {XMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20224, 241},
+ /* 5157 */ {I_VMOVSD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20232, 241},
+ /* 5158 */ {I_VMOVSD, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20240, 241},
+ /* 5159 */ {I_VMOVSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20248, 241},
+ /* 5160 */ {I_VMOVSD, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20256, 241},
+ /* 5161 */ {I_VMOVSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20264, 241},
+ /* 5162 */ {I_VMOVSHDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20272, 240},
+ /* 5163 */ {I_VMOVSHDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20280, 240},
+ /* 5164 */ {I_VMOVSHDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20288, 241},
+ /* 5165 */ {I_VMOVSLDUP, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20296, 240},
+ /* 5166 */ {I_VMOVSLDUP, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20304, 240},
+ /* 5167 */ {I_VMOVSLDUP, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20312, 241},
+ /* 5168 */ {I_VMOVSS, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20320, 241},
+ /* 5169 */ {I_VMOVSS, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20328, 241},
+ /* 5170 */ {I_VMOVSS, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20336, 241},
+ /* 5171 */ {I_VMOVSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20344, 241},
+ /* 5172 */ {I_VMOVSS, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20352, 241},
+ /* 5173 */ {I_VMOVSS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20360, 241},
+ /* 5174 */ {I_VMOVUPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20368, 240},
+ /* 5175 */ {I_VMOVUPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20376, 240},
+ /* 5176 */ {I_VMOVUPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20384, 241},
+ /* 5177 */ {I_VMOVUPD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20392, 240},
+ /* 5178 */ {I_VMOVUPD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20400, 240},
+ /* 5179 */ {I_VMOVUPD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20408, 241},
+ /* 5180 */ {I_VMOVUPD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20416, 240},
+ /* 5181 */ {I_VMOVUPD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20424, 240},
+ /* 5182 */ {I_VMOVUPD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20432, 241},
+ /* 5183 */ {I_VMOVUPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20440, 240},
+ /* 5184 */ {I_VMOVUPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20448, 240},
+ /* 5185 */ {I_VMOVUPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20456, 241},
+ /* 5186 */ {I_VMOVUPS, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20464, 240},
+ /* 5187 */ {I_VMOVUPS, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20472, 240},
+ /* 5188 */ {I_VMOVUPS, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20480, 241},
+ /* 5189 */ {I_VMOVUPS, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20488, 240},
+ /* 5190 */ {I_VMOVUPS, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20496, 240},
+ /* 5191 */ {I_VMOVUPS, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+20504, 241},
+ /* 5192 */ {I_VMULPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20512, 240},
+ /* 5193 */ {I_VMULPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20520, 240},
+ /* 5194 */ {I_VMULPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20528, 240},
+ /* 5195 */ {I_VMULPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20536, 240},
+ /* 5196 */ {I_VMULPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+20544, 241},
+ /* 5197 */ {I_VMULPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+20552, 241},
+ /* 5198 */ {I_VMULPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20560, 240},
+ /* 5199 */ {I_VMULPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20568, 240},
+ /* 5200 */ {I_VMULPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20576, 240},
+ /* 5201 */ {I_VMULPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20584, 240},
+ /* 5202 */ {I_VMULPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+20592, 241},
+ /* 5203 */ {I_VMULPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+20600, 241},
+ /* 5204 */ {I_VMULSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+20608, 241},
+ /* 5205 */ {I_VMULSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+20616, 241},
+ /* 5206 */ {I_VMULSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+20624, 241},
+ /* 5207 */ {I_VMULSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+20632, 241},
+ /* 5208 */ {I_VORPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20640, 242},
+ /* 5209 */ {I_VORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20648, 242},
+ /* 5210 */ {I_VORPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20656, 242},
+ /* 5211 */ {I_VORPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20664, 242},
+ /* 5212 */ {I_VORPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+20672, 243},
+ /* 5213 */ {I_VORPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20680, 243},
+ /* 5214 */ {I_VORPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20688, 242},
+ /* 5215 */ {I_VORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20696, 242},
+ /* 5216 */ {I_VORPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20704, 242},
+ /* 5217 */ {I_VORPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20712, 242},
+ /* 5218 */ {I_VORPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20720, 243},
+ /* 5219 */ {I_VORPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20728, 243},
+ /* 5220 */ {I_VPABSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20736, 244},
+ /* 5221 */ {I_VPABSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20744, 244},
+ /* 5222 */ {I_VPABSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20752, 245},
+ /* 5223 */ {I_VPABSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20760, 240},
+ /* 5224 */ {I_VPABSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20768, 240},
+ /* 5225 */ {I_VPABSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20776, 241},
+ /* 5226 */ {I_VPABSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20784, 240},
+ /* 5227 */ {I_VPABSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20792, 240},
+ /* 5228 */ {I_VPABSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+20800, 241},
+ /* 5229 */ {I_VPABSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20808, 244},
+ /* 5230 */ {I_VPABSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20816, 244},
+ /* 5231 */ {I_VPABSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20824, 245},
+ /* 5232 */ {I_VPACKSSDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20832, 244},
+ /* 5233 */ {I_VPACKSSDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20840, 244},
+ /* 5234 */ {I_VPACKSSDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20848, 244},
+ /* 5235 */ {I_VPACKSSDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20856, 244},
+ /* 5236 */ {I_VPACKSSDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20864, 245},
+ /* 5237 */ {I_VPACKSSDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20872, 245},
+ /* 5238 */ {I_VPACKSSWB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20880, 244},
+ /* 5239 */ {I_VPACKSSWB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20888, 244},
+ /* 5240 */ {I_VPACKSSWB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20896, 244},
+ /* 5241 */ {I_VPACKSSWB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20904, 244},
+ /* 5242 */ {I_VPACKSSWB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20912, 245},
+ /* 5243 */ {I_VPACKSSWB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20920, 245},
+ /* 5244 */ {I_VPACKUSDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20928, 244},
+ /* 5245 */ {I_VPACKUSDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20936, 244},
+ /* 5246 */ {I_VPACKUSDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20944, 244},
+ /* 5247 */ {I_VPACKUSDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20952, 244},
+ /* 5248 */ {I_VPACKUSDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+20960, 245},
+ /* 5249 */ {I_VPACKUSDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+20968, 245},
+ /* 5250 */ {I_VPACKUSWB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20976, 244},
+ /* 5251 */ {I_VPACKUSWB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20984, 244},
+ /* 5252 */ {I_VPACKUSWB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+20992, 244},
+ /* 5253 */ {I_VPACKUSWB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21000, 244},
+ /* 5254 */ {I_VPACKUSWB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21008, 245},
+ /* 5255 */ {I_VPACKUSWB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21016, 245},
+ /* 5256 */ {I_VPADDB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21024, 244},
+ /* 5257 */ {I_VPADDB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21032, 244},
+ /* 5258 */ {I_VPADDB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21040, 244},
+ /* 5259 */ {I_VPADDB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21048, 244},
+ /* 5260 */ {I_VPADDB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21056, 245},
+ /* 5261 */ {I_VPADDB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21064, 245},
+ /* 5262 */ {I_VPADDD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21072, 240},
+ /* 5263 */ {I_VPADDD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21080, 240},
+ /* 5264 */ {I_VPADDD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21088, 240},
+ /* 5265 */ {I_VPADDD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21096, 240},
+ /* 5266 */ {I_VPADDD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21104, 241},
+ /* 5267 */ {I_VPADDD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21112, 241},
+ /* 5268 */ {I_VPADDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21120, 240},
+ /* 5269 */ {I_VPADDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21128, 240},
+ /* 5270 */ {I_VPADDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21136, 240},
+ /* 5271 */ {I_VPADDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21144, 240},
+ /* 5272 */ {I_VPADDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21152, 241},
+ /* 5273 */ {I_VPADDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21160, 241},
+ /* 5274 */ {I_VPADDSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21168, 244},
+ /* 5275 */ {I_VPADDSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21176, 244},
+ /* 5276 */ {I_VPADDSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21184, 244},
+ /* 5277 */ {I_VPADDSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21192, 244},
+ /* 5278 */ {I_VPADDSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21200, 245},
+ /* 5279 */ {I_VPADDSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21208, 245},
+ /* 5280 */ {I_VPADDSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21216, 244},
+ /* 5281 */ {I_VPADDSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21224, 244},
+ /* 5282 */ {I_VPADDSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21232, 244},
+ /* 5283 */ {I_VPADDSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21240, 244},
+ /* 5284 */ {I_VPADDSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21248, 245},
+ /* 5285 */ {I_VPADDSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21256, 245},
+ /* 5286 */ {I_VPADDUSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21264, 244},
+ /* 5287 */ {I_VPADDUSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21272, 244},
+ /* 5288 */ {I_VPADDUSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21280, 244},
+ /* 5289 */ {I_VPADDUSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21288, 244},
+ /* 5290 */ {I_VPADDUSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21296, 245},
+ /* 5291 */ {I_VPADDUSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21304, 245},
+ /* 5292 */ {I_VPADDUSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21312, 244},
+ /* 5293 */ {I_VPADDUSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21320, 244},
+ /* 5294 */ {I_VPADDUSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21328, 244},
+ /* 5295 */ {I_VPADDUSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21336, 244},
+ /* 5296 */ {I_VPADDUSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21344, 245},
+ /* 5297 */ {I_VPADDUSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21352, 245},
+ /* 5298 */ {I_VPADDW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21360, 244},
+ /* 5299 */ {I_VPADDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21368, 244},
+ /* 5300 */ {I_VPADDW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21376, 244},
+ /* 5301 */ {I_VPADDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21384, 244},
+ /* 5302 */ {I_VPADDW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21392, 245},
+ /* 5303 */ {I_VPADDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21400, 245},
+ /* 5304 */ {I_VPALIGNR, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9190, 244},
+ /* 5305 */ {I_VPALIGNR, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9199, 244},
+ /* 5306 */ {I_VPALIGNR, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9208, 244},
+ /* 5307 */ {I_VPALIGNR, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9217, 244},
+ /* 5308 */ {I_VPALIGNR, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9226, 245},
+ /* 5309 */ {I_VPALIGNR, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9235, 245},
+ /* 5310 */ {I_VPANDD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21408, 240},
+ /* 5311 */ {I_VPANDD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21416, 240},
+ /* 5312 */ {I_VPANDD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21424, 240},
+ /* 5313 */ {I_VPANDD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21432, 240},
+ /* 5314 */ {I_VPANDD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21440, 241},
+ /* 5315 */ {I_VPANDD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21448, 241},
+ /* 5316 */ {I_VPANDND, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21456, 240},
+ /* 5317 */ {I_VPANDND, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21464, 240},
+ /* 5318 */ {I_VPANDND, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21472, 240},
+ /* 5319 */ {I_VPANDND, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21480, 240},
+ /* 5320 */ {I_VPANDND, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21488, 241},
+ /* 5321 */ {I_VPANDND, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+21496, 241},
+ /* 5322 */ {I_VPANDNQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21504, 240},
+ /* 5323 */ {I_VPANDNQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21512, 240},
+ /* 5324 */ {I_VPANDNQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21520, 240},
+ /* 5325 */ {I_VPANDNQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21528, 240},
+ /* 5326 */ {I_VPANDNQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21536, 241},
+ /* 5327 */ {I_VPANDNQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21544, 241},
+ /* 5328 */ {I_VPANDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21552, 240},
+ /* 5329 */ {I_VPANDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21560, 240},
+ /* 5330 */ {I_VPANDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21568, 240},
+ /* 5331 */ {I_VPANDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21576, 240},
+ /* 5332 */ {I_VPANDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21584, 241},
+ /* 5333 */ {I_VPANDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+21592, 241},
+ /* 5334 */ {I_VPAVGB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21600, 244},
+ /* 5335 */ {I_VPAVGB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21608, 244},
+ /* 5336 */ {I_VPAVGB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21616, 244},
+ /* 5337 */ {I_VPAVGB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21624, 244},
+ /* 5338 */ {I_VPAVGB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21632, 245},
+ /* 5339 */ {I_VPAVGB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21640, 245},
+ /* 5340 */ {I_VPAVGW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21648, 244},
+ /* 5341 */ {I_VPAVGW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21656, 244},
+ /* 5342 */ {I_VPAVGW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21664, 244},
+ /* 5343 */ {I_VPAVGW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21672, 244},
+ /* 5344 */ {I_VPAVGW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21680, 245},
+ /* 5345 */ {I_VPAVGW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21688, 245},
+ /* 5346 */ {I_VPBLENDMB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21696, 244},
+ /* 5347 */ {I_VPBLENDMB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21704, 244},
+ /* 5348 */ {I_VPBLENDMB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21712, 245},
+ /* 5349 */ {I_VPBLENDMD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21720, 240},
+ /* 5350 */ {I_VPBLENDMD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21728, 240},
+ /* 5351 */ {I_VPBLENDMD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+21736, 241},
+ /* 5352 */ {I_VPBLENDMQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21744, 240},
+ /* 5353 */ {I_VPBLENDMQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21752, 240},
+ /* 5354 */ {I_VPBLENDMQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+21760, 241},
+ /* 5355 */ {I_VPBLENDMW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21768, 244},
+ /* 5356 */ {I_VPBLENDMW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21776, 244},
+ /* 5357 */ {I_VPBLENDMW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21784, 245},
+ /* 5358 */ {I_VPBROADCASTB, 2, {XMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21792, 244},
+ /* 5359 */ {I_VPBROADCASTB, 2, {YMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21800, 244},
+ /* 5360 */ {I_VPBROADCASTB, 2, {ZMMREG,RM_XMM|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21808, 245},
+ /* 5361 */ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ /* 5362 */ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ /* 5363 */ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ /* 5364 */ {I_VPBROADCASTB, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21816, 244},
+ /* 5365 */ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ /* 5366 */ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ /* 5367 */ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ /* 5368 */ {I_VPBROADCASTB, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21824, 244},
+ /* 5369 */ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ /* 5370 */ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ /* 5371 */ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ /* 5372 */ {I_VPBROADCASTB, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21832, 245},
+ /* 5373 */ {I_VPBROADCASTD, 2, {XMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21840, 240},
+ /* 5374 */ {I_VPBROADCASTD, 2, {YMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21848, 240},
+ /* 5375 */ {I_VPBROADCASTD, 2, {ZMMREG,MEMORY|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21856, 241},
+ /* 5376 */ {I_VPBROADCASTD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21864, 240},
+ /* 5377 */ {I_VPBROADCASTD, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21872, 240},
+ /* 5378 */ {I_VPBROADCASTD, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21880, 241},
+ /* 5379 */ {I_VPBROADCASTD, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21888, 240},
+ /* 5380 */ {I_VPBROADCASTD, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21896, 240},
+ /* 5381 */ {I_VPBROADCASTD, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21904, 241},
+ /* 5382 */ {I_VPBROADCASTMB2Q, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21912, 248},
+ /* 5383 */ {I_VPBROADCASTMB2Q, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21920, 248},
+ /* 5384 */ {I_VPBROADCASTMB2Q, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21928, 249},
+ /* 5385 */ {I_VPBROADCASTMW2D, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21936, 248},
+ /* 5386 */ {I_VPBROADCASTMW2D, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21944, 248},
+ /* 5387 */ {I_VPBROADCASTMW2D, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+21952, 249},
+ /* 5388 */ {I_VPBROADCASTQ, 2, {XMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21960, 240},
+ /* 5389 */ {I_VPBROADCASTQ, 2, {YMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21968, 240},
+ /* 5390 */ {I_VPBROADCASTQ, 2, {ZMMREG,MEMORY|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21976, 241},
+ /* 5391 */ {I_VPBROADCASTQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21984, 240},
+ /* 5392 */ {I_VPBROADCASTQ, 2, {YMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+21992, 240},
+ /* 5393 */ {I_VPBROADCASTQ, 2, {ZMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22000, 241},
+ /* 5394 */ {I_VPBROADCASTQ, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22008, 240},
+ /* 5395 */ {I_VPBROADCASTQ, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22016, 240},
+ /* 5396 */ {I_VPBROADCASTQ, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22024, 241},
+ /* 5397 */ {I_VPBROADCASTW, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22032, 244},
+ /* 5398 */ {I_VPBROADCASTW, 2, {YMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22040, 244},
+ /* 5399 */ {I_VPBROADCASTW, 2, {ZMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22048, 245},
+ /* 5400 */ {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22056, 244},
+ /* 5401 */ {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22056, 244},
+ /* 5402 */ {I_VPBROADCASTW, 2, {XMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22056, 244},
+ /* 5403 */ {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22064, 244},
+ /* 5404 */ {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22064, 244},
+ /* 5405 */ {I_VPBROADCASTW, 2, {YMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22064, 244},
+ /* 5406 */ {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22072, 245},
+ /* 5407 */ {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22072, 245},
+ /* 5408 */ {I_VPBROADCASTW, 2, {ZMMREG,REG_GPR|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22072, 245},
+ /* 5409 */ {I_VPCMPEQB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22080, 244},
+ /* 5410 */ {I_VPCMPEQB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22088, 244},
+ /* 5411 */ {I_VPCMPEQB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22096, 245},
+ /* 5412 */ {I_VPCMPEQD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22104, 240},
+ /* 5413 */ {I_VPCMPEQD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22112, 240},
+ /* 5414 */ {I_VPCMPEQD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22120, 241},
+ /* 5415 */ {I_VPCMPEQQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22128, 240},
+ /* 5416 */ {I_VPCMPEQQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22136, 240},
+ /* 5417 */ {I_VPCMPEQQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22144, 241},
+ /* 5418 */ {I_VPCMPEQW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22152, 244},
+ /* 5419 */ {I_VPCMPEQW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22160, 244},
+ /* 5420 */ {I_VPCMPEQW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22168, 245},
+ /* 5421 */ {I_VPCMPGTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22176, 244},
+ /* 5422 */ {I_VPCMPGTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22184, 244},
+ /* 5423 */ {I_VPCMPGTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22192, 245},
+ /* 5424 */ {I_VPCMPGTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22200, 240},
+ /* 5425 */ {I_VPCMPGTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22208, 240},
+ /* 5426 */ {I_VPCMPGTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+22216, 241},
+ /* 5427 */ {I_VPCMPGTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22224, 240},
+ /* 5428 */ {I_VPCMPGTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22232, 240},
+ /* 5429 */ {I_VPCMPGTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+22240, 241},
+ /* 5430 */ {I_VPCMPGTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22248, 244},
+ /* 5431 */ {I_VPCMPGTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22256, 244},
+ /* 5432 */ {I_VPCMPGTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22264, 245},
+ /* 5433 */ {I_VPCMPEQB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2800, 244},
+ /* 5434 */ {I_VPCMPEQB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2810, 244},
+ /* 5435 */ {I_VPCMPEQB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2820, 245},
+ /* 5436 */ {I_VPCMPEQD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2830, 240},
+ /* 5437 */ {I_VPCMPEQD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2840, 240},
+ /* 5438 */ {I_VPCMPEQD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2850, 241},
+ /* 5439 */ {I_VPCMPEQQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2860, 240},
+ /* 5440 */ {I_VPCMPEQQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2870, 240},
+ /* 5441 */ {I_VPCMPEQQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2880, 241},
+ /* 5442 */ {I_VPCMPEQUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2890, 244},
+ /* 5443 */ {I_VPCMPEQUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2900, 244},
+ /* 5444 */ {I_VPCMPEQUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2910, 245},
+ /* 5445 */ {I_VPCMPEQUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2920, 240},
+ /* 5446 */ {I_VPCMPEQUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2930, 240},
+ /* 5447 */ {I_VPCMPEQUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+2940, 241},
+ /* 5448 */ {I_VPCMPEQUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2950, 240},
+ /* 5449 */ {I_VPCMPEQUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2960, 240},
+ /* 5450 */ {I_VPCMPEQUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+2970, 241},
+ /* 5451 */ {I_VPCMPEQUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2980, 244},
+ /* 5452 */ {I_VPCMPEQUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+2990, 244},
+ /* 5453 */ {I_VPCMPEQUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3000, 245},
+ /* 5454 */ {I_VPCMPEQW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3010, 244},
+ /* 5455 */ {I_VPCMPEQW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3020, 244},
+ /* 5456 */ {I_VPCMPEQW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3030, 245},
+ /* 5457 */ {I_VPCMPGEB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3040, 244},
+ /* 5458 */ {I_VPCMPGEB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3050, 244},
+ /* 5459 */ {I_VPCMPGEB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3060, 245},
+ /* 5460 */ {I_VPCMPGED, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3070, 240},
+ /* 5461 */ {I_VPCMPGED, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3080, 240},
+ /* 5462 */ {I_VPCMPGED, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3090, 241},
+ /* 5463 */ {I_VPCMPGEQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3100, 240},
+ /* 5464 */ {I_VPCMPGEQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3110, 240},
+ /* 5465 */ {I_VPCMPGEQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3120, 241},
+ /* 5466 */ {I_VPCMPGEUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3130, 244},
+ /* 5467 */ {I_VPCMPGEUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3140, 244},
+ /* 5468 */ {I_VPCMPGEUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3150, 245},
+ /* 5469 */ {I_VPCMPGEUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3160, 240},
+ /* 5470 */ {I_VPCMPGEUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3170, 240},
+ /* 5471 */ {I_VPCMPGEUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3180, 241},
+ /* 5472 */ {I_VPCMPGEUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3190, 240},
+ /* 5473 */ {I_VPCMPGEUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3200, 240},
+ /* 5474 */ {I_VPCMPGEUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3210, 241},
+ /* 5475 */ {I_VPCMPGEUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3220, 244},
+ /* 5476 */ {I_VPCMPGEUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3230, 244},
+ /* 5477 */ {I_VPCMPGEUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3240, 245},
+ /* 5478 */ {I_VPCMPGEW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3250, 244},
+ /* 5479 */ {I_VPCMPGEW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3260, 244},
+ /* 5480 */ {I_VPCMPGEW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3270, 245},
+ /* 5481 */ {I_VPCMPGTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3280, 244},
+ /* 5482 */ {I_VPCMPGTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3290, 244},
+ /* 5483 */ {I_VPCMPGTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3300, 245},
+ /* 5484 */ {I_VPCMPGTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3310, 240},
+ /* 5485 */ {I_VPCMPGTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3320, 240},
+ /* 5486 */ {I_VPCMPGTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3330, 241},
+ /* 5487 */ {I_VPCMPGTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3340, 240},
+ /* 5488 */ {I_VPCMPGTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3350, 240},
+ /* 5489 */ {I_VPCMPGTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3360, 241},
+ /* 5490 */ {I_VPCMPGTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3370, 244},
+ /* 5491 */ {I_VPCMPGTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3380, 244},
+ /* 5492 */ {I_VPCMPGTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3390, 245},
+ /* 5493 */ {I_VPCMPGTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3400, 240},
+ /* 5494 */ {I_VPCMPGTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3410, 240},
+ /* 5495 */ {I_VPCMPGTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3420, 241},
+ /* 5496 */ {I_VPCMPGTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3430, 240},
+ /* 5497 */ {I_VPCMPGTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3440, 240},
+ /* 5498 */ {I_VPCMPGTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3450, 241},
+ /* 5499 */ {I_VPCMPGTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3460, 244},
+ /* 5500 */ {I_VPCMPGTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3470, 244},
+ /* 5501 */ {I_VPCMPGTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3480, 245},
+ /* 5502 */ {I_VPCMPGTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3490, 244},
+ /* 5503 */ {I_VPCMPGTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3500, 244},
+ /* 5504 */ {I_VPCMPGTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3510, 245},
+ /* 5505 */ {I_VPCMPLEB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3520, 244},
+ /* 5506 */ {I_VPCMPLEB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3530, 244},
+ /* 5507 */ {I_VPCMPLEB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3540, 245},
+ /* 5508 */ {I_VPCMPLED, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3550, 240},
+ /* 5509 */ {I_VPCMPLED, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3560, 240},
+ /* 5510 */ {I_VPCMPLED, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3570, 241},
+ /* 5511 */ {I_VPCMPLEQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3580, 240},
+ /* 5512 */ {I_VPCMPLEQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3590, 240},
+ /* 5513 */ {I_VPCMPLEQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3600, 241},
+ /* 5514 */ {I_VPCMPLEUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3610, 244},
+ /* 5515 */ {I_VPCMPLEUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3620, 244},
+ /* 5516 */ {I_VPCMPLEUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3630, 245},
+ /* 5517 */ {I_VPCMPLEUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3640, 240},
+ /* 5518 */ {I_VPCMPLEUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3650, 240},
+ /* 5519 */ {I_VPCMPLEUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3660, 241},
+ /* 5520 */ {I_VPCMPLEUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3670, 240},
+ /* 5521 */ {I_VPCMPLEUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3680, 240},
+ /* 5522 */ {I_VPCMPLEUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3690, 241},
+ /* 5523 */ {I_VPCMPLEUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3700, 244},
+ /* 5524 */ {I_VPCMPLEUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3710, 244},
+ /* 5525 */ {I_VPCMPLEUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3720, 245},
+ /* 5526 */ {I_VPCMPLEW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3730, 244},
+ /* 5527 */ {I_VPCMPLEW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3740, 244},
+ /* 5528 */ {I_VPCMPLEW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3750, 245},
+ /* 5529 */ {I_VPCMPLTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3760, 244},
+ /* 5530 */ {I_VPCMPLTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3770, 244},
+ /* 5531 */ {I_VPCMPLTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3780, 245},
+ /* 5532 */ {I_VPCMPLTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3790, 240},
+ /* 5533 */ {I_VPCMPLTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3800, 240},
+ /* 5534 */ {I_VPCMPLTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3810, 241},
+ /* 5535 */ {I_VPCMPLTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3820, 240},
+ /* 5536 */ {I_VPCMPLTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3830, 240},
+ /* 5537 */ {I_VPCMPLTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3840, 241},
+ /* 5538 */ {I_VPCMPLTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3850, 244},
+ /* 5539 */ {I_VPCMPLTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3860, 244},
+ /* 5540 */ {I_VPCMPLTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3870, 245},
+ /* 5541 */ {I_VPCMPLTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3880, 240},
+ /* 5542 */ {I_VPCMPLTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3890, 240},
+ /* 5543 */ {I_VPCMPLTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3900, 241},
+ /* 5544 */ {I_VPCMPLTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3910, 240},
+ /* 5545 */ {I_VPCMPLTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3920, 240},
+ /* 5546 */ {I_VPCMPLTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3930, 241},
+ /* 5547 */ {I_VPCMPLTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3940, 244},
+ /* 5548 */ {I_VPCMPLTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3950, 244},
+ /* 5549 */ {I_VPCMPLTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3960, 245},
+ /* 5550 */ {I_VPCMPLTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3970, 244},
+ /* 5551 */ {I_VPCMPLTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3980, 244},
+ /* 5552 */ {I_VPCMPLTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3990, 245},
+ /* 5553 */ {I_VPCMPNEQB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4000, 244},
+ /* 5554 */ {I_VPCMPNEQB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4010, 244},
+ /* 5555 */ {I_VPCMPNEQB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4020, 245},
+ /* 5556 */ {I_VPCMPNEQD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4030, 240},
+ /* 5557 */ {I_VPCMPNEQD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4040, 240},
+ /* 5558 */ {I_VPCMPNEQD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4050, 241},
+ /* 5559 */ {I_VPCMPNEQQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4060, 240},
+ /* 5560 */ {I_VPCMPNEQQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4070, 240},
+ /* 5561 */ {I_VPCMPNEQQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4080, 241},
+ /* 5562 */ {I_VPCMPNEQUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4090, 244},
+ /* 5563 */ {I_VPCMPNEQUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4100, 244},
+ /* 5564 */ {I_VPCMPNEQUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4110, 245},
+ /* 5565 */ {I_VPCMPNEQUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4120, 240},
+ /* 5566 */ {I_VPCMPNEQUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4130, 240},
+ /* 5567 */ {I_VPCMPNEQUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+4140, 241},
+ /* 5568 */ {I_VPCMPNEQUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4150, 240},
+ /* 5569 */ {I_VPCMPNEQUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4160, 240},
+ /* 5570 */ {I_VPCMPNEQUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+4170, 241},
+ /* 5571 */ {I_VPCMPNEQUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4180, 244},
+ /* 5572 */ {I_VPCMPNEQUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4190, 244},
+ /* 5573 */ {I_VPCMPNEQUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4200, 245},
+ /* 5574 */ {I_VPCMPNEQW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4210, 244},
+ /* 5575 */ {I_VPCMPNEQW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4220, 244},
+ /* 5576 */ {I_VPCMPNEQW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+4230, 245},
+ /* 5577 */ {I_VPCMPNGTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3520, 244},
+ /* 5578 */ {I_VPCMPNGTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3530, 244},
+ /* 5579 */ {I_VPCMPNGTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3540, 245},
+ /* 5580 */ {I_VPCMPNGTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3550, 240},
+ /* 5581 */ {I_VPCMPNGTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3560, 240},
+ /* 5582 */ {I_VPCMPNGTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3570, 241},
+ /* 5583 */ {I_VPCMPNGTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3580, 240},
+ /* 5584 */ {I_VPCMPNGTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3590, 240},
+ /* 5585 */ {I_VPCMPNGTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3600, 241},
+ /* 5586 */ {I_VPCMPNGTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3610, 244},
+ /* 5587 */ {I_VPCMPNGTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3620, 244},
+ /* 5588 */ {I_VPCMPNGTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3630, 245},
+ /* 5589 */ {I_VPCMPNGTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3640, 240},
+ /* 5590 */ {I_VPCMPNGTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3650, 240},
+ /* 5591 */ {I_VPCMPNGTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3660, 241},
+ /* 5592 */ {I_VPCMPNGTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3670, 240},
+ /* 5593 */ {I_VPCMPNGTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3680, 240},
+ /* 5594 */ {I_VPCMPNGTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3690, 241},
+ /* 5595 */ {I_VPCMPNGTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3700, 244},
+ /* 5596 */ {I_VPCMPNGTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3710, 244},
+ /* 5597 */ {I_VPCMPNGTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3720, 245},
+ /* 5598 */ {I_VPCMPNGTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3730, 244},
+ /* 5599 */ {I_VPCMPNGTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3740, 244},
+ /* 5600 */ {I_VPCMPNGTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3750, 245},
+ /* 5601 */ {I_VPCMPNLEB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3280, 244},
+ /* 5602 */ {I_VPCMPNLEB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3290, 244},
+ /* 5603 */ {I_VPCMPNLEB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3300, 245},
+ /* 5604 */ {I_VPCMPNLED, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3310, 240},
+ /* 5605 */ {I_VPCMPNLED, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3320, 240},
+ /* 5606 */ {I_VPCMPNLED, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3330, 241},
+ /* 5607 */ {I_VPCMPNLEQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3340, 240},
+ /* 5608 */ {I_VPCMPNLEQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3350, 240},
+ /* 5609 */ {I_VPCMPNLEQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3360, 241},
+ /* 5610 */ {I_VPCMPNLEUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3370, 244},
+ /* 5611 */ {I_VPCMPNLEUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3380, 244},
+ /* 5612 */ {I_VPCMPNLEUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3390, 245},
+ /* 5613 */ {I_VPCMPNLEUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3400, 240},
+ /* 5614 */ {I_VPCMPNLEUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3410, 240},
+ /* 5615 */ {I_VPCMPNLEUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3420, 241},
+ /* 5616 */ {I_VPCMPNLEUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3430, 240},
+ /* 5617 */ {I_VPCMPNLEUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3440, 240},
+ /* 5618 */ {I_VPCMPNLEUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3450, 241},
+ /* 5619 */ {I_VPCMPNLEUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3460, 244},
+ /* 5620 */ {I_VPCMPNLEUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3470, 244},
+ /* 5621 */ {I_VPCMPNLEUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3480, 245},
+ /* 5622 */ {I_VPCMPNLEW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3490, 244},
+ /* 5623 */ {I_VPCMPNLEW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3500, 244},
+ /* 5624 */ {I_VPCMPNLEW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3510, 245},
+ /* 5625 */ {I_VPCMPNLTB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3040, 244},
+ /* 5626 */ {I_VPCMPNLTB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3050, 244},
+ /* 5627 */ {I_VPCMPNLTB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3060, 245},
+ /* 5628 */ {I_VPCMPNLTD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3070, 240},
+ /* 5629 */ {I_VPCMPNLTD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3080, 240},
+ /* 5630 */ {I_VPCMPNLTD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3090, 241},
+ /* 5631 */ {I_VPCMPNLTQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3100, 240},
+ /* 5632 */ {I_VPCMPNLTQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3110, 240},
+ /* 5633 */ {I_VPCMPNLTQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3120, 241},
+ /* 5634 */ {I_VPCMPNLTUB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3130, 244},
+ /* 5635 */ {I_VPCMPNLTUB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3140, 244},
+ /* 5636 */ {I_VPCMPNLTUB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3150, 245},
+ /* 5637 */ {I_VPCMPNLTUD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3160, 240},
+ /* 5638 */ {I_VPCMPNLTUD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3170, 240},
+ /* 5639 */ {I_VPCMPNLTUD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+3180, 241},
+ /* 5640 */ {I_VPCMPNLTUQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3190, 240},
+ /* 5641 */ {I_VPCMPNLTUQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3200, 240},
+ /* 5642 */ {I_VPCMPNLTUQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+3210, 241},
+ /* 5643 */ {I_VPCMPNLTUW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3220, 244},
+ /* 5644 */ {I_VPCMPNLTUW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3230, 244},
+ /* 5645 */ {I_VPCMPNLTUW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3240, 245},
+ /* 5646 */ {I_VPCMPNLTW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3250, 244},
+ /* 5647 */ {I_VPCMPNLTW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3260, 244},
+ /* 5648 */ {I_VPCMPNLTW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+3270, 245},
+ /* 5649 */ {I_VPCMPB, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9244, 244},
+ /* 5650 */ {I_VPCMPB, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9253, 244},
+ /* 5651 */ {I_VPCMPB, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9262, 245},
+ /* 5652 */ {I_VPCMPD, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9271, 240},
+ /* 5653 */ {I_VPCMPD, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9280, 240},
+ /* 5654 */ {I_VPCMPD, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9289, 241},
+ /* 5655 */ {I_VPCMPQ, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9298, 240},
+ /* 5656 */ {I_VPCMPQ, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9307, 240},
+ /* 5657 */ {I_VPCMPQ, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9316, 241},
+ /* 5658 */ {I_VPCMPUB, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9325, 244},
+ /* 5659 */ {I_VPCMPUB, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9334, 244},
+ /* 5660 */ {I_VPCMPUB, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9343, 245},
+ /* 5661 */ {I_VPCMPUD, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9352, 240},
+ /* 5662 */ {I_VPCMPUD, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9361, 240},
+ /* 5663 */ {I_VPCMPUD, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B32,0,0}, nasm_bytecodes+9370, 241},
+ /* 5664 */ {I_VPCMPUQ, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9379, 240},
+ /* 5665 */ {I_VPCMPUQ, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9388, 240},
+ /* 5666 */ {I_VPCMPUQ, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,B64,0,0}, nasm_bytecodes+9397, 241},
+ /* 5667 */ {I_VPCMPUW, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9406, 244},
+ /* 5668 */ {I_VPCMPUW, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9415, 244},
+ /* 5669 */ {I_VPCMPUW, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9424, 245},
+ /* 5670 */ {I_VPCMPW, 4, {KREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9433, 244},
+ /* 5671 */ {I_VPCMPW, 4, {KREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9442, 244},
+ /* 5672 */ {I_VPCMPW, 4, {KREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK,0,0,0,0}, nasm_bytecodes+9451, 245},
+ /* 5673 */ {I_VPCOMPRESSD, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22272, 240},
+ /* 5674 */ {I_VPCOMPRESSD, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22280, 240},
+ /* 5675 */ {I_VPCOMPRESSD, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22288, 241},
+ /* 5676 */ {I_VPCOMPRESSD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22296, 240},
+ /* 5677 */ {I_VPCOMPRESSD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22304, 240},
+ /* 5678 */ {I_VPCOMPRESSD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22312, 241},
+ /* 5679 */ {I_VPCOMPRESSQ, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22320, 240},
+ /* 5680 */ {I_VPCOMPRESSQ, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22328, 240},
+ /* 5681 */ {I_VPCOMPRESSQ, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+22336, 241},
+ /* 5682 */ {I_VPCOMPRESSQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22344, 240},
+ /* 5683 */ {I_VPCOMPRESSQ, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22352, 240},
+ /* 5684 */ {I_VPCOMPRESSQ, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22360, 241},
+ /* 5685 */ {I_VPCONFLICTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22368, 248},
+ /* 5686 */ {I_VPCONFLICTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22376, 248},
+ /* 5687 */ {I_VPCONFLICTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22384, 249},
+ /* 5688 */ {I_VPCONFLICTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22392, 248},
+ /* 5689 */ {I_VPCONFLICTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22400, 248},
+ /* 5690 */ {I_VPCONFLICTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22408, 249},
+ /* 5691 */ {I_VPERMB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22416, 250},
+ /* 5692 */ {I_VPERMB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22424, 250},
+ /* 5693 */ {I_VPERMB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22432, 250},
+ /* 5694 */ {I_VPERMB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22440, 250},
+ /* 5695 */ {I_VPERMB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22448, 251},
+ /* 5696 */ {I_VPERMB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22456, 251},
+ /* 5697 */ {I_VPERMD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22464, 240},
+ /* 5698 */ {I_VPERMD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22472, 240},
+ /* 5699 */ {I_VPERMD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22480, 241},
+ /* 5700 */ {I_VPERMD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22488, 241},
+ /* 5701 */ {I_VPERMI2B, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22496, 250},
+ /* 5702 */ {I_VPERMI2B, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22504, 250},
+ /* 5703 */ {I_VPERMI2B, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22512, 251},
+ /* 5704 */ {I_VPERMI2D, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22520, 240},
+ /* 5705 */ {I_VPERMI2D, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22528, 240},
+ /* 5706 */ {I_VPERMI2D, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22536, 241},
+ /* 5707 */ {I_VPERMI2PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22544, 240},
+ /* 5708 */ {I_VPERMI2PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22552, 240},
+ /* 5709 */ {I_VPERMI2PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22560, 241},
+ /* 5710 */ {I_VPERMI2PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22568, 240},
+ /* 5711 */ {I_VPERMI2PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22576, 240},
+ /* 5712 */ {I_VPERMI2PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22584, 241},
+ /* 5713 */ {I_VPERMI2Q, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22592, 240},
+ /* 5714 */ {I_VPERMI2Q, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22600, 240},
+ /* 5715 */ {I_VPERMI2Q, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22608, 241},
+ /* 5716 */ {I_VPERMI2W, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22616, 244},
+ /* 5717 */ {I_VPERMI2W, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22624, 244},
+ /* 5718 */ {I_VPERMI2W, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22632, 245},
+ /* 5719 */ {I_VPERMILPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9460, 240},
+ /* 5720 */ {I_VPERMILPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9469, 240},
+ /* 5721 */ {I_VPERMILPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9478, 241},
+ /* 5722 */ {I_VPERMILPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22640, 240},
+ /* 5723 */ {I_VPERMILPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22648, 240},
+ /* 5724 */ {I_VPERMILPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22656, 240},
+ /* 5725 */ {I_VPERMILPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22664, 240},
+ /* 5726 */ {I_VPERMILPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22672, 241},
+ /* 5727 */ {I_VPERMILPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22680, 241},
+ /* 5728 */ {I_VPERMILPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9487, 240},
+ /* 5729 */ {I_VPERMILPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9496, 240},
+ /* 5730 */ {I_VPERMILPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9505, 241},
+ /* 5731 */ {I_VPERMILPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22688, 240},
+ /* 5732 */ {I_VPERMILPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22696, 240},
+ /* 5733 */ {I_VPERMILPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22704, 240},
+ /* 5734 */ {I_VPERMILPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22712, 240},
+ /* 5735 */ {I_VPERMILPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22720, 241},
+ /* 5736 */ {I_VPERMILPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22728, 241},
+ /* 5737 */ {I_VPERMPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9514, 240},
+ /* 5738 */ {I_VPERMPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9523, 241},
+ /* 5739 */ {I_VPERMPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22736, 240},
+ /* 5740 */ {I_VPERMPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22744, 240},
+ /* 5741 */ {I_VPERMPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22752, 241},
+ /* 5742 */ {I_VPERMPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22760, 241},
+ /* 5743 */ {I_VPERMPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22768, 240},
+ /* 5744 */ {I_VPERMPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22776, 240},
+ /* 5745 */ {I_VPERMPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22784, 241},
+ /* 5746 */ {I_VPERMPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+22792, 241},
+ /* 5747 */ {I_VPERMQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9532, 240},
+ /* 5748 */ {I_VPERMQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9541, 241},
+ /* 5749 */ {I_VPERMQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22800, 240},
+ /* 5750 */ {I_VPERMQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22808, 240},
+ /* 5751 */ {I_VPERMQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22816, 241},
+ /* 5752 */ {I_VPERMQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+22824, 241},
+ /* 5753 */ {I_VPERMT2B, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22832, 250},
+ /* 5754 */ {I_VPERMT2B, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22840, 250},
+ /* 5755 */ {I_VPERMT2B, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22848, 251},
+ /* 5756 */ {I_VPERMT2D, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22856, 240},
+ /* 5757 */ {I_VPERMT2D, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22864, 240},
+ /* 5758 */ {I_VPERMT2D, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22872, 241},
+ /* 5759 */ {I_VPERMT2PD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22880, 240},
+ /* 5760 */ {I_VPERMT2PD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22888, 240},
+ /* 5761 */ {I_VPERMT2PD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22896, 241},
+ /* 5762 */ {I_VPERMT2PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22904, 240},
+ /* 5763 */ {I_VPERMT2PS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22912, 240},
+ /* 5764 */ {I_VPERMT2PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+22920, 241},
+ /* 5765 */ {I_VPERMT2Q, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22928, 240},
+ /* 5766 */ {I_VPERMT2Q, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22936, 240},
+ /* 5767 */ {I_VPERMT2Q, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+22944, 241},
+ /* 5768 */ {I_VPERMT2W, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22952, 244},
+ /* 5769 */ {I_VPERMT2W, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22960, 244},
+ /* 5770 */ {I_VPERMT2W, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22968, 245},
+ /* 5771 */ {I_VPERMW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22976, 244},
+ /* 5772 */ {I_VPERMW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22984, 244},
+ /* 5773 */ {I_VPERMW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+22992, 244},
+ /* 5774 */ {I_VPERMW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23000, 244},
+ /* 5775 */ {I_VPERMW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23008, 245},
+ /* 5776 */ {I_VPERMW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23016, 245},
+ /* 5777 */ {I_VPEXPANDD, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23024, 240},
+ /* 5778 */ {I_VPEXPANDD, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23032, 240},
+ /* 5779 */ {I_VPEXPANDD, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23040, 241},
+ /* 5780 */ {I_VPEXPANDD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23024, 240},
+ /* 5781 */ {I_VPEXPANDD, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23032, 240},
+ /* 5782 */ {I_VPEXPANDD, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23040, 241},
+ /* 5783 */ {I_VPEXPANDQ, 2, {XMMREG,MEMORY|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23048, 240},
+ /* 5784 */ {I_VPEXPANDQ, 2, {YMMREG,MEMORY|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23056, 240},
+ /* 5785 */ {I_VPEXPANDQ, 2, {ZMMREG,MEMORY|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23064, 241},
+ /* 5786 */ {I_VPEXPANDQ, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23048, 240},
+ /* 5787 */ {I_VPEXPANDQ, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23056, 240},
+ /* 5788 */ {I_VPEXPANDQ, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23064, 241},
+ /* 5789 */ {I_VPEXTRB, 3, {REG_GPR|BITS8,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ /* 5790 */ {I_VPEXTRB, 3, {REG_GPR|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ /* 5791 */ {I_VPEXTRB, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ /* 5792 */ {I_VPEXTRB, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ /* 5793 */ {I_VPEXTRB, 3, {MEMORY|BITS8,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9550, 245},
+ /* 5794 */ {I_VPEXTRD, 3, {RM_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9559, 243},
+ /* 5795 */ {I_VPEXTRQ, 3, {RM_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9568, 243},
+ /* 5796 */ {I_VPEXTRW, 3, {REG_GPR|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ /* 5797 */ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ /* 5798 */ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ /* 5799 */ {I_VPEXTRW, 3, {MEMORY|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9577, 245},
+ /* 5800 */ {I_VPEXTRW, 3, {REG_GPR|BITS16,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9586, 245},
+ /* 5801 */ {I_VPEXTRW, 3, {REG_GPR|BITS32,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9586, 245},
+ /* 5802 */ {I_VPEXTRW, 3, {REG_GPR|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9586, 245},
+ /* 5803 */ {I_VPGATHERDD, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9595, 240},
+ /* 5804 */ {I_VPGATHERDD, 2, {YMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9604, 240},
+ /* 5805 */ {I_VPGATHERDD, 2, {ZMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9613, 241},
+ /* 5806 */ {I_VPGATHERDQ, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9622, 240},
+ /* 5807 */ {I_VPGATHERDQ, 2, {YMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9631, 240},
+ /* 5808 */ {I_VPGATHERDQ, 2, {ZMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9640, 241},
+ /* 5809 */ {I_VPGATHERQD, 2, {XMMREG,XMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9649, 240},
+ /* 5810 */ {I_VPGATHERQD, 2, {XMMREG,YMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9658, 240},
+ /* 5811 */ {I_VPGATHERQD, 2, {YMMREG,ZMEM|BITS32,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9667, 241},
+ /* 5812 */ {I_VPGATHERQQ, 2, {XMMREG,XMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9676, 240},
+ /* 5813 */ {I_VPGATHERQQ, 2, {YMMREG,YMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9685, 240},
+ /* 5814 */ {I_VPGATHERQQ, 2, {ZMMREG,ZMEM|BITS64,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9694, 241},
+ /* 5815 */ {I_VPINSRB, 4, {XMMREG,XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9703, 245},
+ /* 5816 */ {I_VPINSRB, 3, {XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9712, 245},
+ /* 5817 */ {I_VPINSRB, 4, {XMMREG,XMMREG,MEMORY|BITS8,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9703, 245},
+ /* 5818 */ {I_VPINSRB, 3, {XMMREG,MEMORY|BITS8,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9712, 245},
+ /* 5819 */ {I_VPINSRD, 4, {XMMREG,XMMREG,RM_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9721, 243},
+ /* 5820 */ {I_VPINSRD, 3, {XMMREG,RM_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9730, 243},
+ /* 5821 */ {I_VPINSRQ, 4, {XMMREG,XMMREG,RM_GPR|BITS64,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9739, 243},
+ /* 5822 */ {I_VPINSRQ, 3, {XMMREG,RM_GPR|BITS64,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9748, 243},
+ /* 5823 */ {I_VPINSRW, 4, {XMMREG,XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9757, 245},
+ /* 5824 */ {I_VPINSRW, 3, {XMMREG,REG_GPR|BITS32,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9766, 245},
+ /* 5825 */ {I_VPINSRW, 4, {XMMREG,XMMREG,MEMORY|BITS16,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+9757, 245},
+ /* 5826 */ {I_VPINSRW, 3, {XMMREG,MEMORY|BITS16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+9766, 245},
+ /* 5827 */ {I_VPLZCNTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23072, 248},
+ /* 5828 */ {I_VPLZCNTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23080, 248},
+ /* 5829 */ {I_VPLZCNTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23088, 249},
+ /* 5830 */ {I_VPLZCNTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23096, 248},
+ /* 5831 */ {I_VPLZCNTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23104, 248},
+ /* 5832 */ {I_VPLZCNTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23112, 249},
+ /* 5833 */ {I_VPMADD52HUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23120, 252},
+ /* 5834 */ {I_VPMADD52HUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23128, 252},
+ /* 5835 */ {I_VPMADD52HUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23136, 253},
+ /* 5836 */ {I_VPMADD52LUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23144, 252},
+ /* 5837 */ {I_VPMADD52LUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23152, 252},
+ /* 5838 */ {I_VPMADD52LUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23160, 253},
+ /* 5839 */ {I_VPMADDUBSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23168, 244},
+ /* 5840 */ {I_VPMADDUBSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23176, 244},
+ /* 5841 */ {I_VPMADDUBSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23184, 244},
+ /* 5842 */ {I_VPMADDUBSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23192, 244},
+ /* 5843 */ {I_VPMADDUBSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23200, 245},
+ /* 5844 */ {I_VPMADDUBSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23208, 245},
+ /* 5845 */ {I_VPMADDWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23216, 244},
+ /* 5846 */ {I_VPMADDWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23224, 244},
+ /* 5847 */ {I_VPMADDWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23232, 244},
+ /* 5848 */ {I_VPMADDWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23240, 244},
+ /* 5849 */ {I_VPMADDWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23248, 245},
+ /* 5850 */ {I_VPMADDWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23256, 245},
+ /* 5851 */ {I_VPMAXSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23264, 244},
+ /* 5852 */ {I_VPMAXSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23272, 244},
+ /* 5853 */ {I_VPMAXSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23280, 244},
+ /* 5854 */ {I_VPMAXSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23288, 244},
+ /* 5855 */ {I_VPMAXSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23296, 245},
+ /* 5856 */ {I_VPMAXSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23304, 245},
+ /* 5857 */ {I_VPMAXSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23312, 240},
+ /* 5858 */ {I_VPMAXSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23320, 240},
+ /* 5859 */ {I_VPMAXSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23328, 240},
+ /* 5860 */ {I_VPMAXSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23336, 240},
+ /* 5861 */ {I_VPMAXSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23344, 241},
+ /* 5862 */ {I_VPMAXSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23352, 241},
+ /* 5863 */ {I_VPMAXSQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23360, 240},
+ /* 5864 */ {I_VPMAXSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23368, 240},
+ /* 5865 */ {I_VPMAXSQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23376, 240},
+ /* 5866 */ {I_VPMAXSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23384, 240},
+ /* 5867 */ {I_VPMAXSQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23392, 241},
+ /* 5868 */ {I_VPMAXSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23400, 241},
+ /* 5869 */ {I_VPMAXSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23408, 244},
+ /* 5870 */ {I_VPMAXSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23416, 244},
+ /* 5871 */ {I_VPMAXSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23424, 244},
+ /* 5872 */ {I_VPMAXSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23432, 244},
+ /* 5873 */ {I_VPMAXSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23440, 245},
+ /* 5874 */ {I_VPMAXSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23448, 245},
+ /* 5875 */ {I_VPMAXUB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23456, 244},
+ /* 5876 */ {I_VPMAXUB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23464, 244},
+ /* 5877 */ {I_VPMAXUB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23472, 244},
+ /* 5878 */ {I_VPMAXUB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23480, 244},
+ /* 5879 */ {I_VPMAXUB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23488, 245},
+ /* 5880 */ {I_VPMAXUB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23496, 245},
+ /* 5881 */ {I_VPMAXUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23504, 240},
+ /* 5882 */ {I_VPMAXUD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23512, 240},
+ /* 5883 */ {I_VPMAXUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23520, 240},
+ /* 5884 */ {I_VPMAXUD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23528, 240},
+ /* 5885 */ {I_VPMAXUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23536, 241},
+ /* 5886 */ {I_VPMAXUD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23544, 241},
+ /* 5887 */ {I_VPMAXUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23552, 240},
+ /* 5888 */ {I_VPMAXUQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23560, 240},
+ /* 5889 */ {I_VPMAXUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23568, 240},
+ /* 5890 */ {I_VPMAXUQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23576, 240},
+ /* 5891 */ {I_VPMAXUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23584, 241},
+ /* 5892 */ {I_VPMAXUQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23592, 241},
+ /* 5893 */ {I_VPMAXUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23600, 244},
+ /* 5894 */ {I_VPMAXUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23608, 244},
+ /* 5895 */ {I_VPMAXUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23616, 244},
+ /* 5896 */ {I_VPMAXUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23624, 244},
+ /* 5897 */ {I_VPMAXUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23632, 245},
+ /* 5898 */ {I_VPMAXUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23640, 245},
+ /* 5899 */ {I_VPMINSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23648, 244},
+ /* 5900 */ {I_VPMINSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23656, 244},
+ /* 5901 */ {I_VPMINSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23664, 244},
+ /* 5902 */ {I_VPMINSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23672, 244},
+ /* 5903 */ {I_VPMINSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23680, 245},
+ /* 5904 */ {I_VPMINSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23688, 245},
+ /* 5905 */ {I_VPMINSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23696, 240},
+ /* 5906 */ {I_VPMINSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23704, 240},
+ /* 5907 */ {I_VPMINSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23712, 240},
+ /* 5908 */ {I_VPMINSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23720, 240},
+ /* 5909 */ {I_VPMINSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23728, 241},
+ /* 5910 */ {I_VPMINSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23736, 241},
+ /* 5911 */ {I_VPMINSQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23744, 240},
+ /* 5912 */ {I_VPMINSQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23752, 240},
+ /* 5913 */ {I_VPMINSQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23760, 240},
+ /* 5914 */ {I_VPMINSQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23768, 240},
+ /* 5915 */ {I_VPMINSQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23776, 241},
+ /* 5916 */ {I_VPMINSQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23784, 241},
+ /* 5917 */ {I_VPMINSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23792, 244},
+ /* 5918 */ {I_VPMINSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23800, 244},
+ /* 5919 */ {I_VPMINSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23808, 244},
+ /* 5920 */ {I_VPMINSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23816, 244},
+ /* 5921 */ {I_VPMINSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23824, 245},
+ /* 5922 */ {I_VPMINSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23832, 245},
+ /* 5923 */ {I_VPMINUB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23840, 244},
+ /* 5924 */ {I_VPMINUB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23848, 244},
+ /* 5925 */ {I_VPMINUB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23856, 244},
+ /* 5926 */ {I_VPMINUB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23864, 244},
+ /* 5927 */ {I_VPMINUB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23872, 245},
+ /* 5928 */ {I_VPMINUB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23880, 245},
+ /* 5929 */ {I_VPMINUD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23888, 240},
+ /* 5930 */ {I_VPMINUD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23896, 240},
+ /* 5931 */ {I_VPMINUD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23904, 240},
+ /* 5932 */ {I_VPMINUD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23912, 240},
+ /* 5933 */ {I_VPMINUD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+23920, 241},
+ /* 5934 */ {I_VPMINUD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+23928, 241},
+ /* 5935 */ {I_VPMINUQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23936, 240},
+ /* 5936 */ {I_VPMINUQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23944, 240},
+ /* 5937 */ {I_VPMINUQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23952, 240},
+ /* 5938 */ {I_VPMINUQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23960, 240},
+ /* 5939 */ {I_VPMINUQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+23968, 241},
+ /* 5940 */ {I_VPMINUQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+23976, 241},
+ /* 5941 */ {I_VPMINUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23984, 244},
+ /* 5942 */ {I_VPMINUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+23992, 244},
+ /* 5943 */ {I_VPMINUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24000, 244},
+ /* 5944 */ {I_VPMINUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24008, 244},
+ /* 5945 */ {I_VPMINUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24016, 245},
+ /* 5946 */ {I_VPMINUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24024, 245},
+ /* 5947 */ {I_VPMOVB2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24032, 244},
+ /* 5948 */ {I_VPMOVB2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24040, 244},
+ /* 5949 */ {I_VPMOVB2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24048, 245},
+ /* 5950 */ {I_VPMOVD2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24056, 242},
+ /* 5951 */ {I_VPMOVD2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24064, 242},
+ /* 5952 */ {I_VPMOVD2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24072, 243},
+ /* 5953 */ {I_VPMOVDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24080, 240},
+ /* 5954 */ {I_VPMOVDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24088, 240},
+ /* 5955 */ {I_VPMOVDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24096, 241},
+ /* 5956 */ {I_VPMOVDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24104, 240},
+ /* 5957 */ {I_VPMOVDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24112, 240},
+ /* 5958 */ {I_VPMOVDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24120, 241},
+ /* 5959 */ {I_VPMOVDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24128, 240},
+ /* 5960 */ {I_VPMOVDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24136, 240},
+ /* 5961 */ {I_VPMOVDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24144, 241},
+ /* 5962 */ {I_VPMOVDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24152, 240},
+ /* 5963 */ {I_VPMOVDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24160, 240},
+ /* 5964 */ {I_VPMOVDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24168, 241},
+ /* 5965 */ {I_VPMOVM2B, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24176, 244},
+ /* 5966 */ {I_VPMOVM2B, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24184, 244},
+ /* 5967 */ {I_VPMOVM2B, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24192, 245},
+ /* 5968 */ {I_VPMOVM2D, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24200, 242},
+ /* 5969 */ {I_VPMOVM2D, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24208, 242},
+ /* 5970 */ {I_VPMOVM2D, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24216, 243},
+ /* 5971 */ {I_VPMOVM2Q, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24224, 242},
+ /* 5972 */ {I_VPMOVM2Q, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24232, 242},
+ /* 5973 */ {I_VPMOVM2Q, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24240, 243},
+ /* 5974 */ {I_VPMOVM2W, 2, {XMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24248, 244},
+ /* 5975 */ {I_VPMOVM2W, 2, {YMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24256, 244},
+ /* 5976 */ {I_VPMOVM2W, 2, {ZMMREG,KREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24264, 245},
+ /* 5977 */ {I_VPMOVQ2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24272, 242},
+ /* 5978 */ {I_VPMOVQ2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24280, 242},
+ /* 5979 */ {I_VPMOVQ2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+24288, 243},
+ /* 5980 */ {I_VPMOVQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24296, 240},
+ /* 5981 */ {I_VPMOVQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24304, 240},
+ /* 5982 */ {I_VPMOVQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24312, 241},
+ /* 5983 */ {I_VPMOVQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24320, 240},
+ /* 5984 */ {I_VPMOVQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24328, 240},
+ /* 5985 */ {I_VPMOVQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24336, 241},
+ /* 5986 */ {I_VPMOVQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24344, 240},
+ /* 5987 */ {I_VPMOVQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24352, 240},
+ /* 5988 */ {I_VPMOVQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24360, 241},
+ /* 5989 */ {I_VPMOVQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24368, 240},
+ /* 5990 */ {I_VPMOVQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24376, 240},
+ /* 5991 */ {I_VPMOVQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24384, 241},
+ /* 5992 */ {I_VPMOVQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24392, 240},
+ /* 5993 */ {I_VPMOVQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24400, 240},
+ /* 5994 */ {I_VPMOVQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24408, 241},
+ /* 5995 */ {I_VPMOVQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24416, 240},
+ /* 5996 */ {I_VPMOVQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24424, 240},
+ /* 5997 */ {I_VPMOVQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24432, 241},
+ /* 5998 */ {I_VPMOVSDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24440, 240},
+ /* 5999 */ {I_VPMOVSDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24448, 240},
+ /* 6000 */ {I_VPMOVSDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24456, 241},
+ /* 6001 */ {I_VPMOVSDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24464, 240},
+ /* 6002 */ {I_VPMOVSDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24472, 240},
+ /* 6003 */ {I_VPMOVSDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24480, 241},
+ /* 6004 */ {I_VPMOVSDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24488, 240},
+ /* 6005 */ {I_VPMOVSDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24496, 240},
+ /* 6006 */ {I_VPMOVSDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24504, 241},
+ /* 6007 */ {I_VPMOVSDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24512, 240},
+ /* 6008 */ {I_VPMOVSDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24520, 240},
+ /* 6009 */ {I_VPMOVSDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24528, 241},
+ /* 6010 */ {I_VPMOVSQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24536, 240},
+ /* 6011 */ {I_VPMOVSQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24544, 240},
+ /* 6012 */ {I_VPMOVSQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24552, 241},
+ /* 6013 */ {I_VPMOVSQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24560, 240},
+ /* 6014 */ {I_VPMOVSQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24568, 240},
+ /* 6015 */ {I_VPMOVSQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24576, 241},
+ /* 6016 */ {I_VPMOVSQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24584, 240},
+ /* 6017 */ {I_VPMOVSQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24592, 240},
+ /* 6018 */ {I_VPMOVSQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24600, 241},
+ /* 6019 */ {I_VPMOVSQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24608, 240},
+ /* 6020 */ {I_VPMOVSQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24616, 240},
+ /* 6021 */ {I_VPMOVSQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24624, 241},
+ /* 6022 */ {I_VPMOVSQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24632, 240},
+ /* 6023 */ {I_VPMOVSQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24640, 240},
+ /* 6024 */ {I_VPMOVSQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24648, 241},
+ /* 6025 */ {I_VPMOVSQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24656, 240},
+ /* 6026 */ {I_VPMOVSQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24664, 240},
+ /* 6027 */ {I_VPMOVSQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24672, 241},
+ /* 6028 */ {I_VPMOVSWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24680, 244},
+ /* 6029 */ {I_VPMOVSWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24688, 244},
+ /* 6030 */ {I_VPMOVSWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24696, 245},
+ /* 6031 */ {I_VPMOVSWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24704, 244},
+ /* 6032 */ {I_VPMOVSWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24712, 244},
+ /* 6033 */ {I_VPMOVSWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24720, 245},
+ /* 6034 */ {I_VPMOVSXBD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24728, 240},
+ /* 6035 */ {I_VPMOVSXBD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24736, 240},
+ /* 6036 */ {I_VPMOVSXBD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24744, 241},
+ /* 6037 */ {I_VPMOVSXBQ, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24752, 240},
+ /* 6038 */ {I_VPMOVSXBQ, 2, {YMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24760, 240},
+ /* 6039 */ {I_VPMOVSXBQ, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24768, 241},
+ /* 6040 */ {I_VPMOVSXBW, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24776, 244},
+ /* 6041 */ {I_VPMOVSXBW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24784, 244},
+ /* 6042 */ {I_VPMOVSXBW, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24792, 245},
+ /* 6043 */ {I_VPMOVSXDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24800, 240},
+ /* 6044 */ {I_VPMOVSXDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24808, 240},
+ /* 6045 */ {I_VPMOVSXDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24816, 241},
+ /* 6046 */ {I_VPMOVSXWD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24824, 240},
+ /* 6047 */ {I_VPMOVSXWD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24832, 240},
+ /* 6048 */ {I_VPMOVSXWD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24840, 241},
+ /* 6049 */ {I_VPMOVSXWQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24848, 240},
+ /* 6050 */ {I_VPMOVSXWQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24856, 240},
+ /* 6051 */ {I_VPMOVSXWQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24864, 241},
+ /* 6052 */ {I_VPMOVUSDB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24872, 240},
+ /* 6053 */ {I_VPMOVUSDB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24880, 240},
+ /* 6054 */ {I_VPMOVUSDB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24888, 241},
+ /* 6055 */ {I_VPMOVUSDB, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24896, 240},
+ /* 6056 */ {I_VPMOVUSDB, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24904, 240},
+ /* 6057 */ {I_VPMOVUSDB, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24912, 241},
+ /* 6058 */ {I_VPMOVUSDW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24920, 240},
+ /* 6059 */ {I_VPMOVUSDW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24928, 240},
+ /* 6060 */ {I_VPMOVUSDW, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24936, 241},
+ /* 6061 */ {I_VPMOVUSDW, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24944, 240},
+ /* 6062 */ {I_VPMOVUSDW, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24952, 240},
+ /* 6063 */ {I_VPMOVUSDW, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24960, 241},
+ /* 6064 */ {I_VPMOVUSQB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24968, 240},
+ /* 6065 */ {I_VPMOVUSQB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24976, 240},
+ /* 6066 */ {I_VPMOVUSQB, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+24984, 241},
+ /* 6067 */ {I_VPMOVUSQB, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+24992, 240},
+ /* 6068 */ {I_VPMOVUSQB, 2, {MEMORY|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25000, 240},
+ /* 6069 */ {I_VPMOVUSQB, 2, {MEMORY|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25008, 241},
+ /* 6070 */ {I_VPMOVUSQD, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25016, 240},
+ /* 6071 */ {I_VPMOVUSQD, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25024, 240},
+ /* 6072 */ {I_VPMOVUSQD, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25032, 241},
+ /* 6073 */ {I_VPMOVUSQD, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25040, 240},
+ /* 6074 */ {I_VPMOVUSQD, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25048, 240},
+ /* 6075 */ {I_VPMOVUSQD, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25056, 241},
+ /* 6076 */ {I_VPMOVUSQW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25064, 240},
+ /* 6077 */ {I_VPMOVUSQW, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25072, 240},
+ /* 6078 */ {I_VPMOVUSQW, 2, {XMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25080, 241},
+ /* 6079 */ {I_VPMOVUSQW, 2, {MEMORY|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25088, 240},
+ /* 6080 */ {I_VPMOVUSQW, 2, {MEMORY|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25096, 240},
+ /* 6081 */ {I_VPMOVUSQW, 2, {MEMORY|BITS128,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25104, 241},
+ /* 6082 */ {I_VPMOVUSWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25112, 244},
+ /* 6083 */ {I_VPMOVUSWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25120, 244},
+ /* 6084 */ {I_VPMOVUSWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25128, 245},
+ /* 6085 */ {I_VPMOVUSWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25136, 244},
+ /* 6086 */ {I_VPMOVUSWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25144, 244},
+ /* 6087 */ {I_VPMOVUSWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25152, 245},
+ /* 6088 */ {I_VPMOVW2M, 2, {KREG,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+25160, 244},
+ /* 6089 */ {I_VPMOVW2M, 2, {KREG,YMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+25168, 244},
+ /* 6090 */ {I_VPMOVW2M, 2, {KREG,ZMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+25176, 245},
+ /* 6091 */ {I_VPMOVWB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25184, 244},
+ /* 6092 */ {I_VPMOVWB, 2, {XMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25192, 244},
+ /* 6093 */ {I_VPMOVWB, 2, {YMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25200, 245},
+ /* 6094 */ {I_VPMOVWB, 2, {MEMORY|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25208, 244},
+ /* 6095 */ {I_VPMOVWB, 2, {MEMORY|BITS128,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25216, 244},
+ /* 6096 */ {I_VPMOVWB, 2, {MEMORY|BITS256,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+25224, 245},
+ /* 6097 */ {I_VPMOVZXBD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25232, 240},
+ /* 6098 */ {I_VPMOVZXBD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25240, 240},
+ /* 6099 */ {I_VPMOVZXBD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25248, 241},
+ /* 6100 */ {I_VPMOVZXBQ, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25256, 240},
+ /* 6101 */ {I_VPMOVZXBQ, 2, {YMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25264, 240},
+ /* 6102 */ {I_VPMOVZXBQ, 2, {ZMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25272, 241},
+ /* 6103 */ {I_VPMOVZXBW, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25280, 244},
+ /* 6104 */ {I_VPMOVZXBW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25288, 244},
+ /* 6105 */ {I_VPMOVZXBW, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25296, 245},
+ /* 6106 */ {I_VPMOVZXDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25304, 240},
+ /* 6107 */ {I_VPMOVZXDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25312, 240},
+ /* 6108 */ {I_VPMOVZXDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25320, 241},
+ /* 6109 */ {I_VPMOVZXWD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25328, 240},
+ /* 6110 */ {I_VPMOVZXWD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25336, 240},
+ /* 6111 */ {I_VPMOVZXWD, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25344, 241},
+ /* 6112 */ {I_VPMOVZXWQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25352, 240},
+ /* 6113 */ {I_VPMOVZXWQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25360, 240},
+ /* 6114 */ {I_VPMOVZXWQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25368, 241},
+ /* 6115 */ {I_VPMULDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25376, 240},
+ /* 6116 */ {I_VPMULDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25384, 240},
+ /* 6117 */ {I_VPMULDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25392, 240},
+ /* 6118 */ {I_VPMULDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25400, 240},
+ /* 6119 */ {I_VPMULDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25408, 241},
+ /* 6120 */ {I_VPMULDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25416, 241},
+ /* 6121 */ {I_VPMULHRSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25424, 244},
+ /* 6122 */ {I_VPMULHRSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25432, 244},
+ /* 6123 */ {I_VPMULHRSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25440, 244},
+ /* 6124 */ {I_VPMULHRSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25448, 244},
+ /* 6125 */ {I_VPMULHRSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25456, 245},
+ /* 6126 */ {I_VPMULHRSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25464, 245},
+ /* 6127 */ {I_VPMULHUW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25472, 244},
+ /* 6128 */ {I_VPMULHUW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25480, 244},
+ /* 6129 */ {I_VPMULHUW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25488, 244},
+ /* 6130 */ {I_VPMULHUW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25496, 244},
+ /* 6131 */ {I_VPMULHUW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25504, 245},
+ /* 6132 */ {I_VPMULHUW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25512, 245},
+ /* 6133 */ {I_VPMULHW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25520, 244},
+ /* 6134 */ {I_VPMULHW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25528, 244},
+ /* 6135 */ {I_VPMULHW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25536, 244},
+ /* 6136 */ {I_VPMULHW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25544, 244},
+ /* 6137 */ {I_VPMULHW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25552, 245},
+ /* 6138 */ {I_VPMULHW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25560, 245},
+ /* 6139 */ {I_VPMULLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25568, 240},
+ /* 6140 */ {I_VPMULLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25576, 240},
+ /* 6141 */ {I_VPMULLD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25584, 240},
+ /* 6142 */ {I_VPMULLD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25592, 240},
+ /* 6143 */ {I_VPMULLD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25600, 241},
+ /* 6144 */ {I_VPMULLD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25608, 241},
+ /* 6145 */ {I_VPMULLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25616, 242},
+ /* 6146 */ {I_VPMULLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25624, 242},
+ /* 6147 */ {I_VPMULLQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25632, 242},
+ /* 6148 */ {I_VPMULLQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25640, 242},
+ /* 6149 */ {I_VPMULLQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25648, 243},
+ /* 6150 */ {I_VPMULLQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25656, 243},
+ /* 6151 */ {I_VPMULLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25664, 244},
+ /* 6152 */ {I_VPMULLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25672, 244},
+ /* 6153 */ {I_VPMULLW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25680, 244},
+ /* 6154 */ {I_VPMULLW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25688, 244},
+ /* 6155 */ {I_VPMULLW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25696, 245},
+ /* 6156 */ {I_VPMULLW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+25704, 245},
+ /* 6157 */ {I_VPMULTISHIFTQB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25712, 250},
+ /* 6158 */ {I_VPMULTISHIFTQB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25720, 250},
+ /* 6159 */ {I_VPMULTISHIFTQB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25728, 250},
+ /* 6160 */ {I_VPMULTISHIFTQB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25736, 250},
+ /* 6161 */ {I_VPMULTISHIFTQB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25744, 251},
+ /* 6162 */ {I_VPMULTISHIFTQB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25752, 251},
+ /* 6163 */ {I_VPMULUDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25760, 240},
+ /* 6164 */ {I_VPMULUDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25768, 240},
+ /* 6165 */ {I_VPMULUDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25776, 240},
+ /* 6166 */ {I_VPMULUDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25784, 240},
+ /* 6167 */ {I_VPMULUDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25792, 241},
+ /* 6168 */ {I_VPMULUDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25800, 241},
+ /* 6169 */ {I_VPORD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25808, 240},
+ /* 6170 */ {I_VPORD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25816, 240},
+ /* 6171 */ {I_VPORD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25824, 240},
+ /* 6172 */ {I_VPORD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25832, 240},
+ /* 6173 */ {I_VPORD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25840, 241},
+ /* 6174 */ {I_VPORD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25848, 241},
+ /* 6175 */ {I_VPORQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25856, 240},
+ /* 6176 */ {I_VPORQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25864, 240},
+ /* 6177 */ {I_VPORQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25872, 240},
+ /* 6178 */ {I_VPORQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25880, 240},
+ /* 6179 */ {I_VPORQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25888, 241},
+ /* 6180 */ {I_VPORQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25896, 241},
+ /* 6181 */ {I_VPROLD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9775, 240},
+ /* 6182 */ {I_VPROLD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9784, 240},
+ /* 6183 */ {I_VPROLD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9793, 240},
+ /* 6184 */ {I_VPROLD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9802, 240},
+ /* 6185 */ {I_VPROLD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9811, 241},
+ /* 6186 */ {I_VPROLD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9820, 241},
+ /* 6187 */ {I_VPROLQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9829, 240},
+ /* 6188 */ {I_VPROLQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9838, 240},
+ /* 6189 */ {I_VPROLQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9847, 240},
+ /* 6190 */ {I_VPROLQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9856, 240},
+ /* 6191 */ {I_VPROLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9865, 241},
+ /* 6192 */ {I_VPROLQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9874, 241},
+ /* 6193 */ {I_VPROLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25904, 240},
+ /* 6194 */ {I_VPROLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25912, 240},
+ /* 6195 */ {I_VPROLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25920, 240},
+ /* 6196 */ {I_VPROLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25928, 240},
+ /* 6197 */ {I_VPROLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+25936, 241},
+ /* 6198 */ {I_VPROLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+25944, 241},
+ /* 6199 */ {I_VPROLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25952, 240},
+ /* 6200 */ {I_VPROLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25960, 240},
+ /* 6201 */ {I_VPROLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25968, 240},
+ /* 6202 */ {I_VPROLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25976, 240},
+ /* 6203 */ {I_VPROLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+25984, 241},
+ /* 6204 */ {I_VPROLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+25992, 241},
+ /* 6205 */ {I_VPRORD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9883, 240},
+ /* 6206 */ {I_VPRORD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9892, 240},
+ /* 6207 */ {I_VPRORD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9901, 240},
+ /* 6208 */ {I_VPRORD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9910, 240},
+ /* 6209 */ {I_VPRORD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+9919, 241},
+ /* 6210 */ {I_VPRORD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9928, 241},
+ /* 6211 */ {I_VPRORQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9937, 240},
+ /* 6212 */ {I_VPRORQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9946, 240},
+ /* 6213 */ {I_VPRORQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9955, 240},
+ /* 6214 */ {I_VPRORQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9964, 240},
+ /* 6215 */ {I_VPRORQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+9973, 241},
+ /* 6216 */ {I_VPRORQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+9982, 241},
+ /* 6217 */ {I_VPRORVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26000, 240},
+ /* 6218 */ {I_VPRORVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26008, 240},
+ /* 6219 */ {I_VPRORVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26016, 240},
+ /* 6220 */ {I_VPRORVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26024, 240},
+ /* 6221 */ {I_VPRORVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26032, 241},
+ /* 6222 */ {I_VPRORVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26040, 241},
+ /* 6223 */ {I_VPRORVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26048, 240},
+ /* 6224 */ {I_VPRORVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26056, 240},
+ /* 6225 */ {I_VPRORVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26064, 240},
+ /* 6226 */ {I_VPRORVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26072, 240},
+ /* 6227 */ {I_VPRORVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26080, 241},
+ /* 6228 */ {I_VPRORVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26088, 241},
+ /* 6229 */ {I_VPSADBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+26096, 244},
+ /* 6230 */ {I_VPSADBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+26104, 244},
+ /* 6231 */ {I_VPSADBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+26112, 244},
+ /* 6232 */ {I_VPSADBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+26120, 244},
+ /* 6233 */ {I_VPSADBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, NO_DECORATOR, nasm_bytecodes+26128, 245},
+ /* 6234 */ {I_VPSADBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+26136, 245},
+ /* 6235 */ {I_VPSCATTERDD, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+9991, 240},
+ /* 6236 */ {I_VPSCATTERDD, 2, {YMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10000, 240},
+ /* 6237 */ {I_VPSCATTERDD, 2, {ZMEM|BITS32,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10009, 241},
+ /* 6238 */ {I_VPSCATTERDQ, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10018, 240},
+ /* 6239 */ {I_VPSCATTERDQ, 2, {XMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10027, 240},
+ /* 6240 */ {I_VPSCATTERDQ, 2, {YMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10036, 241},
+ /* 6241 */ {I_VPSCATTERQD, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10045, 240},
+ /* 6242 */ {I_VPSCATTERQD, 2, {YMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10054, 240},
+ /* 6243 */ {I_VPSCATTERQD, 2, {ZMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10063, 241},
+ /* 6244 */ {I_VPSCATTERQQ, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10072, 240},
+ /* 6245 */ {I_VPSCATTERQQ, 2, {YMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10081, 240},
+ /* 6246 */ {I_VPSCATTERQQ, 2, {ZMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+10090, 241},
+ /* 6247 */ {I_VPSHUFB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26144, 244},
+ /* 6248 */ {I_VPSHUFB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26152, 244},
+ /* 6249 */ {I_VPSHUFB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26160, 244},
+ /* 6250 */ {I_VPSHUFB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26168, 244},
+ /* 6251 */ {I_VPSHUFB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26176, 245},
+ /* 6252 */ {I_VPSHUFB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26184, 245},
+ /* 6253 */ {I_VPSHUFD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10099, 240},
+ /* 6254 */ {I_VPSHUFD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10108, 240},
+ /* 6255 */ {I_VPSHUFD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10117, 241},
+ /* 6256 */ {I_VPSHUFHW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10126, 244},
+ /* 6257 */ {I_VPSHUFHW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10135, 244},
+ /* 6258 */ {I_VPSHUFHW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10144, 245},
+ /* 6259 */ {I_VPSHUFLW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10153, 244},
+ /* 6260 */ {I_VPSHUFLW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10162, 244},
+ /* 6261 */ {I_VPSHUFLW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10171, 245},
+ /* 6262 */ {I_VPSLLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26192, 240},
+ /* 6263 */ {I_VPSLLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26200, 240},
+ /* 6264 */ {I_VPSLLD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26208, 240},
+ /* 6265 */ {I_VPSLLD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26216, 240},
+ /* 6266 */ {I_VPSLLD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26224, 241},
+ /* 6267 */ {I_VPSLLD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26232, 241},
+ /* 6268 */ {I_VPSLLD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10180, 240},
+ /* 6269 */ {I_VPSLLD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10189, 240},
+ /* 6270 */ {I_VPSLLD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10198, 240},
+ /* 6271 */ {I_VPSLLD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10207, 240},
+ /* 6272 */ {I_VPSLLD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10216, 241},
+ /* 6273 */ {I_VPSLLD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10225, 241},
+ /* 6274 */ {I_VPSLLDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10234, 244},
+ /* 6275 */ {I_VPSLLDQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10243, 244},
+ /* 6276 */ {I_VPSLLDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10252, 244},
+ /* 6277 */ {I_VPSLLDQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10261, 244},
+ /* 6278 */ {I_VPSLLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10270, 245},
+ /* 6279 */ {I_VPSLLDQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10279, 245},
+ /* 6280 */ {I_VPSLLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26240, 240},
+ /* 6281 */ {I_VPSLLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26248, 240},
+ /* 6282 */ {I_VPSLLQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26256, 240},
+ /* 6283 */ {I_VPSLLQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26264, 240},
+ /* 6284 */ {I_VPSLLQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26272, 241},
+ /* 6285 */ {I_VPSLLQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26280, 241},
+ /* 6286 */ {I_VPSLLQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10288, 240},
+ /* 6287 */ {I_VPSLLQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10297, 240},
+ /* 6288 */ {I_VPSLLQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10306, 240},
+ /* 6289 */ {I_VPSLLQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10315, 240},
+ /* 6290 */ {I_VPSLLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10324, 241},
+ /* 6291 */ {I_VPSLLQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10333, 241},
+ /* 6292 */ {I_VPSLLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26288, 240},
+ /* 6293 */ {I_VPSLLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26296, 240},
+ /* 6294 */ {I_VPSLLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26304, 240},
+ /* 6295 */ {I_VPSLLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26312, 240},
+ /* 6296 */ {I_VPSLLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26320, 241},
+ /* 6297 */ {I_VPSLLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26328, 241},
+ /* 6298 */ {I_VPSLLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26336, 240},
+ /* 6299 */ {I_VPSLLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26344, 240},
+ /* 6300 */ {I_VPSLLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26352, 240},
+ /* 6301 */ {I_VPSLLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26360, 240},
+ /* 6302 */ {I_VPSLLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26368, 241},
+ /* 6303 */ {I_VPSLLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26376, 241},
+ /* 6304 */ {I_VPSLLVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26384, 244},
+ /* 6305 */ {I_VPSLLVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26392, 244},
+ /* 6306 */ {I_VPSLLVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26400, 244},
+ /* 6307 */ {I_VPSLLVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26408, 244},
+ /* 6308 */ {I_VPSLLVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26416, 245},
+ /* 6309 */ {I_VPSLLVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26424, 245},
+ /* 6310 */ {I_VPSLLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26432, 244},
+ /* 6311 */ {I_VPSLLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26440, 244},
+ /* 6312 */ {I_VPSLLW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26448, 244},
+ /* 6313 */ {I_VPSLLW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26456, 244},
+ /* 6314 */ {I_VPSLLW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26464, 245},
+ /* 6315 */ {I_VPSLLW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26472, 245},
+ /* 6316 */ {I_VPSLLW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10342, 244},
+ /* 6317 */ {I_VPSLLW, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10351, 244},
+ /* 6318 */ {I_VPSLLW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10360, 244},
+ /* 6319 */ {I_VPSLLW, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10369, 244},
+ /* 6320 */ {I_VPSLLW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10378, 245},
+ /* 6321 */ {I_VPSLLW, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10387, 245},
+ /* 6322 */ {I_VPSRAD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26480, 240},
+ /* 6323 */ {I_VPSRAD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26488, 240},
+ /* 6324 */ {I_VPSRAD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26496, 240},
+ /* 6325 */ {I_VPSRAD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26504, 240},
+ /* 6326 */ {I_VPSRAD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26512, 241},
+ /* 6327 */ {I_VPSRAD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26520, 241},
+ /* 6328 */ {I_VPSRAD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10396, 240},
+ /* 6329 */ {I_VPSRAD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10405, 240},
+ /* 6330 */ {I_VPSRAD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10414, 240},
+ /* 6331 */ {I_VPSRAD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10423, 240},
+ /* 6332 */ {I_VPSRAD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10432, 241},
+ /* 6333 */ {I_VPSRAD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10441, 241},
+ /* 6334 */ {I_VPSRAQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26528, 240},
+ /* 6335 */ {I_VPSRAQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26536, 240},
+ /* 6336 */ {I_VPSRAQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26544, 240},
+ /* 6337 */ {I_VPSRAQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26552, 240},
+ /* 6338 */ {I_VPSRAQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26560, 241},
+ /* 6339 */ {I_VPSRAQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26568, 241},
+ /* 6340 */ {I_VPSRAQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10450, 240},
+ /* 6341 */ {I_VPSRAQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10459, 240},
+ /* 6342 */ {I_VPSRAQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10468, 240},
+ /* 6343 */ {I_VPSRAQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10477, 240},
+ /* 6344 */ {I_VPSRAQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10486, 241},
+ /* 6345 */ {I_VPSRAQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10495, 241},
+ /* 6346 */ {I_VPSRAVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26576, 240},
+ /* 6347 */ {I_VPSRAVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26584, 240},
+ /* 6348 */ {I_VPSRAVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26592, 240},
+ /* 6349 */ {I_VPSRAVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26600, 240},
+ /* 6350 */ {I_VPSRAVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26608, 241},
+ /* 6351 */ {I_VPSRAVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26616, 241},
+ /* 6352 */ {I_VPSRAVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26624, 240},
+ /* 6353 */ {I_VPSRAVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26632, 240},
+ /* 6354 */ {I_VPSRAVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26640, 240},
+ /* 6355 */ {I_VPSRAVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26648, 240},
+ /* 6356 */ {I_VPSRAVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26656, 241},
+ /* 6357 */ {I_VPSRAVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26664, 241},
+ /* 6358 */ {I_VPSRAVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26672, 244},
+ /* 6359 */ {I_VPSRAVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26680, 244},
+ /* 6360 */ {I_VPSRAVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26688, 244},
+ /* 6361 */ {I_VPSRAVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26696, 244},
+ /* 6362 */ {I_VPSRAVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26704, 245},
+ /* 6363 */ {I_VPSRAVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26712, 245},
+ /* 6364 */ {I_VPSRAW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26720, 244},
+ /* 6365 */ {I_VPSRAW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26728, 244},
+ /* 6366 */ {I_VPSRAW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26736, 244},
+ /* 6367 */ {I_VPSRAW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26744, 244},
+ /* 6368 */ {I_VPSRAW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26752, 245},
+ /* 6369 */ {I_VPSRAW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26760, 245},
+ /* 6370 */ {I_VPSRAW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10504, 244},
+ /* 6371 */ {I_VPSRAW, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10513, 244},
+ /* 6372 */ {I_VPSRAW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10522, 244},
+ /* 6373 */ {I_VPSRAW, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10531, 244},
+ /* 6374 */ {I_VPSRAW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10540, 245},
+ /* 6375 */ {I_VPSRAW, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10549, 245},
+ /* 6376 */ {I_VPSRLD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26768, 240},
+ /* 6377 */ {I_VPSRLD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26776, 240},
+ /* 6378 */ {I_VPSRLD, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26784, 240},
+ /* 6379 */ {I_VPSRLD, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26792, 240},
+ /* 6380 */ {I_VPSRLD, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26800, 241},
+ /* 6381 */ {I_VPSRLD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26808, 241},
+ /* 6382 */ {I_VPSRLD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10558, 240},
+ /* 6383 */ {I_VPSRLD, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10567, 240},
+ /* 6384 */ {I_VPSRLD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10576, 240},
+ /* 6385 */ {I_VPSRLD, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10585, 240},
+ /* 6386 */ {I_VPSRLD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10594, 241},
+ /* 6387 */ {I_VPSRLD, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10603, 241},
+ /* 6388 */ {I_VPSRLDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10612, 244},
+ /* 6389 */ {I_VPSRLDQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10621, 244},
+ /* 6390 */ {I_VPSRLDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10630, 244},
+ /* 6391 */ {I_VPSRLDQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10639, 244},
+ /* 6392 */ {I_VPSRLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+10648, 245},
+ /* 6393 */ {I_VPSRLDQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, NO_DECORATOR, nasm_bytecodes+10657, 245},
+ /* 6394 */ {I_VPSRLQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26816, 240},
+ /* 6395 */ {I_VPSRLQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26824, 240},
+ /* 6396 */ {I_VPSRLQ, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26832, 240},
+ /* 6397 */ {I_VPSRLQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26840, 240},
+ /* 6398 */ {I_VPSRLQ, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26848, 241},
+ /* 6399 */ {I_VPSRLQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26856, 241},
+ /* 6400 */ {I_VPSRLQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10666, 240},
+ /* 6401 */ {I_VPSRLQ, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10675, 240},
+ /* 6402 */ {I_VPSRLQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10684, 240},
+ /* 6403 */ {I_VPSRLQ, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10693, 240},
+ /* 6404 */ {I_VPSRLQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10702, 241},
+ /* 6405 */ {I_VPSRLQ, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10711, 241},
+ /* 6406 */ {I_VPSRLVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26864, 240},
+ /* 6407 */ {I_VPSRLVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26872, 240},
+ /* 6408 */ {I_VPSRLVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26880, 240},
+ /* 6409 */ {I_VPSRLVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26888, 240},
+ /* 6410 */ {I_VPSRLVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+26896, 241},
+ /* 6411 */ {I_VPSRLVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+26904, 241},
+ /* 6412 */ {I_VPSRLVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26912, 240},
+ /* 6413 */ {I_VPSRLVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26920, 240},
+ /* 6414 */ {I_VPSRLVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26928, 240},
+ /* 6415 */ {I_VPSRLVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26936, 240},
+ /* 6416 */ {I_VPSRLVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+26944, 241},
+ /* 6417 */ {I_VPSRLVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+26952, 241},
+ /* 6418 */ {I_VPSRLVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26960, 244},
+ /* 6419 */ {I_VPSRLVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26968, 244},
+ /* 6420 */ {I_VPSRLVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26976, 244},
+ /* 6421 */ {I_VPSRLVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26984, 244},
+ /* 6422 */ {I_VPSRLVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+26992, 245},
+ /* 6423 */ {I_VPSRLVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27000, 245},
+ /* 6424 */ {I_VPSRLW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27008, 244},
+ /* 6425 */ {I_VPSRLW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27016, 244},
+ /* 6426 */ {I_VPSRLW, 3, {YMMREG,YMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27024, 244},
+ /* 6427 */ {I_VPSRLW, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27032, 244},
+ /* 6428 */ {I_VPSRLW, 3, {ZMMREG,ZMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27040, 245},
+ /* 6429 */ {I_VPSRLW, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27048, 245},
+ /* 6430 */ {I_VPSRLW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10720, 244},
+ /* 6431 */ {I_VPSRLW, 2, {XMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10729, 244},
+ /* 6432 */ {I_VPSRLW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10738, 244},
+ /* 6433 */ {I_VPSRLW, 2, {YMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10747, 244},
+ /* 6434 */ {I_VPSRLW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10756, 245},
+ /* 6435 */ {I_VPSRLW, 2, {ZMMREG,IMMEDIATE|BITS8,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+10765, 245},
+ /* 6436 */ {I_VPSUBB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27056, 244},
+ /* 6437 */ {I_VPSUBB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27064, 244},
+ /* 6438 */ {I_VPSUBB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27072, 244},
+ /* 6439 */ {I_VPSUBB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27080, 244},
+ /* 6440 */ {I_VPSUBB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27088, 245},
+ /* 6441 */ {I_VPSUBB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27096, 245},
+ /* 6442 */ {I_VPSUBD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27104, 240},
+ /* 6443 */ {I_VPSUBD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27112, 240},
+ /* 6444 */ {I_VPSUBD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27120, 240},
+ /* 6445 */ {I_VPSUBD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27128, 240},
+ /* 6446 */ {I_VPSUBD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27136, 241},
+ /* 6447 */ {I_VPSUBD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27144, 241},
+ /* 6448 */ {I_VPSUBQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27152, 240},
+ /* 6449 */ {I_VPSUBQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27160, 240},
+ /* 6450 */ {I_VPSUBQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27168, 240},
+ /* 6451 */ {I_VPSUBQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27176, 240},
+ /* 6452 */ {I_VPSUBQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27184, 241},
+ /* 6453 */ {I_VPSUBQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27192, 241},
+ /* 6454 */ {I_VPSUBSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27200, 244},
+ /* 6455 */ {I_VPSUBSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27208, 244},
+ /* 6456 */ {I_VPSUBSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27216, 244},
+ /* 6457 */ {I_VPSUBSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27224, 244},
+ /* 6458 */ {I_VPSUBSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27232, 245},
+ /* 6459 */ {I_VPSUBSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27240, 245},
+ /* 6460 */ {I_VPSUBSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27248, 244},
+ /* 6461 */ {I_VPSUBSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27256, 244},
+ /* 6462 */ {I_VPSUBSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27264, 244},
+ /* 6463 */ {I_VPSUBSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27272, 244},
+ /* 6464 */ {I_VPSUBSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27280, 245},
+ /* 6465 */ {I_VPSUBSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27288, 245},
+ /* 6466 */ {I_VPSUBUSB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27296, 244},
+ /* 6467 */ {I_VPSUBUSB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27304, 244},
+ /* 6468 */ {I_VPSUBUSB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27312, 244},
+ /* 6469 */ {I_VPSUBUSB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27320, 244},
+ /* 6470 */ {I_VPSUBUSB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27328, 245},
+ /* 6471 */ {I_VPSUBUSB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27336, 245},
+ /* 6472 */ {I_VPSUBUSW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27344, 244},
+ /* 6473 */ {I_VPSUBUSW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27352, 244},
+ /* 6474 */ {I_VPSUBUSW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27360, 244},
+ /* 6475 */ {I_VPSUBUSW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27368, 244},
+ /* 6476 */ {I_VPSUBUSW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27376, 245},
+ /* 6477 */ {I_VPSUBUSW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27384, 245},
+ /* 6478 */ {I_VPSUBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27392, 244},
+ /* 6479 */ {I_VPSUBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27400, 244},
+ /* 6480 */ {I_VPSUBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27408, 244},
+ /* 6481 */ {I_VPSUBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27416, 244},
+ /* 6482 */ {I_VPSUBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27424, 245},
+ /* 6483 */ {I_VPSUBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27432, 245},
+ /* 6484 */ {I_VPTERNLOGD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10774, 240},
+ /* 6485 */ {I_VPTERNLOGD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10783, 240},
+ /* 6486 */ {I_VPTERNLOGD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10792, 241},
+ /* 6487 */ {I_VPTERNLOGQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10801, 240},
+ /* 6488 */ {I_VPTERNLOGQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10810, 240},
+ /* 6489 */ {I_VPTERNLOGQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10819, 241},
+ /* 6490 */ {I_VPTESTMB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27440, 244},
+ /* 6491 */ {I_VPTESTMB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27448, 244},
+ /* 6492 */ {I_VPTESTMB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27456, 245},
+ /* 6493 */ {I_VPTESTMD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27464, 240},
+ /* 6494 */ {I_VPTESTMD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27472, 240},
+ /* 6495 */ {I_VPTESTMD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27480, 241},
+ /* 6496 */ {I_VPTESTMQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27488, 240},
+ /* 6497 */ {I_VPTESTMQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27496, 240},
+ /* 6498 */ {I_VPTESTMQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27504, 241},
+ /* 6499 */ {I_VPTESTMW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27512, 244},
+ /* 6500 */ {I_VPTESTMW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27520, 244},
+ /* 6501 */ {I_VPTESTMW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27528, 245},
+ /* 6502 */ {I_VPTESTNMB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27536, 244},
+ /* 6503 */ {I_VPTESTNMB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27544, 244},
+ /* 6504 */ {I_VPTESTNMB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27552, 245},
+ /* 6505 */ {I_VPTESTNMD, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27560, 240},
+ /* 6506 */ {I_VPTESTNMD, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27568, 240},
+ /* 6507 */ {I_VPTESTNMD, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B32,0,0}, nasm_bytecodes+27576, 241},
+ /* 6508 */ {I_VPTESTNMQ, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27584, 240},
+ /* 6509 */ {I_VPTESTNMQ, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27592, 240},
+ /* 6510 */ {I_VPTESTNMQ, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,B64,0,0}, nasm_bytecodes+27600, 241},
+ /* 6511 */ {I_VPTESTNMW, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27608, 244},
+ /* 6512 */ {I_VPTESTNMW, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27616, 244},
+ /* 6513 */ {I_VPTESTNMW, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+27624, 245},
+ /* 6514 */ {I_VPUNPCKHBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27632, 244},
+ /* 6515 */ {I_VPUNPCKHBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27640, 244},
+ /* 6516 */ {I_VPUNPCKHBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27648, 244},
+ /* 6517 */ {I_VPUNPCKHBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27656, 244},
+ /* 6518 */ {I_VPUNPCKHBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27664, 245},
+ /* 6519 */ {I_VPUNPCKHBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27672, 245},
+ /* 6520 */ {I_VPUNPCKHDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27680, 240},
+ /* 6521 */ {I_VPUNPCKHDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27688, 240},
+ /* 6522 */ {I_VPUNPCKHDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27696, 240},
+ /* 6523 */ {I_VPUNPCKHDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27704, 240},
+ /* 6524 */ {I_VPUNPCKHDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27712, 241},
+ /* 6525 */ {I_VPUNPCKHDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27720, 241},
+ /* 6526 */ {I_VPUNPCKHQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27728, 240},
+ /* 6527 */ {I_VPUNPCKHQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27736, 240},
+ /* 6528 */ {I_VPUNPCKHQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27744, 240},
+ /* 6529 */ {I_VPUNPCKHQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27752, 240},
+ /* 6530 */ {I_VPUNPCKHQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27760, 241},
+ /* 6531 */ {I_VPUNPCKHQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27768, 241},
+ /* 6532 */ {I_VPUNPCKHWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27776, 244},
+ /* 6533 */ {I_VPUNPCKHWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27784, 244},
+ /* 6534 */ {I_VPUNPCKHWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27792, 244},
+ /* 6535 */ {I_VPUNPCKHWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27800, 244},
+ /* 6536 */ {I_VPUNPCKHWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27808, 245},
+ /* 6537 */ {I_VPUNPCKHWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27816, 245},
+ /* 6538 */ {I_VPUNPCKLBW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27824, 244},
+ /* 6539 */ {I_VPUNPCKLBW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27832, 244},
+ /* 6540 */ {I_VPUNPCKLBW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27840, 244},
+ /* 6541 */ {I_VPUNPCKLBW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27848, 244},
+ /* 6542 */ {I_VPUNPCKLBW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27856, 245},
+ /* 6543 */ {I_VPUNPCKLBW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27864, 245},
+ /* 6544 */ {I_VPUNPCKLDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27872, 240},
+ /* 6545 */ {I_VPUNPCKLDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27880, 240},
+ /* 6546 */ {I_VPUNPCKLDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27888, 240},
+ /* 6547 */ {I_VPUNPCKLDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27896, 240},
+ /* 6548 */ {I_VPUNPCKLDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+27904, 241},
+ /* 6549 */ {I_VPUNPCKLDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+27912, 241},
+ /* 6550 */ {I_VPUNPCKLQDQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27920, 240},
+ /* 6551 */ {I_VPUNPCKLQDQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27928, 240},
+ /* 6552 */ {I_VPUNPCKLQDQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27936, 240},
+ /* 6553 */ {I_VPUNPCKLQDQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27944, 240},
+ /* 6554 */ {I_VPUNPCKLQDQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+27952, 241},
+ /* 6555 */ {I_VPUNPCKLQDQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+27960, 241},
+ /* 6556 */ {I_VPUNPCKLWD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27968, 244},
+ /* 6557 */ {I_VPUNPCKLWD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27976, 244},
+ /* 6558 */ {I_VPUNPCKLWD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27984, 244},
+ /* 6559 */ {I_VPUNPCKLWD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+27992, 244},
+ /* 6560 */ {I_VPUNPCKLWD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28000, 245},
+ /* 6561 */ {I_VPUNPCKLWD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28008, 245},
+ /* 6562 */ {I_VPXORD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28016, 240},
+ /* 6563 */ {I_VPXORD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28024, 240},
+ /* 6564 */ {I_VPXORD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28032, 240},
+ /* 6565 */ {I_VPXORD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28040, 240},
+ /* 6566 */ {I_VPXORD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28048, 241},
+ /* 6567 */ {I_VPXORD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28056, 241},
+ /* 6568 */ {I_VPXORQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28064, 240},
+ /* 6569 */ {I_VPXORQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28072, 240},
+ /* 6570 */ {I_VPXORQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28080, 240},
+ /* 6571 */ {I_VPXORQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28088, 240},
+ /* 6572 */ {I_VPXORQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28096, 241},
+ /* 6573 */ {I_VPXORQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28104, 241},
+ /* 6574 */ {I_VRANGEPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10828, 242},
+ /* 6575 */ {I_VRANGEPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10837, 242},
+ /* 6576 */ {I_VRANGEPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+10846, 242},
+ /* 6577 */ {I_VRANGEPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10855, 242},
+ /* 6578 */ {I_VRANGEPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64|SAE,0,0}, nasm_bytecodes+10864, 243},
+ /* 6579 */ {I_VRANGEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+10873, 243},
+ /* 6580 */ {I_VRANGEPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10882, 242},
+ /* 6581 */ {I_VRANGEPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10891, 242},
+ /* 6582 */ {I_VRANGEPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+10900, 242},
+ /* 6583 */ {I_VRANGEPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10909, 242},
+ /* 6584 */ {I_VRANGEPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32|SAE,0,0}, nasm_bytecodes+10918, 243},
+ /* 6585 */ {I_VRANGEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+10927, 243},
+ /* 6586 */ {I_VRANGESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+10936, 243},
+ /* 6587 */ {I_VRANGESD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+10945, 243},
+ /* 6588 */ {I_VRANGESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+10954, 243},
+ /* 6589 */ {I_VRANGESS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+10963, 243},
+ /* 6590 */ {I_VRCP14PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28112, 240},
+ /* 6591 */ {I_VRCP14PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28120, 240},
+ /* 6592 */ {I_VRCP14PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28128, 241},
+ /* 6593 */ {I_VRCP14PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28136, 240},
+ /* 6594 */ {I_VRCP14PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28144, 240},
+ /* 6595 */ {I_VRCP14PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28152, 241},
+ /* 6596 */ {I_VRCP14SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28160, 241},
+ /* 6597 */ {I_VRCP14SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28168, 241},
+ /* 6598 */ {I_VRCP14SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28176, 241},
+ /* 6599 */ {I_VRCP14SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28184, 241},
+ /* 6600 */ {I_VRCP28PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+28192, 246},
+ /* 6601 */ {I_VRCP28PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+28200, 246},
+ /* 6602 */ {I_VRCP28SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28208, 246},
+ /* 6603 */ {I_VRCP28SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28216, 246},
+ /* 6604 */ {I_VRCP28SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28224, 246},
+ /* 6605 */ {I_VRCP28SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28232, 246},
+ /* 6606 */ {I_VREDUCEPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10972, 242},
+ /* 6607 */ {I_VREDUCEPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+10981, 242},
+ /* 6608 */ {I_VREDUCEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+10990, 243},
+ /* 6609 */ {I_VREDUCEPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+10999, 242},
+ /* 6610 */ {I_VREDUCEPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11008, 242},
+ /* 6611 */ {I_VREDUCEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+11017, 243},
+ /* 6612 */ {I_VREDUCESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11026, 243},
+ /* 6613 */ {I_VREDUCESD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11035, 243},
+ /* 6614 */ {I_VREDUCESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11044, 243},
+ /* 6615 */ {I_VREDUCESS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11053, 243},
+ /* 6616 */ {I_VRNDSCALEPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11062, 240},
+ /* 6617 */ {I_VRNDSCALEPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11071, 240},
+ /* 6618 */ {I_VRNDSCALEPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+11080, 241},
+ /* 6619 */ {I_VRNDSCALEPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11089, 240},
+ /* 6620 */ {I_VRNDSCALEPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11098, 240},
+ /* 6621 */ {I_VRNDSCALEPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+11107, 241},
+ /* 6622 */ {I_VRNDSCALESD, 4, {XMMREG,XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11116, 241},
+ /* 6623 */ {I_VRNDSCALESD, 3, {XMMREG,RM_XMM|BITS64,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11125, 241},
+ /* 6624 */ {I_VRNDSCALESS, 4, {XMMREG,XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+11134, 241},
+ /* 6625 */ {I_VRNDSCALESS, 3, {XMMREG,RM_XMM|BITS32,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+11143, 241},
+ /* 6626 */ {I_VRSQRT14PD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28240, 240},
+ /* 6627 */ {I_VRSQRT14PD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28248, 240},
+ /* 6628 */ {I_VRSQRT14PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28256, 241},
+ /* 6629 */ {I_VRSQRT14PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28264, 240},
+ /* 6630 */ {I_VRSQRT14PS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28272, 240},
+ /* 6631 */ {I_VRSQRT14PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28280, 241},
+ /* 6632 */ {I_VRSQRT14SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28288, 241},
+ /* 6633 */ {I_VRSQRT14SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28296, 241},
+ /* 6634 */ {I_VRSQRT14SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28304, 241},
+ /* 6635 */ {I_VRSQRT14SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+28312, 241},
+ /* 6636 */ {I_VRSQRT28PD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|SAE,0,0,0}, nasm_bytecodes+28320, 246},
+ /* 6637 */ {I_VRSQRT28PS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|SAE,0,0,0}, nasm_bytecodes+28328, 246},
+ /* 6638 */ {I_VRSQRT28SD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28336, 246},
+ /* 6639 */ {I_VRSQRT28SD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28344, 246},
+ /* 6640 */ {I_VRSQRT28SS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+28352, 246},
+ /* 6641 */ {I_VRSQRT28SS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+28360, 246},
+ /* 6642 */ {I_VSCALEFPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28368, 240},
+ /* 6643 */ {I_VSCALEFPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28376, 240},
+ /* 6644 */ {I_VSCALEFPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28384, 240},
+ /* 6645 */ {I_VSCALEFPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28392, 240},
+ /* 6646 */ {I_VSCALEFPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+28400, 241},
+ /* 6647 */ {I_VSCALEFPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+28408, 241},
+ /* 6648 */ {I_VSCALEFPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28416, 240},
+ /* 6649 */ {I_VSCALEFPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28424, 240},
+ /* 6650 */ {I_VSCALEFPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28432, 240},
+ /* 6651 */ {I_VSCALEFPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28440, 240},
+ /* 6652 */ {I_VSCALEFPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+28448, 241},
+ /* 6653 */ {I_VSCALEFPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+28456, 241},
+ /* 6654 */ {I_VSCALEFSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28464, 241},
+ /* 6655 */ {I_VSCALEFSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28472, 241},
+ /* 6656 */ {I_VSCALEFSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28480, 241},
+ /* 6657 */ {I_VSCALEFSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28488, 241},
+ /* 6658 */ {I_VSCATTERDPD, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11152, 240},
+ /* 6659 */ {I_VSCATTERDPD, 2, {XMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11161, 240},
+ /* 6660 */ {I_VSCATTERDPD, 2, {YMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11170, 241},
+ /* 6661 */ {I_VSCATTERDPS, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11179, 240},
+ /* 6662 */ {I_VSCATTERDPS, 2, {YMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11188, 240},
+ /* 6663 */ {I_VSCATTERDPS, 2, {ZMEM|BITS32,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11197, 241},
+ /* 6664 */ {I_VSCATTERPF0DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11206, 247},
+ /* 6665 */ {I_VSCATTERPF0DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11215, 247},
+ /* 6666 */ {I_VSCATTERPF0QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11224, 247},
+ /* 6667 */ {I_VSCATTERPF0QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11233, 247},
+ /* 6668 */ {I_VSCATTERPF1DPD, 1, {YMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11242, 247},
+ /* 6669 */ {I_VSCATTERPF1DPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11251, 247},
+ /* 6670 */ {I_VSCATTERPF1QPD, 1, {ZMEM|BITS64,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11260, 247},
+ /* 6671 */ {I_VSCATTERPF1QPS, 1, {ZMEM|BITS32,0,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11269, 247},
+ /* 6672 */ {I_VSCATTERQPD, 2, {XMEM|BITS64,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11278, 240},
+ /* 6673 */ {I_VSCATTERQPD, 2, {YMEM|BITS64,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11287, 240},
+ /* 6674 */ {I_VSCATTERQPD, 2, {ZMEM|BITS64,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11296, 241},
+ /* 6675 */ {I_VSCATTERQPS, 2, {XMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11305, 240},
+ /* 6676 */ {I_VSCATTERQPS, 2, {YMEM|BITS32,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11314, 240},
+ /* 6677 */ {I_VSCATTERQPS, 2, {ZMEM|BITS32,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+11323, 241},
+ /* 6678 */ {I_VSHUFF32X4, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11332, 240},
+ /* 6679 */ {I_VSHUFF32X4, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11341, 240},
+ /* 6680 */ {I_VSHUFF32X4, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11350, 241},
+ /* 6681 */ {I_VSHUFF32X4, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11359, 241},
+ /* 6682 */ {I_VSHUFF64X2, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11368, 240},
+ /* 6683 */ {I_VSHUFF64X2, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11377, 240},
+ /* 6684 */ {I_VSHUFF64X2, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11386, 241},
+ /* 6685 */ {I_VSHUFF64X2, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11395, 241},
+ /* 6686 */ {I_VSHUFI32X4, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11404, 240},
+ /* 6687 */ {I_VSHUFI32X4, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11413, 240},
+ /* 6688 */ {I_VSHUFI32X4, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11422, 241},
+ /* 6689 */ {I_VSHUFI32X4, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11431, 241},
+ /* 6690 */ {I_VSHUFI64X2, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11440, 240},
+ /* 6691 */ {I_VSHUFI64X2, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11449, 240},
+ /* 6692 */ {I_VSHUFI64X2, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11458, 241},
+ /* 6693 */ {I_VSHUFI64X2, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11467, 241},
+ /* 6694 */ {I_VSHUFPD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11476, 240},
+ /* 6695 */ {I_VSHUFPD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11485, 240},
+ /* 6696 */ {I_VSHUFPD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11494, 240},
+ /* 6697 */ {I_VSHUFPD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11503, 240},
+ /* 6698 */ {I_VSHUFPD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11512, 241},
+ /* 6699 */ {I_VSHUFPD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11521, 241},
+ /* 6700 */ {I_VSHUFPS, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11530, 240},
+ /* 6701 */ {I_VSHUFPS, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11539, 240},
+ /* 6702 */ {I_VSHUFPS, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11548, 240},
+ /* 6703 */ {I_VSHUFPS, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11557, 240},
+ /* 6704 */ {I_VSHUFPS, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11566, 241},
+ /* 6705 */ {I_VSHUFPS, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11575, 241},
+ /* 6706 */ {I_VSQRTPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28496, 240},
+ /* 6707 */ {I_VSQRTPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28504, 240},
+ /* 6708 */ {I_VSQRTPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+28512, 241},
+ /* 6709 */ {I_VSQRTPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28520, 240},
+ /* 6710 */ {I_VSQRTPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28528, 240},
+ /* 6711 */ {I_VSQRTPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+28536, 241},
+ /* 6712 */ {I_VSQRTSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28544, 241},
+ /* 6713 */ {I_VSQRTSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28552, 241},
+ /* 6714 */ {I_VSQRTSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28560, 241},
+ /* 6715 */ {I_VSQRTSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28568, 241},
+ /* 6716 */ {I_VSUBPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28576, 240},
+ /* 6717 */ {I_VSUBPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28584, 240},
+ /* 6718 */ {I_VSUBPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28592, 240},
+ /* 6719 */ {I_VSUBPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28600, 240},
+ /* 6720 */ {I_VSUBPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64|ER,0,0}, nasm_bytecodes+28608, 241},
+ /* 6721 */ {I_VSUBPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+28616, 241},
+ /* 6722 */ {I_VSUBPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28624, 240},
+ /* 6723 */ {I_VSUBPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28632, 240},
+ /* 6724 */ {I_VSUBPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28640, 240},
+ /* 6725 */ {I_VSUBPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28648, 240},
+ /* 6726 */ {I_VSUBPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+28656, 241},
+ /* 6727 */ {I_VSUBPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+28664, 241},
+ /* 6728 */ {I_VSUBSD, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28672, 241},
+ /* 6729 */ {I_VSUBSD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28680, 241},
+ /* 6730 */ {I_VSUBSS, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+28688, 241},
+ /* 6731 */ {I_VSUBSS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+28696, 241},
+ /* 6732 */ {I_VUCOMISD, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+28704, 241},
+ /* 6733 */ {I_VUCOMISS, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+28712, 241},
+ /* 6734 */ {I_VUNPCKHPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28720, 240},
+ /* 6735 */ {I_VUNPCKHPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28728, 240},
+ /* 6736 */ {I_VUNPCKHPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28736, 240},
+ /* 6737 */ {I_VUNPCKHPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28744, 240},
+ /* 6738 */ {I_VUNPCKHPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28752, 241},
+ /* 6739 */ {I_VUNPCKHPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28760, 241},
+ /* 6740 */ {I_VUNPCKHPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28768, 240},
+ /* 6741 */ {I_VUNPCKHPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28776, 240},
+ /* 6742 */ {I_VUNPCKHPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28784, 240},
+ /* 6743 */ {I_VUNPCKHPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28792, 240},
+ /* 6744 */ {I_VUNPCKHPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28800, 241},
+ /* 6745 */ {I_VUNPCKHPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28808, 241},
+ /* 6746 */ {I_VUNPCKLPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28816, 240},
+ /* 6747 */ {I_VUNPCKLPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28824, 240},
+ /* 6748 */ {I_VUNPCKLPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28832, 240},
+ /* 6749 */ {I_VUNPCKLPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28840, 240},
+ /* 6750 */ {I_VUNPCKLPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28848, 241},
+ /* 6751 */ {I_VUNPCKLPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28856, 241},
+ /* 6752 */ {I_VUNPCKLPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28864, 240},
+ /* 6753 */ {I_VUNPCKLPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28872, 240},
+ /* 6754 */ {I_VUNPCKLPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28880, 240},
+ /* 6755 */ {I_VUNPCKLPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28888, 240},
+ /* 6756 */ {I_VUNPCKLPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28896, 241},
+ /* 6757 */ {I_VUNPCKLPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28904, 241},
+ /* 6758 */ {I_VXORPD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28912, 242},
+ /* 6759 */ {I_VXORPD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28920, 242},
+ /* 6760 */ {I_VXORPD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28928, 242},
+ /* 6761 */ {I_VXORPD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28936, 242},
+ /* 6762 */ {I_VXORPD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+28944, 243},
+ /* 6763 */ {I_VXORPD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+28952, 243},
+ /* 6764 */ {I_VXORPS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28960, 242},
+ /* 6765 */ {I_VXORPS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28968, 242},
+ /* 6766 */ {I_VXORPS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28976, 242},
+ /* 6767 */ {I_VXORPS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+28984, 242},
+ /* 6768 */ {I_VXORPS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+28992, 243},
+ /* 6769 */ {I_VXORPS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29000, 243},
+ /* 6770 */ {I_RDPKRU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46072, 136},
+ /* 6771 */ {I_WRPKRU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46078, 136},
+ /* 6772 */ {I_RDPID, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42322, 254},
+ /* 6773 */ {I_RDPID, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42321, 136},
+ /* 6774 */ {I_RDPID, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42322, 255},
+ /* 6775 */ {I_CLFLUSHOPT, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45951, 135},
+ /* 6776 */ {I_CLWB, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45957, 135},
+ /* 6777 */ {I_PCOMMIT, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45963, 256},
+ /* 6778 */ {I_CLZERO, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45982, 257},
+ /* 6779 */ {I_PTWRITE, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34020, 135},
+ /* 6780 */ {I_PTWRITE, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+34019, 136},
+ /* 6781 */ {I_CLDEMOTE, 1, {MEMORY,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45987, 135},
+ /* 6782 */ {I_MOVDIRI, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42328, 260},
+ /* 6783 */ {I_MOVDIRI, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42335, 261},
+ /* 6784 */ {I_MOVDIR64B, 2, {REG_GPR|BITS16,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29008, 254},
+ /* 6785 */ {I_MOVDIR64B, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29016, 135},
+ /* 6786 */ {I_MOVDIR64B, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+11584, 136},
+ /* 6787 */ {I_PCONFIG, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45993, 135},
+ /* 6788 */ {I_TPAUSE, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45957, 135},
+ /* 6789 */ {I_UMONITOR, 1, {REG_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42342, 254},
+ /* 6790 */ {I_UMONITOR, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42349, 135},
+ /* 6791 */ {I_UMONITOR, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+29024, 136},
+ /* 6792 */ {I_UMWAIT, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45999, 135},
+ /* 6793 */ {I_WBNOINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49182, 135},
+ /* 6794 */ {I_GF2P8AFFINEINVQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29032, 262},
+ /* 6795 */ {I_VGF2P8AFFINEINVQB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29040, 263},
+ /* 6796 */ {I_VGF2P8AFFINEINVQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29048, 263},
+ /* 6797 */ {I_VGF2P8AFFINEINVQB, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29056, 263},
+ /* 6798 */ {I_VGF2P8AFFINEINVQB, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29064, 263},
+ /* 6799 */ {I_VGF2P8AFFINEINVQB, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11593, 264},
+ /* 6800 */ {I_VGF2P8AFFINEINVQB, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11602, 264},
+ /* 6801 */ {I_VGF2P8AFFINEINVQB, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11611, 264},
+ /* 6802 */ {I_VGF2P8AFFINEINVQB, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11620, 264},
+ /* 6803 */ {I_VGF2P8AFFINEINVQB, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11629, 265},
+ /* 6804 */ {I_VGF2P8AFFINEINVQB, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11638, 265},
+ /* 6805 */ {I_GF2P8AFFINEQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29072, 262},
+ /* 6806 */ {I_VGF2P8AFFINEQB, 4, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29080, 263},
+ /* 6807 */ {I_VGF2P8AFFINEQB, 3, {XMM_L16,RM_XMM_L16|BITS128,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29088, 263},
+ /* 6808 */ {I_VGF2P8AFFINEQB, 4, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0}, NO_DECORATOR, nasm_bytecodes+29096, 263},
+ /* 6809 */ {I_VGF2P8AFFINEQB, 3, {YMM_L16,RM_YMM_L16|BITS256,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+29104, 263},
+ /* 6810 */ {I_VGF2P8AFFINEQB, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11647, 264},
+ /* 6811 */ {I_VGF2P8AFFINEQB, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11656, 264},
+ /* 6812 */ {I_VGF2P8AFFINEQB, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11665, 264},
+ /* 6813 */ {I_VGF2P8AFFINEQB, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11674, 264},
+ /* 6814 */ {I_VGF2P8AFFINEQB, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11683, 265},
+ /* 6815 */ {I_VGF2P8AFFINEQB, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11692, 265},
+ /* 6816 */ {I_GF2P8MULB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+42356, 262},
+ /* 6817 */ {I_VGF2P8MULB, 3, {XMM_L16,XMM_L16,RM_XMM_L16|BITS128,0,0}, NO_DECORATOR, nasm_bytecodes+42363, 263},
+ /* 6818 */ {I_VGF2P8MULB, 2, {XMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+42370, 263},
+ /* 6819 */ {I_VGF2P8MULB, 3, {YMM_L16,YMM_L16,RM_YMM_L16|BITS256,0,0}, NO_DECORATOR, nasm_bytecodes+42377, 263},
+ /* 6820 */ {I_VGF2P8MULB, 2, {YMM_L16,RM_YMM_L16|BITS256,0,0,0}, NO_DECORATOR, nasm_bytecodes+42384, 263},
+ /* 6821 */ {I_VGF2P8MULB, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29112, 264},
+ /* 6822 */ {I_VGF2P8MULB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29120, 264},
+ /* 6823 */ {I_VGF2P8MULB, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29128, 264},
+ /* 6824 */ {I_VGF2P8MULB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29136, 264},
+ /* 6825 */ {I_VGF2P8MULB, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29144, 265},
+ /* 6826 */ {I_VGF2P8MULB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29152, 265},
+ /* 6827 */ {I_VPCOMPRESSB, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29160, 266},
+ /* 6828 */ {I_VPCOMPRESSB, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29168, 266},
+ /* 6829 */ {I_VPCOMPRESSB, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29176, 267},
+ /* 6830 */ {I_VPCOMPRESSB, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29184, 266},
+ /* 6831 */ {I_VPCOMPRESSB, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29192, 266},
+ /* 6832 */ {I_VPCOMPRESSB, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29200, 267},
+ /* 6833 */ {I_VPCOMPRESSW, 2, {MEMORY|BITS128,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29208, 266},
+ /* 6834 */ {I_VPCOMPRESSW, 2, {MEMORY|BITS256,YMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29216, 266},
+ /* 6835 */ {I_VPCOMPRESSW, 2, {MEMORY|BITS512,ZMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29224, 267},
+ /* 6836 */ {I_VPCOMPRESSW, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29232, 266},
+ /* 6837 */ {I_VPCOMPRESSW, 2, {YMMREG,YMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29240, 266},
+ /* 6838 */ {I_VPCOMPRESSW, 2, {ZMMREG,ZMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29248, 267},
+ /* 6839 */ {I_VPEXPANDB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29256, 266},
+ /* 6840 */ {I_VPEXPANDB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29264, 266},
+ /* 6841 */ {I_VPEXPANDB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29272, 267},
+ /* 6842 */ {I_VPEXPANDW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29280, 266},
+ /* 6843 */ {I_VPEXPANDW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29288, 266},
+ /* 6844 */ {I_VPEXPANDW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29296, 267},
+ /* 6845 */ {I_VPSHLDW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11701, 266},
+ /* 6846 */ {I_VPSHLDW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11710, 266},
+ /* 6847 */ {I_VPSHLDW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11719, 266},
+ /* 6848 */ {I_VPSHLDW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11728, 266},
+ /* 6849 */ {I_VPSHLDW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11737, 267},
+ /* 6850 */ {I_VPSHLDW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11746, 267},
+ /* 6851 */ {I_VPSHLDD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11755, 266},
+ /* 6852 */ {I_VPSHLDD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11764, 266},
+ /* 6853 */ {I_VPSHLDD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11773, 266},
+ /* 6854 */ {I_VPSHLDD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11782, 266},
+ /* 6855 */ {I_VPSHLDD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11791, 267},
+ /* 6856 */ {I_VPSHLDD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11800, 267},
+ /* 6857 */ {I_VPSHLDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11809, 266},
+ /* 6858 */ {I_VPSHLDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11818, 266},
+ /* 6859 */ {I_VPSHLDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11827, 266},
+ /* 6860 */ {I_VPSHLDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11836, 266},
+ /* 6861 */ {I_VPSHLDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11845, 267},
+ /* 6862 */ {I_VPSHLDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11854, 267},
+ /* 6863 */ {I_VPSHLDVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29304, 266},
+ /* 6864 */ {I_VPSHLDVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29312, 266},
+ /* 6865 */ {I_VPSHLDVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29320, 266},
+ /* 6866 */ {I_VPSHLDVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29328, 266},
+ /* 6867 */ {I_VPSHLDVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29336, 267},
+ /* 6868 */ {I_VPSHLDVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29344, 267},
+ /* 6869 */ {I_VPSHLDVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29352, 266},
+ /* 6870 */ {I_VPSHLDVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29360, 266},
+ /* 6871 */ {I_VPSHLDVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29368, 266},
+ /* 6872 */ {I_VPSHLDVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29376, 266},
+ /* 6873 */ {I_VPSHLDVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29384, 267},
+ /* 6874 */ {I_VPSHLDVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29392, 267},
+ /* 6875 */ {I_VPSHLDVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29400, 266},
+ /* 6876 */ {I_VPSHLDVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29408, 266},
+ /* 6877 */ {I_VPSHLDVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29416, 266},
+ /* 6878 */ {I_VPSHLDVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29424, 266},
+ /* 6879 */ {I_VPSHLDVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29432, 267},
+ /* 6880 */ {I_VPSHLDVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29440, 267},
+ /* 6881 */ {I_VPSHRDW, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11863, 266},
+ /* 6882 */ {I_VPSHRDW, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11872, 266},
+ /* 6883 */ {I_VPSHRDW, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11881, 266},
+ /* 6884 */ {I_VPSHRDW, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11890, 266},
+ /* 6885 */ {I_VPSHRDW, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11899, 267},
+ /* 6886 */ {I_VPSHRDW, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+11908, 267},
+ /* 6887 */ {I_VPSHRDD, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11917, 266},
+ /* 6888 */ {I_VPSHRDD, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11926, 266},
+ /* 6889 */ {I_VPSHRDD, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11935, 266},
+ /* 6890 */ {I_VPSHRDD, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11944, 266},
+ /* 6891 */ {I_VPSHRDD, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+11953, 267},
+ /* 6892 */ {I_VPSHRDD, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+11962, 267},
+ /* 6893 */ {I_VPSHRDQ, 4, {XMMREG,XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11971, 266},
+ /* 6894 */ {I_VPSHRDQ, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11980, 266},
+ /* 6895 */ {I_VPSHRDQ, 4, {YMMREG,YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+11989, 266},
+ /* 6896 */ {I_VPSHRDQ, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+11998, 266},
+ /* 6897 */ {I_VPSHRDQ, 4, {ZMMREG,ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+12007, 267},
+ /* 6898 */ {I_VPSHRDQ, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+12016, 267},
+ /* 6899 */ {I_VPSHRDVW, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29448, 266},
+ /* 6900 */ {I_VPSHRDVW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29456, 266},
+ /* 6901 */ {I_VPSHRDVW, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29464, 266},
+ /* 6902 */ {I_VPSHRDVW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29472, 266},
+ /* 6903 */ {I_VPSHRDVW, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29480, 267},
+ /* 6904 */ {I_VPSHRDVW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29488, 267},
+ /* 6905 */ {I_VPSHRDVD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29496, 266},
+ /* 6906 */ {I_VPSHRDVD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29504, 266},
+ /* 6907 */ {I_VPSHRDVD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29512, 266},
+ /* 6908 */ {I_VPSHRDVD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29520, 266},
+ /* 6909 */ {I_VPSHRDVD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29528, 267},
+ /* 6910 */ {I_VPSHRDVD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29536, 267},
+ /* 6911 */ {I_VPSHRDVQ, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29544, 266},
+ /* 6912 */ {I_VPSHRDVQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29552, 266},
+ /* 6913 */ {I_VPSHRDVQ, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29560, 266},
+ /* 6914 */ {I_VPSHRDVQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29568, 266},
+ /* 6915 */ {I_VPSHRDVQ, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B64,0,0}, nasm_bytecodes+29576, 267},
+ /* 6916 */ {I_VPSHRDVQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+29584, 267},
+ /* 6917 */ {I_VPDPBUSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29592, 268},
+ /* 6918 */ {I_VPDPBUSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29600, 268},
+ /* 6919 */ {I_VPDPBUSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29608, 268},
+ /* 6920 */ {I_VPDPBUSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29616, 268},
+ /* 6921 */ {I_VPDPBUSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29624, 269},
+ /* 6922 */ {I_VPDPBUSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29632, 269},
+ /* 6923 */ {I_VPDPBUSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29640, 268},
+ /* 6924 */ {I_VPDPBUSDS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29648, 268},
+ /* 6925 */ {I_VPDPBUSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29656, 268},
+ /* 6926 */ {I_VPDPBUSDS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29664, 268},
+ /* 6927 */ {I_VPDPBUSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29672, 269},
+ /* 6928 */ {I_VPDPBUSDS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29680, 269},
+ /* 6929 */ {I_VPDPWSSD, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29688, 268},
+ /* 6930 */ {I_VPDPWSSD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29696, 268},
+ /* 6931 */ {I_VPDPWSSD, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29704, 268},
+ /* 6932 */ {I_VPDPWSSD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29712, 268},
+ /* 6933 */ {I_VPDPWSSD, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29720, 269},
+ /* 6934 */ {I_VPDPWSSD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29728, 269},
+ /* 6935 */ {I_VPDPWSSDS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29736, 268},
+ /* 6936 */ {I_VPDPWSSDS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29744, 268},
+ /* 6937 */ {I_VPDPWSSDS, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29752, 268},
+ /* 6938 */ {I_VPDPWSSDS, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29760, 268},
+ /* 6939 */ {I_VPDPWSSDS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+29768, 269},
+ /* 6940 */ {I_VPDPWSSDS, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+29776, 269},
+ /* 6941 */ {I_VPOPCNTB, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29784, 270},
+ /* 6942 */ {I_VPOPCNTB, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29792, 270},
+ /* 6943 */ {I_VPOPCNTB, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29800, 271},
+ /* 6944 */ {I_VPOPCNTW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29808, 270},
+ /* 6945 */ {I_VPOPCNTW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29816, 270},
+ /* 6946 */ {I_VPOPCNTW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29824, 271},
+ /* 6947 */ {I_VPOPCNTD, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29832, 272},
+ /* 6948 */ {I_VPOPCNTD, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29840, 272},
+ /* 6949 */ {I_VPOPCNTD, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29848, 273},
+ /* 6950 */ {I_VPOPCNTQ, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29856, 272},
+ /* 6951 */ {I_VPOPCNTQ, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29864, 272},
+ /* 6952 */ {I_VPOPCNTQ, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29872, 273},
+ /* 6953 */ {I_VPSHUFBITQMB, 3, {KREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29880, 270},
+ /* 6954 */ {I_VPSHUFBITQMB, 3, {KREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29888, 270},
+ /* 6955 */ {I_VPSHUFBITQMB, 3, {KREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+29896, 271},
+ /* 6956 */ {I_V4FMADDPS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29904, 274},
+ /* 6957 */ {I_V4FNMADDPS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29912, 274},
+ /* 6958 */ {I_V4FMADDSS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29920, 274},
+ /* 6959 */ {I_V4FNMADDSS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29928, 274},
+ /* 6960 */ {I_V4DPWSSDS, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29936, 275},
+ /* 6961 */ {I_V4DPWSSD, 3, {ZMM_L16,ZMM_L16|RS4,MEMORY,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+29944, 275},
+ /* 6962 */ {I_ENCLS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46005, 276},
+ /* 6963 */ {I_ENCLU, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46011, 276},
+ /* 6964 */ {I_ENCLV, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46017, 276},
+ /* 6965 */ {I_CLRSSBSY, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42350, 277},
+ /* 6966 */ {I_ENDBR32, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46023, 277},
+ /* 6967 */ {I_ENDBR64, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46029, 277},
+ /* 6968 */ {I_INCSSPD, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42391, 277},
+ /* 6969 */ {I_INCSSPQ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42398, 278},
+ /* 6970 */ {I_RDSSPD, 1, {REG_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42405, 277},
+ /* 6971 */ {I_RDSSPQ, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42412, 278},
+ /* 6972 */ {I_RSTORSSP, 1, {MEMORY|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46035, 277},
+ /* 6973 */ {I_SAVEPREVSSP, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46041, 277},
+ /* 6974 */ {I_SETSSBSY, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46047, 277},
+ /* 6975 */ {I_WRUSSD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+29952, 277},
+ /* 6976 */ {I_WRUSSQ, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+29960, 278},
+ /* 6977 */ {I_WRSSD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+42419, 277},
+ /* 6978 */ {I_WRSSQ, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+42426, 278},
+ /* 6979 */ {I_ENQCMD, 2, {REG_GPR|BITS16,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29968, 279},
+ /* 6980 */ {I_ENQCMD, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29976, 280},
+ /* 6981 */ {I_ENQCMD, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29984, 281},
+ /* 6982 */ {I_ENQCMDS, 2, {REG_GPR|BITS16,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+29992, 282},
+ /* 6983 */ {I_ENQCMDS, 2, {REG_GPR|BITS32,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+30000, 283},
+ /* 6984 */ {I_ENQCMDS, 2, {REG_GPR|BITS64,MEMORY|BITS512,0,0,0}, NO_DECORATOR, nasm_bytecodes+30008, 284},
+ /* 6985 */ {I_PCONFIG, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+45993, 285},
+ /* 6986 */ {I_SERIALIZE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46053, 286},
+ /* 6987 */ {I_WBNOINVD, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+49182, 287},
+ /* 6988 */ {I_XRESLDTRK, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46059, 288},
+ /* 6989 */ {I_XSUSLDTRK, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46065, 288},
+ /* 6990 */ {I_VCVTNE2PS2BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30016, 289},
+ /* 6991 */ {I_VCVTNE2PS2BF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30024, 289},
+ /* 6992 */ {I_VCVTNE2PS2BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30032, 289},
+ /* 6993 */ {I_VCVTNE2PS2BF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30040, 289},
+ /* 6994 */ {I_VCVTNE2PS2BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30048, 289},
+ /* 6995 */ {I_VCVTNE2PS2BF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30056, 289},
+ /* 6996 */ {I_VCVTNEPS2BF16, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30064, 289},
+ /* 6997 */ {I_VCVTNEPS2BF16, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30072, 289},
+ /* 6998 */ {I_VCVTNEPS2BF16, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30080, 289},
+ /* 6999 */ {I_VCVTNEPS2BF16, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30088, 289},
+ /* 7000 */ {I_VCVTNEPS2BF16, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30096, 289},
+ /* 7001 */ {I_VCVTNEPS2BF16, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30104, 289},
+ /* 7002 */ {I_VDPBF16PS, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30112, 289},
+ /* 7003 */ {I_VDPBF16PS, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30120, 289},
+ /* 7004 */ {I_VDPBF16PS, 3, {YMMREG,YMMREG,RM_YMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30128, 289},
+ /* 7005 */ {I_VDPBF16PS, 2, {YMMREG,RM_YMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30136, 289},
+ /* 7006 */ {I_VDPBF16PS, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+30144, 289},
+ /* 7007 */ {I_VDPBF16PS, 2, {ZMMREG,RM_ZMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30152, 289},
+ /* 7008 */ {I_VP2INTERSECTD, 3, {KREG|RS2,XMMREG,RM_XMM|BITS128,0,0}, {0,0,B32,0,0}, nasm_bytecodes+30160, 289},
+ /* 7009 */ {I_VP2INTERSECTD, 3, {KREG|RS2,YMMREG,RM_YMM|BITS128,0,0}, {0,0,B32,0,0}, nasm_bytecodes+30168, 289},
+ /* 7010 */ {I_VP2INTERSECTD, 3, {KREG|RS2,ZMMREG,RM_ZMM|BITS128,0,0}, {0,0,B32,0,0}, nasm_bytecodes+30176, 289},
+ /* 7011 */ {I_LDTILECFG, 1, {MEMORY|BITS512,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42433, 290},
+ /* 7012 */ {I_STTILECFG, 1, {MEMORY|BITS512,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42440, 290},
+ /* 7013 */ {I_TDPBF16PS, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42447, 291},
+ /* 7014 */ {I_TDPBSSD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42454, 292},
+ /* 7015 */ {I_TDPBSUD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42461, 292},
+ /* 7016 */ {I_TDPBUSD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42468, 292},
+ /* 7017 */ {I_TDPBUUD, 3, {TMMREG,TMMREG,TMMREG,0,0}, NO_DECORATOR, nasm_bytecodes+42475, 292},
+ /* 7018 */ {I_TILELOADD, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42482, 293},
+ /* 7019 */ {I_TILELOADDT1, 2, {TMMREG,MEMORY,0,0,0}, NO_DECORATOR, nasm_bytecodes+42489, 293},
+ /* 7020 */ {I_TILERELEASE, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42496, 294},
+ /* 7021 */ {I_TILESTORED, 2, {MEMORY,TMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+42503, 293},
+ /* 7022 */ {I_TILEZERO, 1, {TMMREG,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+30184, 294},
+ /* 7023 */ {I_VADDPH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30192, 295},
+ /* 7024 */ {I_VADDPH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30200, 295},
+ /* 7025 */ {I_VADDPH, 3, {YMMREG,YMMREG,RM_YMM|BITS16,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30208, 295},
+ /* 7026 */ {I_VADDPH, 2, {YMMREG,RM_YMM|BITS16,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30216, 295},
+ /* 7027 */ {I_VADDPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS16,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+30224, 296},
+ /* 7028 */ {I_VADDPH, 2, {ZMMREG,RM_ZMM|BITS16,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30232, 296},
+ /* 7029 */ {I_VADDSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+30240, 296},
+ /* 7030 */ {I_VADDSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+30248, 296},
+ /* 7031 */ {I_VCMPPH, 4, {KREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+12025, 295},
+ /* 7032 */ {I_VCMPPH, 3, {KREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12034, 295},
+ /* 7033 */ {I_VCMPPH, 4, {KREG,YMMREG,RM_YMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,B16,0,0}, nasm_bytecodes+12043, 295},
+ /* 7034 */ {I_VCMPPH, 3, {KREG,RM_YMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12052, 295},
+ /* 7035 */ {I_VCMPPH, 4, {KREG,ZMMREG,RM_ZMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,B16|SAE,0,0}, nasm_bytecodes+12061, 296},
+ /* 7036 */ {I_VCMPPH, 3, {KREG,RM_ZMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,B16|SAE,0,0,0}, nasm_bytecodes+12070, 296},
+ /* 7037 */ {I_VCMPSH, 4, {KREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK,0,SAE,0,0}, nasm_bytecodes+12079, 296},
+ /* 7038 */ {I_VCMPSH, 3, {KREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+12088, 296},
+ /* 7039 */ {I_VCOMISH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30256, 296},
+ /* 7040 */ {I_VCVTDQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30264, 295},
+ /* 7041 */ {I_VCVTDQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30272, 295},
+ /* 7042 */ {I_VCVTDQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+30280, 296},
+ /* 7043 */ {I_VCVTPD2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30288, 295},
+ /* 7044 */ {I_VCVTPD2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30296, 295},
+ /* 7045 */ {I_VCVTPD2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+30304, 296},
+ /* 7046 */ {I_VCVTPH2DQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30312, 295},
+ /* 7047 */ {I_VCVTPH2DQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30320, 295},
+ /* 7048 */ {I_VCVTPH2DQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30328, 296},
+ /* 7049 */ {I_VCVTPH2PD, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30336, 295},
+ /* 7050 */ {I_VCVTPH2PD, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30344, 295},
+ /* 7051 */ {I_VCVTPH2PD, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30352, 296},
+ /* 7052 */ {I_VCVTPH2PS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+39108, 297},
+ /* 7053 */ {I_VCVTPH2PS, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, NO_DECORATOR, nasm_bytecodes+39101, 297},
+ /* 7054 */ {I_VCVTPH2PS, 2, {XMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17240, 240},
+ /* 7055 */ {I_VCVTPH2PS, 2, {YMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+17248, 240},
+ /* 7056 */ {I_VCVTPH2PS, 2, {ZMM_L16,RM_YMM_L16|BITS256,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+17256, 241},
+ /* 7057 */ {I_VCVTPH2PSX, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30360, 295},
+ /* 7058 */ {I_VCVTPH2PSX, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30368, 295},
+ /* 7059 */ {I_VCVTPH2PSX, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30376, 296},
+ /* 7060 */ {I_VCVTPH2QQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30384, 295},
+ /* 7061 */ {I_VCVTPH2QQ, 2, {YMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30392, 295},
+ /* 7062 */ {I_VCVTPH2QQ, 2, {ZMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30400, 296},
+ /* 7063 */ {I_VCVTPH2UDQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30408, 295},
+ /* 7064 */ {I_VCVTPH2UDQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30416, 295},
+ /* 7065 */ {I_VCVTPH2UDQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30424, 296},
+ /* 7066 */ {I_VCVTPH2UQQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30432, 295},
+ /* 7067 */ {I_VCVTPH2UQQ, 2, {YMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30440, 295},
+ /* 7068 */ {I_VCVTPH2UQQ, 2, {ZMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30448, 296},
+ /* 7069 */ {I_VCVTPH2UW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30456, 295},
+ /* 7070 */ {I_VCVTPH2UW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30464, 295},
+ /* 7071 */ {I_VCVTPH2UW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30472, 296},
+ /* 7072 */ {I_VCVTPH2W, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30480, 295},
+ /* 7073 */ {I_VCVTPH2W, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30488, 295},
+ /* 7074 */ {I_VCVTPH2W, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30496, 296},
+ /* 7075 */ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS64,XMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14232, 298},
+ /* 7076 */ {I_VCVTPS2PH, 3, {RM_XMM_L16|BITS128,YMM_L16,IMMEDIATE|BITS8,0,0}, NO_DECORATOR, nasm_bytecodes+14224, 298},
+ /* 7077 */ {I_VCVTPS2PH, 3, {XMMREG,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8182, 240},
+ /* 7078 */ {I_VCVTPS2PH, 3, {MEMORY|BITS64,XMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8182, 240},
+ /* 7079 */ {I_VCVTPS2PH, 3, {XMMREG,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+8191, 240},
+ /* 7080 */ {I_VCVTPS2PH, 3, {MEMORY|BITS128,YMMREG,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+8191, 240},
+ /* 7081 */ {I_VCVTPS2PH, 3, {YMMREG,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ /* 7082 */ {I_VCVTPS2PH, 3, {MEMORY|BITS256,ZMMREG,IMMEDIATE|BITS8,0,0}, {MASK,SAE,0,0,0}, nasm_bytecodes+8200, 241},
+ /* 7083 */ {I_VCVTPS2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30504, 295},
+ /* 7084 */ {I_VCVTPS2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30512, 295},
+ /* 7085 */ {I_VCVTPS2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+30520, 296},
+ /* 7086 */ {I_VCVTQQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30528, 295},
+ /* 7087 */ {I_VCVTQQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B64,0,0,0}, nasm_bytecodes+30536, 295},
+ /* 7088 */ {I_VCVTQQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B64|ER,0,0,0}, nasm_bytecodes+30544, 295},
+ /* 7089 */ {I_VCVTSD2SH, 3, {XMMREG,XMMREG,RM_XMM|BITS64,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+30552, 296},
+ /* 7090 */ {I_VCVTSD2SH, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+30560, 296},
+ /* 7091 */ {I_VCVTSH2SD, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {0,0,SAE,0,0}, nasm_bytecodes+30568, 296},
+ /* 7092 */ {I_VCVTSH2SD, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30576, 296},
+ /* 7093 */ {I_VCVTSH2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30584, 296},
+ /* 7094 */ {I_VCVTSH2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30592, 296},
+ /* 7095 */ {I_VCVTSH2SS, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+30600, 296},
+ /* 7096 */ {I_VCVTSH2SS, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+30608, 296},
+ /* 7097 */ {I_VCVTSH2USI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30616, 296},
+ /* 7098 */ {I_VCVTSH2USI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30624, 296},
+ /* 7099 */ {I_VCVTSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,0,ER,0,0}, nasm_bytecodes+30632, 296},
+ /* 7100 */ {I_VCVTSI2SH, 2, {XMMREG,RM_GPR|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30640, 296},
+ /* 7101 */ {I_VCVTSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,0,ER,0,0}, nasm_bytecodes+30648, 296},
+ /* 7102 */ {I_VCVTSI2SH, 2, {XMMREG,RM_GPR|BITS64,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30656, 296},
+ /* 7103 */ {I_VCVTSS2SH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {0,0,ER,0,0}, nasm_bytecodes+30664, 296},
+ /* 7104 */ {I_VCVTSS2SH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {0,ER,0,0,0}, nasm_bytecodes+30672, 296},
+ /* 7105 */ {I_VCVTTPH2DQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30680, 295},
+ /* 7106 */ {I_VCVTTPH2DQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30688, 295},
+ /* 7107 */ {I_VCVTTPH2DQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30696, 296},
+ /* 7108 */ {I_VCVTTPH2QQ, 2, {XMM_L16,RM_XMM_L16|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30704, 295},
+ /* 7109 */ {I_VCVTTPH2QQ, 2, {YMM_L16,RM_XMM_L16|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30712, 295},
+ /* 7110 */ {I_VCVTTPH2QQ, 2, {ZMM_L16,RM_XMM_L16|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30720, 296},
+ /* 7111 */ {I_VCVTTPH2UDQ, 2, {XMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30728, 295},
+ /* 7112 */ {I_VCVTTPH2UDQ, 2, {YMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30736, 295},
+ /* 7113 */ {I_VCVTTPH2UDQ, 2, {ZMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30744, 296},
+ /* 7114 */ {I_VCVTTPH2UQQ, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30752, 295},
+ /* 7115 */ {I_VCVTTPH2UQQ, 2, {YMMREG,RM_XMM|BITS64,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30760, 295},
+ /* 7116 */ {I_VCVTTPH2UQQ, 2, {ZMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30768, 296},
+ /* 7117 */ {I_VCVTTPH2UW, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30776, 295},
+ /* 7118 */ {I_VCVTTPH2UW, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30784, 295},
+ /* 7119 */ {I_VCVTTPH2UW, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30792, 296},
+ /* 7120 */ {I_VCVTTPH2W, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30800, 295},
+ /* 7121 */ {I_VCVTTPH2W, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30808, 295},
+ /* 7122 */ {I_VCVTTPH2W, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+30816, 296},
+ /* 7123 */ {I_VCVTTSH2SI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30824, 296},
+ /* 7124 */ {I_VCVTTSH2SI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30832, 296},
+ /* 7125 */ {I_VCVTTSH2USI, 2, {REG_GPR|BITS32,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30840, 296},
+ /* 7126 */ {I_VCVTTSH2USI, 2, {REG_GPR|BITS64,RM_XMM_L16|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+30848, 296},
+ /* 7127 */ {I_VCVTUDQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30856, 295},
+ /* 7128 */ {I_VCVTUDQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30864, 295},
+ /* 7129 */ {I_VCVTUDQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30872, 296},
+ /* 7130 */ {I_VCVTUQQ2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30880, 295},
+ /* 7131 */ {I_VCVTUQQ2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30888, 295},
+ /* 7132 */ {I_VCVTUQQ2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+30896, 296},
+ /* 7133 */ {I_VCVTUSI2SH, 3, {XMMREG,XMMREG,RM_GPR|BITS32,0,0}, {0,ER,ER,0,0}, nasm_bytecodes+30904, 296},
+ /* 7134 */ {I_VCVTUSI2SS, 3, {XMMREG,XMMREG,RM_GPR|BITS64,0,0}, {0,ER,ER,0,0}, nasm_bytecodes+30912, 296},
+ /* 7135 */ {I_VCVTUW2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30920, 295},
+ /* 7136 */ {I_VCVTUW2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30928, 295},
+ /* 7137 */ {I_VCVTUW2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30936, 296},
+ /* 7138 */ {I_VCVTW2PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30944, 295},
+ /* 7139 */ {I_VCVTW2PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30952, 295},
+ /* 7140 */ {I_VCVTW2PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+30960, 296},
+ /* 7141 */ {I_VDIVPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30968, 295},
+ /* 7142 */ {I_VDIVPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30976, 295},
+ /* 7143 */ {I_VDIVPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+30984, 295},
+ /* 7144 */ {I_VDIVPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+30992, 295},
+ /* 7145 */ {I_VDIVPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31000, 296},
+ /* 7146 */ {I_VDIVPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31008, 296},
+ /* 7147 */ {I_VDIVSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31016, 296},
+ /* 7148 */ {I_VDIVSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31024, 296},
+ /* 7149 */ {I_VFCMADDCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31032, 295},
+ /* 7150 */ {I_VFCMADDCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31040, 295},
+ /* 7151 */ {I_VFCMADDCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31048, 295},
+ /* 7152 */ {I_VFCMADDCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31056, 295},
+ /* 7153 */ {I_VFCMADDCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31064, 295},
+ /* 7154 */ {I_VFCMADDCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31072, 295},
+ /* 7155 */ {I_VFMADDCPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31080, 295},
+ /* 7156 */ {I_VFMADDCPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31088, 295},
+ /* 7157 */ {I_VFMADDCPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31096, 295},
+ /* 7158 */ {I_VFMADDCPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31104, 295},
+ /* 7159 */ {I_VFMADDCPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31112, 295},
+ /* 7160 */ {I_VFMADDCPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31120, 295},
+ /* 7161 */ {I_VFCMADDCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31128, 296},
+ /* 7162 */ {I_VFCMADDCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31136, 296},
+ /* 7163 */ {I_VFMADDCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31144, 296},
+ /* 7164 */ {I_VFMADDCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31152, 296},
+ /* 7165 */ {I_VFCMULCPCH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31160, 295},
+ /* 7166 */ {I_VFCMULCPCH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31168, 295},
+ /* 7167 */ {I_VFCMULCPCH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31176, 295},
+ /* 7168 */ {I_VFCMULCPCH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31184, 295},
+ /* 7169 */ {I_VFCMULCPCH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31192, 295},
+ /* 7170 */ {I_VFCMULCPCH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31200, 295},
+ /* 7171 */ {I_VFMULCPCH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31208, 295},
+ /* 7172 */ {I_VFMULCPCH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31216, 295},
+ /* 7173 */ {I_VFMULCPCH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B32,0,0}, nasm_bytecodes+31224, 295},
+ /* 7174 */ {I_VFMULCPCH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B32,0,0,0}, nasm_bytecodes+31232, 295},
+ /* 7175 */ {I_VFMULCPCH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B32|ER,0,0}, nasm_bytecodes+31240, 295},
+ /* 7176 */ {I_VFMULCPCH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B32|ER,0,0,0}, nasm_bytecodes+31248, 295},
+ /* 7177 */ {I_VFCMULCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31256, 296},
+ /* 7178 */ {I_VFCMULCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31264, 296},
+ /* 7179 */ {I_VFMULCSH, 3, {XMMREG,XMMREG,RM_XMM|BITS32,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31272, 296},
+ /* 7180 */ {I_VFMULCSH, 2, {XMMREG,RM_XMM|BITS32,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31280, 296},
+ /* 7181 */ {I_VFMADDSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31288, 295},
+ /* 7182 */ {I_VFMADDSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31296, 295},
+ /* 7183 */ {I_VFMADDSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31304, 295},
+ /* 7184 */ {I_VFMADDSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31312, 295},
+ /* 7185 */ {I_VFMADDSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31320, 296},
+ /* 7186 */ {I_VFMADDSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31328, 296},
+ /* 7187 */ {I_VFMADDSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31336, 295},
+ /* 7188 */ {I_VFMADDSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31344, 295},
+ /* 7189 */ {I_VFMADDSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31352, 295},
+ /* 7190 */ {I_VFMADDSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31360, 295},
+ /* 7191 */ {I_VFMADDSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31368, 296},
+ /* 7192 */ {I_VFMADDSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31376, 296},
+ /* 7193 */ {I_VFMADDSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31384, 295},
+ /* 7194 */ {I_VFMADDSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31392, 295},
+ /* 7195 */ {I_VFMADDSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31400, 295},
+ /* 7196 */ {I_VFMADDSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31408, 295},
+ /* 7197 */ {I_VFMADDSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31416, 296},
+ /* 7198 */ {I_VFMADDSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31424, 296},
+ /* 7199 */ {I_VFMSUBADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31432, 295},
+ /* 7200 */ {I_VFMSUBADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31440, 295},
+ /* 7201 */ {I_VFMSUBADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31448, 295},
+ /* 7202 */ {I_VFMSUBADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31456, 295},
+ /* 7203 */ {I_VFMSUBADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31464, 296},
+ /* 7204 */ {I_VFMSUBADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31472, 296},
+ /* 7205 */ {I_VFMSUBADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31480, 295},
+ /* 7206 */ {I_VFMSUBADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31488, 295},
+ /* 7207 */ {I_VFMSUBADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31496, 295},
+ /* 7208 */ {I_VFMSUBADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31504, 295},
+ /* 7209 */ {I_VFMSUBADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31512, 296},
+ /* 7210 */ {I_VFMSUBADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31520, 296},
+ /* 7211 */ {I_VFMSUBADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31528, 295},
+ /* 7212 */ {I_VFMSUBADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31536, 295},
+ /* 7213 */ {I_VFMSUBADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31544, 295},
+ /* 7214 */ {I_VFMSUBADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31552, 295},
+ /* 7215 */ {I_VFMSUBADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31560, 296},
+ /* 7216 */ {I_VFMSUBADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31568, 296},
+ /* 7217 */ {I_VPMADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31576, 295},
+ /* 7218 */ {I_VPMADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31584, 295},
+ /* 7219 */ {I_VPMADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31592, 295},
+ /* 7220 */ {I_VPMADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31600, 295},
+ /* 7221 */ {I_VPMADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31608, 296},
+ /* 7222 */ {I_VPMADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31616, 296},
+ /* 7223 */ {I_VPMADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31624, 295},
+ /* 7224 */ {I_VPMADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31632, 295},
+ /* 7225 */ {I_VPMADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31640, 295},
+ /* 7226 */ {I_VPMADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31648, 295},
+ /* 7227 */ {I_VPMADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31656, 296},
+ /* 7228 */ {I_VPMADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31664, 296},
+ /* 7229 */ {I_VPMADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31672, 295},
+ /* 7230 */ {I_VPMADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31680, 295},
+ /* 7231 */ {I_VPMADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31688, 295},
+ /* 7232 */ {I_VPMADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31696, 295},
+ /* 7233 */ {I_VPMADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31704, 296},
+ /* 7234 */ {I_VPMADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31712, 296},
+ /* 7235 */ {I_VFMADD132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31720, 295},
+ /* 7236 */ {I_VFMADD132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31728, 295},
+ /* 7237 */ {I_VFMADD132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31736, 295},
+ /* 7238 */ {I_VFMADD132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31744, 295},
+ /* 7239 */ {I_VFMADD132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31752, 296},
+ /* 7240 */ {I_VFMADD132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31760, 296},
+ /* 7241 */ {I_VFMADD213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31768, 295},
+ /* 7242 */ {I_VFMADD213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31776, 295},
+ /* 7243 */ {I_VFMADD213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31784, 295},
+ /* 7244 */ {I_VFMADD213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31792, 295},
+ /* 7245 */ {I_VFMADD213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31800, 296},
+ /* 7246 */ {I_VFMADD213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31808, 296},
+ /* 7247 */ {I_VFMADD231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31816, 295},
+ /* 7248 */ {I_VFMADD231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31824, 295},
+ /* 7249 */ {I_VFMADD231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31832, 295},
+ /* 7250 */ {I_VFMADD231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31840, 295},
+ /* 7251 */ {I_VFMADD231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31848, 296},
+ /* 7252 */ {I_VFMADD231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+31856, 296},
+ /* 7253 */ {I_VPMADD132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31864, 296},
+ /* 7254 */ {I_VPMADD132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31872, 296},
+ /* 7255 */ {I_VPMADD213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31880, 296},
+ /* 7256 */ {I_VPMADD213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31888, 296},
+ /* 7257 */ {I_VPMADD231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31896, 296},
+ /* 7258 */ {I_VPMADD231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31904, 296},
+ /* 7259 */ {I_VPNMADD132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31912, 296},
+ /* 7260 */ {I_VPNMADD132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31920, 296},
+ /* 7261 */ {I_VPNMADD213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31928, 296},
+ /* 7262 */ {I_VPNMADD213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31936, 296},
+ /* 7263 */ {I_VPNMADD231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+31944, 296},
+ /* 7264 */ {I_VPNMADD231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+31952, 296},
+ /* 7265 */ {I_VPMSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31960, 295},
+ /* 7266 */ {I_VPMSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31968, 295},
+ /* 7267 */ {I_VPMSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+31976, 295},
+ /* 7268 */ {I_VPMSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+31984, 295},
+ /* 7269 */ {I_VPMSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+31992, 296},
+ /* 7270 */ {I_VPMSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32000, 296},
+ /* 7271 */ {I_VPMSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32008, 295},
+ /* 7272 */ {I_VPMSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32016, 295},
+ /* 7273 */ {I_VPMSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32024, 295},
+ /* 7274 */ {I_VPMSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32032, 295},
+ /* 7275 */ {I_VPMSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32040, 296},
+ /* 7276 */ {I_VPMSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32048, 296},
+ /* 7277 */ {I_VPMSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32056, 295},
+ /* 7278 */ {I_VPMSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32064, 295},
+ /* 7279 */ {I_VPMSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32072, 295},
+ /* 7280 */ {I_VPMSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32080, 295},
+ /* 7281 */ {I_VPMSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32088, 296},
+ /* 7282 */ {I_VPMSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32096, 296},
+ /* 7283 */ {I_VFMSUB132PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32104, 295},
+ /* 7284 */ {I_VFMSUB132PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32112, 295},
+ /* 7285 */ {I_VFMSUB132PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32120, 295},
+ /* 7286 */ {I_VFMSUB132PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32128, 295},
+ /* 7287 */ {I_VFMSUB132PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32136, 296},
+ /* 7288 */ {I_VFMSUB132PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32144, 296},
+ /* 7289 */ {I_VFMSUB213PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32152, 295},
+ /* 7290 */ {I_VFMSUB213PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32160, 295},
+ /* 7291 */ {I_VFMSUB213PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32168, 295},
+ /* 7292 */ {I_VFMSUB213PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32176, 295},
+ /* 7293 */ {I_VFMSUB213PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32184, 296},
+ /* 7294 */ {I_VFMSUB213PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32192, 296},
+ /* 7295 */ {I_VFMSUB231PH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32200, 295},
+ /* 7296 */ {I_VFMSUB231PH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32208, 295},
+ /* 7297 */ {I_VFMSUB231PH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32216, 295},
+ /* 7298 */ {I_VFMSUB231PH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32224, 295},
+ /* 7299 */ {I_VFMSUB231PH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32232, 296},
+ /* 7300 */ {I_VFMSUB231PH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32240, 296},
+ /* 7301 */ {I_VPMSUB132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32248, 296},
+ /* 7302 */ {I_VPMSUB132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32256, 296},
+ /* 7303 */ {I_VPMSUB213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32264, 296},
+ /* 7304 */ {I_VPMSUB213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32272, 296},
+ /* 7305 */ {I_VPMSUB231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32280, 296},
+ /* 7306 */ {I_VPMSUB231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32288, 296},
+ /* 7307 */ {I_VPNMSUB132SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32296, 296},
+ /* 7308 */ {I_VPNMSUB132SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32304, 296},
+ /* 7309 */ {I_VPNMSUB213SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32312, 296},
+ /* 7310 */ {I_VPNMSUB213SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32320, 296},
+ /* 7311 */ {I_VPNMSUB231SH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32328, 296},
+ /* 7312 */ {I_VPNMSUB231SH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32336, 296},
+ /* 7313 */ {I_VFPCLASSPH, 3, {KREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12097, 295},
+ /* 7314 */ {I_VFPCLASSPH, 3, {KREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12106, 295},
+ /* 7315 */ {I_VFPCLASSPH, 3, {KREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK,B16,0,0,0}, nasm_bytecodes+12115, 296},
+ /* 7316 */ {I_VFPCLASSSH, 3, {KREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+12124, 296},
+ /* 7317 */ {I_VGETEXPPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32344, 295},
+ /* 7318 */ {I_VGETEXPPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32352, 295},
+ /* 7319 */ {I_VGETEXPPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+32360, 296},
+ /* 7320 */ {I_VGETEXPSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32368, 296},
+ /* 7321 */ {I_VGETMANTPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12133, 295},
+ /* 7322 */ {I_VGETMANTPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12142, 295},
+ /* 7323 */ {I_VGETMANTPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12151, 296},
+ /* 7324 */ {I_VGETMANTSH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12160, 296},
+ /* 7325 */ {I_VGETMAXPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32376, 295},
+ /* 7326 */ {I_VGETMAXPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32384, 295},
+ /* 7327 */ {I_VGETMAXPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+32392, 296},
+ /* 7328 */ {I_VGETMAXSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32400, 296},
+ /* 7329 */ {I_VGETMINPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32408, 295},
+ /* 7330 */ {I_VGETMINPH, 2, {YMMREG,RM_XMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32416, 295},
+ /* 7331 */ {I_VGETMINPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+32424, 296},
+ /* 7332 */ {I_VGETMINSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32432, 296},
+ /* 7333 */ {I_VMOVSH, 2, {XMMREG,MEMORY|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32440, 296},
+ /* 7334 */ {I_VMOVSH, 2, {MEMORY|BITS16,XMMREG,0,0,0}, {MASK,0,0,0,0}, nasm_bytecodes+32448, 296},
+ /* 7335 */ {I_VMOVSH, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32456, 296},
+ /* 7336 */ {I_VMOVSH, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32464, 296},
+ /* 7337 */ {I_VMOVSH, 3, {XMMREG,XMMREG,XMMREG,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32472, 296},
+ /* 7338 */ {I_VMOVSH, 2, {XMMREG,XMMREG,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32480, 296},
+ /* 7339 */ {I_VMOVW, 2, {XMMREG,RM_GPR|BITS16,0,0,0}, {MASK|Z,0,0,0,0}, nasm_bytecodes+32488, 296},
+ /* 7340 */ {I_VMOVW, 2, {RM_GPR|BITS16,XMMREG,0,0,0}, NO_DECORATOR, nasm_bytecodes+32496, 296},
+ /* 7341 */ {I_VMULPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32504, 295},
+ /* 7342 */ {I_VMULPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32512, 295},
+ /* 7343 */ {I_VMULPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32520, 295},
+ /* 7344 */ {I_VMULPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32528, 295},
+ /* 7345 */ {I_VMULPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32536, 296},
+ /* 7346 */ {I_VMULPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32544, 296},
+ /* 7347 */ {I_VMULSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32552, 296},
+ /* 7348 */ {I_VMULSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32560, 296},
+ /* 7349 */ {I_VRCPPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32568, 295},
+ /* 7350 */ {I_VRCPPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32576, 295},
+ /* 7351 */ {I_VRCPPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32584, 295},
+ /* 7352 */ {I_VRCPPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32592, 295},
+ /* 7353 */ {I_VRCPPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32600, 296},
+ /* 7354 */ {I_VRCPPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32608, 296},
+ /* 7355 */ {I_VRCPSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+32616, 296},
+ /* 7356 */ {I_VRCPSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+32624, 296},
+ /* 7357 */ {I_VREDUCEPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12169, 295},
+ /* 7358 */ {I_VREDUCEPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12178, 295},
+ /* 7359 */ {I_VREDUCEPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12187, 296},
+ /* 7360 */ {I_VREDUCESH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+12196, 296},
+ /* 7361 */ {I_VREDUCESH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12205, 296},
+ /* 7362 */ {I_VENDSCALEPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12214, 295},
+ /* 7363 */ {I_VENDSCALEPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12223, 295},
+ /* 7364 */ {I_VENDSCALEPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12232, 296},
+ /* 7365 */ {I_VENDSCALESH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+12241, 296},
+ /* 7366 */ {I_VENDSCALESH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12250, 296},
+ /* 7367 */ {I_VRSQRTPH, 3, {XMMREG,RM_XMM|BITS128,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12259, 295},
+ /* 7368 */ {I_VRSQRTPH, 3, {YMMREG,RM_YMM|BITS256,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+12268, 295},
+ /* 7369 */ {I_VRSQRTPH, 3, {ZMMREG,RM_ZMM|BITS512,IMMEDIATE|BITS8,0,0}, {MASK|Z,B16|SAE,0,0,0}, nasm_bytecodes+12277, 296},
+ /* 7370 */ {I_VRSQRTSH, 4, {XMMREG,XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0}, {MASK|Z,0,SAE,0,0}, nasm_bytecodes+12286, 296},
+ /* 7371 */ {I_VRSQRTSH, 3, {XMMREG,RM_XMM|BITS16,IMMEDIATE|BITS8,0,0}, {MASK|Z,SAE,0,0,0}, nasm_bytecodes+12295, 296},
+ /* 7372 */ {I_VSCALEFPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32632, 295},
+ /* 7373 */ {I_VSCALEFPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32640, 295},
+ /* 7374 */ {I_VSCALEFPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32648, 295},
+ /* 7375 */ {I_VSCALEFPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32656, 295},
+ /* 7376 */ {I_VSCALEFPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32664, 296},
+ /* 7377 */ {I_VSCALEFPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32672, 296},
+ /* 7378 */ {I_VSCALEFSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32680, 296},
+ /* 7379 */ {I_VSCALEFSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32688, 296},
+ /* 7380 */ {I_VSQRTPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32696, 295},
+ /* 7381 */ {I_VSQRTPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32704, 295},
+ /* 7382 */ {I_VSQRTPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32712, 296},
+ /* 7383 */ {I_VSQRTSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32720, 296},
+ /* 7384 */ {I_VSQRTSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32728, 296},
+ /* 7385 */ {I_VSUBPH, 3, {XMMREG,XMMREG,RM_XMM|BITS128,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32736, 295},
+ /* 7386 */ {I_VSUBPH, 2, {XMMREG,RM_XMM|BITS128,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32744, 295},
+ /* 7387 */ {I_VSUBPH, 3, {YMMREG,YMMREG,RM_YMM|BITS256,0,0}, {MASK|Z,0,B16,0,0}, nasm_bytecodes+32752, 295},
+ /* 7388 */ {I_VSUBPH, 2, {YMMREG,RM_YMM|BITS256,0,0,0}, {MASK|Z,B16,0,0,0}, nasm_bytecodes+32760, 295},
+ /* 7389 */ {I_VSUBPH, 3, {ZMMREG,ZMMREG,RM_ZMM|BITS512,0,0}, {MASK|Z,0,B16|ER,0,0}, nasm_bytecodes+32768, 296},
+ /* 7390 */ {I_VSUBPH, 2, {ZMMREG,RM_ZMM|BITS512,0,0,0}, {MASK|Z,B16|ER,0,0,0}, nasm_bytecodes+32776, 296},
+ /* 7391 */ {I_VSUBSH, 3, {XMMREG,XMMREG,RM_XMM|BITS16,0,0}, {MASK|Z,0,ER,0,0}, nasm_bytecodes+32784, 296},
+ /* 7392 */ {I_VSUBSH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {MASK|Z,ER,0,0,0}, nasm_bytecodes+32792, 296},
+ /* 7393 */ {I_VUCOMISH, 2, {XMMREG,RM_XMM|BITS16,0,0,0}, {0,SAE,0,0,0}, nasm_bytecodes+32800, 296},
+ /* 7394 */ {I_AADD, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32808, 299},
+ /* 7395 */ {I_AADD, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+32816, 300},
+ /* 7396 */ {I_AAND, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32824, 299},
+ /* 7397 */ {I_AAND, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+32832, 300},
+ /* 7398 */ {I_AXOR, 2, {MEMORY|BITS32,REG_GPR|BITS32,0,0,0}, NO_DECORATOR, nasm_bytecodes+32840, 299},
+ /* 7399 */ {I_AXOR, 2, {MEMORY|BITS64,REG_GPR|BITS64,0,0,0}, NO_DECORATOR, nasm_bytecodes+32848, 300},
+ /* 7400 */ {I_CLUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46071, 301},
+ /* 7401 */ {I_SENDUIPI, 1, {REG_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+42510, 301},
+ /* 7402 */ {I_STUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46077, 301},
+ /* 7403 */ {I_TESTUI, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46083, 301},
+ /* 7404 */ {I_UIRET, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46089, 301},
+ /* 7405 */ {I_CMPAXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42517, 302},
+ /* 7406 */ {I_CMPCXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42531, 302},
+ /* 7407 */ {I_CMPGXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42552, 302},
+ /* 7408 */ {I_CMPLXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42566, 302},
+ /* 7409 */ {I_CMPNAXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42538, 302},
+ /* 7410 */ {I_CMPNCXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42524, 302},
+ /* 7411 */ {I_CMPNGXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42573, 302},
+ /* 7412 */ {I_CMPNLXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42559, 302},
+ /* 7413 */ {I_CMPNOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42587, 302},
+ /* 7414 */ {I_CMPNSXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42601, 302},
+ /* 7415 */ {I_CMPNZXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42580, 302},
+ /* 7416 */ {I_CMPOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42608, 302},
+ /* 7417 */ {I_CMPPEXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42615, 302},
+ /* 7418 */ {I_CMPPOXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42594, 302},
+ /* 7419 */ {I_CMPSXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42622, 302},
+ /* 7420 */ {I_CMPZXADD, 3, {MEMORY|BITS32,REG_GPR|BITS32,REG_GPR|BITS32,0,0}, NO_DECORATOR, nasm_bytecodes+42545, 302},
+ /* 7421 */ {I_CMPAXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42629, 303},
+ /* 7422 */ {I_CMPCXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42643, 303},
+ /* 7423 */ {I_CMPGXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42664, 303},
+ /* 7424 */ {I_CMPLXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42678, 303},
+ /* 7425 */ {I_CMPNAXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42650, 303},
+ /* 7426 */ {I_CMPNCXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42636, 303},
+ /* 7427 */ {I_CMPNGXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42685, 303},
+ /* 7428 */ {I_CMPNLXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42671, 303},
+ /* 7429 */ {I_CMPNOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42699, 303},
+ /* 7430 */ {I_CMPNSXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42713, 303},
+ /* 7431 */ {I_CMPNZXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42692, 303},
+ /* 7432 */ {I_CMPOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42720, 303},
+ /* 7433 */ {I_CMPPEXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42727, 303},
+ /* 7434 */ {I_CMPPOXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42706, 303},
+ /* 7435 */ {I_CMPSXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42734, 303},
+ /* 7436 */ {I_CMPZXADD, 3, {MEMORY|BITS64,REG_GPR|BITS64,REG_GPR|BITS64,0,0}, NO_DECORATOR, nasm_bytecodes+42657, 303},
+ /* 7437 */ {I_WRMSRNS, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46095, 304},
+ /* 7438 */ {I_RDMSRLIST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46101, 305},
+ /* 7439 */ {I_WRMSRLIST, 0, {0,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46107, 305},
+ /* 7440 */ {I_HRESET, 2, {IMMEDIATE,REG_EAX,0,0,0}, NO_DECORATOR, nasm_bytecodes+32856, 306},
+ /* 7441 */ {I_HINT_NOP0, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46113, 307},
+ /* 7442 */ {I_HINT_NOP0, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46119, 307},
+ /* 7443 */ {I_HINT_NOP0, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46125, 308},
+ /* 7444 */ {I_HINT_NOP1, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46131, 307},
+ /* 7445 */ {I_HINT_NOP1, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46137, 307},
+ /* 7446 */ {I_HINT_NOP1, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46143, 308},
+ /* 7447 */ {I_HINT_NOP2, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46149, 307},
+ /* 7448 */ {I_HINT_NOP2, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46155, 307},
+ /* 7449 */ {I_HINT_NOP2, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46161, 308},
+ /* 7450 */ {I_HINT_NOP3, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46167, 307},
+ /* 7451 */ {I_HINT_NOP3, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46173, 307},
+ /* 7452 */ {I_HINT_NOP3, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46179, 308},
+ /* 7453 */ {I_HINT_NOP4, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46185, 307},
+ /* 7454 */ {I_HINT_NOP4, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46191, 307},
+ /* 7455 */ {I_HINT_NOP4, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46197, 308},
+ /* 7456 */ {I_HINT_NOP5, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46203, 307},
+ /* 7457 */ {I_HINT_NOP5, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46209, 307},
+ /* 7458 */ {I_HINT_NOP5, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46215, 308},
+ /* 7459 */ {I_HINT_NOP6, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46221, 307},
+ /* 7460 */ {I_HINT_NOP6, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46227, 307},
+ /* 7461 */ {I_HINT_NOP6, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46233, 308},
+ /* 7462 */ {I_HINT_NOP7, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46239, 307},
+ /* 7463 */ {I_HINT_NOP7, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46245, 307},
+ /* 7464 */ {I_HINT_NOP7, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46251, 308},
+ /* 7465 */ {I_HINT_NOP8, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46257, 307},
+ /* 7466 */ {I_HINT_NOP8, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46263, 307},
+ /* 7467 */ {I_HINT_NOP8, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46269, 308},
+ /* 7468 */ {I_HINT_NOP9, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46275, 307},
+ /* 7469 */ {I_HINT_NOP9, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46281, 307},
+ /* 7470 */ {I_HINT_NOP9, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46287, 308},
+ /* 7471 */ {I_HINT_NOP10, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46293, 307},
+ /* 7472 */ {I_HINT_NOP10, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46299, 307},
+ /* 7473 */ {I_HINT_NOP10, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46305, 308},
+ /* 7474 */ {I_HINT_NOP11, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46311, 307},
+ /* 7475 */ {I_HINT_NOP11, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46317, 307},
+ /* 7476 */ {I_HINT_NOP11, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46323, 308},
+ /* 7477 */ {I_HINT_NOP12, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46329, 307},
+ /* 7478 */ {I_HINT_NOP12, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46335, 307},
+ /* 7479 */ {I_HINT_NOP12, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46341, 308},
+ /* 7480 */ {I_HINT_NOP13, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46347, 307},
+ /* 7481 */ {I_HINT_NOP13, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46353, 307},
+ /* 7482 */ {I_HINT_NOP13, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46359, 308},
+ /* 7483 */ {I_HINT_NOP14, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46365, 307},
+ /* 7484 */ {I_HINT_NOP14, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46371, 307},
+ /* 7485 */ {I_HINT_NOP14, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46377, 308},
+ /* 7486 */ {I_HINT_NOP15, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46383, 307},
+ /* 7487 */ {I_HINT_NOP15, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46389, 307},
+ /* 7488 */ {I_HINT_NOP15, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46395, 308},
+ /* 7489 */ {I_HINT_NOP16, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46401, 307},
+ /* 7490 */ {I_HINT_NOP16, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46407, 307},
+ /* 7491 */ {I_HINT_NOP16, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46413, 308},
+ /* 7492 */ {I_HINT_NOP17, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46419, 307},
+ /* 7493 */ {I_HINT_NOP17, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46425, 307},
+ /* 7494 */ {I_HINT_NOP17, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46431, 308},
+ /* 7495 */ {I_HINT_NOP18, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46437, 307},
+ /* 7496 */ {I_HINT_NOP18, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46443, 307},
+ /* 7497 */ {I_HINT_NOP18, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46449, 308},
+ /* 7498 */ {I_HINT_NOP19, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46455, 307},
+ /* 7499 */ {I_HINT_NOP19, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46461, 307},
+ /* 7500 */ {I_HINT_NOP19, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46467, 308},
+ /* 7501 */ {I_HINT_NOP20, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46473, 307},
+ /* 7502 */ {I_HINT_NOP20, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46479, 307},
+ /* 7503 */ {I_HINT_NOP20, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46485, 308},
+ /* 7504 */ {I_HINT_NOP21, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46491, 307},
+ /* 7505 */ {I_HINT_NOP21, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46497, 307},
+ /* 7506 */ {I_HINT_NOP21, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46503, 308},
+ /* 7507 */ {I_HINT_NOP22, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46509, 307},
+ /* 7508 */ {I_HINT_NOP22, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46515, 307},
+ /* 7509 */ {I_HINT_NOP22, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46521, 308},
+ /* 7510 */ {I_HINT_NOP23, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46527, 307},
+ /* 7511 */ {I_HINT_NOP23, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46533, 307},
+ /* 7512 */ {I_HINT_NOP23, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46539, 308},
+ /* 7513 */ {I_HINT_NOP24, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46545, 307},
+ /* 7514 */ {I_HINT_NOP24, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46551, 307},
+ /* 7515 */ {I_HINT_NOP24, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46557, 308},
+ /* 7516 */ {I_HINT_NOP25, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46563, 307},
+ /* 7517 */ {I_HINT_NOP25, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46569, 307},
+ /* 7518 */ {I_HINT_NOP25, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46575, 308},
+ /* 7519 */ {I_HINT_NOP26, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46581, 307},
+ /* 7520 */ {I_HINT_NOP26, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46587, 307},
+ /* 7521 */ {I_HINT_NOP26, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46593, 308},
+ /* 7522 */ {I_HINT_NOP27, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46599, 307},
+ /* 7523 */ {I_HINT_NOP27, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46605, 307},
+ /* 7524 */ {I_HINT_NOP27, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46611, 308},
+ /* 7525 */ {I_HINT_NOP28, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46617, 307},
+ /* 7526 */ {I_HINT_NOP28, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46623, 307},
+ /* 7527 */ {I_HINT_NOP28, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46629, 308},
+ /* 7528 */ {I_HINT_NOP29, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46635, 307},
+ /* 7529 */ {I_HINT_NOP29, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46641, 307},
+ /* 7530 */ {I_HINT_NOP29, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46647, 308},
+ /* 7531 */ {I_HINT_NOP30, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46653, 307},
+ /* 7532 */ {I_HINT_NOP30, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46659, 307},
+ /* 7533 */ {I_HINT_NOP30, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46665, 308},
+ /* 7534 */ {I_HINT_NOP31, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46671, 307},
+ /* 7535 */ {I_HINT_NOP31, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46677, 307},
+ /* 7536 */ {I_HINT_NOP31, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46683, 308},
+ /* 7537 */ {I_HINT_NOP32, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46689, 307},
+ /* 7538 */ {I_HINT_NOP32, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46695, 307},
+ /* 7539 */ {I_HINT_NOP32, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46701, 308},
+ /* 7540 */ {I_HINT_NOP33, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46707, 307},
+ /* 7541 */ {I_HINT_NOP33, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46713, 307},
+ /* 7542 */ {I_HINT_NOP33, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46719, 308},
+ /* 7543 */ {I_HINT_NOP34, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46725, 307},
+ /* 7544 */ {I_HINT_NOP34, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46731, 307},
+ /* 7545 */ {I_HINT_NOP34, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46737, 308},
+ /* 7546 */ {I_HINT_NOP35, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46743, 307},
+ /* 7547 */ {I_HINT_NOP35, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46749, 307},
+ /* 7548 */ {I_HINT_NOP35, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46755, 308},
+ /* 7549 */ {I_HINT_NOP36, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46761, 307},
+ /* 7550 */ {I_HINT_NOP36, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46767, 307},
+ /* 7551 */ {I_HINT_NOP36, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46773, 308},
+ /* 7552 */ {I_HINT_NOP37, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46779, 307},
+ /* 7553 */ {I_HINT_NOP37, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46785, 307},
+ /* 7554 */ {I_HINT_NOP37, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46791, 308},
+ /* 7555 */ {I_HINT_NOP38, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46797, 307},
+ /* 7556 */ {I_HINT_NOP38, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46803, 307},
+ /* 7557 */ {I_HINT_NOP38, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46809, 308},
+ /* 7558 */ {I_HINT_NOP39, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46815, 307},
+ /* 7559 */ {I_HINT_NOP39, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46821, 307},
+ /* 7560 */ {I_HINT_NOP39, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46827, 308},
+ /* 7561 */ {I_HINT_NOP40, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46833, 307},
+ /* 7562 */ {I_HINT_NOP40, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46839, 307},
+ /* 7563 */ {I_HINT_NOP40, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46845, 308},
+ /* 7564 */ {I_HINT_NOP41, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46851, 307},
+ /* 7565 */ {I_HINT_NOP41, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46857, 307},
+ /* 7566 */ {I_HINT_NOP41, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46863, 308},
+ /* 7567 */ {I_HINT_NOP42, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46869, 307},
+ /* 7568 */ {I_HINT_NOP42, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46875, 307},
+ /* 7569 */ {I_HINT_NOP42, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46881, 308},
+ /* 7570 */ {I_HINT_NOP43, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46887, 307},
+ /* 7571 */ {I_HINT_NOP43, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46893, 307},
+ /* 7572 */ {I_HINT_NOP43, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46899, 308},
+ /* 7573 */ {I_HINT_NOP44, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46905, 307},
+ /* 7574 */ {I_HINT_NOP44, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46911, 307},
+ /* 7575 */ {I_HINT_NOP44, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46917, 308},
+ /* 7576 */ {I_HINT_NOP45, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46923, 307},
+ /* 7577 */ {I_HINT_NOP45, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46929, 307},
+ /* 7578 */ {I_HINT_NOP45, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46935, 308},
+ /* 7579 */ {I_HINT_NOP46, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46941, 307},
+ /* 7580 */ {I_HINT_NOP46, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46947, 307},
+ /* 7581 */ {I_HINT_NOP46, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46953, 308},
+ /* 7582 */ {I_HINT_NOP47, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46959, 307},
+ /* 7583 */ {I_HINT_NOP47, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46965, 307},
+ /* 7584 */ {I_HINT_NOP47, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46971, 308},
+ /* 7585 */ {I_HINT_NOP48, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46977, 307},
+ /* 7586 */ {I_HINT_NOP48, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46983, 307},
+ /* 7587 */ {I_HINT_NOP48, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46989, 308},
+ /* 7588 */ {I_HINT_NOP49, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+46995, 307},
+ /* 7589 */ {I_HINT_NOP49, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47001, 307},
+ /* 7590 */ {I_HINT_NOP49, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47007, 308},
+ /* 7591 */ {I_HINT_NOP50, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47013, 307},
+ /* 7592 */ {I_HINT_NOP50, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47019, 307},
+ /* 7593 */ {I_HINT_NOP50, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47025, 308},
+ /* 7594 */ {I_HINT_NOP51, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47031, 307},
+ /* 7595 */ {I_HINT_NOP51, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47037, 307},
+ /* 7596 */ {I_HINT_NOP51, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47043, 308},
+ /* 7597 */ {I_HINT_NOP52, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47049, 307},
+ /* 7598 */ {I_HINT_NOP52, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47055, 307},
+ /* 7599 */ {I_HINT_NOP52, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47061, 308},
+ /* 7600 */ {I_HINT_NOP53, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47067, 307},
+ /* 7601 */ {I_HINT_NOP53, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47073, 307},
+ /* 7602 */ {I_HINT_NOP53, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47079, 308},
+ /* 7603 */ {I_HINT_NOP54, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47085, 307},
+ /* 7604 */ {I_HINT_NOP54, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47091, 307},
+ /* 7605 */ {I_HINT_NOP54, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47097, 308},
+ /* 7606 */ {I_HINT_NOP55, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47103, 307},
+ /* 7607 */ {I_HINT_NOP55, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47109, 307},
+ /* 7608 */ {I_HINT_NOP55, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47115, 308},
+ /* 7609 */ {I_HINT_NOP56, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43437, 307},
+ /* 7610 */ {I_HINT_NOP56, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43443, 307},
+ /* 7611 */ {I_HINT_NOP56, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+43449, 308},
+ /* 7612 */ {I_HINT_NOP57, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47121, 307},
+ /* 7613 */ {I_HINT_NOP57, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47127, 307},
+ /* 7614 */ {I_HINT_NOP57, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47133, 308},
+ /* 7615 */ {I_HINT_NOP58, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47139, 307},
+ /* 7616 */ {I_HINT_NOP58, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47145, 307},
+ /* 7617 */ {I_HINT_NOP58, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47151, 308},
+ /* 7618 */ {I_HINT_NOP59, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47157, 307},
+ /* 7619 */ {I_HINT_NOP59, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47163, 307},
+ /* 7620 */ {I_HINT_NOP59, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47169, 308},
+ /* 7621 */ {I_HINT_NOP60, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47175, 307},
+ /* 7622 */ {I_HINT_NOP60, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47181, 307},
+ /* 7623 */ {I_HINT_NOP60, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47187, 308},
+ /* 7624 */ {I_HINT_NOP61, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47193, 307},
+ /* 7625 */ {I_HINT_NOP61, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47199, 307},
+ /* 7626 */ {I_HINT_NOP61, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47205, 308},
+ /* 7627 */ {I_HINT_NOP62, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47211, 307},
+ /* 7628 */ {I_HINT_NOP62, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47217, 307},
+ /* 7629 */ {I_HINT_NOP62, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47223, 308},
+ /* 7630 */ {I_HINT_NOP63, 1, {RM_GPR|BITS16,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47229, 307},
+ /* 7631 */ {I_HINT_NOP63, 1, {RM_GPR|BITS32,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47235, 307},
+ /* 7632 */ {I_HINT_NOP63, 1, {RM_GPR|BITS64,0,0,0,0}, NO_DECORATOR, nasm_bytecodes+47241, 308},
+};
+
+static const struct itemplate * const itable_00[] = {
+ instrux + 43,
+ instrux + 44,
+};
+
+static const struct itemplate * const itable_01[] = {
+ instrux + 45,
+ instrux + 46,
+ instrux + 47,
+ instrux + 48,
+ instrux + 49,
+ instrux + 50,
+};
+
+static const struct itemplate * const itable_02[] = {
+ instrux + 51,
+ instrux + 52,
+};
+
+static const struct itemplate * const itable_03[] = {
+ instrux + 53,
+ instrux + 54,
+ instrux + 55,
+ instrux + 56,
+ instrux + 57,
+ instrux + 58,
+};
+
+static const struct itemplate * const itable_04[] = {
+ instrux + 62,
+};
+
+static const struct itemplate * const itable_05[] = {
+ instrux + 63,
+ instrux + 64,
+ instrux + 65,
+};
+
+static const struct itemplate * const itable_06[] = {
+ instrux + 845,
+};
+
+static const struct itemplate * const itable_07[] = {
+ instrux + 794,
+};
+
+static const struct itemplate * const itable_08[] = {
+ instrux + 697,
+ instrux + 698,
+};
+
+static const struct itemplate * const itable_09[] = {
+ instrux + 699,
+ instrux + 700,
+ instrux + 701,
+ instrux + 702,
+ instrux + 703,
+ instrux + 704,
+};
+
+static const struct itemplate * const itable_0A[] = {
+ instrux + 705,
+ instrux + 706,
+};
+
+static const struct itemplate * const itable_0B[] = {
+ instrux + 707,
+ instrux + 708,
+ instrux + 709,
+ instrux + 710,
+ instrux + 711,
+ instrux + 712,
+};
+
+static const struct itemplate * const itable_0C[] = {
+ instrux + 716,
+};
+
+static const struct itemplate * const itable_0D[] = {
+ instrux + 717,
+ instrux + 718,
+ instrux + 719,
+};
+
+static const struct itemplate * const itable_0E[] = {
+ instrux + 846,
+};
+
+static const struct itemplate * const itable_0F00[] = {
+ instrux + 525,
+ instrux + 526,
+ instrux + 555,
+ instrux + 556,
+ instrux + 557,
+ instrux + 598,
+ instrux + 599,
+ instrux + 600,
+ instrux + 1045,
+ instrux + 1046,
+ instrux + 1047,
+ instrux + 1048,
+ instrux + 1049,
+ instrux + 1064,
+ instrux + 1065,
+ instrux + 1066,
+ instrux + 1067,
+ instrux + 1068,
+ instrux + 1137,
+ instrux + 1138,
+ instrux + 1139,
+ instrux + 1140,
+ instrux + 1141,
+ instrux + 1142,
+};
+
+static const struct itemplate * const itable_0F01[] = {
+ instrux + 491,
+ instrux + 492,
+ instrux + 493,
+ instrux + 494,
+ instrux + 495,
+ instrux + 550,
+ instrux + 554,
+ instrux + 558,
+ instrux + 559,
+ instrux + 560,
+ instrux + 602,
+ instrux + 603,
+ instrux + 683,
+ instrux + 684,
+ instrux + 893,
+ instrux + 995,
+ instrux + 1044,
+ instrux + 1050,
+ instrux + 1052,
+ instrux + 1053,
+ instrux + 1054,
+ instrux + 1055,
+ instrux + 1056,
+ instrux + 1101,
+ instrux + 1495,
+ instrux + 1496,
+ instrux + 1728,
+ instrux + 1729,
+ instrux + 1730,
+ instrux + 1732,
+ instrux + 1733,
+ instrux + 1734,
+ instrux + 1735,
+ instrux + 1740,
+ instrux + 1741,
+ instrux + 1742,
+ instrux + 1745,
+ instrux + 1751,
+ instrux + 1752,
+ instrux + 1753,
+ instrux + 1754,
+ instrux + 3380,
+ instrux + 3381,
+ instrux + 3989,
+ instrux + 3990,
+ instrux + 6770,
+ instrux + 6771,
+ instrux + 6778,
+ instrux + 6787,
+ instrux + 6962,
+ instrux + 6963,
+ instrux + 6964,
+ instrux + 6972,
+ instrux + 6973,
+ instrux + 6974,
+ instrux + 6985,
+ instrux + 6986,
+ instrux + 6988,
+ instrux + 6989,
+ instrux + 7400,
+ instrux + 7402,
+ instrux + 7403,
+ instrux + 7404,
+ instrux + 7437,
+ instrux + 7438,
+ instrux + 7439,
+};
+
+static const struct itemplate * const itable_0F02[] = {
+ instrux + 528,
+ instrux + 529,
+ instrux + 530,
+ instrux + 531,
+ instrux + 532,
+ instrux + 533,
+ instrux + 534,
+ instrux + 535,
+ instrux + 536,
+ instrux + 537,
+};
+
+static const struct itemplate * const itable_0F03[] = {
+ instrux + 585,
+ instrux + 586,
+ instrux + 587,
+ instrux + 588,
+ instrux + 589,
+ instrux + 590,
+ instrux + 591,
+ instrux + 592,
+ instrux + 593,
+ instrux + 594,
+};
+
+static const struct itemplate * const itable_0F05[] = {
+ instrux + 1102,
+};
+
+static const struct itemplate * const itable_0F06[] = {
+ instrux + 181,
+};
+
+static const struct itemplate * const itable_0F07[] = {
+ instrux + 1105,
+};
+
+static const struct itemplate * const itable_0F08[] = {
+ instrux + 488,
+};
+
+static const struct itemplate * const itable_0F09[] = {
+ instrux + 1144,
+ instrux + 6793,
+ instrux + 6987,
+};
+
+static const struct itemplate * const itable_0F0B[] = {
+ instrux + 1136,
+};
+
+static const struct itemplate * const itable_0F0D[] = {
+ instrux + 807,
+ instrux + 808,
+ instrux + 4040,
+};
+
+static const struct itemplate * const itable_0F0E[] = {
+ instrux + 314,
+};
+
+static const struct itemplate * const itable_0F0F[] = {
+ instrux + 751,
+ instrux + 759,
+ instrux + 760,
+ instrux + 761,
+ instrux + 762,
+ instrux + 763,
+ instrux + 764,
+ instrux + 765,
+ instrux + 766,
+ instrux + 767,
+ instrux + 768,
+ instrux + 769,
+ instrux + 770,
+ instrux + 771,
+ instrux + 772,
+ instrux + 773,
+ instrux + 774,
+ instrux + 775,
+ instrux + 780,
+ instrux + 1532,
+ instrux + 1533,
+ instrux + 1534,
+ instrux + 1535,
+ instrux + 1536,
+ instrux + 1869,
+ instrux + 1870,
+};
+
+static const struct itemplate * const itable_0F10[] = {
+ instrux + 1470,
+ instrux + 1472,
+ instrux + 1702,
+ instrux + 1704,
+};
+
+static const struct itemplate * const itable_0F11[] = {
+ instrux + 1471,
+ instrux + 1473,
+ instrux + 1703,
+ instrux + 1705,
+};
+
+static const struct itemplate * const itable_0F12[] = {
+ instrux + 1464,
+ instrux + 1466,
+ instrux + 1699,
+ instrux + 1725,
+ instrux + 1727,
+};
+
+static const struct itemplate * const itable_0F13[] = {
+ instrux + 1465,
+ instrux + 1698,
+};
+
+static const struct itemplate * const itable_0F14[] = {
+ instrux + 1489,
+ instrux + 1716,
+};
+
+static const struct itemplate * const itable_0F15[] = {
+ instrux + 1488,
+ instrux + 1715,
+};
+
+static const struct itemplate * const itable_0F16[] = {
+ instrux + 1461,
+ instrux + 1463,
+ instrux + 1697,
+ instrux + 1726,
+};
+
+static const struct itemplate * const itable_0F17[] = {
+ instrux + 1462,
+ instrux + 1696,
+};
+
+static const struct itemplate * const itable_0F18[] = {
+ instrux + 1509,
+ instrux + 1510,
+ instrux + 1511,
+ instrux + 1512,
+ instrux + 1513,
+ instrux + 1514,
+ instrux + 7441,
+ instrux + 7442,
+ instrux + 7443,
+ instrux + 7444,
+ instrux + 7445,
+ instrux + 7446,
+ instrux + 7447,
+ instrux + 7448,
+ instrux + 7449,
+ instrux + 7450,
+ instrux + 7451,
+ instrux + 7452,
+ instrux + 7453,
+ instrux + 7454,
+ instrux + 7455,
+ instrux + 7456,
+ instrux + 7457,
+ instrux + 7458,
+ instrux + 7459,
+ instrux + 7460,
+ instrux + 7461,
+ instrux + 7462,
+ instrux + 7463,
+ instrux + 7464,
+};
+
+static const struct itemplate * const itable_0F19[] = {
+ instrux + 7465,
+ instrux + 7466,
+ instrux + 7467,
+ instrux + 7468,
+ instrux + 7469,
+ instrux + 7470,
+ instrux + 7471,
+ instrux + 7472,
+ instrux + 7473,
+ instrux + 7474,
+ instrux + 7475,
+ instrux + 7476,
+ instrux + 7477,
+ instrux + 7478,
+ instrux + 7479,
+ instrux + 7480,
+ instrux + 7481,
+ instrux + 7482,
+ instrux + 7483,
+ instrux + 7484,
+ instrux + 7485,
+ instrux + 7486,
+ instrux + 7487,
+ instrux + 7488,
+};
+
+static const struct itemplate * const itable_0F1A[] = {
+ instrux + 4042,
+ instrux + 4043,
+ instrux + 4044,
+ instrux + 4045,
+ instrux + 4046,
+ instrux + 4047,
+ instrux + 4051,
+ instrux + 4052,
+ instrux + 4055,
+ instrux + 4056,
+ instrux + 4057,
+ instrux + 7489,
+ instrux + 7490,
+ instrux + 7491,
+ instrux + 7492,
+ instrux + 7493,
+ instrux + 7494,
+ instrux + 7495,
+ instrux + 7496,
+ instrux + 7497,
+ instrux + 7498,
+ instrux + 7499,
+ instrux + 7500,
+ instrux + 7501,
+ instrux + 7502,
+ instrux + 7503,
+ instrux + 7504,
+ instrux + 7505,
+ instrux + 7506,
+ instrux + 7507,
+ instrux + 7508,
+ instrux + 7509,
+ instrux + 7510,
+ instrux + 7511,
+ instrux + 7512,
+};
+
+static const struct itemplate * const itable_0F1B[] = {
+ instrux + 4041,
+ instrux + 4048,
+ instrux + 4049,
+ instrux + 4050,
+ instrux + 4053,
+ instrux + 4054,
+ instrux + 4058,
+ instrux + 4059,
+ instrux + 4060,
+ instrux + 4061,
+ instrux + 4062,
+ instrux + 7513,
+ instrux + 7514,
+ instrux + 7515,
+ instrux + 7516,
+ instrux + 7517,
+ instrux + 7518,
+ instrux + 7519,
+ instrux + 7520,
+ instrux + 7521,
+ instrux + 7522,
+ instrux + 7523,
+ instrux + 7524,
+ instrux + 7525,
+ instrux + 7526,
+ instrux + 7527,
+ instrux + 7528,
+ instrux + 7529,
+ instrux + 7530,
+ instrux + 7531,
+ instrux + 7532,
+ instrux + 7533,
+ instrux + 7534,
+ instrux + 7535,
+ instrux + 7536,
+};
+
+static const struct itemplate * const itable_0F1C[] = {
+ instrux + 6781,
+ instrux + 7537,
+ instrux + 7538,
+ instrux + 7539,
+ instrux + 7540,
+ instrux + 7541,
+ instrux + 7542,
+ instrux + 7543,
+ instrux + 7544,
+ instrux + 7545,
+ instrux + 7546,
+ instrux + 7547,
+ instrux + 7548,
+ instrux + 7549,
+ instrux + 7550,
+ instrux + 7551,
+ instrux + 7552,
+ instrux + 7553,
+ instrux + 7554,
+ instrux + 7555,
+ instrux + 7556,
+ instrux + 7557,
+ instrux + 7558,
+ instrux + 7559,
+ instrux + 7560,
+};
+
+static const struct itemplate * const itable_0F1D[] = {
+ instrux + 7561,
+ instrux + 7562,
+ instrux + 7563,
+ instrux + 7564,
+ instrux + 7565,
+ instrux + 7566,
+ instrux + 7567,
+ instrux + 7568,
+ instrux + 7569,
+ instrux + 7570,
+ instrux + 7571,
+ instrux + 7572,
+ instrux + 7573,
+ instrux + 7574,
+ instrux + 7575,
+ instrux + 7576,
+ instrux + 7577,
+ instrux + 7578,
+ instrux + 7579,
+ instrux + 7580,
+ instrux + 7581,
+ instrux + 7582,
+ instrux + 7583,
+ instrux + 7584,
+};
+
+static const struct itemplate * const itable_0F1E[] = {
+ instrux + 6966,
+ instrux + 6967,
+ instrux + 6970,
+ instrux + 6971,
+ instrux + 7585,
+ instrux + 7586,
+ instrux + 7587,
+ instrux + 7588,
+ instrux + 7589,
+ instrux + 7590,
+ instrux + 7591,
+ instrux + 7592,
+ instrux + 7593,
+ instrux + 7594,
+ instrux + 7595,
+ instrux + 7596,
+ instrux + 7597,
+ instrux + 7598,
+ instrux + 7599,
+ instrux + 7600,
+ instrux + 7601,
+ instrux + 7602,
+ instrux + 7603,
+ instrux + 7604,
+ instrux + 7605,
+ instrux + 7606,
+ instrux + 7607,
+ instrux + 7608,
+};
+
+static const struct itemplate * const itable_0F1F[] = {
+ instrux + 690,
+ instrux + 691,
+ instrux + 692,
+ instrux + 7609,
+ instrux + 7610,
+ instrux + 7611,
+ instrux + 7612,
+ instrux + 7613,
+ instrux + 7614,
+ instrux + 7615,
+ instrux + 7616,
+ instrux + 7617,
+ instrux + 7618,
+ instrux + 7619,
+ instrux + 7620,
+ instrux + 7621,
+ instrux + 7622,
+ instrux + 7623,
+ instrux + 7624,
+ instrux + 7625,
+ instrux + 7626,
+ instrux + 7627,
+ instrux + 7628,
+ instrux + 7629,
+ instrux + 7630,
+ instrux + 7631,
+ instrux + 7632,
+};
+
+static const struct itemplate * const itable_0F20[] = {
+ instrux + 620,
+ instrux + 621,
+};
+
+static const struct itemplate * const itable_0F21[] = {
+ instrux + 624,
+ instrux + 625,
+};
+
+static const struct itemplate * const itable_0F22[] = {
+ instrux + 622,
+ instrux + 623,
+};
+
+static const struct itemplate * const itable_0F23[] = {
+ instrux + 626,
+ instrux + 627,
+};
+
+static const struct itemplate * const itable_0F28[] = {
+ instrux + 1459,
+ instrux + 1694,
+};
+
+static const struct itemplate * const itable_0F29[] = {
+ instrux + 1460,
+ instrux + 1695,
+};
+
+static const struct itemplate * const itable_0F2A[] = {
+ instrux + 1441,
+ instrux + 1443,
+ instrux + 1444,
+ instrux + 1670,
+ instrux + 1678,
+ instrux + 1679,
+};
+
+static const struct itemplate * const itable_0F2B[] = {
+ instrux + 1469,
+ instrux + 1542,
+ instrux + 1791,
+ instrux + 1792,
+};
+
+static const struct itemplate * const itable_0F2C[] = {
+ instrux + 1449,
+ instrux + 1450,
+ instrux + 1451,
+ instrux + 1681,
+ instrux + 1684,
+ instrux + 1685,
+ instrux + 1686,
+ instrux + 1687,
+};
+
+static const struct itemplate * const itable_0F2D[] = {
+ instrux + 1442,
+ instrux + 1445,
+ instrux + 1446,
+ instrux + 1447,
+ instrux + 1448,
+ instrux + 1668,
+ instrux + 1673,
+ instrux + 1674,
+ instrux + 1675,
+ instrux + 1676,
+};
+
+static const struct itemplate * const itable_0F2E[] = {
+ instrux + 1487,
+ instrux + 1714,
+};
+
+static const struct itemplate * const itable_0F2F[] = {
+ instrux + 1440,
+ instrux + 1664,
+};
+
+static const struct itemplate * const itable_0F30[] = {
+ instrux + 1146,
+};
+
+static const struct itemplate * const itable_0F31[] = {
+ instrux + 892,
+};
+
+static const struct itemplate * const itable_0F32[] = {
+ instrux + 890,
+};
+
+static const struct itemplate * const itable_0F33[] = {
+ instrux + 891,
+};
+
+static const struct itemplate * const itable_0F34[] = {
+ instrux + 1103,
+};
+
+static const struct itemplate * const itable_0F35[] = {
+ instrux + 1104,
+};
+
+static const struct itemplate * const itable_0F36[] = {
+ instrux + 889,
+};
+
+static const struct itemplate * const itable_0F37[] = {
+ instrux + 1145,
+ instrux + 1868,
+};
+
+static const struct itemplate * const itable_0F3800[] = {
+ instrux + 1779,
+ instrux + 1780,
+};
+
+static const struct itemplate * const itable_0F3801[] = {
+ instrux + 1763,
+ instrux + 1764,
+};
+
+static const struct itemplate * const itable_0F3802[] = {
+ instrux + 1765,
+ instrux + 1766,
+};
+
+static const struct itemplate * const itable_0F3803[] = {
+ instrux + 1767,
+ instrux + 1768,
+};
+
+static const struct itemplate * const itable_0F3804[] = {
+ instrux + 1775,
+ instrux + 1776,
+};
+
+static const struct itemplate * const itable_0F3805[] = {
+ instrux + 1769,
+ instrux + 1770,
+};
+
+static const struct itemplate * const itable_0F3806[] = {
+ instrux + 1771,
+ instrux + 1772,
+};
+
+static const struct itemplate * const itable_0F3807[] = {
+ instrux + 1773,
+ instrux + 1774,
+};
+
+static const struct itemplate * const itable_0F3808[] = {
+ instrux + 1781,
+ instrux + 1782,
+};
+
+static const struct itemplate * const itable_0F3809[] = {
+ instrux + 1783,
+ instrux + 1784,
+};
+
+static const struct itemplate * const itable_0F380A[] = {
+ instrux + 1785,
+ instrux + 1786,
+};
+
+static const struct itemplate * const itable_0F380B[] = {
+ instrux + 1777,
+ instrux + 1778,
+};
+
+static const struct itemplate * const itable_0F3810[] = {
+ instrux + 1810,
+ instrux + 1811,
+};
+
+static const struct itemplate * const itable_0F3814[] = {
+ instrux + 1800,
+ instrux + 1801,
+};
+
+static const struct itemplate * const itable_0F3815[] = {
+ instrux + 1798,
+ instrux + 1799,
+};
+
+static const struct itemplate * const itable_0F3817[] = {
+ instrux + 1850,
+};
+
+static const struct itemplate * const itable_0F381C[] = {
+ instrux + 1755,
+ instrux + 1756,
+};
+
+static const struct itemplate * const itable_0F381D[] = {
+ instrux + 1757,
+ instrux + 1758,
+};
+
+static const struct itemplate * const itable_0F381E[] = {
+ instrux + 1759,
+ instrux + 1760,
+};
+
+static const struct itemplate * const itable_0F3820[] = {
+ instrux + 1836,
+};
+
+static const struct itemplate * const itable_0F3821[] = {
+ instrux + 1837,
+};
+
+static const struct itemplate * const itable_0F3822[] = {
+ instrux + 1838,
+};
+
+static const struct itemplate * const itable_0F3823[] = {
+ instrux + 1839,
+};
+
+static const struct itemplate * const itable_0F3824[] = {
+ instrux + 1840,
+};
+
+static const struct itemplate * const itable_0F3825[] = {
+ instrux + 1841,
+};
+
+static const struct itemplate * const itable_0F3828[] = {
+ instrux + 1848,
+};
+
+static const struct itemplate * const itable_0F3829[] = {
+ instrux + 1813,
+};
+
+static const struct itemplate * const itable_0F382A[] = {
+ instrux + 1807,
+};
+
+static const struct itemplate * const itable_0F382B[] = {
+ instrux + 1809,
+};
+
+static const struct itemplate * const itable_0F3830[] = {
+ instrux + 1842,
+};
+
+static const struct itemplate * const itable_0F3831[] = {
+ instrux + 1843,
+};
+
+static const struct itemplate * const itable_0F3832[] = {
+ instrux + 1844,
+};
+
+static const struct itemplate * const itable_0F3833[] = {
+ instrux + 1845,
+};
+
+static const struct itemplate * const itable_0F3834[] = {
+ instrux + 1846,
+};
+
+static const struct itemplate * const itable_0F3835[] = {
+ instrux + 1847,
+};
+
+static const struct itemplate * const itable_0F3837[] = {
+ instrux + 1864,
+};
+
+static const struct itemplate * const itable_0F3838[] = {
+ instrux + 1832,
+};
+
+static const struct itemplate * const itable_0F3839[] = {
+ instrux + 1833,
+};
+
+static const struct itemplate * const itable_0F383A[] = {
+ instrux + 1835,
+};
+
+static const struct itemplate * const itable_0F383B[] = {
+ instrux + 1834,
+};
+
+static const struct itemplate * const itable_0F383C[] = {
+ instrux + 1828,
+};
+
+static const struct itemplate * const itable_0F383D[] = {
+ instrux + 1829,
+};
+
+static const struct itemplate * const itable_0F383E[] = {
+ instrux + 1831,
+};
+
+static const struct itemplate * const itable_0F383F[] = {
+ instrux + 1830,
+};
+
+static const struct itemplate * const itable_0F3840[] = {
+ instrux + 1849,
+};
+
+static const struct itemplate * const itable_0F3841[] = {
+ instrux + 1822,
+};
+
+static const struct itemplate * const itable_0F3880[] = {
+ instrux + 1747,
+ instrux + 1748,
+};
+
+static const struct itemplate * const itable_0F3881[] = {
+ instrux + 1749,
+ instrux + 1750,
+};
+
+static const struct itemplate * const itable_0F3882[] = {
+ instrux + 489,
+ instrux + 490,
+};
+
+static const struct itemplate * const itable_0F38C8[] = {
+ instrux + 4065,
+};
+
+static const struct itemplate * const itable_0F38C9[] = {
+ instrux + 4063,
+};
+
+static const struct itemplate * const itable_0F38CA[] = {
+ instrux + 4064,
+};
+
+static const struct itemplate * const itable_0F38CB[] = {
+ instrux + 4069,
+ instrux + 4070,
+};
+
+static const struct itemplate * const itable_0F38CC[] = {
+ instrux + 4067,
+};
+
+static const struct itemplate * const itable_0F38CD[] = {
+ instrux + 4068,
+};
+
+static const struct itemplate * const itable_0F38CF[] = {
+ instrux + 6816,
+};
+
+static const struct itemplate * const itable_0F38DB[] = {
+ instrux + 1881,
+};
+
+static const struct itemplate * const itable_0F38DC[] = {
+ instrux + 1877,
+};
+
+static const struct itemplate * const itable_0F38DD[] = {
+ instrux + 1878,
+};
+
+static const struct itemplate * const itable_0F38DE[] = {
+ instrux + 1879,
+};
+
+static const struct itemplate * const itable_0F38DF[] = {
+ instrux + 1880,
+};
+
+static const struct itemplate * const itable_0F38F0[] = {
+ instrux + 1855,
+ instrux + 1858,
+ instrux + 1871,
+ instrux + 1872,
+ instrux + 1873,
+};
+
+static const struct itemplate * const itable_0F38F1[] = {
+ instrux + 1856,
+ instrux + 1857,
+ instrux + 1859,
+ instrux + 1874,
+ instrux + 1875,
+ instrux + 1876,
+};
+
+static const struct itemplate * const itable_0F38F5[] = {
+ instrux + 6975,
+ instrux + 6976,
+};
+
+static const struct itemplate * const itable_0F38F6[] = {
+ instrux + 3373,
+ instrux + 3374,
+ instrux + 3375,
+ instrux + 3376,
+ instrux + 6977,
+ instrux + 6978,
+};
+
+static const struct itemplate * const itable_0F38F8[] = {
+ instrux + 6784,
+ instrux + 6785,
+ instrux + 6786,
+ instrux + 6979,
+ instrux + 6980,
+ instrux + 6981,
+ instrux + 6982,
+ instrux + 6983,
+ instrux + 6984,
+};
+
+static const struct itemplate * const itable_0F38F9[] = {
+ instrux + 6782,
+ instrux + 6783,
+};
+
+static const struct itemplate * const itable_0F38FC[] = {
+ instrux + 7394,
+ instrux + 7395,
+ instrux + 7396,
+ instrux + 7397,
+ instrux + 7398,
+ instrux + 7399,
+};
+
+static const struct itemplate * const itable_0F39[] = {
+ instrux + 245,
+};
+
+static const struct itemplate * const itable_0F3A08[] = {
+ instrux + 1852,
+};
+
+static const struct itemplate * const itable_0F3A09[] = {
+ instrux + 1851,
+};
+
+static const struct itemplate * const itable_0F3A0A[] = {
+ instrux + 1854,
+};
+
+static const struct itemplate * const itable_0F3A0B[] = {
+ instrux + 1853,
+};
+
+static const struct itemplate * const itable_0F3A0C[] = {
+ instrux + 1797,
+};
+
+static const struct itemplate * const itable_0F3A0D[] = {
+ instrux + 1796,
+};
+
+static const struct itemplate * const itable_0F3A0E[] = {
+ instrux + 1812,
+};
+
+static const struct itemplate * const itable_0F3A0F[] = {
+ instrux + 1761,
+ instrux + 1762,
+};
+
+static const struct itemplate * const itable_0F3A14[] = {
+ instrux + 1814,
+ instrux + 1815,
+ instrux + 1816,
+};
+
+static const struct itemplate * const itable_0F3A15[] = {
+ instrux + 1819,
+ instrux + 1820,
+ instrux + 1821,
+};
+
+static const struct itemplate * const itable_0F3A16[] = {
+ instrux + 1817,
+ instrux + 1818,
+};
+
+static const struct itemplate * const itable_0F3A17[] = {
+ instrux + 1804,
+ instrux + 1805,
+};
+
+static const struct itemplate * const itable_0F3A20[] = {
+ instrux + 1823,
+ instrux + 1824,
+ instrux + 1825,
+};
+
+static const struct itemplate * const itable_0F3A21[] = {
+ instrux + 1806,
+};
+
+static const struct itemplate * const itable_0F3A22[] = {
+ instrux + 1826,
+ instrux + 1827,
+};
+
+static const struct itemplate * const itable_0F3A40[] = {
+ instrux + 1803,
+};
+
+static const struct itemplate * const itable_0F3A41[] = {
+ instrux + 1802,
+};
+
+static const struct itemplate * const itable_0F3A42[] = {
+ instrux + 1808,
+};
+
+static const struct itemplate * const itable_0F3A44[] = {
+ instrux + 3111,
+ instrux + 3112,
+ instrux + 3113,
+ instrux + 3114,
+ instrux + 3115,
+};
+
+static const struct itemplate * const itable_0F3A60[] = {
+ instrux + 1861,
+};
+
+static const struct itemplate * const itable_0F3A61[] = {
+ instrux + 1860,
+};
+
+static const struct itemplate * const itable_0F3A62[] = {
+ instrux + 1863,
+};
+
+static const struct itemplate * const itable_0F3A63[] = {
+ instrux + 1862,
+};
+
+static const struct itemplate * const itable_0F3ACC[] = {
+ instrux + 4066,
+};
+
+static const struct itemplate * const itable_0F3ACE[] = {
+ instrux + 6805,
+};
+
+static const struct itemplate * const itable_0F3ACF[] = {
+ instrux + 6794,
+};
+
+static const struct itemplate * const itable_0F3ADF[] = {
+ instrux + 1882,
+};
+
+static const struct itemplate * const itable_0F3AF0[] = {
+ instrux + 7440,
+};
+
+static const struct itemplate * const itable_0F3C[] = {
+ instrux + 229,
+};
+
+static const struct itemplate * const itable_0F3D[] = {
+ instrux + 228,
+};
+
+static const struct itemplate * const itable_0F40[] = {
+ instrux + 1221,
+ instrux + 1237,
+ instrux + 1253,
+ instrux + 1269,
+ instrux + 1285,
+ instrux + 1301,
+};
+
+static const struct itemplate * const itable_0F41[] = {
+ instrux + 1218,
+ instrux + 1234,
+ instrux + 1250,
+ instrux + 1266,
+ instrux + 1282,
+ instrux + 1298,
+};
+
+static const struct itemplate * const itable_0F42[] = {
+ instrux + 1211,
+ instrux + 1227,
+ instrux + 1243,
+ instrux + 1259,
+ instrux + 1275,
+ instrux + 1291,
+};
+
+static const struct itemplate * const itable_0F43[] = {
+ instrux + 1215,
+ instrux + 1231,
+ instrux + 1247,
+ instrux + 1263,
+ instrux + 1279,
+ instrux + 1295,
+};
+
+static const struct itemplate * const itable_0F44[] = {
+ instrux + 1225,
+ instrux + 1241,
+ instrux + 1257,
+ instrux + 1273,
+ instrux + 1289,
+ instrux + 1305,
+};
+
+static const struct itemplate * const itable_0F45[] = {
+ instrux + 1220,
+ instrux + 1236,
+ instrux + 1252,
+ instrux + 1268,
+ instrux + 1284,
+ instrux + 1300,
+};
+
+static const struct itemplate * const itable_0F46[] = {
+ instrux + 1214,
+ instrux + 1230,
+ instrux + 1246,
+ instrux + 1262,
+ instrux + 1278,
+ instrux + 1294,
+};
+
+static const struct itemplate * const itable_0F47[] = {
+ instrux + 1210,
+ instrux + 1226,
+ instrux + 1242,
+ instrux + 1258,
+ instrux + 1274,
+ instrux + 1290,
+};
+
+static const struct itemplate * const itable_0F48[] = {
+ instrux + 1224,
+ instrux + 1240,
+ instrux + 1256,
+ instrux + 1272,
+ instrux + 1288,
+ instrux + 1304,
+};
+
+static const struct itemplate * const itable_0F49[] = {
+ instrux + 1219,
+ instrux + 1235,
+ instrux + 1251,
+ instrux + 1267,
+ instrux + 1283,
+ instrux + 1299,
+};
+
+static const struct itemplate * const itable_0F4A[] = {
+ instrux + 1222,
+ instrux + 1238,
+ instrux + 1254,
+ instrux + 1270,
+ instrux + 1286,
+ instrux + 1302,
+};
+
+static const struct itemplate * const itable_0F4B[] = {
+ instrux + 1223,
+ instrux + 1239,
+ instrux + 1255,
+ instrux + 1271,
+ instrux + 1287,
+ instrux + 1303,
+};
+
+static const struct itemplate * const itable_0F4C[] = {
+ instrux + 1213,
+ instrux + 1229,
+ instrux + 1245,
+ instrux + 1261,
+ instrux + 1277,
+ instrux + 1293,
+};
+
+static const struct itemplate * const itable_0F4D[] = {
+ instrux + 1217,
+ instrux + 1233,
+ instrux + 1249,
+ instrux + 1265,
+ instrux + 1281,
+ instrux + 1297,
+};
+
+static const struct itemplate * const itable_0F4E[] = {
+ instrux + 1216,
+ instrux + 1232,
+ instrux + 1248,
+ instrux + 1264,
+ instrux + 1280,
+ instrux + 1296,
+};
+
+static const struct itemplate * const itable_0F4F[] = {
+ instrux + 1212,
+ instrux + 1228,
+ instrux + 1244,
+ instrux + 1260,
+ instrux + 1276,
+ instrux + 1292,
+};
+
+static const struct itemplate * const itable_0F50[] = {
+ instrux + 750,
+ instrux + 1467,
+ instrux + 1468,
+ instrux + 1700,
+ instrux + 1701,
+};
+
+static const struct itemplate * const itable_0F51[] = {
+ instrux + 742,
+ instrux + 1482,
+ instrux + 1483,
+ instrux + 1710,
+ instrux + 1711,
+};
+
+static const struct itemplate * const itable_0F52[] = {
+ instrux + 778,
+ instrux + 1479,
+ instrux + 1480,
+};
+
+static const struct itemplate * const itable_0F53[] = {
+ instrux + 1477,
+ instrux + 1478,
+};
+
+static const struct itemplate * const itable_0F54[] = {
+ instrux + 758,
+ instrux + 1421,
+ instrux + 1645,
+};
+
+static const struct itemplate * const itable_0F55[] = {
+ instrux + 828,
+ instrux + 1420,
+ instrux + 1644,
+};
+
+static const struct itemplate * const itable_0F56[] = {
+ instrux + 1476,
+ instrux + 1708,
+};
+
+static const struct itemplate * const itable_0F57[] = {
+ instrux + 1490,
+ instrux + 1717,
+};
+
+static const struct itemplate * const itable_0F58[] = {
+ instrux + 787,
+ instrux + 1418,
+ instrux + 1419,
+ instrux + 1642,
+ instrux + 1643,
+};
+
+static const struct itemplate * const itable_0F59[] = {
+ instrux + 781,
+ instrux + 1474,
+ instrux + 1475,
+ instrux + 1706,
+ instrux + 1707,
+};
+
+static const struct itemplate * const itable_0F5A[] = {
+ instrux + 786,
+ instrux + 1669,
+ instrux + 1672,
+ instrux + 1677,
+ instrux + 1680,
+};
+
+static const struct itemplate * const itable_0F5B[] = {
+ instrux + 785,
+ instrux + 1666,
+ instrux + 1671,
+ instrux + 1683,
+};
+
+static const struct itemplate * const itable_0F5C[] = {
+ instrux + 784,
+ instrux + 1485,
+ instrux + 1486,
+ instrux + 1712,
+ instrux + 1713,
+};
+
+static const struct itemplate * const itable_0F5D[] = {
+ instrux + 779,
+ instrux + 1457,
+ instrux + 1458,
+ instrux + 1692,
+ instrux + 1693,
+};
+
+static const struct itemplate * const itable_0F5E[] = {
+ instrux + 776,
+ instrux + 1452,
+ instrux + 1453,
+ instrux + 1688,
+ instrux + 1689,
+};
+
+static const struct itemplate * const itable_0F5F[] = {
+ instrux + 1455,
+ instrux + 1456,
+ instrux + 1690,
+ instrux + 1691,
+};
+
+static const struct itemplate * const itable_0F60[] = {
+ instrux + 836,
+ instrux + 1637,
+};
+
+static const struct itemplate * const itable_0F61[] = {
+ instrux + 838,
+ instrux + 1638,
+};
+
+static const struct itemplate * const itable_0F62[] = {
+ instrux + 837,
+ instrux + 1639,
+};
+
+static const struct itemplate * const itable_0F63[] = {
+ instrux + 737,
+ instrux + 1561,
+};
+
+static const struct itemplate * const itable_0F64[] = {
+ instrux + 755,
+ instrux + 1580,
+};
+
+static const struct itemplate * const itable_0F65[] = {
+ instrux + 757,
+ instrux + 1581,
+};
+
+static const struct itemplate * const itable_0F66[] = {
+ instrux + 756,
+ instrux + 1582,
+};
+
+static const struct itemplate * const itable_0F67[] = {
+ instrux + 738,
+ instrux + 1563,
+};
+
+static const struct itemplate * const itable_0F68[] = {
+ instrux + 833,
+ instrux + 1633,
+};
+
+static const struct itemplate * const itable_0F69[] = {
+ instrux + 835,
+ instrux + 1634,
+};
+
+static const struct itemplate * const itable_0F6A[] = {
+ instrux + 834,
+ instrux + 1635,
+};
+
+static const struct itemplate * const itable_0F6B[] = {
+ instrux + 736,
+ instrux + 1562,
+};
+
+static const struct itemplate * const itable_0F6C[] = {
+ instrux + 1640,
+};
+
+static const struct itemplate * const itable_0F6D[] = {
+ instrux + 1636,
+};
+
+static const struct itemplate * const itable_0F6E[] = {
+ instrux + 656,
+ instrux + 660,
+ instrux + 1546,
+ instrux + 1547,
+ instrux + 1558,
+};
+
+static const struct itemplate * const itable_0F6F[] = {
+ instrux + 658,
+ instrux + 1549,
+ instrux + 1551,
+};
+
+static const struct itemplate * const itable_0F70[] = {
+ instrux + 1531,
+ instrux + 1600,
+ instrux + 1601,
+ instrux + 1602,
+ instrux + 1603,
+ instrux + 1604,
+ instrux + 1605,
+};
+
+static const struct itemplate * const itable_0F71[] = {
+ instrux + 814,
+ instrux + 818,
+ instrux + 824,
+ instrux + 1608,
+ instrux + 1614,
+ instrux + 1619,
+};
+
+static const struct itemplate * const itable_0F72[] = {
+ instrux + 810,
+ instrux + 816,
+ instrux + 820,
+ instrux + 1610,
+ instrux + 1616,
+ instrux + 1621,
+};
+
+static const struct itemplate * const itable_0F73[] = {
+ instrux + 812,
+ instrux + 822,
+ instrux + 1606,
+ instrux + 1612,
+ instrux + 1617,
+ instrux + 1623,
+};
+
+static const struct itemplate * const itable_0F74[] = {
+ instrux + 752,
+ instrux + 1577,
+};
+
+static const struct itemplate * const itable_0F75[] = {
+ instrux + 754,
+ instrux + 1578,
+};
+
+static const struct itemplate * const itable_0F76[] = {
+ instrux + 753,
+ instrux + 1579,
+};
+
+static const struct itemplate * const itable_0F77[] = {
+ instrux + 246,
+};
+
+static const struct itemplate * const itable_0F78[] = {
+ instrux + 1099,
+ instrux + 1738,
+ instrux + 1739,
+ instrux + 1787,
+ instrux + 1789,
+};
+
+static const struct itemplate * const itable_0F79[] = {
+ instrux + 942,
+ instrux + 1743,
+ instrux + 1744,
+ instrux + 1788,
+ instrux + 1790,
+};
+
+static const struct itemplate * const itable_0F7B[] = {
+ instrux + 943,
+};
+
+static const struct itemplate * const itable_0F7C[] = {
+ instrux + 1100,
+ instrux + 1720,
+ instrux + 1721,
+};
+
+static const struct itemplate * const itable_0F7D[] = {
+ instrux + 945,
+ instrux + 1722,
+ instrux + 1723,
+};
+
+static const struct itemplate * const itable_0F7E[] = {
+ instrux + 657,
+ instrux + 661,
+ instrux + 1545,
+ instrux + 1548,
+ instrux + 1554,
+ instrux + 1557,
+ instrux + 1559,
+};
+
+static const struct itemplate * const itable_0F7F[] = {
+ instrux + 659,
+ instrux + 1550,
+ instrux + 1552,
+};
+
+static const struct itemplate * const itable_0F80[] = {
+ instrux + 1317,
+ instrux + 1333,
+ instrux + 1349,
+ instrux + 1365,
+};
+
+static const struct itemplate * const itable_0F81[] = {
+ instrux + 1314,
+ instrux + 1330,
+ instrux + 1346,
+ instrux + 1362,
+};
+
+static const struct itemplate * const itable_0F82[] = {
+ instrux + 1307,
+ instrux + 1323,
+ instrux + 1339,
+ instrux + 1355,
+};
+
+static const struct itemplate * const itable_0F83[] = {
+ instrux + 1311,
+ instrux + 1327,
+ instrux + 1343,
+ instrux + 1359,
+};
+
+static const struct itemplate * const itable_0F84[] = {
+ instrux + 1321,
+ instrux + 1337,
+ instrux + 1353,
+ instrux + 1369,
+};
+
+static const struct itemplate * const itable_0F85[] = {
+ instrux + 1316,
+ instrux + 1332,
+ instrux + 1348,
+ instrux + 1364,
+};
+
+static const struct itemplate * const itable_0F86[] = {
+ instrux + 1310,
+ instrux + 1326,
+ instrux + 1342,
+ instrux + 1358,
+};
+
+static const struct itemplate * const itable_0F87[] = {
+ instrux + 1306,
+ instrux + 1322,
+ instrux + 1338,
+ instrux + 1354,
+};
+
+static const struct itemplate * const itable_0F88[] = {
+ instrux + 1320,
+ instrux + 1336,
+ instrux + 1352,
+ instrux + 1368,
+};
+
+static const struct itemplate * const itable_0F89[] = {
+ instrux + 1315,
+ instrux + 1331,
+ instrux + 1347,
+ instrux + 1363,
+};
+
+static const struct itemplate * const itable_0F8A[] = {
+ instrux + 1318,
+ instrux + 1334,
+ instrux + 1350,
+ instrux + 1366,
+};
+
+static const struct itemplate * const itable_0F8B[] = {
+ instrux + 1319,
+ instrux + 1335,
+ instrux + 1351,
+ instrux + 1367,
+};
+
+static const struct itemplate * const itable_0F8C[] = {
+ instrux + 1309,
+ instrux + 1325,
+ instrux + 1341,
+ instrux + 1357,
+};
+
+static const struct itemplate * const itable_0F8D[] = {
+ instrux + 1313,
+ instrux + 1329,
+ instrux + 1345,
+ instrux + 1361,
+};
+
+static const struct itemplate * const itable_0F8E[] = {
+ instrux + 1312,
+ instrux + 1328,
+ instrux + 1344,
+ instrux + 1360,
+};
+
+static const struct itemplate * const itable_0F8F[] = {
+ instrux + 1308,
+ instrux + 1324,
+ instrux + 1340,
+ instrux + 1356,
+};
+
+static const struct itemplate * const itable_0F90[] = {
+ instrux + 1397,
+ instrux + 1413,
+};
+
+static const struct itemplate * const itable_0F91[] = {
+ instrux + 1394,
+ instrux + 1410,
+};
+
+static const struct itemplate * const itable_0F92[] = {
+ instrux + 1387,
+ instrux + 1403,
+};
+
+static const struct itemplate * const itable_0F93[] = {
+ instrux + 1391,
+ instrux + 1407,
+};
+
+static const struct itemplate * const itable_0F94[] = {
+ instrux + 1401,
+ instrux + 1417,
+};
+
+static const struct itemplate * const itable_0F95[] = {
+ instrux + 1396,
+ instrux + 1412,
+};
+
+static const struct itemplate * const itable_0F96[] = {
+ instrux + 1390,
+ instrux + 1406,
+};
+
+static const struct itemplate * const itable_0F97[] = {
+ instrux + 1386,
+ instrux + 1402,
+};
+
+static const struct itemplate * const itable_0F98[] = {
+ instrux + 1400,
+ instrux + 1416,
+};
+
+static const struct itemplate * const itable_0F99[] = {
+ instrux + 1395,
+ instrux + 1411,
+};
+
+static const struct itemplate * const itable_0F9A[] = {
+ instrux + 1398,
+ instrux + 1414,
+};
+
+static const struct itemplate * const itable_0F9B[] = {
+ instrux + 1399,
+ instrux + 1415,
+};
+
+static const struct itemplate * const itable_0F9C[] = {
+ instrux + 1389,
+ instrux + 1405,
+};
+
+static const struct itemplate * const itable_0F9D[] = {
+ instrux + 1393,
+ instrux + 1409,
+};
+
+static const struct itemplate * const itable_0F9E[] = {
+ instrux + 1392,
+ instrux + 1408,
+};
+
+static const struct itemplate * const itable_0F9F[] = {
+ instrux + 1388,
+ instrux + 1404,
+};
+
+static const struct itemplate * const itable_0FA0[] = {
+ instrux + 849,
+};
+
+static const struct itemplate * const itable_0FA1[] = {
+ instrux + 797,
+};
+
+static const struct itemplate * const itable_0FA2[] = {
+ instrux + 227,
+};
+
+static const struct itemplate * const itable_0FA3[] = {
+ instrux + 121,
+ instrux + 122,
+ instrux + 123,
+ instrux + 124,
+ instrux + 125,
+ instrux + 126,
+};
+
+static const struct itemplate * const itable_0FA4[] = {
+ instrux + 1008,
+ instrux + 1009,
+ instrux + 1010,
+ instrux + 1011,
+ instrux + 1012,
+ instrux + 1013,
+};
+
+static const struct itemplate * const itable_0FA5[] = {
+ instrux + 1014,
+ instrux + 1015,
+ instrux + 1016,
+ instrux + 1017,
+ instrux + 1018,
+ instrux + 1019,
+};
+
+static const struct itemplate * const itable_0FA6C0[] = {
+ instrux + 3388,
+};
+
+static const struct itemplate * const itable_0FA6C8[] = {
+ instrux + 3389,
+};
+
+static const struct itemplate * const itable_0FA6D0[] = {
+ instrux + 3390,
+};
+
+static const struct itemplate * const itable_0FA7C0[] = {
+ instrux + 3382,
+};
+
+static const struct itemplate * const itable_0FA7C8[] = {
+ instrux + 3383,
+};
+
+static const struct itemplate * const itable_0FA7D0[] = {
+ instrux + 3384,
+};
+
+static const struct itemplate * const itable_0FA7D8[] = {
+ instrux + 3385,
+};
+
+static const struct itemplate * const itable_0FA7E0[] = {
+ instrux + 3386,
+};
+
+static const struct itemplate * const itable_0FA7E8[] = {
+ instrux + 3387,
+};
+
+static const struct itemplate * const itable_0FA8[] = {
+ instrux + 850,
+};
+
+static const struct itemplate * const itable_0FA9[] = {
+ instrux + 798,
+};
+
+static const struct itemplate * const itable_0FAA[] = {
+ instrux + 944,
+};
+
+static const struct itemplate * const itable_0FAB[] = {
+ instrux + 148,
+ instrux + 149,
+ instrux + 150,
+ instrux + 151,
+ instrux + 152,
+ instrux + 153,
+};
+
+static const struct itemplate * const itable_0FAC[] = {
+ instrux + 1032,
+ instrux + 1033,
+ instrux + 1034,
+ instrux + 1035,
+ instrux + 1036,
+ instrux + 1037,
+};
+
+static const struct itemplate * const itable_0FAD[] = {
+ instrux + 1038,
+ instrux + 1039,
+ instrux + 1040,
+ instrux + 1041,
+ instrux + 1042,
+ instrux + 1043,
+};
+
+static const struct itemplate * const itable_0FAE[] = {
+ instrux + 546,
+ instrux + 601,
+ instrux + 994,
+ instrux + 1454,
+ instrux + 1484,
+ instrux + 1491,
+ instrux + 1492,
+ instrux + 1493,
+ instrux + 1494,
+ instrux + 1497,
+ instrux + 1498,
+ instrux + 1501,
+ instrux + 1502,
+ instrux + 1505,
+ instrux + 1506,
+ instrux + 1515,
+ instrux + 1538,
+ instrux + 1543,
+ instrux + 1544,
+ instrux + 3358,
+ instrux + 3359,
+ instrux + 3360,
+ instrux + 3361,
+ instrux + 3365,
+ instrux + 3366,
+ instrux + 3367,
+ instrux + 3368,
+ instrux + 6775,
+ instrux + 6776,
+ instrux + 6777,
+ instrux + 6779,
+ instrux + 6780,
+ instrux + 6788,
+ instrux + 6789,
+ instrux + 6790,
+ instrux + 6791,
+ instrux + 6792,
+ instrux + 6965,
+ instrux + 6968,
+ instrux + 6969,
+};
+
+static const struct itemplate * const itable_0FAF[] = {
+ instrux + 445,
+ instrux + 446,
+ instrux + 447,
+ instrux + 448,
+ instrux + 449,
+ instrux + 450,
+};
+
+static const struct itemplate * const itable_0FB0[] = {
+ instrux + 217,
+ instrux + 218,
+};
+
+static const struct itemplate * const itable_0FB1[] = {
+ instrux + 219,
+ instrux + 220,
+ instrux + 221,
+ instrux + 222,
+ instrux + 223,
+ instrux + 224,
+};
+
+static const struct itemplate * const itable_0FB2[] = {
+ instrux + 595,
+ instrux + 596,
+ instrux + 597,
+};
+
+static const struct itemplate * const itable_0FB3[] = {
+ instrux + 139,
+ instrux + 140,
+ instrux + 141,
+ instrux + 142,
+ instrux + 143,
+ instrux + 144,
+};
+
+static const struct itemplate * const itable_0FB4[] = {
+ instrux + 547,
+ instrux + 548,
+ instrux + 549,
+};
+
+static const struct itemplate * const itable_0FB5[] = {
+ instrux + 551,
+ instrux + 552,
+ instrux + 553,
+};
+
+static const struct itemplate * const itable_0FB6[] = {
+ instrux + 673,
+ instrux + 674,
+ instrux + 675,
+ instrux + 677,
+};
+
+static const struct itemplate * const itable_0FB7[] = {
+ instrux + 676,
+ instrux + 678,
+};
+
+static const struct itemplate * const itable_0FB8[] = {
+ instrux + 522,
+ instrux + 523,
+ instrux + 524,
+ instrux + 1865,
+ instrux + 1866,
+ instrux + 1867,
+};
+
+static const struct itemplate * const itable_0FB9[] = {
+ instrux + 1133,
+ instrux + 1134,
+ instrux + 1135,
+};
+
+static const struct itemplate * const itable_0FBA[] = {
+ instrux + 127,
+ instrux + 128,
+ instrux + 129,
+ instrux + 136,
+ instrux + 137,
+ instrux + 138,
+ instrux + 145,
+ instrux + 146,
+ instrux + 147,
+ instrux + 154,
+ instrux + 155,
+ instrux + 156,
+};
+
+static const struct itemplate * const itable_0FBB[] = {
+ instrux + 130,
+ instrux + 131,
+ instrux + 132,
+ instrux + 133,
+ instrux + 134,
+ instrux + 135,
+};
+
+static const struct itemplate * const itable_0FBC[] = {
+ instrux + 107,
+ instrux + 108,
+ instrux + 109,
+ instrux + 110,
+ instrux + 111,
+ instrux + 112,
+ instrux + 4033,
+ instrux + 4034,
+ instrux + 4035,
+};
+
+static const struct itemplate * const itable_0FBD[] = {
+ instrux + 113,
+ instrux + 114,
+ instrux + 115,
+ instrux + 116,
+ instrux + 117,
+ instrux + 118,
+ instrux + 1793,
+ instrux + 1794,
+ instrux + 1795,
+};
+
+static const struct itemplate * const itable_0FBE[] = {
+ instrux + 666,
+ instrux + 667,
+ instrux + 668,
+ instrux + 670,
+};
+
+static const struct itemplate * const itable_0FBF[] = {
+ instrux + 669,
+ instrux + 671,
+};
+
+static const struct itemplate * const itable_0FC0[] = {
+ instrux + 1147,
+ instrux + 1148,
+};
+
+static const struct itemplate * const itable_0FC1[] = {
+ instrux + 1149,
+ instrux + 1150,
+ instrux + 1151,
+ instrux + 1152,
+ instrux + 1153,
+ instrux + 1154,
+};
+
+static const struct itemplate * const itable_0FC2[] = {
+ instrux + 1422,
+ instrux + 1423,
+ instrux + 1424,
+ instrux + 1425,
+ instrux + 1426,
+ instrux + 1427,
+ instrux + 1428,
+ instrux + 1429,
+ instrux + 1430,
+ instrux + 1431,
+ instrux + 1432,
+ instrux + 1433,
+ instrux + 1434,
+ instrux + 1435,
+ instrux + 1436,
+ instrux + 1437,
+ instrux + 1438,
+ instrux + 1439,
+ instrux + 1646,
+ instrux + 1647,
+ instrux + 1648,
+ instrux + 1649,
+ instrux + 1650,
+ instrux + 1651,
+ instrux + 1652,
+ instrux + 1653,
+ instrux + 1654,
+ instrux + 1655,
+ instrux + 1656,
+ instrux + 1657,
+ instrux + 1658,
+ instrux + 1659,
+ instrux + 1660,
+ instrux + 1661,
+ instrux + 1662,
+ instrux + 1663,
+};
+
+static const struct itemplate * const itable_0FC3[] = {
+ instrux + 1540,
+ instrux + 1541,
+};
+
+static const struct itemplate * const itable_0FC4[] = {
+ instrux + 1521,
+ instrux + 1522,
+ instrux + 1523,
+ instrux + 1584,
+ instrux + 1585,
+ instrux + 1586,
+};
+
+static const struct itemplate * const itable_0FC5[] = {
+ instrux + 1520,
+ instrux + 1583,
+};
+
+static const struct itemplate * const itable_0FC6[] = {
+ instrux + 1481,
+ instrux + 1709,
+};
+
+static const struct itemplate * const itable_0FC7[] = {
+ instrux + 225,
+ instrux + 226,
+ instrux + 1499,
+ instrux + 1500,
+ instrux + 1503,
+ instrux + 1504,
+ instrux + 1507,
+ instrux + 1508,
+ instrux + 1731,
+ instrux + 1736,
+ instrux + 1737,
+ instrux + 1746,
+ instrux + 3362,
+ instrux + 3363,
+ instrux + 3364,
+ instrux + 3377,
+ instrux + 3378,
+ instrux + 3379,
+ instrux + 6772,
+ instrux + 6773,
+ instrux + 6774,
+ instrux + 7401,
+};
+
+static const struct itemplate * const itable_0FC8[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FC9[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FCA[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FCB[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FCC[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FCD[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FCE[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FCF[] = {
+ instrux + 119,
+ instrux + 120,
+};
+
+static const struct itemplate * const itable_0FD0[] = {
+ instrux + 1718,
+ instrux + 1719,
+};
+
+static const struct itemplate * const itable_0FD1[] = {
+ instrux + 823,
+ instrux + 1618,
+};
+
+static const struct itemplate * const itable_0FD2[] = {
+ instrux + 819,
+ instrux + 1620,
+};
+
+static const struct itemplate * const itable_0FD3[] = {
+ instrux + 821,
+ instrux + 1622,
+};
+
+static const struct itemplate * const itable_0FD4[] = {
+ instrux + 1567,
+ instrux + 1568,
+};
+
+static const struct itemplate * const itable_0FD5[] = {
+ instrux + 783,
+ instrux + 1595,
+};
+
+static const struct itemplate * const itable_0FD6[] = {
+ instrux + 1553,
+ instrux + 1555,
+ instrux + 1556,
+ instrux + 1560,
+};
+
+static const struct itemplate * const itable_0FD7[] = {
+ instrux + 1528,
+ instrux + 1592,
+};
+
+static const struct itemplate * const itable_0FD8[] = {
+ instrux + 830,
+ instrux + 1631,
+};
+
+static const struct itemplate * const itable_0FD9[] = {
+ instrux + 831,
+ instrux + 1632,
+};
+
+static const struct itemplate * const itable_0FDA[] = {
+ instrux + 1527,
+ instrux + 1591,
+};
+
+static const struct itemplate * const itable_0FDB[] = {
+ instrux + 747,
+ instrux + 1573,
+};
+
+static const struct itemplate * const itable_0FDC[] = {
+ instrux + 744,
+ instrux + 1571,
+};
+
+static const struct itemplate * const itable_0FDD[] = {
+ instrux + 745,
+ instrux + 1572,
+};
+
+static const struct itemplate * const itable_0FDE[] = {
+ instrux + 1525,
+ instrux + 1589,
+};
+
+static const struct itemplate * const itable_0FDF[] = {
+ instrux + 748,
+ instrux + 1574,
+};
+
+static const struct itemplate * const itable_0FE0[] = {
+ instrux + 1518,
+ instrux + 1575,
+};
+
+static const struct itemplate * const itable_0FE1[] = {
+ instrux + 817,
+ instrux + 1613,
+};
+
+static const struct itemplate * const itable_0FE2[] = {
+ instrux + 815,
+ instrux + 1615,
+};
+
+static const struct itemplate * const itable_0FE3[] = {
+ instrux + 1519,
+ instrux + 1576,
+};
+
+static const struct itemplate * const itable_0FE4[] = {
+ instrux + 1529,
+ instrux + 1593,
+};
+
+static const struct itemplate * const itable_0FE5[] = {
+ instrux + 782,
+ instrux + 1594,
+};
+
+static const struct itemplate * const itable_0FE6[] = {
+ instrux + 1665,
+ instrux + 1667,
+ instrux + 1682,
+};
+
+static const struct itemplate * const itable_0FE7[] = {
+ instrux + 1517,
+ instrux + 1539,
+};
+
+static const struct itemplate * const itable_0FE8[] = {
+ instrux + 827,
+ instrux + 1629,
+};
+
+static const struct itemplate * const itable_0FE9[] = {
+ instrux + 829,
+ instrux + 1630,
+};
+
+static const struct itemplate * const itable_0FEA[] = {
+ instrux + 1526,
+ instrux + 1590,
+};
+
+static const struct itemplate * const itable_0FEB[] = {
+ instrux + 806,
+ instrux + 1598,
+};
+
+static const struct itemplate * const itable_0FEC[] = {
+ instrux + 741,
+ instrux + 1569,
+};
+
+static const struct itemplate * const itable_0FED[] = {
+ instrux + 743,
+ instrux + 1570,
+};
+
+static const struct itemplate * const itable_0FEE[] = {
+ instrux + 1524,
+ instrux + 1588,
+};
+
+static const struct itemplate * const itable_0FEF[] = {
+ instrux + 864,
+ instrux + 1641,
+};
+
+static const struct itemplate * const itable_0FF0[] = {
+ instrux + 1724,
+};
+
+static const struct itemplate * const itable_0FF1[] = {
+ instrux + 813,
+ instrux + 1607,
+};
+
+static const struct itemplate * const itable_0FF2[] = {
+ instrux + 809,
+ instrux + 1609,
+};
+
+static const struct itemplate * const itable_0FF3[] = {
+ instrux + 811,
+ instrux + 1611,
+};
+
+static const struct itemplate * const itable_0FF4[] = {
+ instrux + 1596,
+ instrux + 1597,
+};
+
+static const struct itemplate * const itable_0FF5[] = {
+ instrux + 777,
+ instrux + 1587,
+};
+
+static const struct itemplate * const itable_0FF6[] = {
+ instrux + 1530,
+ instrux + 1599,
+};
+
+static const struct itemplate * const itable_0FF7[] = {
+ instrux + 1516,
+ instrux + 1537,
+};
+
+static const struct itemplate * const itable_0FF8[] = {
+ instrux + 825,
+ instrux + 1624,
+};
+
+static const struct itemplate * const itable_0FF9[] = {
+ instrux + 832,
+ instrux + 1625,
+};
+
+static const struct itemplate * const itable_0FFA[] = {
+ instrux + 826,
+ instrux + 1626,
+};
+
+static const struct itemplate * const itable_0FFB[] = {
+ instrux + 1627,
+ instrux + 1628,
+};
+
+static const struct itemplate * const itable_0FFC[] = {
+ instrux + 739,
+ instrux + 1564,
+};
+
+static const struct itemplate * const itable_0FFD[] = {
+ instrux + 746,
+ instrux + 1565,
+};
+
+static const struct itemplate * const itable_0FFE[] = {
+ instrux + 740,
+ instrux + 1566,
+};
+
+static const struct itemplate * const itable_0FFF[] = {
+ instrux + 1129,
+ instrux + 1130,
+ instrux + 1131,
+ instrux + 1132,
+};
+
+static const struct itemplate * const itable_10[] = {
+ instrux + 14,
+ instrux + 15,
+};
+
+static const struct itemplate * const itable_11[] = {
+ instrux + 16,
+ instrux + 17,
+ instrux + 18,
+ instrux + 19,
+ instrux + 20,
+ instrux + 21,
+};
+
+static const struct itemplate * const itable_12[] = {
+ instrux + 22,
+ instrux + 23,
+};
+
+static const struct itemplate * const itable_13[] = {
+ instrux + 24,
+ instrux + 25,
+ instrux + 26,
+ instrux + 27,
+ instrux + 28,
+ instrux + 29,
+};
+
+static const struct itemplate * const itable_14[] = {
+ instrux + 33,
+};
+
+static const struct itemplate * const itable_15[] = {
+ instrux + 34,
+ instrux + 35,
+ instrux + 36,
+};
+
+static const struct itemplate * const itable_16[] = {
+ instrux + 847,
+};
+
+static const struct itemplate * const itable_17[] = {
+ instrux + 795,
+};
+
+static const struct itemplate * const itable_18[] = {
+ instrux + 960,
+ instrux + 961,
+};
+
+static const struct itemplate * const itable_19[] = {
+ instrux + 962,
+ instrux + 963,
+ instrux + 964,
+ instrux + 965,
+ instrux + 966,
+ instrux + 967,
+};
+
+static const struct itemplate * const itable_1A[] = {
+ instrux + 968,
+ instrux + 969,
+};
+
+static const struct itemplate * const itable_1B[] = {
+ instrux + 970,
+ instrux + 971,
+ instrux + 972,
+ instrux + 973,
+ instrux + 974,
+ instrux + 975,
+};
+
+static const struct itemplate * const itable_1C[] = {
+ instrux + 979,
+};
+
+static const struct itemplate * const itable_1D[] = {
+ instrux + 980,
+ instrux + 981,
+ instrux + 982,
+};
+
+static const struct itemplate * const itable_1E[] = {
+ instrux + 848,
+};
+
+static const struct itemplate * const itable_1F[] = {
+ instrux + 796,
+};
+
+static const struct itemplate * const itable_20[] = {
+ instrux + 73,
+ instrux + 74,
+};
+
+static const struct itemplate * const itable_21[] = {
+ instrux + 75,
+ instrux + 76,
+ instrux + 77,
+ instrux + 78,
+ instrux + 79,
+ instrux + 80,
+};
+
+static const struct itemplate * const itable_22[] = {
+ instrux + 81,
+ instrux + 82,
+};
+
+static const struct itemplate * const itable_23[] = {
+ instrux + 83,
+ instrux + 84,
+ instrux + 85,
+ instrux + 86,
+ instrux + 87,
+ instrux + 88,
+};
+
+static const struct itemplate * const itable_24[] = {
+ instrux + 92,
+};
+
+static const struct itemplate * const itable_25[] = {
+ instrux + 93,
+ instrux + 94,
+ instrux + 95,
+};
+
+static const struct itemplate * const itable_27[] = {
+ instrux + 233,
+};
+
+static const struct itemplate * const itable_28[] = {
+ instrux + 1069,
+ instrux + 1070,
+};
+
+static const struct itemplate * const itable_29[] = {
+ instrux + 1071,
+ instrux + 1072,
+ instrux + 1073,
+ instrux + 1074,
+ instrux + 1075,
+ instrux + 1076,
+};
+
+static const struct itemplate * const itable_2A[] = {
+ instrux + 1077,
+ instrux + 1078,
+};
+
+static const struct itemplate * const itable_2B[] = {
+ instrux + 1079,
+ instrux + 1080,
+ instrux + 1081,
+ instrux + 1082,
+ instrux + 1083,
+ instrux + 1084,
+};
+
+static const struct itemplate * const itable_2C[] = {
+ instrux + 1088,
+};
+
+static const struct itemplate * const itable_2D[] = {
+ instrux + 1089,
+ instrux + 1090,
+ instrux + 1091,
+};
+
+static const struct itemplate * const itable_2F[] = {
+ instrux + 234,
+};
+
+static const struct itemplate * const itable_30[] = {
+ instrux + 1180,
+ instrux + 1181,
+};
+
+static const struct itemplate * const itable_31[] = {
+ instrux + 1182,
+ instrux + 1183,
+ instrux + 1184,
+ instrux + 1185,
+ instrux + 1186,
+ instrux + 1187,
+};
+
+static const struct itemplate * const itable_32[] = {
+ instrux + 1188,
+ instrux + 1189,
+};
+
+static const struct itemplate * const itable_33[] = {
+ instrux + 1190,
+ instrux + 1191,
+ instrux + 1192,
+ instrux + 1193,
+ instrux + 1194,
+ instrux + 1195,
+};
+
+static const struct itemplate * const itable_34[] = {
+ instrux + 1199,
+};
+
+static const struct itemplate * const itable_35[] = {
+ instrux + 1200,
+ instrux + 1201,
+ instrux + 1202,
+};
+
+static const struct itemplate * const itable_37[] = {
+ instrux + 8,
+};
+
+static const struct itemplate * const itable_38[] = {
+ instrux + 183,
+ instrux + 184,
+};
+
+static const struct itemplate * const itable_39[] = {
+ instrux + 185,
+ instrux + 186,
+ instrux + 187,
+ instrux + 188,
+ instrux + 189,
+ instrux + 190,
+};
+
+static const struct itemplate * const itable_3A[] = {
+ instrux + 191,
+ instrux + 192,
+};
+
+static const struct itemplate * const itable_3B[] = {
+ instrux + 193,
+ instrux + 194,
+ instrux + 195,
+ instrux + 196,
+ instrux + 197,
+ instrux + 198,
+};
+
+static const struct itemplate * const itable_3C[] = {
+ instrux + 202,
+};
+
+static const struct itemplate * const itable_3D[] = {
+ instrux + 203,
+ instrux + 204,
+ instrux + 205,
+};
+
+static const struct itemplate * const itable_3F[] = {
+ instrux + 13,
+};
+
+static const struct itemplate * const itable_40[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_41[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_42[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_43[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_44[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_45[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_46[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_47[] = {
+ instrux + 475,
+ instrux + 476,
+};
+
+static const struct itemplate * const itable_48[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_49[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_4A[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_4B[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_4C[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_4D[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_4E[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_4F[] = {
+ instrux + 235,
+ instrux + 236,
+};
+
+static const struct itemplate * const itable_50[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_51[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_52[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_53[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_54[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_55[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_56[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_57[] = {
+ instrux + 839,
+ instrux + 840,
+ instrux + 841,
+};
+
+static const struct itemplate * const itable_58[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_59[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_5A[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_5B[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_5C[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_5D[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_5E[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_5F[] = {
+ instrux + 788,
+ instrux + 789,
+ instrux + 790,
+};
+
+static const struct itemplate * const itable_60[] = {
+ instrux + 857,
+ instrux + 858,
+ instrux + 859,
+};
+
+static const struct itemplate * const itable_61[] = {
+ instrux + 799,
+ instrux + 800,
+ instrux + 801,
+};
+
+static const struct itemplate * const itable_62[] = {
+ instrux + 105,
+ instrux + 106,
+};
+
+static const struct itemplate * const itable_63[] = {
+ instrux + 103,
+ instrux + 104,
+ instrux + 672,
+};
+
+static const struct itemplate * const itable_68[] = {
+ instrux + 852,
+ instrux + 853,
+ instrux + 854,
+ instrux + 855,
+ instrux + 856,
+};
+
+static const struct itemplate * const itable_69[] = {
+ instrux + 452,
+ instrux + 454,
+ instrux + 456,
+ instrux + 458,
+ instrux + 460,
+ instrux + 462,
+ instrux + 464,
+ instrux + 466,
+ instrux + 468,
+};
+
+static const struct itemplate * const itable_6A[] = {
+ instrux + 851,
+};
+
+static const struct itemplate * const itable_6B[] = {
+ instrux + 451,
+ instrux + 453,
+ instrux + 455,
+ instrux + 457,
+ instrux + 459,
+ instrux + 461,
+ instrux + 463,
+ instrux + 465,
+ instrux + 467,
+};
+
+static const struct itemplate * const itable_6C[] = {
+ instrux + 481,
+};
+
+static const struct itemplate * const itable_6D[] = {
+ instrux + 482,
+ instrux + 483,
+};
+
+static const struct itemplate * const itable_6E[] = {
+ instrux + 733,
+};
+
+static const struct itemplate * const itable_6F[] = {
+ instrux + 734,
+ instrux + 735,
+};
+
+static const struct itemplate * const itable_70[] = {
+ instrux + 1381,
+};
+
+static const struct itemplate * const itable_71[] = {
+ instrux + 1378,
+};
+
+static const struct itemplate * const itable_72[] = {
+ instrux + 1371,
+};
+
+static const struct itemplate * const itable_73[] = {
+ instrux + 1375,
+};
+
+static const struct itemplate * const itable_74[] = {
+ instrux + 1385,
+};
+
+static const struct itemplate * const itable_75[] = {
+ instrux + 1380,
+};
+
+static const struct itemplate * const itable_76[] = {
+ instrux + 1374,
+};
+
+static const struct itemplate * const itable_77[] = {
+ instrux + 1370,
+};
+
+static const struct itemplate * const itable_78[] = {
+ instrux + 1384,
+};
+
+static const struct itemplate * const itable_79[] = {
+ instrux + 1379,
+};
+
+static const struct itemplate * const itable_7A[] = {
+ instrux + 1382,
+};
+
+static const struct itemplate * const itable_7B[] = {
+ instrux + 1383,
+};
+
+static const struct itemplate * const itable_7C[] = {
+ instrux + 1373,
+};
+
+static const struct itemplate * const itable_7D[] = {
+ instrux + 1377,
+};
+
+static const struct itemplate * const itable_7E[] = {
+ instrux + 1376,
+};
+
+static const struct itemplate * const itable_7F[] = {
+ instrux + 1372,
+};
+
+static const struct itemplate * const itable_80[] = {
+ instrux + 37,
+ instrux + 66,
+ instrux + 70,
+ instrux + 96,
+ instrux + 100,
+ instrux + 206,
+ instrux + 210,
+ instrux + 720,
+ instrux + 724,
+ instrux + 983,
+ instrux + 987,
+ instrux + 1092,
+ instrux + 1096,
+ instrux + 1203,
+ instrux + 1207,
+};
+
+static const struct itemplate * const itable_81[] = {
+ instrux + 38,
+ instrux + 39,
+ instrux + 40,
+ instrux + 41,
+ instrux + 42,
+ instrux + 67,
+ instrux + 68,
+ instrux + 69,
+ instrux + 71,
+ instrux + 72,
+ instrux + 97,
+ instrux + 98,
+ instrux + 99,
+ instrux + 101,
+ instrux + 102,
+ instrux + 207,
+ instrux + 208,
+ instrux + 209,
+ instrux + 211,
+ instrux + 212,
+ instrux + 721,
+ instrux + 722,
+ instrux + 723,
+ instrux + 725,
+ instrux + 726,
+ instrux + 984,
+ instrux + 985,
+ instrux + 986,
+ instrux + 988,
+ instrux + 989,
+ instrux + 1093,
+ instrux + 1094,
+ instrux + 1095,
+ instrux + 1097,
+ instrux + 1098,
+ instrux + 1204,
+ instrux + 1205,
+ instrux + 1206,
+ instrux + 1208,
+ instrux + 1209,
+};
+
+static const struct itemplate * const itable_83[] = {
+ instrux + 30,
+ instrux + 31,
+ instrux + 32,
+ instrux + 59,
+ instrux + 60,
+ instrux + 61,
+ instrux + 89,
+ instrux + 90,
+ instrux + 91,
+ instrux + 199,
+ instrux + 200,
+ instrux + 201,
+ instrux + 713,
+ instrux + 714,
+ instrux + 715,
+ instrux + 976,
+ instrux + 977,
+ instrux + 978,
+ instrux + 1085,
+ instrux + 1086,
+ instrux + 1087,
+ instrux + 1196,
+ instrux + 1197,
+ instrux + 1198,
+};
+
+static const struct itemplate * const itable_84[] = {
+ instrux + 1106,
+ instrux + 1107,
+ instrux + 1114,
+};
+
+static const struct itemplate * const itable_85[] = {
+ instrux + 1108,
+ instrux + 1109,
+ instrux + 1110,
+ instrux + 1111,
+ instrux + 1112,
+ instrux + 1113,
+ instrux + 1115,
+ instrux + 1116,
+ instrux + 1117,
+};
+
+static const struct itemplate * const itable_86[] = {
+ instrux + 1162,
+ instrux + 1163,
+ instrux + 1170,
+ instrux + 1171,
+};
+
+static const struct itemplate * const itable_87[] = {
+ instrux + 1164,
+ instrux + 1165,
+ instrux + 1166,
+ instrux + 1167,
+ instrux + 1168,
+ instrux + 1169,
+ instrux + 1172,
+ instrux + 1173,
+ instrux + 1174,
+ instrux + 1175,
+ instrux + 1176,
+ instrux + 1177,
+};
+
+static const struct itemplate * const itable_88[] = {
+ instrux + 628,
+ instrux + 629,
+};
+
+static const struct itemplate * const itable_89[] = {
+ instrux + 630,
+ instrux + 631,
+ instrux + 632,
+ instrux + 633,
+ instrux + 634,
+ instrux + 635,
+};
+
+static const struct itemplate * const itable_8A[] = {
+ instrux + 636,
+ instrux + 637,
+};
+
+static const struct itemplate * const itable_8B[] = {
+ instrux + 638,
+ instrux + 639,
+ instrux + 640,
+ instrux + 641,
+ instrux + 642,
+ instrux + 643,
+};
+
+static const struct itemplate * const itable_8C[] = {
+ instrux + 604,
+ instrux + 605,
+ instrux + 606,
+ instrux + 607,
+};
+
+static const struct itemplate * const itable_8D[] = {
+ instrux + 540,
+ instrux + 541,
+ instrux + 542,
+};
+
+static const struct itemplate * const itable_8E[] = {
+ instrux + 608,
+ instrux + 609,
+ instrux + 610,
+ instrux + 611,
+};
+
+static const struct itemplate * const itable_8F[] = {
+ instrux + 791,
+ instrux + 792,
+ instrux + 793,
+};
+
+static const struct itemplate * const itable_90[] = {
+ instrux + 689,
+ instrux + 749,
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+ instrux + 1161,
+};
+
+static const struct itemplate * const itable_91[] = {
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+};
+
+static const struct itemplate * const itable_92[] = {
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+};
+
+static const struct itemplate * const itable_93[] = {
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+};
+
+static const struct itemplate * const itable_94[] = {
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+};
+
+static const struct itemplate * const itable_95[] = {
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+};
+
+static const struct itemplate * const itable_96[] = {
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+};
+
+static const struct itemplate * const itable_97[] = {
+ instrux + 1155,
+ instrux + 1156,
+ instrux + 1157,
+ instrux + 1158,
+ instrux + 1159,
+ instrux + 1160,
+};
+
+static const struct itemplate * const itable_98[] = {
+ instrux + 175,
+ instrux + 177,
+ instrux + 232,
+};
+
+static const struct itemplate * const itable_99[] = {
+ instrux + 176,
+ instrux + 230,
+ instrux + 231,
+};
+
+static const struct itemplate * const itable_9A[] = {
+ instrux + 161,
+ instrux + 162,
+ instrux + 163,
+ instrux + 164,
+ instrux + 165,
+};
+
+static const struct itemplate * const itable_9C[] = {
+ instrux + 860,
+ instrux + 861,
+ instrux + 862,
+ instrux + 863,
+};
+
+static const struct itemplate * const itable_9D[] = {
+ instrux + 802,
+ instrux + 803,
+ instrux + 804,
+ instrux + 805,
+};
+
+static const struct itemplate * const itable_9E[] = {
+ instrux + 946,
+};
+
+static const struct itemplate * const itable_9F[] = {
+ instrux + 527,
+};
+
+static const struct itemplate * const itable_A0[] = {
+ instrux + 612,
+};
+
+static const struct itemplate * const itable_A1[] = {
+ instrux + 613,
+ instrux + 614,
+ instrux + 615,
+};
+
+static const struct itemplate * const itable_A2[] = {
+ instrux + 616,
+};
+
+static const struct itemplate * const itable_A3[] = {
+ instrux + 617,
+ instrux + 618,
+ instrux + 619,
+};
+
+static const struct itemplate * const itable_A4[] = {
+ instrux + 662,
+};
+
+static const struct itemplate * const itable_A5[] = {
+ instrux + 663,
+ instrux + 664,
+ instrux + 665,
+};
+
+static const struct itemplate * const itable_A6[] = {
+ instrux + 213,
+};
+
+static const struct itemplate * const itable_A7[] = {
+ instrux + 214,
+ instrux + 215,
+ instrux + 216,
+};
+
+static const struct itemplate * const itable_A8[] = {
+ instrux + 1118,
+};
+
+static const struct itemplate * const itable_A9[] = {
+ instrux + 1119,
+ instrux + 1120,
+ instrux + 1121,
+};
+
+static const struct itemplate * const itable_AA[] = {
+ instrux + 1060,
+};
+
+static const struct itemplate * const itable_AB[] = {
+ instrux + 1061,
+ instrux + 1062,
+ instrux + 1063,
+};
+
+static const struct itemplate * const itable_AC[] = {
+ instrux + 561,
+};
+
+static const struct itemplate * const itable_AD[] = {
+ instrux + 562,
+ instrux + 563,
+ instrux + 564,
+};
+
+static const struct itemplate * const itable_AE[] = {
+ instrux + 990,
+};
+
+static const struct itemplate * const itable_AF[] = {
+ instrux + 991,
+ instrux + 992,
+ instrux + 993,
+};
+
+static const struct itemplate * const itable_B0[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B1[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B2[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B3[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B4[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B5[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B6[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B7[] = {
+ instrux + 644,
+};
+
+static const struct itemplate * const itable_B8[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_B9[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_BA[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_BB[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_BC[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_BD[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_BE[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_BF[] = {
+ instrux + 645,
+ instrux + 646,
+ instrux + 647,
+};
+
+static const struct itemplate * const itable_C0[] = {
+ instrux + 867,
+ instrux + 879,
+ instrux + 920,
+ instrux + 932,
+ instrux + 950,
+ instrux + 998,
+ instrux + 1022,
+};
+
+static const struct itemplate * const itable_C1[] = {
+ instrux + 870,
+ instrux + 873,
+ instrux + 876,
+ instrux + 882,
+ instrux + 885,
+ instrux + 888,
+ instrux + 923,
+ instrux + 926,
+ instrux + 929,
+ instrux + 935,
+ instrux + 938,
+ instrux + 941,
+ instrux + 953,
+ instrux + 956,
+ instrux + 959,
+ instrux + 1001,
+ instrux + 1004,
+ instrux + 1007,
+ instrux + 1025,
+ instrux + 1028,
+ instrux + 1031,
+};
+
+static const struct itemplate * const itable_C2[] = {
+ instrux + 895,
+ instrux + 899,
+ instrux + 901,
+ instrux + 905,
+ instrux + 907,
+ instrux + 911,
+ instrux + 913,
+ instrux + 917,
+};
+
+static const struct itemplate * const itable_C3[] = {
+ instrux + 894,
+ instrux + 898,
+ instrux + 900,
+ instrux + 904,
+ instrux + 906,
+ instrux + 910,
+ instrux + 912,
+ instrux + 916,
+};
+
+static const struct itemplate * const itable_C4[] = {
+ instrux + 544,
+ instrux + 545,
+};
+
+static const struct itemplate * const itable_C5[] = {
+ instrux + 538,
+ instrux + 539,
+};
+
+static const struct itemplate * const itable_C6[] = {
+ instrux + 648,
+ instrux + 653,
+ instrux + 3983,
+ instrux + 3984,
+};
+
+static const struct itemplate * const itable_C7[] = {
+ instrux + 649,
+ instrux + 650,
+ instrux + 651,
+ instrux + 652,
+ instrux + 654,
+ instrux + 655,
+ instrux + 3985,
+ instrux + 3986,
+ instrux + 3987,
+ instrux + 3988,
+};
+
+static const struct itemplate * const itable_C8[] = {
+ instrux + 247,
+};
+
+static const struct itemplate * const itable_C9[] = {
+ instrux + 543,
+};
+
+static const struct itemplate * const itable_CA[] = {
+ instrux + 897,
+ instrux + 903,
+ instrux + 909,
+ instrux + 915,
+};
+
+static const struct itemplate * const itable_CB[] = {
+ instrux + 896,
+ instrux + 902,
+ instrux + 908,
+ instrux + 914,
+};
+
+static const struct itemplate * const itable_CC[] = {
+ instrux + 486,
+};
+
+static const struct itemplate * const itable_CD[] = {
+ instrux + 484,
+};
+
+static const struct itemplate * const itable_CE[] = {
+ instrux + 487,
+};
+
+static const struct itemplate * const itable_CF[] = {
+ instrux + 496,
+ instrux + 497,
+ instrux + 498,
+ instrux + 499,
+};
+
+static const struct itemplate * const itable_D0[] = {
+ instrux + 865,
+ instrux + 877,
+ instrux + 918,
+ instrux + 930,
+ instrux + 948,
+ instrux + 996,
+ instrux + 1020,
+};
+
+static const struct itemplate * const itable_D1[] = {
+ instrux + 868,
+ instrux + 871,
+ instrux + 874,
+ instrux + 880,
+ instrux + 883,
+ instrux + 886,
+ instrux + 921,
+ instrux + 924,
+ instrux + 927,
+ instrux + 933,
+ instrux + 936,
+ instrux + 939,
+ instrux + 951,
+ instrux + 954,
+ instrux + 957,
+ instrux + 999,
+ instrux + 1002,
+ instrux + 1005,
+ instrux + 1023,
+ instrux + 1026,
+ instrux + 1029,
+};
+
+static const struct itemplate * const itable_D2[] = {
+ instrux + 866,
+ instrux + 878,
+ instrux + 919,
+ instrux + 931,
+ instrux + 949,
+ instrux + 997,
+ instrux + 1021,
+};
+
+static const struct itemplate * const itable_D3[] = {
+ instrux + 869,
+ instrux + 872,
+ instrux + 875,
+ instrux + 881,
+ instrux + 884,
+ instrux + 887,
+ instrux + 922,
+ instrux + 925,
+ instrux + 928,
+ instrux + 934,
+ instrux + 937,
+ instrux + 940,
+ instrux + 952,
+ instrux + 955,
+ instrux + 958,
+ instrux + 1000,
+ instrux + 1003,
+ instrux + 1006,
+ instrux + 1024,
+ instrux + 1027,
+ instrux + 1030,
+};
+
+static const struct itemplate * const itable_D4[] = {
+ instrux + 11,
+ instrux + 12,
+};
+
+static const struct itemplate * const itable_D5[] = {
+ instrux + 9,
+ instrux + 10,
+};
+
+static const struct itemplate * const itable_D6[] = {
+ instrux + 947,
+};
+
+static const struct itemplate * const itable_D7[] = {
+ instrux + 1178,
+ instrux + 1179,
+};
+
+static const struct itemplate * const itable_D8[] = {
+ instrux + 252,
+ instrux + 255,
+ instrux + 257,
+ instrux + 282,
+ instrux + 284,
+ instrux + 285,
+ instrux + 290,
+ instrux + 292,
+ instrux + 293,
+ instrux + 298,
+ instrux + 301,
+ instrux + 303,
+ instrux + 306,
+ instrux + 310,
+ instrux + 311,
+ instrux + 362,
+ instrux + 366,
+ instrux + 367,
+ instrux + 403,
+ instrux + 407,
+ instrux + 408,
+ instrux + 411,
+ instrux + 415,
+ instrux + 416,
+};
+
+static const struct itemplate * const itable_D9[] = {
+ instrux + 250,
+ instrux + 251,
+ instrux + 264,
+ instrux + 295,
+ instrux + 296,
+ instrux + 335,
+ instrux + 349,
+ instrux + 352,
+ instrux + 353,
+ instrux + 354,
+ instrux + 355,
+ instrux + 356,
+ instrux + 357,
+ instrux + 358,
+ instrux + 359,
+ instrux + 360,
+ instrux + 361,
+ instrux + 374,
+ instrux + 376,
+ instrux + 377,
+ instrux + 380,
+ instrux + 381,
+ instrux + 382,
+ instrux + 383,
+ instrux + 384,
+ instrux + 387,
+ instrux + 389,
+ instrux + 390,
+ instrux + 391,
+ instrux + 392,
+ instrux + 395,
+ instrux + 396,
+ instrux + 397,
+ instrux + 419,
+ instrux + 429,
+ instrux + 430,
+ instrux + 431,
+ instrux + 432,
+ instrux + 433,
+ instrux + 434,
+ instrux + 435,
+};
+
+static const struct itemplate * const itable_DA[] = {
+ instrux + 266,
+ instrux + 267,
+ instrux + 268,
+ instrux + 269,
+ instrux + 270,
+ instrux + 271,
+ instrux + 280,
+ instrux + 281,
+ instrux + 320,
+ instrux + 322,
+ instrux + 324,
+ instrux + 326,
+ instrux + 328,
+ instrux + 333,
+ instrux + 345,
+ instrux + 347,
+ instrux + 428,
+};
+
+static const struct itemplate * const itable_DB[] = {
+ instrux + 265,
+ instrux + 272,
+ instrux + 273,
+ instrux + 274,
+ instrux + 275,
+ instrux + 276,
+ instrux + 277,
+ instrux + 278,
+ instrux + 279,
+ instrux + 286,
+ instrux + 287,
+ instrux + 297,
+ instrux + 315,
+ instrux + 330,
+ instrux + 336,
+ instrux + 337,
+ instrux + 339,
+ instrux + 343,
+ instrux + 351,
+ instrux + 370,
+ instrux + 371,
+ instrux + 372,
+ instrux + 373,
+ instrux + 388,
+ instrux + 399,
+ instrux + 422,
+ instrux + 423,
+};
+
+static const struct itemplate * const itable_DC[] = {
+ instrux + 253,
+ instrux + 254,
+ instrux + 256,
+ instrux + 283,
+ instrux + 291,
+ instrux + 299,
+ instrux + 300,
+ instrux + 302,
+ instrux + 307,
+ instrux + 308,
+ instrux + 309,
+ instrux + 363,
+ instrux + 364,
+ instrux + 365,
+ instrux + 404,
+ instrux + 405,
+ instrux + 406,
+ instrux + 412,
+ instrux + 413,
+ instrux + 414,
+};
+
+static const struct itemplate * const itable_DD[] = {
+ instrux + 316,
+ instrux + 317,
+ instrux + 344,
+ instrux + 350,
+ instrux + 375,
+ instrux + 378,
+ instrux + 385,
+ instrux + 386,
+ instrux + 393,
+ instrux + 394,
+ instrux + 398,
+ instrux + 400,
+ instrux + 401,
+ instrux + 420,
+ instrux + 421,
+ instrux + 426,
+ instrux + 427,
+};
+
+static const struct itemplate * const itable_DE[] = {
+ instrux + 258,
+ instrux + 259,
+ instrux + 294,
+ instrux + 304,
+ instrux + 305,
+ instrux + 312,
+ instrux + 313,
+ instrux + 321,
+ instrux + 323,
+ instrux + 325,
+ instrux + 327,
+ instrux + 329,
+ instrux + 334,
+ instrux + 346,
+ instrux + 348,
+ instrux + 368,
+ instrux + 369,
+ instrux + 409,
+ instrux + 410,
+ instrux + 417,
+ instrux + 418,
+};
+
+static const struct itemplate * const itable_DF[] = {
+ instrux + 260,
+ instrux + 261,
+ instrux + 262,
+ instrux + 263,
+ instrux + 288,
+ instrux + 289,
+ instrux + 318,
+ instrux + 319,
+ instrux + 331,
+ instrux + 332,
+ instrux + 338,
+ instrux + 340,
+ instrux + 341,
+ instrux + 342,
+ instrux + 379,
+ instrux + 402,
+ instrux + 424,
+ instrux + 425,
+};
+
+static const struct itemplate * const itable_E0[] = {
+ instrux + 573,
+ instrux + 574,
+ instrux + 575,
+ instrux + 576,
+ instrux + 577,
+ instrux + 578,
+ instrux + 579,
+ instrux + 580,
+};
+
+static const struct itemplate * const itable_E1[] = {
+ instrux + 569,
+ instrux + 570,
+ instrux + 571,
+ instrux + 572,
+ instrux + 581,
+ instrux + 582,
+ instrux + 583,
+ instrux + 584,
+};
+
+static const struct itemplate * const itable_E2[] = {
+ instrux + 565,
+ instrux + 566,
+ instrux + 567,
+ instrux + 568,
+};
+
+static const struct itemplate * const itable_E3[] = {
+ instrux + 500,
+ instrux + 501,
+ instrux + 502,
+};
+
+static const struct itemplate * const itable_E4[] = {
+ instrux + 469,
+};
+
+static const struct itemplate * const itable_E5[] = {
+ instrux + 470,
+ instrux + 471,
+};
+
+static const struct itemplate * const itable_E6[] = {
+ instrux + 727,
+};
+
+static const struct itemplate * const itable_E7[] = {
+ instrux + 728,
+ instrux + 729,
+};
+
+static const struct itemplate * const itable_E8[] = {
+ instrux + 157,
+ instrux + 158,
+ instrux + 159,
+ instrux + 160,
+};
+
+static const struct itemplate * const itable_E9[] = {
+ instrux + 504,
+ instrux + 505,
+ instrux + 506,
+ instrux + 507,
+};
+
+static const struct itemplate * const itable_EA[] = {
+ instrux + 508,
+ instrux + 509,
+ instrux + 510,
+ instrux + 511,
+ instrux + 512,
+};
+
+static const struct itemplate * const itable_EB[] = {
+ instrux + 503,
+};
+
+static const struct itemplate * const itable_EC[] = {
+ instrux + 472,
+};
+
+static const struct itemplate * const itable_ED[] = {
+ instrux + 473,
+ instrux + 474,
+};
+
+static const struct itemplate * const itable_EE[] = {
+ instrux + 730,
+};
+
+static const struct itemplate * const itable_EF[] = {
+ instrux + 731,
+ instrux + 732,
+};
+
+static const struct itemplate * const itable_F1[] = {
+ instrux + 485,
+ instrux + 1051,
+};
+
+static const struct itemplate * const itable_F4[] = {
+ instrux + 436,
+};
+
+static const struct itemplate * const itable_F5[] = {
+ instrux + 182,
+};
+
+static const struct itemplate * const itable_F6[] = {
+ instrux + 241,
+ instrux + 437,
+ instrux + 441,
+ instrux + 679,
+ instrux + 685,
+ instrux + 693,
+ instrux + 1122,
+ instrux + 1126,
+};
+
+static const struct itemplate * const itable_F7[] = {
+ instrux + 242,
+ instrux + 243,
+ instrux + 244,
+ instrux + 438,
+ instrux + 439,
+ instrux + 440,
+ instrux + 442,
+ instrux + 443,
+ instrux + 444,
+ instrux + 680,
+ instrux + 681,
+ instrux + 682,
+ instrux + 686,
+ instrux + 687,
+ instrux + 688,
+ instrux + 694,
+ instrux + 695,
+ instrux + 696,
+ instrux + 1123,
+ instrux + 1124,
+ instrux + 1125,
+ instrux + 1127,
+ instrux + 1128,
+};
+
+static const struct itemplate * const itable_F8[] = {
+ instrux + 178,
+};
+
+static const struct itemplate * const itable_F9[] = {
+ instrux + 1057,
+};
+
+static const struct itemplate * const itable_FA[] = {
+ instrux + 180,
+};
+
+static const struct itemplate * const itable_FB[] = {
+ instrux + 1059,
+};
+
+static const struct itemplate * const itable_FC[] = {
+ instrux + 179,
+};
+
+static const struct itemplate * const itable_FD[] = {
+ instrux + 1058,
+};
+
+static const struct itemplate * const itable_FE[] = {
+ instrux + 237,
+ instrux + 477,
+};
+
+static const struct itemplate * const itable_FF[] = {
+ instrux + 166,
+ instrux + 167,
+ instrux + 168,
+ instrux + 169,
+ instrux + 170,
+ instrux + 171,
+ instrux + 172,
+ instrux + 173,
+ instrux + 174,
+ instrux + 238,
+ instrux + 239,
+ instrux + 240,
+ instrux + 478,
+ instrux + 479,
+ instrux + 480,
+ instrux + 513,
+ instrux + 514,
+ instrux + 515,
+ instrux + 516,
+ instrux + 517,
+ instrux + 518,
+ instrux + 519,
+ instrux + 520,
+ instrux + 521,
+ instrux + 842,
+ instrux + 843,
+ instrux + 844,
+};
+
+static const struct itemplate * const itable_evex01010[] = {
+ instrux + 5183,
+ instrux + 5184,
+ instrux + 5185,
+};
+
+static const struct itemplate * const itable_evex01011[] = {
+ instrux + 5186,
+ instrux + 5187,
+ instrux + 5188,
+ instrux + 5189,
+ instrux + 5190,
+ instrux + 5191,
+};
+
+static const struct itemplate * const itable_evex01012[] = {
+ instrux + 5124,
+ instrux + 5125,
+ instrux + 5137,
+ instrux + 5138,
+};
+
+static const struct itemplate * const itable_evex01013[] = {
+ instrux + 5139,
+};
+
+static const struct itemplate * const itable_evex01014[] = {
+ instrux + 6752,
+ instrux + 6753,
+ instrux + 6754,
+ instrux + 6755,
+ instrux + 6756,
+ instrux + 6757,
+};
+
+static const struct itemplate * const itable_evex01015[] = {
+ instrux + 6740,
+ instrux + 6741,
+ instrux + 6742,
+ instrux + 6743,
+ instrux + 6744,
+ instrux + 6745,
+};
+
+static const struct itemplate * const itable_evex01016[] = {
+ instrux + 5129,
+ instrux + 5130,
+ instrux + 5132,
+ instrux + 5133,
+};
+
+static const struct itemplate * const itable_evex01017[] = {
+ instrux + 5131,
+};
+
+static const struct itemplate * const itable_evex01028[] = {
+ instrux + 5074,
+ instrux + 5075,
+ instrux + 5076,
+};
+
+static const struct itemplate * const itable_evex01029[] = {
+ instrux + 5077,
+ instrux + 5078,
+ instrux + 5079,
+ instrux + 5080,
+ instrux + 5081,
+ instrux + 5082,
+};
+
+static const struct itemplate * const itable_evex0102B[] = {
+ instrux + 5149,
+ instrux + 5150,
+ instrux + 5151,
+};
+
+static const struct itemplate * const itable_evex0102E[] = {
+ instrux + 6733,
+};
+
+static const struct itemplate * const itable_evex0102F[] = {
+ instrux + 4626,
+};
+
+static const struct itemplate * const itable_evex01051[] = {
+ instrux + 6709,
+ instrux + 6710,
+ instrux + 6711,
+};
+
+static const struct itemplate * const itable_evex01054[] = {
+ instrux + 4210,
+ instrux + 4211,
+ instrux + 4212,
+ instrux + 4213,
+ instrux + 4214,
+ instrux + 4215,
+};
+
+static const struct itemplate * const itable_evex01055[] = {
+ instrux + 4198,
+ instrux + 4199,
+ instrux + 4200,
+ instrux + 4201,
+ instrux + 4202,
+ instrux + 4203,
+};
+
+static const struct itemplate * const itable_evex01056[] = {
+ instrux + 5214,
+ instrux + 5215,
+ instrux + 5216,
+ instrux + 5217,
+ instrux + 5218,
+ instrux + 5219,
+};
+
+static const struct itemplate * const itable_evex01057[] = {
+ instrux + 6764,
+ instrux + 6765,
+ instrux + 6766,
+ instrux + 6767,
+ instrux + 6768,
+ instrux + 6769,
+};
+
+static const struct itemplate * const itable_evex01058[] = {
+ instrux + 4170,
+ instrux + 4171,
+ instrux + 4172,
+ instrux + 4173,
+ instrux + 4174,
+ instrux + 4175,
+};
+
+static const struct itemplate * const itable_evex01059[] = {
+ instrux + 5198,
+ instrux + 5199,
+ instrux + 5200,
+ instrux + 5201,
+ instrux + 5202,
+ instrux + 5203,
+};
+
+static const struct itemplate * const itable_evex0105A[] = {
+ instrux + 4666,
+ instrux + 4667,
+ instrux + 4668,
+};
+
+static const struct itemplate * const itable_evex0105B[] = {
+ instrux + 4642,
+ instrux + 4643,
+ instrux + 4644,
+ instrux + 4687,
+ instrux + 4688,
+ instrux + 4689,
+};
+
+static const struct itemplate * const itable_evex0105C[] = {
+ instrux + 6722,
+ instrux + 6723,
+ instrux + 6724,
+ instrux + 6725,
+ instrux + 6726,
+ instrux + 6727,
+};
+
+static const struct itemplate * const itable_evex0105D[] = {
+ instrux + 5055,
+ instrux + 5056,
+ instrux + 5057,
+ instrux + 5058,
+ instrux + 5059,
+ instrux + 5060,
+};
+
+static const struct itemplate * const itable_evex0105E[] = {
+ instrux + 4764,
+ instrux + 4765,
+ instrux + 4766,
+ instrux + 4767,
+ instrux + 4768,
+ instrux + 4769,
+};
+
+static const struct itemplate * const itable_evex0105F[] = {
+ instrux + 5039,
+ instrux + 5040,
+ instrux + 5041,
+ instrux + 5042,
+ instrux + 5043,
+ instrux + 5044,
+};
+
+static const struct itemplate * const itable_evex01078[] = {
+ instrux + 4710,
+ instrux + 4711,
+ instrux + 4712,
+ instrux + 4722,
+ instrux + 4723,
+ instrux + 4724,
+};
+
+static const struct itemplate * const itable_evex01079[] = {
+ instrux + 4654,
+ instrux + 4655,
+ instrux + 4656,
+ instrux + 4678,
+ instrux + 4679,
+ instrux + 4680,
+};
+
+static const struct itemplate * const itable_evex010C2[] = {
+ instrux + 4252,
+ instrux + 4253,
+ instrux + 4254,
+ instrux + 4260,
+ instrux + 4261,
+ instrux + 4262,
+ instrux + 4268,
+ instrux + 4269,
+ instrux + 4270,
+ instrux + 4276,
+ instrux + 4277,
+ instrux + 4278,
+ instrux + 4284,
+ instrux + 4285,
+ instrux + 4286,
+ instrux + 4292,
+ instrux + 4293,
+ instrux + 4294,
+ instrux + 4300,
+ instrux + 4301,
+ instrux + 4302,
+ instrux + 4308,
+ instrux + 4309,
+ instrux + 4310,
+ instrux + 4316,
+ instrux + 4317,
+ instrux + 4318,
+ instrux + 4324,
+ instrux + 4325,
+ instrux + 4326,
+ instrux + 4332,
+ instrux + 4333,
+ instrux + 4334,
+ instrux + 4340,
+ instrux + 4341,
+ instrux + 4342,
+ instrux + 4348,
+ instrux + 4349,
+ instrux + 4350,
+ instrux + 4356,
+ instrux + 4357,
+ instrux + 4358,
+ instrux + 4364,
+ instrux + 4365,
+ instrux + 4366,
+ instrux + 4372,
+ instrux + 4373,
+ instrux + 4374,
+ instrux + 4380,
+ instrux + 4381,
+ instrux + 4382,
+ instrux + 4388,
+ instrux + 4389,
+ instrux + 4390,
+ instrux + 4396,
+ instrux + 4397,
+ instrux + 4398,
+ instrux + 4404,
+ instrux + 4405,
+ instrux + 4406,
+ instrux + 4412,
+ instrux + 4413,
+ instrux + 4414,
+ instrux + 4420,
+ instrux + 4421,
+ instrux + 4422,
+ instrux + 4428,
+ instrux + 4429,
+ instrux + 4430,
+ instrux + 4436,
+ instrux + 4437,
+ instrux + 4438,
+ instrux + 4444,
+ instrux + 4445,
+ instrux + 4446,
+ instrux + 4452,
+ instrux + 4453,
+ instrux + 4454,
+ instrux + 4460,
+ instrux + 4461,
+ instrux + 4462,
+ instrux + 4468,
+ instrux + 4469,
+ instrux + 4470,
+ instrux + 4476,
+ instrux + 4477,
+ instrux + 4478,
+ instrux + 4484,
+ instrux + 4485,
+ instrux + 4486,
+ instrux + 4492,
+ instrux + 4493,
+ instrux + 4494,
+ instrux + 4500,
+ instrux + 4501,
+ instrux + 4502,
+ instrux + 4508,
+ instrux + 4509,
+ instrux + 4510,
+ instrux + 4516,
+ instrux + 4517,
+ instrux + 4518,
+ instrux + 4524,
+ instrux + 4525,
+ instrux + 4526,
+ instrux + 4532,
+ instrux + 4533,
+ instrux + 4534,
+ instrux + 4540,
+ instrux + 4541,
+ instrux + 4542,
+ instrux + 4548,
+ instrux + 4549,
+ instrux + 4550,
+ instrux + 4556,
+ instrux + 4557,
+ instrux + 4558,
+ instrux + 4564,
+ instrux + 4565,
+ instrux + 4566,
+ instrux + 4572,
+ instrux + 4573,
+ instrux + 4574,
+ instrux + 4580,
+ instrux + 4581,
+ instrux + 4582,
+ instrux + 4588,
+ instrux + 4589,
+ instrux + 4590,
+ instrux + 4596,
+ instrux + 4597,
+ instrux + 4598,
+ instrux + 4604,
+ instrux + 4605,
+ instrux + 4606,
+ instrux + 4612,
+ instrux + 4613,
+ instrux + 4614,
+ instrux + 4620,
+ instrux + 4621,
+ instrux + 4622,
+};
+
+static const struct itemplate * const itable_evex010C6[] = {
+ instrux + 6700,
+ instrux + 6701,
+ instrux + 6702,
+ instrux + 6703,
+ instrux + 6704,
+ instrux + 6705,
+};
+
+static const struct itemplate * const itable_evex01110[] = {
+ instrux + 5174,
+ instrux + 5175,
+ instrux + 5176,
+};
+
+static const struct itemplate * const itable_evex01111[] = {
+ instrux + 5177,
+ instrux + 5178,
+ instrux + 5179,
+ instrux + 5180,
+ instrux + 5181,
+ instrux + 5182,
+};
+
+static const struct itemplate * const itable_evex01112[] = {
+ instrux + 5134,
+ instrux + 5135,
+};
+
+static const struct itemplate * const itable_evex01113[] = {
+ instrux + 5136,
+};
+
+static const struct itemplate * const itable_evex01114[] = {
+ instrux + 6746,
+ instrux + 6747,
+ instrux + 6748,
+ instrux + 6749,
+ instrux + 6750,
+ instrux + 6751,
+};
+
+static const struct itemplate * const itable_evex01115[] = {
+ instrux + 6734,
+ instrux + 6735,
+ instrux + 6736,
+ instrux + 6737,
+ instrux + 6738,
+ instrux + 6739,
+};
+
+static const struct itemplate * const itable_evex01116[] = {
+ instrux + 5126,
+ instrux + 5127,
+};
+
+static const struct itemplate * const itable_evex01117[] = {
+ instrux + 5128,
+};
+
+static const struct itemplate * const itable_evex01128[] = {
+ instrux + 5065,
+ instrux + 5066,
+ instrux + 5067,
+};
+
+static const struct itemplate * const itable_evex01129[] = {
+ instrux + 5068,
+ instrux + 5069,
+ instrux + 5070,
+ instrux + 5071,
+ instrux + 5072,
+ instrux + 5073,
+};
+
+static const struct itemplate * const itable_evex0112B[] = {
+ instrux + 5146,
+ instrux + 5147,
+ instrux + 5148,
+};
+
+static const struct itemplate * const itable_evex0112E[] = {
+ instrux + 6732,
+};
+
+static const struct itemplate * const itable_evex0112F[] = {
+ instrux + 4625,
+};
+
+static const struct itemplate * const itable_evex01151[] = {
+ instrux + 6706,
+ instrux + 6707,
+ instrux + 6708,
+};
+
+static const struct itemplate * const itable_evex01154[] = {
+ instrux + 4204,
+ instrux + 4205,
+ instrux + 4206,
+ instrux + 4207,
+ instrux + 4208,
+ instrux + 4209,
+};
+
+static const struct itemplate * const itable_evex01155[] = {
+ instrux + 4192,
+ instrux + 4193,
+ instrux + 4194,
+ instrux + 4195,
+ instrux + 4196,
+ instrux + 4197,
+};
+
+static const struct itemplate * const itable_evex01156[] = {
+ instrux + 5208,
+ instrux + 5209,
+ instrux + 5210,
+ instrux + 5211,
+ instrux + 5212,
+ instrux + 5213,
+};
+
+static const struct itemplate * const itable_evex01157[] = {
+ instrux + 6758,
+ instrux + 6759,
+ instrux + 6760,
+ instrux + 6761,
+ instrux + 6762,
+ instrux + 6763,
+};
+
+static const struct itemplate * const itable_evex01158[] = {
+ instrux + 4164,
+ instrux + 4165,
+ instrux + 4166,
+ instrux + 4167,
+ instrux + 4168,
+ instrux + 4169,
+};
+
+static const struct itemplate * const itable_evex01159[] = {
+ instrux + 5192,
+ instrux + 5193,
+ instrux + 5194,
+ instrux + 5195,
+ instrux + 5196,
+ instrux + 5197,
+};
+
+static const struct itemplate * const itable_evex0115A[] = {
+ instrux + 4648,
+ instrux + 4649,
+ instrux + 4650,
+};
+
+static const struct itemplate * const itable_evex0115B[] = {
+ instrux + 4663,
+ instrux + 4664,
+ instrux + 4665,
+};
+
+static const struct itemplate * const itable_evex0115C[] = {
+ instrux + 6716,
+ instrux + 6717,
+ instrux + 6718,
+ instrux + 6719,
+ instrux + 6720,
+ instrux + 6721,
+};
+
+static const struct itemplate * const itable_evex0115D[] = {
+ instrux + 5049,
+ instrux + 5050,
+ instrux + 5051,
+ instrux + 5052,
+ instrux + 5053,
+ instrux + 5054,
+};
+
+static const struct itemplate * const itable_evex0115E[] = {
+ instrux + 4758,
+ instrux + 4759,
+ instrux + 4760,
+ instrux + 4761,
+ instrux + 4762,
+ instrux + 4763,
+};
+
+static const struct itemplate * const itable_evex0115F[] = {
+ instrux + 5033,
+ instrux + 5034,
+ instrux + 5035,
+ instrux + 5036,
+ instrux + 5037,
+ instrux + 5038,
+};
+
+static const struct itemplate * const itable_evex01160[] = {
+ instrux + 6538,
+ instrux + 6539,
+ instrux + 6540,
+ instrux + 6541,
+ instrux + 6542,
+ instrux + 6543,
+};
+
+static const struct itemplate * const itable_evex01161[] = {
+ instrux + 6556,
+ instrux + 6557,
+ instrux + 6558,
+ instrux + 6559,
+ instrux + 6560,
+ instrux + 6561,
+};
+
+static const struct itemplate * const itable_evex01162[] = {
+ instrux + 6544,
+ instrux + 6545,
+ instrux + 6546,
+ instrux + 6547,
+ instrux + 6548,
+ instrux + 6549,
+};
+
+static const struct itemplate * const itable_evex01163[] = {
+ instrux + 5238,
+ instrux + 5239,
+ instrux + 5240,
+ instrux + 5241,
+ instrux + 5242,
+ instrux + 5243,
+};
+
+static const struct itemplate * const itable_evex01164[] = {
+ instrux + 5421,
+ instrux + 5422,
+ instrux + 5423,
+};
+
+static const struct itemplate * const itable_evex01165[] = {
+ instrux + 5430,
+ instrux + 5431,
+ instrux + 5432,
+};
+
+static const struct itemplate * const itable_evex01166[] = {
+ instrux + 5424,
+ instrux + 5425,
+ instrux + 5426,
+};
+
+static const struct itemplate * const itable_evex01167[] = {
+ instrux + 5250,
+ instrux + 5251,
+ instrux + 5252,
+ instrux + 5253,
+ instrux + 5254,
+ instrux + 5255,
+};
+
+static const struct itemplate * const itable_evex01168[] = {
+ instrux + 6514,
+ instrux + 6515,
+ instrux + 6516,
+ instrux + 6517,
+ instrux + 6518,
+ instrux + 6519,
+};
+
+static const struct itemplate * const itable_evex01169[] = {
+ instrux + 6532,
+ instrux + 6533,
+ instrux + 6534,
+ instrux + 6535,
+ instrux + 6536,
+ instrux + 6537,
+};
+
+static const struct itemplate * const itable_evex0116A[] = {
+ instrux + 6520,
+ instrux + 6521,
+ instrux + 6522,
+ instrux + 6523,
+ instrux + 6524,
+ instrux + 6525,
+};
+
+static const struct itemplate * const itable_evex0116B[] = {
+ instrux + 5232,
+ instrux + 5233,
+ instrux + 5234,
+ instrux + 5235,
+ instrux + 5236,
+ instrux + 5237,
+};
+
+static const struct itemplate * const itable_evex0116C[] = {
+ instrux + 6550,
+ instrux + 6551,
+ instrux + 6552,
+ instrux + 6553,
+ instrux + 6554,
+ instrux + 6555,
+};
+
+static const struct itemplate * const itable_evex0116D[] = {
+ instrux + 6526,
+ instrux + 6527,
+ instrux + 6528,
+ instrux + 6529,
+ instrux + 6530,
+ instrux + 6531,
+};
+
+static const struct itemplate * const itable_evex0116E[] = {
+ instrux + 5083,
+ instrux + 5152,
+};
+
+static const struct itemplate * const itable_evex0116F[] = {
+ instrux + 5088,
+ instrux + 5089,
+ instrux + 5090,
+ instrux + 5094,
+ instrux + 5095,
+ instrux + 5096,
+};
+
+static const struct itemplate * const itable_evex01170[] = {
+ instrux + 6253,
+ instrux + 6254,
+ instrux + 6255,
+};
+
+static const struct itemplate * const itable_evex01171[] = {
+ instrux + 6316,
+ instrux + 6317,
+ instrux + 6318,
+ instrux + 6319,
+ instrux + 6320,
+ instrux + 6321,
+ instrux + 6370,
+ instrux + 6371,
+ instrux + 6372,
+ instrux + 6373,
+ instrux + 6374,
+ instrux + 6375,
+ instrux + 6430,
+ instrux + 6431,
+ instrux + 6432,
+ instrux + 6433,
+ instrux + 6434,
+ instrux + 6435,
+};
+
+static const struct itemplate * const itable_evex01172[] = {
+ instrux + 6181,
+ instrux + 6182,
+ instrux + 6183,
+ instrux + 6184,
+ instrux + 6185,
+ instrux + 6186,
+ instrux + 6187,
+ instrux + 6188,
+ instrux + 6189,
+ instrux + 6190,
+ instrux + 6191,
+ instrux + 6192,
+ instrux + 6205,
+ instrux + 6206,
+ instrux + 6207,
+ instrux + 6208,
+ instrux + 6209,
+ instrux + 6210,
+ instrux + 6211,
+ instrux + 6212,
+ instrux + 6213,
+ instrux + 6214,
+ instrux + 6215,
+ instrux + 6216,
+ instrux + 6268,
+ instrux + 6269,
+ instrux + 6270,
+ instrux + 6271,
+ instrux + 6272,
+ instrux + 6273,
+ instrux + 6328,
+ instrux + 6329,
+ instrux + 6330,
+ instrux + 6331,
+ instrux + 6332,
+ instrux + 6333,
+ instrux + 6340,
+ instrux + 6341,
+ instrux + 6342,
+ instrux + 6343,
+ instrux + 6344,
+ instrux + 6345,
+ instrux + 6382,
+ instrux + 6383,
+ instrux + 6384,
+ instrux + 6385,
+ instrux + 6386,
+ instrux + 6387,
+};
+
+static const struct itemplate * const itable_evex01173[] = {
+ instrux + 6274,
+ instrux + 6275,
+ instrux + 6276,
+ instrux + 6277,
+ instrux + 6278,
+ instrux + 6279,
+ instrux + 6286,
+ instrux + 6287,
+ instrux + 6288,
+ instrux + 6289,
+ instrux + 6290,
+ instrux + 6291,
+ instrux + 6388,
+ instrux + 6389,
+ instrux + 6390,
+ instrux + 6391,
+ instrux + 6392,
+ instrux + 6393,
+ instrux + 6400,
+ instrux + 6401,
+ instrux + 6402,
+ instrux + 6403,
+ instrux + 6404,
+ instrux + 6405,
+};
+
+static const struct itemplate * const itable_evex01174[] = {
+ instrux + 5409,
+ instrux + 5410,
+ instrux + 5411,
+};
+
+static const struct itemplate * const itable_evex01175[] = {
+ instrux + 5418,
+ instrux + 5419,
+ instrux + 5420,
+};
+
+static const struct itemplate * const itable_evex01176[] = {
+ instrux + 5412,
+ instrux + 5413,
+ instrux + 5414,
+};
+
+static const struct itemplate * const itable_evex01178[] = {
+ instrux + 4713,
+ instrux + 4714,
+ instrux + 4715,
+ instrux + 4725,
+ instrux + 4726,
+ instrux + 4727,
+};
+
+static const struct itemplate * const itable_evex01179[] = {
+ instrux + 4657,
+ instrux + 4658,
+ instrux + 4659,
+ instrux + 4681,
+ instrux + 4682,
+ instrux + 4683,
+};
+
+static const struct itemplate * const itable_evex0117A[] = {
+ instrux + 4707,
+ instrux + 4708,
+ instrux + 4709,
+ instrux + 4719,
+ instrux + 4720,
+ instrux + 4721,
+};
+
+static const struct itemplate * const itable_evex0117B[] = {
+ instrux + 4651,
+ instrux + 4652,
+ instrux + 4653,
+ instrux + 4675,
+ instrux + 4676,
+ instrux + 4677,
+};
+
+static const struct itemplate * const itable_evex0117E[] = {
+ instrux + 5084,
+ instrux + 5153,
+};
+
+static const struct itemplate * const itable_evex0117F[] = {
+ instrux + 5091,
+ instrux + 5092,
+ instrux + 5093,
+ instrux + 5097,
+ instrux + 5098,
+ instrux + 5099,
+};
+
+static const struct itemplate * const itable_evex011C2[] = {
+ instrux + 4249,
+ instrux + 4250,
+ instrux + 4251,
+ instrux + 4257,
+ instrux + 4258,
+ instrux + 4259,
+ instrux + 4265,
+ instrux + 4266,
+ instrux + 4267,
+ instrux + 4273,
+ instrux + 4274,
+ instrux + 4275,
+ instrux + 4281,
+ instrux + 4282,
+ instrux + 4283,
+ instrux + 4289,
+ instrux + 4290,
+ instrux + 4291,
+ instrux + 4297,
+ instrux + 4298,
+ instrux + 4299,
+ instrux + 4305,
+ instrux + 4306,
+ instrux + 4307,
+ instrux + 4313,
+ instrux + 4314,
+ instrux + 4315,
+ instrux + 4321,
+ instrux + 4322,
+ instrux + 4323,
+ instrux + 4329,
+ instrux + 4330,
+ instrux + 4331,
+ instrux + 4337,
+ instrux + 4338,
+ instrux + 4339,
+ instrux + 4345,
+ instrux + 4346,
+ instrux + 4347,
+ instrux + 4353,
+ instrux + 4354,
+ instrux + 4355,
+ instrux + 4361,
+ instrux + 4362,
+ instrux + 4363,
+ instrux + 4369,
+ instrux + 4370,
+ instrux + 4371,
+ instrux + 4377,
+ instrux + 4378,
+ instrux + 4379,
+ instrux + 4385,
+ instrux + 4386,
+ instrux + 4387,
+ instrux + 4393,
+ instrux + 4394,
+ instrux + 4395,
+ instrux + 4401,
+ instrux + 4402,
+ instrux + 4403,
+ instrux + 4409,
+ instrux + 4410,
+ instrux + 4411,
+ instrux + 4417,
+ instrux + 4418,
+ instrux + 4419,
+ instrux + 4425,
+ instrux + 4426,
+ instrux + 4427,
+ instrux + 4433,
+ instrux + 4434,
+ instrux + 4435,
+ instrux + 4441,
+ instrux + 4442,
+ instrux + 4443,
+ instrux + 4449,
+ instrux + 4450,
+ instrux + 4451,
+ instrux + 4457,
+ instrux + 4458,
+ instrux + 4459,
+ instrux + 4465,
+ instrux + 4466,
+ instrux + 4467,
+ instrux + 4473,
+ instrux + 4474,
+ instrux + 4475,
+ instrux + 4481,
+ instrux + 4482,
+ instrux + 4483,
+ instrux + 4489,
+ instrux + 4490,
+ instrux + 4491,
+ instrux + 4497,
+ instrux + 4498,
+ instrux + 4499,
+ instrux + 4505,
+ instrux + 4506,
+ instrux + 4507,
+ instrux + 4513,
+ instrux + 4514,
+ instrux + 4515,
+ instrux + 4521,
+ instrux + 4522,
+ instrux + 4523,
+ instrux + 4529,
+ instrux + 4530,
+ instrux + 4531,
+ instrux + 4537,
+ instrux + 4538,
+ instrux + 4539,
+ instrux + 4545,
+ instrux + 4546,
+ instrux + 4547,
+ instrux + 4553,
+ instrux + 4554,
+ instrux + 4555,
+ instrux + 4561,
+ instrux + 4562,
+ instrux + 4563,
+ instrux + 4569,
+ instrux + 4570,
+ instrux + 4571,
+ instrux + 4577,
+ instrux + 4578,
+ instrux + 4579,
+ instrux + 4585,
+ instrux + 4586,
+ instrux + 4587,
+ instrux + 4593,
+ instrux + 4594,
+ instrux + 4595,
+ instrux + 4601,
+ instrux + 4602,
+ instrux + 4603,
+ instrux + 4609,
+ instrux + 4610,
+ instrux + 4611,
+ instrux + 4617,
+ instrux + 4618,
+ instrux + 4619,
+};
+
+static const struct itemplate * const itable_evex011C4[] = {
+ instrux + 5823,
+ instrux + 5824,
+ instrux + 5825,
+ instrux + 5826,
+};
+
+static const struct itemplate * const itable_evex011C5[] = {
+ instrux + 5800,
+ instrux + 5801,
+ instrux + 5802,
+};
+
+static const struct itemplate * const itable_evex011C6[] = {
+ instrux + 6694,
+ instrux + 6695,
+ instrux + 6696,
+ instrux + 6697,
+ instrux + 6698,
+ instrux + 6699,
+};
+
+static const struct itemplate * const itable_evex011D1[] = {
+ instrux + 6424,
+ instrux + 6425,
+ instrux + 6426,
+ instrux + 6427,
+ instrux + 6428,
+ instrux + 6429,
+};
+
+static const struct itemplate * const itable_evex011D2[] = {
+ instrux + 6376,
+ instrux + 6377,
+ instrux + 6378,
+ instrux + 6379,
+ instrux + 6380,
+ instrux + 6381,
+};
+
+static const struct itemplate * const itable_evex011D3[] = {
+ instrux + 6394,
+ instrux + 6395,
+ instrux + 6396,
+ instrux + 6397,
+ instrux + 6398,
+ instrux + 6399,
+};
+
+static const struct itemplate * const itable_evex011D4[] = {
+ instrux + 5268,
+ instrux + 5269,
+ instrux + 5270,
+ instrux + 5271,
+ instrux + 5272,
+ instrux + 5273,
+};
+
+static const struct itemplate * const itable_evex011D5[] = {
+ instrux + 6151,
+ instrux + 6152,
+ instrux + 6153,
+ instrux + 6154,
+ instrux + 6155,
+ instrux + 6156,
+};
+
+static const struct itemplate * const itable_evex011D6[] = {
+ instrux + 5155,
+};
+
+static const struct itemplate * const itable_evex011D8[] = {
+ instrux + 6466,
+ instrux + 6467,
+ instrux + 6468,
+ instrux + 6469,
+ instrux + 6470,
+ instrux + 6471,
+};
+
+static const struct itemplate * const itable_evex011D9[] = {
+ instrux + 6472,
+ instrux + 6473,
+ instrux + 6474,
+ instrux + 6475,
+ instrux + 6476,
+ instrux + 6477,
+};
+
+static const struct itemplate * const itable_evex011DA[] = {
+ instrux + 5923,
+ instrux + 5924,
+ instrux + 5925,
+ instrux + 5926,
+ instrux + 5927,
+ instrux + 5928,
+};
+
+static const struct itemplate * const itable_evex011DB[] = {
+ instrux + 5310,
+ instrux + 5311,
+ instrux + 5312,
+ instrux + 5313,
+ instrux + 5314,
+ instrux + 5315,
+ instrux + 5328,
+ instrux + 5329,
+ instrux + 5330,
+ instrux + 5331,
+ instrux + 5332,
+ instrux + 5333,
+};
+
+static const struct itemplate * const itable_evex011DC[] = {
+ instrux + 5286,
+ instrux + 5287,
+ instrux + 5288,
+ instrux + 5289,
+ instrux + 5290,
+ instrux + 5291,
+};
+
+static const struct itemplate * const itable_evex011DD[] = {
+ instrux + 5292,
+ instrux + 5293,
+ instrux + 5294,
+ instrux + 5295,
+ instrux + 5296,
+ instrux + 5297,
+};
+
+static const struct itemplate * const itable_evex011DE[] = {
+ instrux + 5875,
+ instrux + 5876,
+ instrux + 5877,
+ instrux + 5878,
+ instrux + 5879,
+ instrux + 5880,
+};
+
+static const struct itemplate * const itable_evex011DF[] = {
+ instrux + 5316,
+ instrux + 5317,
+ instrux + 5318,
+ instrux + 5319,
+ instrux + 5320,
+ instrux + 5321,
+ instrux + 5322,
+ instrux + 5323,
+ instrux + 5324,
+ instrux + 5325,
+ instrux + 5326,
+ instrux + 5327,
+};
+
+static const struct itemplate * const itable_evex011E0[] = {
+ instrux + 5334,
+ instrux + 5335,
+ instrux + 5336,
+ instrux + 5337,
+ instrux + 5338,
+ instrux + 5339,
+};
+
+static const struct itemplate * const itable_evex011E1[] = {
+ instrux + 6364,
+ instrux + 6365,
+ instrux + 6366,
+ instrux + 6367,
+ instrux + 6368,
+ instrux + 6369,
+};
+
+static const struct itemplate * const itable_evex011E2[] = {
+ instrux + 6322,
+ instrux + 6323,
+ instrux + 6324,
+ instrux + 6325,
+ instrux + 6326,
+ instrux + 6327,
+ instrux + 6334,
+ instrux + 6335,
+ instrux + 6336,
+ instrux + 6337,
+ instrux + 6338,
+ instrux + 6339,
+};
+
+static const struct itemplate * const itable_evex011E3[] = {
+ instrux + 5340,
+ instrux + 5341,
+ instrux + 5342,
+ instrux + 5343,
+ instrux + 5344,
+ instrux + 5345,
+};
+
+static const struct itemplate * const itable_evex011E4[] = {
+ instrux + 6127,
+ instrux + 6128,
+ instrux + 6129,
+ instrux + 6130,
+ instrux + 6131,
+ instrux + 6132,
+};
+
+static const struct itemplate * const itable_evex011E5[] = {
+ instrux + 6133,
+ instrux + 6134,
+ instrux + 6135,
+ instrux + 6136,
+ instrux + 6137,
+ instrux + 6138,
+};
+
+static const struct itemplate * const itable_evex011E6[] = {
+ instrux + 4704,
+ instrux + 4705,
+ instrux + 4706,
+};
+
+static const struct itemplate * const itable_evex011E7[] = {
+ instrux + 5140,
+ instrux + 5141,
+ instrux + 5142,
+};
+
+static const struct itemplate * const itable_evex011E8[] = {
+ instrux + 6454,
+ instrux + 6455,
+ instrux + 6456,
+ instrux + 6457,
+ instrux + 6458,
+ instrux + 6459,
+};
+
+static const struct itemplate * const itable_evex011E9[] = {
+ instrux + 6460,
+ instrux + 6461,
+ instrux + 6462,
+ instrux + 6463,
+ instrux + 6464,
+ instrux + 6465,
+};
+
+static const struct itemplate * const itable_evex011EA[] = {
+ instrux + 5917,
+ instrux + 5918,
+ instrux + 5919,
+ instrux + 5920,
+ instrux + 5921,
+ instrux + 5922,
+};
+
+static const struct itemplate * const itable_evex011EB[] = {
+ instrux + 6169,
+ instrux + 6170,
+ instrux + 6171,
+ instrux + 6172,
+ instrux + 6173,
+ instrux + 6174,
+ instrux + 6175,
+ instrux + 6176,
+ instrux + 6177,
+ instrux + 6178,
+ instrux + 6179,
+ instrux + 6180,
+};
+
+static const struct itemplate * const itable_evex011EC[] = {
+ instrux + 5274,
+ instrux + 5275,
+ instrux + 5276,
+ instrux + 5277,
+ instrux + 5278,
+ instrux + 5279,
+};
+
+static const struct itemplate * const itable_evex011ED[] = {
+ instrux + 5280,
+ instrux + 5281,
+ instrux + 5282,
+ instrux + 5283,
+ instrux + 5284,
+ instrux + 5285,
+};
+
+static const struct itemplate * const itable_evex011EE[] = {
+ instrux + 5869,
+ instrux + 5870,
+ instrux + 5871,
+ instrux + 5872,
+ instrux + 5873,
+ instrux + 5874,
+};
+
+static const struct itemplate * const itable_evex011EF[] = {
+ instrux + 6562,
+ instrux + 6563,
+ instrux + 6564,
+ instrux + 6565,
+ instrux + 6566,
+ instrux + 6567,
+ instrux + 6568,
+ instrux + 6569,
+ instrux + 6570,
+ instrux + 6571,
+ instrux + 6572,
+ instrux + 6573,
+};
+
+static const struct itemplate * const itable_evex011F1[] = {
+ instrux + 6310,
+ instrux + 6311,
+ instrux + 6312,
+ instrux + 6313,
+ instrux + 6314,
+ instrux + 6315,
+};
+
+static const struct itemplate * const itable_evex011F2[] = {
+ instrux + 6262,
+ instrux + 6263,
+ instrux + 6264,
+ instrux + 6265,
+ instrux + 6266,
+ instrux + 6267,
+};
+
+static const struct itemplate * const itable_evex011F3[] = {
+ instrux + 6280,
+ instrux + 6281,
+ instrux + 6282,
+ instrux + 6283,
+ instrux + 6284,
+ instrux + 6285,
+};
+
+static const struct itemplate * const itable_evex011F4[] = {
+ instrux + 6163,
+ instrux + 6164,
+ instrux + 6165,
+ instrux + 6166,
+ instrux + 6167,
+ instrux + 6168,
+};
+
+static const struct itemplate * const itable_evex011F5[] = {
+ instrux + 5845,
+ instrux + 5846,
+ instrux + 5847,
+ instrux + 5848,
+ instrux + 5849,
+ instrux + 5850,
+};
+
+static const struct itemplate * const itable_evex011F6[] = {
+ instrux + 6229,
+ instrux + 6230,
+ instrux + 6231,
+ instrux + 6232,
+ instrux + 6233,
+ instrux + 6234,
+};
+
+static const struct itemplate * const itable_evex011F8[] = {
+ instrux + 6436,
+ instrux + 6437,
+ instrux + 6438,
+ instrux + 6439,
+ instrux + 6440,
+ instrux + 6441,
+};
+
+static const struct itemplate * const itable_evex011F9[] = {
+ instrux + 6478,
+ instrux + 6479,
+ instrux + 6480,
+ instrux + 6481,
+ instrux + 6482,
+ instrux + 6483,
+};
+
+static const struct itemplate * const itable_evex011FA[] = {
+ instrux + 6442,
+ instrux + 6443,
+ instrux + 6444,
+ instrux + 6445,
+ instrux + 6446,
+ instrux + 6447,
+};
+
+static const struct itemplate * const itable_evex011FB[] = {
+ instrux + 6448,
+ instrux + 6449,
+ instrux + 6450,
+ instrux + 6451,
+ instrux + 6452,
+ instrux + 6453,
+};
+
+static const struct itemplate * const itable_evex011FC[] = {
+ instrux + 5256,
+ instrux + 5257,
+ instrux + 5258,
+ instrux + 5259,
+ instrux + 5260,
+ instrux + 5261,
+};
+
+static const struct itemplate * const itable_evex011FD[] = {
+ instrux + 5298,
+ instrux + 5299,
+ instrux + 5300,
+ instrux + 5301,
+ instrux + 5302,
+ instrux + 5303,
+};
+
+static const struct itemplate * const itable_evex011FE[] = {
+ instrux + 5262,
+ instrux + 5263,
+ instrux + 5264,
+ instrux + 5265,
+ instrux + 5266,
+ instrux + 5267,
+};
+
+static const struct itemplate * const itable_evex01210[] = {
+ instrux + 5168,
+ instrux + 5170,
+ instrux + 5171,
+};
+
+static const struct itemplate * const itable_evex01211[] = {
+ instrux + 5169,
+ instrux + 5172,
+ instrux + 5173,
+};
+
+static const struct itemplate * const itable_evex01212[] = {
+ instrux + 5165,
+ instrux + 5166,
+ instrux + 5167,
+};
+
+static const struct itemplate * const itable_evex01216[] = {
+ instrux + 5162,
+ instrux + 5163,
+ instrux + 5164,
+};
+
+static const struct itemplate * const itable_evex0122A[] = {
+ instrux + 4697,
+ instrux + 4698,
+};
+
+static const struct itemplate * const itable_evex0122C[] = {
+ instrux + 4732,
+ instrux + 4733,
+};
+
+static const struct itemplate * const itable_evex0122D[] = {
+ instrux + 4700,
+ instrux + 4701,
+};
+
+static const struct itemplate * const itable_evex01251[] = {
+ instrux + 6714,
+ instrux + 6715,
+};
+
+static const struct itemplate * const itable_evex01258[] = {
+ instrux + 4178,
+ instrux + 4179,
+};
+
+static const struct itemplate * const itable_evex01259[] = {
+ instrux + 5206,
+ instrux + 5207,
+};
+
+static const struct itemplate * const itable_evex0125A[] = {
+ instrux + 4699,
+};
+
+static const struct itemplate * const itable_evex0125B[] = {
+ instrux + 4716,
+ instrux + 4717,
+ instrux + 4718,
+};
+
+static const struct itemplate * const itable_evex0125C[] = {
+ instrux + 6730,
+ instrux + 6731,
+};
+
+static const struct itemplate * const itable_evex0125D[] = {
+ instrux + 5063,
+ instrux + 5064,
+};
+
+static const struct itemplate * const itable_evex0125E[] = {
+ instrux + 4772,
+ instrux + 4773,
+};
+
+static const struct itemplate * const itable_evex0125F[] = {
+ instrux + 5047,
+ instrux + 5048,
+};
+
+static const struct itemplate * const itable_evex0126F[] = {
+ instrux + 5106,
+ instrux + 5107,
+ instrux + 5108,
+ instrux + 5112,
+ instrux + 5113,
+ instrux + 5114,
+};
+
+static const struct itemplate * const itable_evex01270[] = {
+ instrux + 6256,
+ instrux + 6257,
+ instrux + 6258,
+};
+
+static const struct itemplate * const itable_evex01278[] = {
+ instrux + 4734,
+ instrux + 4735,
+};
+
+static const struct itemplate * const itable_evex01279[] = {
+ instrux + 4702,
+ instrux + 4703,
+};
+
+static const struct itemplate * const itable_evex0127A[] = {
+ instrux + 4736,
+ instrux + 4737,
+ instrux + 4738,
+ instrux + 4742,
+ instrux + 4743,
+ instrux + 4744,
+};
+
+static const struct itemplate * const itable_evex0127B[] = {
+ instrux + 4750,
+ instrux + 4751,
+};
+
+static const struct itemplate * const itable_evex0127E[] = {
+ instrux + 5154,
+};
+
+static const struct itemplate * const itable_evex0127F[] = {
+ instrux + 5109,
+ instrux + 5110,
+ instrux + 5111,
+ instrux + 5115,
+ instrux + 5116,
+ instrux + 5117,
+};
+
+static const struct itemplate * const itable_evex012C2[] = {
+ instrux + 4256,
+ instrux + 4264,
+ instrux + 4272,
+ instrux + 4280,
+ instrux + 4288,
+ instrux + 4296,
+ instrux + 4304,
+ instrux + 4312,
+ instrux + 4320,
+ instrux + 4328,
+ instrux + 4336,
+ instrux + 4344,
+ instrux + 4352,
+ instrux + 4360,
+ instrux + 4368,
+ instrux + 4376,
+ instrux + 4384,
+ instrux + 4392,
+ instrux + 4400,
+ instrux + 4408,
+ instrux + 4416,
+ instrux + 4424,
+ instrux + 4432,
+ instrux + 4440,
+ instrux + 4448,
+ instrux + 4456,
+ instrux + 4464,
+ instrux + 4472,
+ instrux + 4480,
+ instrux + 4488,
+ instrux + 4496,
+ instrux + 4504,
+ instrux + 4512,
+ instrux + 4520,
+ instrux + 4528,
+ instrux + 4536,
+ instrux + 4544,
+ instrux + 4552,
+ instrux + 4560,
+ instrux + 4568,
+ instrux + 4576,
+ instrux + 4584,
+ instrux + 4592,
+ instrux + 4600,
+ instrux + 4608,
+ instrux + 4616,
+ instrux + 4624,
+};
+
+static const struct itemplate * const itable_evex012E6[] = {
+ instrux + 4639,
+ instrux + 4640,
+ instrux + 4641,
+ instrux + 4684,
+ instrux + 4685,
+ instrux + 4686,
+};
+
+static const struct itemplate * const itable_evex01310[] = {
+ instrux + 5156,
+ instrux + 5158,
+ instrux + 5159,
+};
+
+static const struct itemplate * const itable_evex01311[] = {
+ instrux + 5157,
+ instrux + 5160,
+ instrux + 5161,
+};
+
+static const struct itemplate * const itable_evex01312[] = {
+ instrux + 5085,
+ instrux + 5086,
+ instrux + 5087,
+};
+
+static const struct itemplate * const itable_evex0132A[] = {
+ instrux + 4695,
+ instrux + 4696,
+};
+
+static const struct itemplate * const itable_evex0132C[] = {
+ instrux + 4728,
+ instrux + 4729,
+};
+
+static const struct itemplate * const itable_evex0132D[] = {
+ instrux + 4690,
+ instrux + 4691,
+};
+
+static const struct itemplate * const itable_evex01351[] = {
+ instrux + 6712,
+ instrux + 6713,
+};
+
+static const struct itemplate * const itable_evex01358[] = {
+ instrux + 4176,
+ instrux + 4177,
+};
+
+static const struct itemplate * const itable_evex01359[] = {
+ instrux + 5204,
+ instrux + 5205,
+};
+
+static const struct itemplate * const itable_evex0135A[] = {
+ instrux + 4692,
+};
+
+static const struct itemplate * const itable_evex0135C[] = {
+ instrux + 6728,
+ instrux + 6729,
+};
+
+static const struct itemplate * const itable_evex0135D[] = {
+ instrux + 5061,
+ instrux + 5062,
+};
+
+static const struct itemplate * const itable_evex0135E[] = {
+ instrux + 4770,
+ instrux + 4771,
+};
+
+static const struct itemplate * const itable_evex0135F[] = {
+ instrux + 5045,
+ instrux + 5046,
+};
+
+static const struct itemplate * const itable_evex0136F[] = {
+ instrux + 5100,
+ instrux + 5101,
+ instrux + 5102,
+ instrux + 5118,
+ instrux + 5119,
+ instrux + 5120,
+};
+
+static const struct itemplate * const itable_evex01370[] = {
+ instrux + 6259,
+ instrux + 6260,
+ instrux + 6261,
+};
+
+static const struct itemplate * const itable_evex01378[] = {
+ instrux + 4730,
+ instrux + 4731,
+};
+
+static const struct itemplate * const itable_evex01379[] = {
+ instrux + 4693,
+ instrux + 4694,
+};
+
+static const struct itemplate * const itable_evex0137A[] = {
+ instrux + 4739,
+ instrux + 4740,
+ instrux + 4741,
+ instrux + 4745,
+ instrux + 4746,
+ instrux + 4747,
+};
+
+static const struct itemplate * const itable_evex0137B[] = {
+ instrux + 4748,
+ instrux + 4749,
+};
+
+static const struct itemplate * const itable_evex0137F[] = {
+ instrux + 5103,
+ instrux + 5104,
+ instrux + 5105,
+ instrux + 5121,
+ instrux + 5122,
+ instrux + 5123,
+};
+
+static const struct itemplate * const itable_evex013C2[] = {
+ instrux + 4255,
+ instrux + 4263,
+ instrux + 4271,
+ instrux + 4279,
+ instrux + 4287,
+ instrux + 4295,
+ instrux + 4303,
+ instrux + 4311,
+ instrux + 4319,
+ instrux + 4327,
+ instrux + 4335,
+ instrux + 4343,
+ instrux + 4351,
+ instrux + 4359,
+ instrux + 4367,
+ instrux + 4375,
+ instrux + 4383,
+ instrux + 4391,
+ instrux + 4399,
+ instrux + 4407,
+ instrux + 4415,
+ instrux + 4423,
+ instrux + 4431,
+ instrux + 4439,
+ instrux + 4447,
+ instrux + 4455,
+ instrux + 4463,
+ instrux + 4471,
+ instrux + 4479,
+ instrux + 4487,
+ instrux + 4495,
+ instrux + 4503,
+ instrux + 4511,
+ instrux + 4519,
+ instrux + 4527,
+ instrux + 4535,
+ instrux + 4543,
+ instrux + 4551,
+ instrux + 4559,
+ instrux + 4567,
+ instrux + 4575,
+ instrux + 4583,
+ instrux + 4591,
+ instrux + 4599,
+ instrux + 4607,
+ instrux + 4615,
+ instrux + 4623,
+};
+
+static const struct itemplate * const itable_evex013E6[] = {
+ instrux + 4645,
+ instrux + 4646,
+ instrux + 4647,
+};
+
+static const struct itemplate * const itable_evex02100[] = {
+ instrux + 6247,
+ instrux + 6248,
+ instrux + 6249,
+ instrux + 6250,
+ instrux + 6251,
+ instrux + 6252,
+};
+
+static const struct itemplate * const itable_evex02104[] = {
+ instrux + 5839,
+ instrux + 5840,
+ instrux + 5841,
+ instrux + 5842,
+ instrux + 5843,
+ instrux + 5844,
+};
+
+static const struct itemplate * const itable_evex0210B[] = {
+ instrux + 6121,
+ instrux + 6122,
+ instrux + 6123,
+ instrux + 6124,
+ instrux + 6125,
+ instrux + 6126,
+};
+
+static const struct itemplate * const itable_evex0210C[] = {
+ instrux + 5731,
+ instrux + 5732,
+ instrux + 5733,
+ instrux + 5734,
+ instrux + 5735,
+ instrux + 5736,
+};
+
+static const struct itemplate * const itable_evex0210D[] = {
+ instrux + 5722,
+ instrux + 5723,
+ instrux + 5724,
+ instrux + 5725,
+ instrux + 5726,
+ instrux + 5727,
+};
+
+static const struct itemplate * const itable_evex02110[] = {
+ instrux + 6418,
+ instrux + 6419,
+ instrux + 6420,
+ instrux + 6421,
+ instrux + 6422,
+ instrux + 6423,
+};
+
+static const struct itemplate * const itable_evex02111[] = {
+ instrux + 6358,
+ instrux + 6359,
+ instrux + 6360,
+ instrux + 6361,
+ instrux + 6362,
+ instrux + 6363,
+};
+
+static const struct itemplate * const itable_evex02112[] = {
+ instrux + 6304,
+ instrux + 6305,
+ instrux + 6306,
+ instrux + 6307,
+ instrux + 6308,
+ instrux + 6309,
+};
+
+static const struct itemplate * const itable_evex02113[] = {
+ instrux + 4660,
+ instrux + 4661,
+ instrux + 4662,
+ instrux + 7054,
+ instrux + 7055,
+ instrux + 7056,
+};
+
+static const struct itemplate * const itable_evex02114[] = {
+ instrux + 6217,
+ instrux + 6218,
+ instrux + 6219,
+ instrux + 6220,
+ instrux + 6221,
+ instrux + 6222,
+ instrux + 6223,
+ instrux + 6224,
+ instrux + 6225,
+ instrux + 6226,
+ instrux + 6227,
+ instrux + 6228,
+};
+
+static const struct itemplate * const itable_evex02115[] = {
+ instrux + 6193,
+ instrux + 6194,
+ instrux + 6195,
+ instrux + 6196,
+ instrux + 6197,
+ instrux + 6198,
+ instrux + 6199,
+ instrux + 6200,
+ instrux + 6201,
+ instrux + 6202,
+ instrux + 6203,
+ instrux + 6204,
+};
+
+static const struct itemplate * const itable_evex02116[] = {
+ instrux + 5739,
+ instrux + 5740,
+ instrux + 5741,
+ instrux + 5742,
+ instrux + 5743,
+ instrux + 5744,
+ instrux + 5745,
+ instrux + 5746,
+};
+
+static const struct itemplate * const itable_evex02118[] = {
+ instrux + 4243,
+ instrux + 4244,
+ instrux + 4245,
+ instrux + 4246,
+ instrux + 4247,
+ instrux + 4248,
+};
+
+static const struct itemplate * const itable_evex02119[] = {
+ instrux + 4222,
+ instrux + 4223,
+ instrux + 4239,
+ instrux + 4240,
+ instrux + 4241,
+ instrux + 4242,
+};
+
+static const struct itemplate * const itable_evex0211A[] = {
+ instrux + 4224,
+ instrux + 4225,
+ instrux + 4227,
+ instrux + 4228,
+};
+
+static const struct itemplate * const itable_evex0211B[] = {
+ instrux + 4226,
+ instrux + 4229,
+};
+
+static const struct itemplate * const itable_evex0211C[] = {
+ instrux + 5220,
+ instrux + 5221,
+ instrux + 5222,
+};
+
+static const struct itemplate * const itable_evex0211D[] = {
+ instrux + 5229,
+ instrux + 5230,
+ instrux + 5231,
+};
+
+static const struct itemplate * const itable_evex0211E[] = {
+ instrux + 5223,
+ instrux + 5224,
+ instrux + 5225,
+};
+
+static const struct itemplate * const itable_evex0211F[] = {
+ instrux + 5226,
+ instrux + 5227,
+ instrux + 5228,
+};
+
+static const struct itemplate * const itable_evex02120[] = {
+ instrux + 6040,
+ instrux + 6041,
+ instrux + 6042,
+};
+
+static const struct itemplate * const itable_evex02121[] = {
+ instrux + 6034,
+ instrux + 6035,
+ instrux + 6036,
+};
+
+static const struct itemplate * const itable_evex02122[] = {
+ instrux + 6037,
+ instrux + 6038,
+ instrux + 6039,
+};
+
+static const struct itemplate * const itable_evex02123[] = {
+ instrux + 6046,
+ instrux + 6047,
+ instrux + 6048,
+};
+
+static const struct itemplate * const itable_evex02124[] = {
+ instrux + 6049,
+ instrux + 6050,
+ instrux + 6051,
+};
+
+static const struct itemplate * const itable_evex02125[] = {
+ instrux + 6043,
+ instrux + 6044,
+ instrux + 6045,
+};
+
+static const struct itemplate * const itable_evex02126[] = {
+ instrux + 6490,
+ instrux + 6491,
+ instrux + 6492,
+ instrux + 6499,
+ instrux + 6500,
+ instrux + 6501,
+};
+
+static const struct itemplate * const itable_evex02127[] = {
+ instrux + 6493,
+ instrux + 6494,
+ instrux + 6495,
+ instrux + 6496,
+ instrux + 6497,
+ instrux + 6498,
+};
+
+static const struct itemplate * const itable_evex02128[] = {
+ instrux + 6115,
+ instrux + 6116,
+ instrux + 6117,
+ instrux + 6118,
+ instrux + 6119,
+ instrux + 6120,
+};
+
+static const struct itemplate * const itable_evex02129[] = {
+ instrux + 5415,
+ instrux + 5416,
+ instrux + 5417,
+};
+
+static const struct itemplate * const itable_evex0212A[] = {
+ instrux + 5143,
+ instrux + 5144,
+ instrux + 5145,
+};
+
+static const struct itemplate * const itable_evex0212B[] = {
+ instrux + 5244,
+ instrux + 5245,
+ instrux + 5246,
+ instrux + 5247,
+ instrux + 5248,
+ instrux + 5249,
+};
+
+static const struct itemplate * const itable_evex0212C[] = {
+ instrux + 6642,
+ instrux + 6643,
+ instrux + 6644,
+ instrux + 6645,
+ instrux + 6646,
+ instrux + 6647,
+ instrux + 6648,
+ instrux + 6649,
+ instrux + 6650,
+ instrux + 6651,
+ instrux + 6652,
+ instrux + 6653,
+};
+
+static const struct itemplate * const itable_evex0212D[] = {
+ instrux + 6654,
+ instrux + 6655,
+ instrux + 6656,
+ instrux + 6657,
+};
+
+static const struct itemplate * const itable_evex02130[] = {
+ instrux + 6103,
+ instrux + 6104,
+ instrux + 6105,
+};
+
+static const struct itemplate * const itable_evex02131[] = {
+ instrux + 6097,
+ instrux + 6098,
+ instrux + 6099,
+};
+
+static const struct itemplate * const itable_evex02132[] = {
+ instrux + 6100,
+ instrux + 6101,
+ instrux + 6102,
+};
+
+static const struct itemplate * const itable_evex02133[] = {
+ instrux + 6109,
+ instrux + 6110,
+ instrux + 6111,
+};
+
+static const struct itemplate * const itable_evex02134[] = {
+ instrux + 6112,
+ instrux + 6113,
+ instrux + 6114,
+};
+
+static const struct itemplate * const itable_evex02135[] = {
+ instrux + 6106,
+ instrux + 6107,
+ instrux + 6108,
+};
+
+static const struct itemplate * const itable_evex02136[] = {
+ instrux + 5697,
+ instrux + 5698,
+ instrux + 5699,
+ instrux + 5700,
+ instrux + 5749,
+ instrux + 5750,
+ instrux + 5751,
+ instrux + 5752,
+};
+
+static const struct itemplate * const itable_evex02137[] = {
+ instrux + 5427,
+ instrux + 5428,
+ instrux + 5429,
+};
+
+static const struct itemplate * const itable_evex02138[] = {
+ instrux + 5899,
+ instrux + 5900,
+ instrux + 5901,
+ instrux + 5902,
+ instrux + 5903,
+ instrux + 5904,
+};
+
+static const struct itemplate * const itable_evex02139[] = {
+ instrux + 5905,
+ instrux + 5906,
+ instrux + 5907,
+ instrux + 5908,
+ instrux + 5909,
+ instrux + 5910,
+ instrux + 5911,
+ instrux + 5912,
+ instrux + 5913,
+ instrux + 5914,
+ instrux + 5915,
+ instrux + 5916,
+};
+
+static const struct itemplate * const itable_evex0213A[] = {
+ instrux + 5941,
+ instrux + 5942,
+ instrux + 5943,
+ instrux + 5944,
+ instrux + 5945,
+ instrux + 5946,
+};
+
+static const struct itemplate * const itable_evex0213B[] = {
+ instrux + 5929,
+ instrux + 5930,
+ instrux + 5931,
+ instrux + 5932,
+ instrux + 5933,
+ instrux + 5934,
+ instrux + 5935,
+ instrux + 5936,
+ instrux + 5937,
+ instrux + 5938,
+ instrux + 5939,
+ instrux + 5940,
+};
+
+static const struct itemplate * const itable_evex0213C[] = {
+ instrux + 5851,
+ instrux + 5852,
+ instrux + 5853,
+ instrux + 5854,
+ instrux + 5855,
+ instrux + 5856,
+};
+
+static const struct itemplate * const itable_evex0213D[] = {
+ instrux + 5857,
+ instrux + 5858,
+ instrux + 5859,
+ instrux + 5860,
+ instrux + 5861,
+ instrux + 5862,
+ instrux + 5863,
+ instrux + 5864,
+ instrux + 5865,
+ instrux + 5866,
+ instrux + 5867,
+ instrux + 5868,
+};
+
+static const struct itemplate * const itable_evex0213E[] = {
+ instrux + 5893,
+ instrux + 5894,
+ instrux + 5895,
+ instrux + 5896,
+ instrux + 5897,
+ instrux + 5898,
+};
+
+static const struct itemplate * const itable_evex0213F[] = {
+ instrux + 5881,
+ instrux + 5882,
+ instrux + 5883,
+ instrux + 5884,
+ instrux + 5885,
+ instrux + 5886,
+ instrux + 5887,
+ instrux + 5888,
+ instrux + 5889,
+ instrux + 5890,
+ instrux + 5891,
+ instrux + 5892,
+};
+
+static const struct itemplate * const itable_evex02140[] = {
+ instrux + 6139,
+ instrux + 6140,
+ instrux + 6141,
+ instrux + 6142,
+ instrux + 6143,
+ instrux + 6144,
+ instrux + 6145,
+ instrux + 6146,
+ instrux + 6147,
+ instrux + 6148,
+ instrux + 6149,
+ instrux + 6150,
+};
+
+static const struct itemplate * const itable_evex02142[] = {
+ instrux + 4991,
+ instrux + 4992,
+ instrux + 4993,
+ instrux + 4994,
+ instrux + 4995,
+ instrux + 4996,
+};
+
+static const struct itemplate * const itable_evex02143[] = {
+ instrux + 4997,
+ instrux + 4998,
+};
+
+static const struct itemplate * const itable_evex02144[] = {
+ instrux + 5827,
+ instrux + 5828,
+ instrux + 5829,
+ instrux + 5830,
+ instrux + 5831,
+ instrux + 5832,
+};
+
+static const struct itemplate * const itable_evex02145[] = {
+ instrux + 6406,
+ instrux + 6407,
+ instrux + 6408,
+ instrux + 6409,
+ instrux + 6410,
+ instrux + 6411,
+ instrux + 6412,
+ instrux + 6413,
+ instrux + 6414,
+ instrux + 6415,
+ instrux + 6416,
+ instrux + 6417,
+};
+
+static const struct itemplate * const itable_evex02146[] = {
+ instrux + 6346,
+ instrux + 6347,
+ instrux + 6348,
+ instrux + 6349,
+ instrux + 6350,
+ instrux + 6351,
+ instrux + 6352,
+ instrux + 6353,
+ instrux + 6354,
+ instrux + 6355,
+ instrux + 6356,
+ instrux + 6357,
+};
+
+static const struct itemplate * const itable_evex02147[] = {
+ instrux + 6292,
+ instrux + 6293,
+ instrux + 6294,
+ instrux + 6295,
+ instrux + 6296,
+ instrux + 6297,
+ instrux + 6298,
+ instrux + 6299,
+ instrux + 6300,
+ instrux + 6301,
+ instrux + 6302,
+ instrux + 6303,
+};
+
+static const struct itemplate * const itable_evex0214C[] = {
+ instrux + 6590,
+ instrux + 6591,
+ instrux + 6592,
+ instrux + 6593,
+ instrux + 6594,
+ instrux + 6595,
+};
+
+static const struct itemplate * const itable_evex0214D[] = {
+ instrux + 6596,
+ instrux + 6597,
+ instrux + 6598,
+ instrux + 6599,
+};
+
+static const struct itemplate * const itable_evex0214E[] = {
+ instrux + 6626,
+ instrux + 6627,
+ instrux + 6628,
+ instrux + 6629,
+ instrux + 6630,
+ instrux + 6631,
+};
+
+static const struct itemplate * const itable_evex0214F[] = {
+ instrux + 6632,
+ instrux + 6633,
+ instrux + 6634,
+ instrux + 6635,
+};
+
+static const struct itemplate * const itable_evex02150[] = {
+ instrux + 6917,
+ instrux + 6918,
+ instrux + 6919,
+ instrux + 6920,
+ instrux + 6921,
+ instrux + 6922,
+};
+
+static const struct itemplate * const itable_evex02151[] = {
+ instrux + 6923,
+ instrux + 6924,
+ instrux + 6925,
+ instrux + 6926,
+ instrux + 6927,
+ instrux + 6928,
+};
+
+static const struct itemplate * const itable_evex02152[] = {
+ instrux + 6929,
+ instrux + 6930,
+ instrux + 6931,
+ instrux + 6932,
+ instrux + 6933,
+ instrux + 6934,
+};
+
+static const struct itemplate * const itable_evex02153[] = {
+ instrux + 6935,
+ instrux + 6936,
+ instrux + 6937,
+ instrux + 6938,
+ instrux + 6939,
+ instrux + 6940,
+};
+
+static const struct itemplate * const itable_evex02154[] = {
+ instrux + 6941,
+ instrux + 6942,
+ instrux + 6943,
+ instrux + 6944,
+ instrux + 6945,
+ instrux + 6946,
+};
+
+static const struct itemplate * const itable_evex02155[] = {
+ instrux + 6947,
+ instrux + 6948,
+ instrux + 6949,
+ instrux + 6950,
+ instrux + 6951,
+ instrux + 6952,
+};
+
+static const struct itemplate * const itable_evex02158[] = {
+ instrux + 5373,
+ instrux + 5374,
+ instrux + 5375,
+ instrux + 5376,
+ instrux + 5377,
+ instrux + 5378,
+};
+
+static const struct itemplate * const itable_evex02159[] = {
+ instrux + 4230,
+ instrux + 4231,
+ instrux + 4232,
+ instrux + 5388,
+ instrux + 5389,
+ instrux + 5390,
+ instrux + 5391,
+ instrux + 5392,
+ instrux + 5393,
+};
+
+static const struct itemplate * const itable_evex0215A[] = {
+ instrux + 4233,
+ instrux + 4234,
+ instrux + 4236,
+ instrux + 4237,
+};
+
+static const struct itemplate * const itable_evex0215B[] = {
+ instrux + 4235,
+ instrux + 4238,
+};
+
+static const struct itemplate * const itable_evex02162[] = {
+ instrux + 6839,
+ instrux + 6840,
+ instrux + 6841,
+ instrux + 6842,
+ instrux + 6843,
+ instrux + 6844,
+};
+
+static const struct itemplate * const itable_evex02163[] = {
+ instrux + 6827,
+ instrux + 6828,
+ instrux + 6829,
+ instrux + 6830,
+ instrux + 6831,
+ instrux + 6832,
+ instrux + 6833,
+ instrux + 6834,
+ instrux + 6835,
+ instrux + 6836,
+ instrux + 6837,
+ instrux + 6838,
+};
+
+static const struct itemplate * const itable_evex02164[] = {
+ instrux + 5349,
+ instrux + 5350,
+ instrux + 5351,
+ instrux + 5352,
+ instrux + 5353,
+ instrux + 5354,
+};
+
+static const struct itemplate * const itable_evex02165[] = {
+ instrux + 4216,
+ instrux + 4217,
+ instrux + 4218,
+ instrux + 4219,
+ instrux + 4220,
+ instrux + 4221,
+};
+
+static const struct itemplate * const itable_evex02166[] = {
+ instrux + 5346,
+ instrux + 5347,
+ instrux + 5348,
+ instrux + 5355,
+ instrux + 5356,
+ instrux + 5357,
+};
+
+static const struct itemplate * const itable_evex02170[] = {
+ instrux + 6863,
+ instrux + 6864,
+ instrux + 6865,
+ instrux + 6866,
+ instrux + 6867,
+ instrux + 6868,
+};
+
+static const struct itemplate * const itable_evex02171[] = {
+ instrux + 6869,
+ instrux + 6870,
+ instrux + 6871,
+ instrux + 6872,
+ instrux + 6873,
+ instrux + 6874,
+ instrux + 6875,
+ instrux + 6876,
+ instrux + 6877,
+ instrux + 6878,
+ instrux + 6879,
+ instrux + 6880,
+};
+
+static const struct itemplate * const itable_evex02172[] = {
+ instrux + 6899,
+ instrux + 6900,
+ instrux + 6901,
+ instrux + 6902,
+ instrux + 6903,
+ instrux + 6904,
+};
+
+static const struct itemplate * const itable_evex02173[] = {
+ instrux + 6905,
+ instrux + 6906,
+ instrux + 6907,
+ instrux + 6908,
+ instrux + 6909,
+ instrux + 6910,
+ instrux + 6911,
+ instrux + 6912,
+ instrux + 6913,
+ instrux + 6914,
+ instrux + 6915,
+ instrux + 6916,
+};
+
+static const struct itemplate * const itable_evex02175[] = {
+ instrux + 5701,
+ instrux + 5702,
+ instrux + 5703,
+ instrux + 5716,
+ instrux + 5717,
+ instrux + 5718,
+};
+
+static const struct itemplate * const itable_evex02176[] = {
+ instrux + 5704,
+ instrux + 5705,
+ instrux + 5706,
+ instrux + 5713,
+ instrux + 5714,
+ instrux + 5715,
+};
+
+static const struct itemplate * const itable_evex02177[] = {
+ instrux + 5707,
+ instrux + 5708,
+ instrux + 5709,
+ instrux + 5710,
+ instrux + 5711,
+ instrux + 5712,
+};
+
+static const struct itemplate * const itable_evex02178[] = {
+ instrux + 5358,
+ instrux + 5359,
+ instrux + 5360,
+};
+
+static const struct itemplate * const itable_evex02179[] = {
+ instrux + 5397,
+ instrux + 5398,
+ instrux + 5399,
+};
+
+static const struct itemplate * const itable_evex0217A[] = {
+ instrux + 5361,
+ instrux + 5362,
+ instrux + 5363,
+ instrux + 5364,
+ instrux + 5365,
+ instrux + 5366,
+ instrux + 5367,
+ instrux + 5368,
+ instrux + 5369,
+ instrux + 5370,
+ instrux + 5371,
+ instrux + 5372,
+};
+
+static const struct itemplate * const itable_evex0217B[] = {
+ instrux + 5400,
+ instrux + 5401,
+ instrux + 5402,
+ instrux + 5403,
+ instrux + 5404,
+ instrux + 5405,
+ instrux + 5406,
+ instrux + 5407,
+ instrux + 5408,
+};
+
+static const struct itemplate * const itable_evex0217C[] = {
+ instrux + 5379,
+ instrux + 5380,
+ instrux + 5381,
+ instrux + 5394,
+ instrux + 5395,
+ instrux + 5396,
+};
+
+static const struct itemplate * const itable_evex0217D[] = {
+ instrux + 5753,
+ instrux + 5754,
+ instrux + 5755,
+ instrux + 5768,
+ instrux + 5769,
+ instrux + 5770,
+};
+
+static const struct itemplate * const itable_evex0217E[] = {
+ instrux + 5756,
+ instrux + 5757,
+ instrux + 5758,
+ instrux + 5765,
+ instrux + 5766,
+ instrux + 5767,
+};
+
+static const struct itemplate * const itable_evex0217F[] = {
+ instrux + 5759,
+ instrux + 5760,
+ instrux + 5761,
+ instrux + 5762,
+ instrux + 5763,
+ instrux + 5764,
+};
+
+static const struct itemplate * const itable_evex02183[] = {
+ instrux + 6157,
+ instrux + 6158,
+ instrux + 6159,
+ instrux + 6160,
+ instrux + 6161,
+ instrux + 6162,
+};
+
+static const struct itemplate * const itable_evex02188[] = {
+ instrux + 4776,
+ instrux + 4777,
+ instrux + 4778,
+ instrux + 4779,
+ instrux + 4780,
+ instrux + 4781,
+ instrux + 4782,
+ instrux + 4783,
+ instrux + 4784,
+ instrux + 4785,
+ instrux + 4786,
+ instrux + 4787,
+};
+
+static const struct itemplate * const itable_evex02189[] = {
+ instrux + 5777,
+ instrux + 5778,
+ instrux + 5779,
+ instrux + 5780,
+ instrux + 5781,
+ instrux + 5782,
+ instrux + 5783,
+ instrux + 5784,
+ instrux + 5785,
+ instrux + 5786,
+ instrux + 5787,
+ instrux + 5788,
+};
+
+static const struct itemplate * const itable_evex0218A[] = {
+ instrux + 4627,
+ instrux + 4628,
+ instrux + 4629,
+ instrux + 4630,
+ instrux + 4631,
+ instrux + 4632,
+ instrux + 4633,
+ instrux + 4634,
+ instrux + 4635,
+ instrux + 4636,
+ instrux + 4637,
+ instrux + 4638,
+};
+
+static const struct itemplate * const itable_evex0218B[] = {
+ instrux + 5673,
+ instrux + 5674,
+ instrux + 5675,
+ instrux + 5676,
+ instrux + 5677,
+ instrux + 5678,
+ instrux + 5679,
+ instrux + 5680,
+ instrux + 5681,
+ instrux + 5682,
+ instrux + 5683,
+ instrux + 5684,
+};
+
+static const struct itemplate * const itable_evex0218D[] = {
+ instrux + 5691,
+ instrux + 5692,
+ instrux + 5693,
+ instrux + 5694,
+ instrux + 5695,
+ instrux + 5696,
+ instrux + 5771,
+ instrux + 5772,
+ instrux + 5773,
+ instrux + 5774,
+ instrux + 5775,
+ instrux + 5776,
+};
+
+static const struct itemplate * const itable_evex0218F[] = {
+ instrux + 6953,
+ instrux + 6954,
+ instrux + 6955,
+};
+
+static const struct itemplate * const itable_evex02190[] = {
+ instrux + 5803,
+ instrux + 5804,
+ instrux + 5805,
+ instrux + 5806,
+ instrux + 5807,
+ instrux + 5808,
+};
+
+static const struct itemplate * const itable_evex02191[] = {
+ instrux + 5809,
+ instrux + 5810,
+ instrux + 5811,
+ instrux + 5812,
+ instrux + 5813,
+ instrux + 5814,
+};
+
+static const struct itemplate * const itable_evex02192[] = {
+ instrux + 4971,
+ instrux + 4972,
+ instrux + 4973,
+ instrux + 4974,
+ instrux + 4975,
+ instrux + 4976,
+};
+
+static const struct itemplate * const itable_evex02193[] = {
+ instrux + 4985,
+ instrux + 4986,
+ instrux + 4987,
+ instrux + 4988,
+ instrux + 4989,
+ instrux + 4990,
+};
+
+static const struct itemplate * const itable_evex02196[] = {
+ instrux + 4855,
+ instrux + 4856,
+ instrux + 4857,
+ instrux + 4858,
+ instrux + 4859,
+ instrux + 4860,
+};
+
+static const struct itemplate * const itable_evex02197[] = {
+ instrux + 4897,
+ instrux + 4898,
+ instrux + 4899,
+ instrux + 4900,
+ instrux + 4901,
+ instrux + 4902,
+};
+
+static const struct itemplate * const itable_evex02198[] = {
+ instrux + 4831,
+ instrux + 4832,
+ instrux + 4833,
+ instrux + 4834,
+ instrux + 4835,
+ instrux + 4836,
+};
+
+static const struct itemplate * const itable_evex02199[] = {
+ instrux + 4837,
+ instrux + 4838,
+};
+
+static const struct itemplate * const itable_evex0219A[] = {
+ instrux + 4873,
+ instrux + 4874,
+ instrux + 4875,
+ instrux + 4876,
+ instrux + 4877,
+ instrux + 4878,
+};
+
+static const struct itemplate * const itable_evex0219B[] = {
+ instrux + 4879,
+ instrux + 4880,
+};
+
+static const struct itemplate * const itable_evex0219C[] = {
+ instrux + 4915,
+ instrux + 4916,
+ instrux + 4917,
+ instrux + 4918,
+ instrux + 4919,
+ instrux + 4920,
+};
+
+static const struct itemplate * const itable_evex0219D[] = {
+ instrux + 4921,
+ instrux + 4922,
+};
+
+static const struct itemplate * const itable_evex0219E[] = {
+ instrux + 4939,
+ instrux + 4940,
+ instrux + 4941,
+ instrux + 4942,
+ instrux + 4943,
+ instrux + 4944,
+};
+
+static const struct itemplate * const itable_evex0219F[] = {
+ instrux + 4945,
+ instrux + 4946,
+};
+
+static const struct itemplate * const itable_evex021A0[] = {
+ instrux + 6235,
+ instrux + 6236,
+ instrux + 6237,
+ instrux + 6238,
+ instrux + 6239,
+ instrux + 6240,
+};
+
+static const struct itemplate * const itable_evex021A1[] = {
+ instrux + 6241,
+ instrux + 6242,
+ instrux + 6243,
+ instrux + 6244,
+ instrux + 6245,
+ instrux + 6246,
+};
+
+static const struct itemplate * const itable_evex021A2[] = {
+ instrux + 6658,
+ instrux + 6659,
+ instrux + 6660,
+ instrux + 6661,
+ instrux + 6662,
+ instrux + 6663,
+};
+
+static const struct itemplate * const itable_evex021A3[] = {
+ instrux + 6672,
+ instrux + 6673,
+ instrux + 6674,
+ instrux + 6675,
+ instrux + 6676,
+ instrux + 6677,
+};
+
+static const struct itemplate * const itable_evex021A6[] = {
+ instrux + 4861,
+ instrux + 4862,
+ instrux + 4863,
+ instrux + 4864,
+ instrux + 4865,
+ instrux + 4866,
+};
+
+static const struct itemplate * const itable_evex021A7[] = {
+ instrux + 4903,
+ instrux + 4904,
+ instrux + 4905,
+ instrux + 4906,
+ instrux + 4907,
+ instrux + 4908,
+};
+
+static const struct itemplate * const itable_evex021A8[] = {
+ instrux + 4839,
+ instrux + 4840,
+ instrux + 4841,
+ instrux + 4842,
+ instrux + 4843,
+ instrux + 4844,
+};
+
+static const struct itemplate * const itable_evex021A9[] = {
+ instrux + 4845,
+ instrux + 4846,
+};
+
+static const struct itemplate * const itable_evex021AA[] = {
+ instrux + 4881,
+ instrux + 4882,
+ instrux + 4883,
+ instrux + 4884,
+ instrux + 4885,
+ instrux + 4886,
+};
+
+static const struct itemplate * const itable_evex021AB[] = {
+ instrux + 4887,
+ instrux + 4888,
+};
+
+static const struct itemplate * const itable_evex021AC[] = {
+ instrux + 4923,
+ instrux + 4924,
+ instrux + 4925,
+ instrux + 4926,
+ instrux + 4927,
+ instrux + 4928,
+};
+
+static const struct itemplate * const itable_evex021AD[] = {
+ instrux + 4929,
+ instrux + 4930,
+};
+
+static const struct itemplate * const itable_evex021AE[] = {
+ instrux + 4947,
+ instrux + 4948,
+ instrux + 4949,
+ instrux + 4950,
+ instrux + 4951,
+ instrux + 4952,
+};
+
+static const struct itemplate * const itable_evex021AF[] = {
+ instrux + 4953,
+ instrux + 4954,
+};
+
+static const struct itemplate * const itable_evex021B4[] = {
+ instrux + 5836,
+ instrux + 5837,
+ instrux + 5838,
+};
+
+static const struct itemplate * const itable_evex021B5[] = {
+ instrux + 5833,
+ instrux + 5834,
+ instrux + 5835,
+};
+
+static const struct itemplate * const itable_evex021B6[] = {
+ instrux + 4867,
+ instrux + 4868,
+ instrux + 4869,
+ instrux + 4870,
+ instrux + 4871,
+ instrux + 4872,
+};
+
+static const struct itemplate * const itable_evex021B7[] = {
+ instrux + 4909,
+ instrux + 4910,
+ instrux + 4911,
+ instrux + 4912,
+ instrux + 4913,
+ instrux + 4914,
+};
+
+static const struct itemplate * const itable_evex021B8[] = {
+ instrux + 4847,
+ instrux + 4848,
+ instrux + 4849,
+ instrux + 4850,
+ instrux + 4851,
+ instrux + 4852,
+};
+
+static const struct itemplate * const itable_evex021B9[] = {
+ instrux + 4853,
+ instrux + 4854,
+};
+
+static const struct itemplate * const itable_evex021BA[] = {
+ instrux + 4889,
+ instrux + 4890,
+ instrux + 4891,
+ instrux + 4892,
+ instrux + 4893,
+ instrux + 4894,
+};
+
+static const struct itemplate * const itable_evex021BB[] = {
+ instrux + 4895,
+ instrux + 4896,
+};
+
+static const struct itemplate * const itable_evex021BC[] = {
+ instrux + 4931,
+ instrux + 4932,
+ instrux + 4933,
+ instrux + 4934,
+ instrux + 4935,
+ instrux + 4936,
+};
+
+static const struct itemplate * const itable_evex021BD[] = {
+ instrux + 4937,
+ instrux + 4938,
+};
+
+static const struct itemplate * const itable_evex021BE[] = {
+ instrux + 4955,
+ instrux + 4956,
+ instrux + 4957,
+ instrux + 4958,
+ instrux + 4959,
+ instrux + 4960,
+};
+
+static const struct itemplate * const itable_evex021BF[] = {
+ instrux + 4961,
+ instrux + 4962,
+};
+
+static const struct itemplate * const itable_evex021C4[] = {
+ instrux + 5685,
+ instrux + 5686,
+ instrux + 5687,
+ instrux + 5688,
+ instrux + 5689,
+ instrux + 5690,
+};
+
+static const struct itemplate * const itable_evex021C6[] = {
+ instrux + 4977,
+ instrux + 4978,
+ instrux + 4981,
+ instrux + 4982,
+ instrux + 6664,
+ instrux + 6665,
+ instrux + 6668,
+ instrux + 6669,
+};
+
+static const struct itemplate * const itable_evex021C7[] = {
+ instrux + 4979,
+ instrux + 4980,
+ instrux + 4983,
+ instrux + 4984,
+ instrux + 6666,
+ instrux + 6667,
+ instrux + 6670,
+ instrux + 6671,
+};
+
+static const struct itemplate * const itable_evex021C8[] = {
+ instrux + 4774,
+ instrux + 4775,
+};
+
+static const struct itemplate * const itable_evex021CA[] = {
+ instrux + 6600,
+ instrux + 6601,
+};
+
+static const struct itemplate * const itable_evex021CB[] = {
+ instrux + 6602,
+ instrux + 6603,
+ instrux + 6604,
+ instrux + 6605,
+};
+
+static const struct itemplate * const itable_evex021CC[] = {
+ instrux + 6636,
+ instrux + 6637,
+};
+
+static const struct itemplate * const itable_evex021CD[] = {
+ instrux + 6638,
+ instrux + 6639,
+ instrux + 6640,
+ instrux + 6641,
+};
+
+static const struct itemplate * const itable_evex021CF[] = {
+ instrux + 6821,
+ instrux + 6822,
+ instrux + 6823,
+ instrux + 6824,
+ instrux + 6825,
+ instrux + 6826,
+};
+
+static const struct itemplate * const itable_evex021DC[] = {
+ instrux + 1901,
+ instrux + 1902,
+ instrux + 1903,
+ instrux + 1904,
+ instrux + 1917,
+ instrux + 1918,
+};
+
+static const struct itemplate * const itable_evex021DD[] = {
+ instrux + 1905,
+ instrux + 1906,
+ instrux + 1907,
+ instrux + 1908,
+ instrux + 1919,
+ instrux + 1920,
+};
+
+static const struct itemplate * const itable_evex021DE[] = {
+ instrux + 1909,
+ instrux + 1910,
+ instrux + 1911,
+ instrux + 1912,
+ instrux + 1921,
+ instrux + 1922,
+};
+
+static const struct itemplate * const itable_evex021DF[] = {
+ instrux + 1913,
+ instrux + 1914,
+ instrux + 1915,
+ instrux + 1916,
+ instrux + 1923,
+ instrux + 1924,
+};
+
+static const struct itemplate * const itable_evex02210[] = {
+ instrux + 6082,
+ instrux + 6083,
+ instrux + 6084,
+ instrux + 6085,
+ instrux + 6086,
+ instrux + 6087,
+};
+
+static const struct itemplate * const itable_evex02211[] = {
+ instrux + 6052,
+ instrux + 6053,
+ instrux + 6054,
+ instrux + 6055,
+ instrux + 6056,
+ instrux + 6057,
+};
+
+static const struct itemplate * const itable_evex02212[] = {
+ instrux + 6064,
+ instrux + 6065,
+ instrux + 6066,
+ instrux + 6067,
+ instrux + 6068,
+ instrux + 6069,
+};
+
+static const struct itemplate * const itable_evex02213[] = {
+ instrux + 6058,
+ instrux + 6059,
+ instrux + 6060,
+ instrux + 6061,
+ instrux + 6062,
+ instrux + 6063,
+};
+
+static const struct itemplate * const itable_evex02214[] = {
+ instrux + 6076,
+ instrux + 6077,
+ instrux + 6078,
+ instrux + 6079,
+ instrux + 6080,
+ instrux + 6081,
+};
+
+static const struct itemplate * const itable_evex02215[] = {
+ instrux + 6070,
+ instrux + 6071,
+ instrux + 6072,
+ instrux + 6073,
+ instrux + 6074,
+ instrux + 6075,
+};
+
+static const struct itemplate * const itable_evex02220[] = {
+ instrux + 6028,
+ instrux + 6029,
+ instrux + 6030,
+ instrux + 6031,
+ instrux + 6032,
+ instrux + 6033,
+};
+
+static const struct itemplate * const itable_evex02221[] = {
+ instrux + 5998,
+ instrux + 5999,
+ instrux + 6000,
+ instrux + 6001,
+ instrux + 6002,
+ instrux + 6003,
+};
+
+static const struct itemplate * const itable_evex02222[] = {
+ instrux + 6010,
+ instrux + 6011,
+ instrux + 6012,
+ instrux + 6013,
+ instrux + 6014,
+ instrux + 6015,
+};
+
+static const struct itemplate * const itable_evex02223[] = {
+ instrux + 6004,
+ instrux + 6005,
+ instrux + 6006,
+ instrux + 6007,
+ instrux + 6008,
+ instrux + 6009,
+};
+
+static const struct itemplate * const itable_evex02224[] = {
+ instrux + 6022,
+ instrux + 6023,
+ instrux + 6024,
+ instrux + 6025,
+ instrux + 6026,
+ instrux + 6027,
+};
+
+static const struct itemplate * const itable_evex02225[] = {
+ instrux + 6016,
+ instrux + 6017,
+ instrux + 6018,
+ instrux + 6019,
+ instrux + 6020,
+ instrux + 6021,
+};
+
+static const struct itemplate * const itable_evex02226[] = {
+ instrux + 6502,
+ instrux + 6503,
+ instrux + 6504,
+ instrux + 6511,
+ instrux + 6512,
+ instrux + 6513,
+};
+
+static const struct itemplate * const itable_evex02227[] = {
+ instrux + 6505,
+ instrux + 6506,
+ instrux + 6507,
+ instrux + 6508,
+ instrux + 6509,
+ instrux + 6510,
+};
+
+static const struct itemplate * const itable_evex02228[] = {
+ instrux + 5965,
+ instrux + 5966,
+ instrux + 5967,
+ instrux + 5974,
+ instrux + 5975,
+ instrux + 5976,
+};
+
+static const struct itemplate * const itable_evex02229[] = {
+ instrux + 5947,
+ instrux + 5948,
+ instrux + 5949,
+ instrux + 6088,
+ instrux + 6089,
+ instrux + 6090,
+};
+
+static const struct itemplate * const itable_evex0222A[] = {
+ instrux + 5382,
+ instrux + 5383,
+ instrux + 5384,
+};
+
+static const struct itemplate * const itable_evex02230[] = {
+ instrux + 6091,
+ instrux + 6092,
+ instrux + 6093,
+ instrux + 6094,
+ instrux + 6095,
+ instrux + 6096,
+};
+
+static const struct itemplate * const itable_evex02231[] = {
+ instrux + 5953,
+ instrux + 5954,
+ instrux + 5955,
+ instrux + 5956,
+ instrux + 5957,
+ instrux + 5958,
+};
+
+static const struct itemplate * const itable_evex02232[] = {
+ instrux + 5980,
+ instrux + 5981,
+ instrux + 5982,
+ instrux + 5983,
+ instrux + 5984,
+ instrux + 5985,
+};
+
+static const struct itemplate * const itable_evex02233[] = {
+ instrux + 5959,
+ instrux + 5960,
+ instrux + 5961,
+ instrux + 5962,
+ instrux + 5963,
+ instrux + 5964,
+};
+
+static const struct itemplate * const itable_evex02234[] = {
+ instrux + 5992,
+ instrux + 5993,
+ instrux + 5994,
+ instrux + 5995,
+ instrux + 5996,
+ instrux + 5997,
+};
+
+static const struct itemplate * const itable_evex02235[] = {
+ instrux + 5986,
+ instrux + 5987,
+ instrux + 5988,
+ instrux + 5989,
+ instrux + 5990,
+ instrux + 5991,
+};
+
+static const struct itemplate * const itable_evex02238[] = {
+ instrux + 5968,
+ instrux + 5969,
+ instrux + 5970,
+ instrux + 5971,
+ instrux + 5972,
+ instrux + 5973,
+};
+
+static const struct itemplate * const itable_evex02239[] = {
+ instrux + 5950,
+ instrux + 5951,
+ instrux + 5952,
+ instrux + 5977,
+ instrux + 5978,
+ instrux + 5979,
+};
+
+static const struct itemplate * const itable_evex0223A[] = {
+ instrux + 5385,
+ instrux + 5386,
+ instrux + 5387,
+};
+
+static const struct itemplate * const itable_evex02252[] = {
+ instrux + 7002,
+ instrux + 7003,
+ instrux + 7004,
+ instrux + 7005,
+ instrux + 7006,
+ instrux + 7007,
+};
+
+static const struct itemplate * const itable_evex02272[] = {
+ instrux + 6996,
+ instrux + 6997,
+ instrux + 6998,
+ instrux + 6999,
+ instrux + 7000,
+ instrux + 7001,
+};
+
+static const struct itemplate * const itable_evex02352[] = {
+ instrux + 6961,
+};
+
+static const struct itemplate * const itable_evex02353[] = {
+ instrux + 6960,
+};
+
+static const struct itemplate * const itable_evex02368[] = {
+ instrux + 7008,
+ instrux + 7009,
+ instrux + 7010,
+};
+
+static const struct itemplate * const itable_evex02372[] = {
+ instrux + 6990,
+ instrux + 6991,
+ instrux + 6992,
+ instrux + 6993,
+ instrux + 6994,
+ instrux + 6995,
+};
+
+static const struct itemplate * const itable_evex0239A[] = {
+ instrux + 6956,
+};
+
+static const struct itemplate * const itable_evex0239B[] = {
+ instrux + 6958,
+};
+
+static const struct itemplate * const itable_evex023AA[] = {
+ instrux + 6957,
+};
+
+static const struct itemplate * const itable_evex023AB[] = {
+ instrux + 6959,
+};
+
+static const struct itemplate * const itable_evex03008[] = {
+ instrux + 7362,
+ instrux + 7363,
+ instrux + 7364,
+};
+
+static const struct itemplate * const itable_evex0300A[] = {
+ instrux + 7365,
+ instrux + 7366,
+};
+
+static const struct itemplate * const itable_evex03025[] = {
+ instrux + 7321,
+ instrux + 7322,
+ instrux + 7323,
+};
+
+static const struct itemplate * const itable_evex03027[] = {
+ instrux + 7324,
+};
+
+static const struct itemplate * const itable_evex03056[] = {
+ instrux + 7357,
+ instrux + 7358,
+ instrux + 7359,
+};
+
+static const struct itemplate * const itable_evex03057[] = {
+ instrux + 7360,
+ instrux + 7361,
+};
+
+static const struct itemplate * const itable_evex03066[] = {
+ instrux + 7313,
+ instrux + 7314,
+ instrux + 7315,
+};
+
+static const struct itemplate * const itable_evex03067[] = {
+ instrux + 7316,
+};
+
+static const struct itemplate * const itable_evex030C2[] = {
+ instrux + 7031,
+ instrux + 7032,
+ instrux + 7033,
+ instrux + 7034,
+ instrux + 7035,
+ instrux + 7036,
+};
+
+static const struct itemplate * const itable_evex03100[] = {
+ instrux + 5747,
+ instrux + 5748,
+};
+
+static const struct itemplate * const itable_evex03101[] = {
+ instrux + 5737,
+ instrux + 5738,
+};
+
+static const struct itemplate * const itable_evex03103[] = {
+ instrux + 4180,
+ instrux + 4181,
+ instrux + 4182,
+ instrux + 4183,
+ instrux + 4184,
+ instrux + 4185,
+ instrux + 4186,
+ instrux + 4187,
+ instrux + 4188,
+ instrux + 4189,
+ instrux + 4190,
+ instrux + 4191,
+};
+
+static const struct itemplate * const itable_evex03104[] = {
+ instrux + 5728,
+ instrux + 5729,
+ instrux + 5730,
+};
+
+static const struct itemplate * const itable_evex03105[] = {
+ instrux + 5719,
+ instrux + 5720,
+ instrux + 5721,
+};
+
+static const struct itemplate * const itable_evex03108[] = {
+ instrux + 6619,
+ instrux + 6620,
+ instrux + 6621,
+};
+
+static const struct itemplate * const itable_evex03109[] = {
+ instrux + 6616,
+ instrux + 6617,
+ instrux + 6618,
+};
+
+static const struct itemplate * const itable_evex0310A[] = {
+ instrux + 6624,
+ instrux + 6625,
+};
+
+static const struct itemplate * const itable_evex0310B[] = {
+ instrux + 6622,
+ instrux + 6623,
+};
+
+static const struct itemplate * const itable_evex0310F[] = {
+ instrux + 5304,
+ instrux + 5305,
+ instrux + 5306,
+ instrux + 5307,
+ instrux + 5308,
+ instrux + 5309,
+};
+
+static const struct itemplate * const itable_evex03114[] = {
+ instrux + 5789,
+ instrux + 5790,
+ instrux + 5791,
+ instrux + 5792,
+ instrux + 5793,
+};
+
+static const struct itemplate * const itable_evex03115[] = {
+ instrux + 5796,
+ instrux + 5797,
+ instrux + 5798,
+ instrux + 5799,
+};
+
+static const struct itemplate * const itable_evex03116[] = {
+ instrux + 5794,
+ instrux + 5795,
+};
+
+static const struct itemplate * const itable_evex03117[] = {
+ instrux + 4812,
+ instrux + 4813,
+ instrux + 4814,
+};
+
+static const struct itemplate * const itable_evex03118[] = {
+ instrux + 5007,
+ instrux + 5008,
+ instrux + 5009,
+ instrux + 5010,
+ instrux + 5013,
+ instrux + 5014,
+ instrux + 5015,
+ instrux + 5016,
+};
+
+static const struct itemplate * const itable_evex03119[] = {
+ instrux + 4788,
+ instrux + 4789,
+ instrux + 4790,
+ instrux + 4791,
+ instrux + 4794,
+ instrux + 4795,
+ instrux + 4796,
+ instrux + 4797,
+};
+
+static const struct itemplate * const itable_evex0311A[] = {
+ instrux + 5011,
+ instrux + 5012,
+ instrux + 5017,
+ instrux + 5018,
+};
+
+static const struct itemplate * const itable_evex0311B[] = {
+ instrux + 4792,
+ instrux + 4793,
+ instrux + 4798,
+ instrux + 4799,
+};
+
+static const struct itemplate * const itable_evex0311D[] = {
+ instrux + 4669,
+ instrux + 4670,
+ instrux + 4671,
+ instrux + 4672,
+ instrux + 4673,
+ instrux + 4674,
+ instrux + 7077,
+ instrux + 7078,
+ instrux + 7079,
+ instrux + 7080,
+ instrux + 7081,
+ instrux + 7082,
+};
+
+static const struct itemplate * const itable_evex0311E[] = {
+ instrux + 5445,
+ instrux + 5446,
+ instrux + 5447,
+ instrux + 5448,
+ instrux + 5449,
+ instrux + 5450,
+ instrux + 5469,
+ instrux + 5470,
+ instrux + 5471,
+ instrux + 5472,
+ instrux + 5473,
+ instrux + 5474,
+ instrux + 5493,
+ instrux + 5494,
+ instrux + 5495,
+ instrux + 5496,
+ instrux + 5497,
+ instrux + 5498,
+ instrux + 5517,
+ instrux + 5518,
+ instrux + 5519,
+ instrux + 5520,
+ instrux + 5521,
+ instrux + 5522,
+ instrux + 5541,
+ instrux + 5542,
+ instrux + 5543,
+ instrux + 5544,
+ instrux + 5545,
+ instrux + 5546,
+ instrux + 5565,
+ instrux + 5566,
+ instrux + 5567,
+ instrux + 5568,
+ instrux + 5569,
+ instrux + 5570,
+ instrux + 5589,
+ instrux + 5590,
+ instrux + 5591,
+ instrux + 5592,
+ instrux + 5593,
+ instrux + 5594,
+ instrux + 5613,
+ instrux + 5614,
+ instrux + 5615,
+ instrux + 5616,
+ instrux + 5617,
+ instrux + 5618,
+ instrux + 5637,
+ instrux + 5638,
+ instrux + 5639,
+ instrux + 5640,
+ instrux + 5641,
+ instrux + 5642,
+ instrux + 5661,
+ instrux + 5662,
+ instrux + 5663,
+ instrux + 5664,
+ instrux + 5665,
+ instrux + 5666,
+};
+
+static const struct itemplate * const itable_evex0311F[] = {
+ instrux + 5436,
+ instrux + 5437,
+ instrux + 5438,
+ instrux + 5439,
+ instrux + 5440,
+ instrux + 5441,
+ instrux + 5460,
+ instrux + 5461,
+ instrux + 5462,
+ instrux + 5463,
+ instrux + 5464,
+ instrux + 5465,
+ instrux + 5484,
+ instrux + 5485,
+ instrux + 5486,
+ instrux + 5487,
+ instrux + 5488,
+ instrux + 5489,
+ instrux + 5508,
+ instrux + 5509,
+ instrux + 5510,
+ instrux + 5511,
+ instrux + 5512,
+ instrux + 5513,
+ instrux + 5532,
+ instrux + 5533,
+ instrux + 5534,
+ instrux + 5535,
+ instrux + 5536,
+ instrux + 5537,
+ instrux + 5556,
+ instrux + 5557,
+ instrux + 5558,
+ instrux + 5559,
+ instrux + 5560,
+ instrux + 5561,
+ instrux + 5580,
+ instrux + 5581,
+ instrux + 5582,
+ instrux + 5583,
+ instrux + 5584,
+ instrux + 5585,
+ instrux + 5604,
+ instrux + 5605,
+ instrux + 5606,
+ instrux + 5607,
+ instrux + 5608,
+ instrux + 5609,
+ instrux + 5628,
+ instrux + 5629,
+ instrux + 5630,
+ instrux + 5631,
+ instrux + 5632,
+ instrux + 5633,
+ instrux + 5652,
+ instrux + 5653,
+ instrux + 5654,
+ instrux + 5655,
+ instrux + 5656,
+ instrux + 5657,
+};
+
+static const struct itemplate * const itable_evex03120[] = {
+ instrux + 5815,
+ instrux + 5816,
+ instrux + 5817,
+ instrux + 5818,
+};
+
+static const struct itemplate * const itable_evex03121[] = {
+ instrux + 5031,
+ instrux + 5032,
+};
+
+static const struct itemplate * const itable_evex03122[] = {
+ instrux + 5819,
+ instrux + 5820,
+ instrux + 5821,
+ instrux + 5822,
+};
+
+static const struct itemplate * const itable_evex03123[] = {
+ instrux + 6678,
+ instrux + 6679,
+ instrux + 6680,
+ instrux + 6681,
+ instrux + 6682,
+ instrux + 6683,
+ instrux + 6684,
+ instrux + 6685,
+};
+
+static const struct itemplate * const itable_evex03125[] = {
+ instrux + 6484,
+ instrux + 6485,
+ instrux + 6486,
+ instrux + 6487,
+ instrux + 6488,
+ instrux + 6489,
+};
+
+static const struct itemplate * const itable_evex03126[] = {
+ instrux + 4999,
+ instrux + 5000,
+ instrux + 5001,
+ instrux + 5002,
+ instrux + 5003,
+ instrux + 5004,
+};
+
+static const struct itemplate * const itable_evex03127[] = {
+ instrux + 5005,
+ instrux + 5006,
+};
+
+static const struct itemplate * const itable_evex03138[] = {
+ instrux + 5019,
+ instrux + 5020,
+ instrux + 5021,
+ instrux + 5022,
+ instrux + 5025,
+ instrux + 5026,
+ instrux + 5027,
+ instrux + 5028,
+};
+
+static const struct itemplate * const itable_evex03139[] = {
+ instrux + 4800,
+ instrux + 4801,
+ instrux + 4802,
+ instrux + 4803,
+ instrux + 4806,
+ instrux + 4807,
+ instrux + 4808,
+ instrux + 4809,
+};
+
+static const struct itemplate * const itable_evex0313A[] = {
+ instrux + 5023,
+ instrux + 5024,
+ instrux + 5029,
+ instrux + 5030,
+};
+
+static const struct itemplate * const itable_evex0313B[] = {
+ instrux + 4804,
+ instrux + 4805,
+ instrux + 4810,
+ instrux + 4811,
+};
+
+static const struct itemplate * const itable_evex0313E[] = {
+ instrux + 5442,
+ instrux + 5443,
+ instrux + 5444,
+ instrux + 5451,
+ instrux + 5452,
+ instrux + 5453,
+ instrux + 5466,
+ instrux + 5467,
+ instrux + 5468,
+ instrux + 5475,
+ instrux + 5476,
+ instrux + 5477,
+ instrux + 5490,
+ instrux + 5491,
+ instrux + 5492,
+ instrux + 5499,
+ instrux + 5500,
+ instrux + 5501,
+ instrux + 5514,
+ instrux + 5515,
+ instrux + 5516,
+ instrux + 5523,
+ instrux + 5524,
+ instrux + 5525,
+ instrux + 5538,
+ instrux + 5539,
+ instrux + 5540,
+ instrux + 5547,
+ instrux + 5548,
+ instrux + 5549,
+ instrux + 5562,
+ instrux + 5563,
+ instrux + 5564,
+ instrux + 5571,
+ instrux + 5572,
+ instrux + 5573,
+ instrux + 5586,
+ instrux + 5587,
+ instrux + 5588,
+ instrux + 5595,
+ instrux + 5596,
+ instrux + 5597,
+ instrux + 5610,
+ instrux + 5611,
+ instrux + 5612,
+ instrux + 5619,
+ instrux + 5620,
+ instrux + 5621,
+ instrux + 5634,
+ instrux + 5635,
+ instrux + 5636,
+ instrux + 5643,
+ instrux + 5644,
+ instrux + 5645,
+ instrux + 5658,
+ instrux + 5659,
+ instrux + 5660,
+ instrux + 5667,
+ instrux + 5668,
+ instrux + 5669,
+};
+
+static const struct itemplate * const itable_evex0313F[] = {
+ instrux + 5433,
+ instrux + 5434,
+ instrux + 5435,
+ instrux + 5454,
+ instrux + 5455,
+ instrux + 5456,
+ instrux + 5457,
+ instrux + 5458,
+ instrux + 5459,
+ instrux + 5478,
+ instrux + 5479,
+ instrux + 5480,
+ instrux + 5481,
+ instrux + 5482,
+ instrux + 5483,
+ instrux + 5502,
+ instrux + 5503,
+ instrux + 5504,
+ instrux + 5505,
+ instrux + 5506,
+ instrux + 5507,
+ instrux + 5526,
+ instrux + 5527,
+ instrux + 5528,
+ instrux + 5529,
+ instrux + 5530,
+ instrux + 5531,
+ instrux + 5550,
+ instrux + 5551,
+ instrux + 5552,
+ instrux + 5553,
+ instrux + 5554,
+ instrux + 5555,
+ instrux + 5574,
+ instrux + 5575,
+ instrux + 5576,
+ instrux + 5577,
+ instrux + 5578,
+ instrux + 5579,
+ instrux + 5598,
+ instrux + 5599,
+ instrux + 5600,
+ instrux + 5601,
+ instrux + 5602,
+ instrux + 5603,
+ instrux + 5622,
+ instrux + 5623,
+ instrux + 5624,
+ instrux + 5625,
+ instrux + 5626,
+ instrux + 5627,
+ instrux + 5646,
+ instrux + 5647,
+ instrux + 5648,
+ instrux + 5649,
+ instrux + 5650,
+ instrux + 5651,
+ instrux + 5670,
+ instrux + 5671,
+ instrux + 5672,
+};
+
+static const struct itemplate * const itable_evex03142[] = {
+ instrux + 4752,
+ instrux + 4753,
+ instrux + 4754,
+ instrux + 4755,
+ instrux + 4756,
+ instrux + 4757,
+};
+
+static const struct itemplate * const itable_evex03143[] = {
+ instrux + 6686,
+ instrux + 6687,
+ instrux + 6688,
+ instrux + 6689,
+ instrux + 6690,
+ instrux + 6691,
+ instrux + 6692,
+ instrux + 6693,
+};
+
+static const struct itemplate * const itable_evex03144[] = {
+ instrux + 3136,
+ instrux + 3137,
+ instrux + 3138,
+ instrux + 3139,
+ instrux + 3140,
+ instrux + 3141,
+ instrux + 3142,
+ instrux + 3143,
+ instrux + 3144,
+ instrux + 3145,
+ instrux + 3146,
+ instrux + 3147,
+ instrux + 3148,
+ instrux + 3149,
+ instrux + 3150,
+ instrux + 3151,
+ instrux + 3152,
+ instrux + 3153,
+ instrux + 3154,
+ instrux + 3155,
+ instrux + 3156,
+ instrux + 3157,
+ instrux + 3158,
+ instrux + 3159,
+ instrux + 3160,
+ instrux + 3161,
+ instrux + 3162,
+ instrux + 3163,
+ instrux + 3164,
+ instrux + 3165,
+};
+
+static const struct itemplate * const itable_evex03150[] = {
+ instrux + 6574,
+ instrux + 6575,
+ instrux + 6576,
+ instrux + 6577,
+ instrux + 6578,
+ instrux + 6579,
+ instrux + 6580,
+ instrux + 6581,
+ instrux + 6582,
+ instrux + 6583,
+ instrux + 6584,
+ instrux + 6585,
+};
+
+static const struct itemplate * const itable_evex03151[] = {
+ instrux + 6586,
+ instrux + 6587,
+ instrux + 6588,
+ instrux + 6589,
+};
+
+static const struct itemplate * const itable_evex03154[] = {
+ instrux + 4815,
+ instrux + 4816,
+ instrux + 4817,
+ instrux + 4818,
+ instrux + 4819,
+ instrux + 4820,
+ instrux + 4821,
+ instrux + 4822,
+ instrux + 4823,
+ instrux + 4824,
+ instrux + 4825,
+ instrux + 4826,
+};
+
+static const struct itemplate * const itable_evex03155[] = {
+ instrux + 4827,
+ instrux + 4828,
+ instrux + 4829,
+ instrux + 4830,
+};
+
+static const struct itemplate * const itable_evex03156[] = {
+ instrux + 6606,
+ instrux + 6607,
+ instrux + 6608,
+ instrux + 6609,
+ instrux + 6610,
+ instrux + 6611,
+};
+
+static const struct itemplate * const itable_evex03157[] = {
+ instrux + 6612,
+ instrux + 6613,
+ instrux + 6614,
+ instrux + 6615,
+};
+
+static const struct itemplate * const itable_evex03166[] = {
+ instrux + 4963,
+ instrux + 4964,
+ instrux + 4965,
+ instrux + 4966,
+ instrux + 4967,
+ instrux + 4968,
+};
+
+static const struct itemplate * const itable_evex03167[] = {
+ instrux + 4969,
+ instrux + 4970,
+};
+
+static const struct itemplate * const itable_evex03170[] = {
+ instrux + 6845,
+ instrux + 6846,
+ instrux + 6847,
+ instrux + 6848,
+ instrux + 6849,
+ instrux + 6850,
+};
+
+static const struct itemplate * const itable_evex03171[] = {
+ instrux + 6851,
+ instrux + 6852,
+ instrux + 6853,
+ instrux + 6854,
+ instrux + 6855,
+ instrux + 6856,
+ instrux + 6857,
+ instrux + 6858,
+ instrux + 6859,
+ instrux + 6860,
+ instrux + 6861,
+ instrux + 6862,
+};
+
+static const struct itemplate * const itable_evex03172[] = {
+ instrux + 6881,
+ instrux + 6882,
+ instrux + 6883,
+ instrux + 6884,
+ instrux + 6885,
+ instrux + 6886,
+};
+
+static const struct itemplate * const itable_evex03173[] = {
+ instrux + 6887,
+ instrux + 6888,
+ instrux + 6889,
+ instrux + 6890,
+ instrux + 6891,
+ instrux + 6892,
+ instrux + 6893,
+ instrux + 6894,
+ instrux + 6895,
+ instrux + 6896,
+ instrux + 6897,
+ instrux + 6898,
+};
+
+static const struct itemplate * const itable_evex031CE[] = {
+ instrux + 6810,
+ instrux + 6811,
+ instrux + 6812,
+ instrux + 6813,
+ instrux + 6814,
+ instrux + 6815,
+};
+
+static const struct itemplate * const itable_evex031CF[] = {
+ instrux + 6799,
+ instrux + 6800,
+ instrux + 6801,
+ instrux + 6802,
+ instrux + 6803,
+ instrux + 6804,
+};
+
+static const struct itemplate * const itable_evex032C2[] = {
+ instrux + 7037,
+ instrux + 7038,
+};
+
+static const struct itemplate * const itable_evex0501D[] = {
+ instrux + 7103,
+ instrux + 7104,
+};
+
+static const struct itemplate * const itable_evex0502E[] = {
+ instrux + 7393,
+};
+
+static const struct itemplate * const itable_evex0502F[] = {
+ instrux + 7039,
+};
+
+static const struct itemplate * const itable_evex05051[] = {
+ instrux + 7380,
+ instrux + 7381,
+ instrux + 7382,
+};
+
+static const struct itemplate * const itable_evex05058[] = {
+ instrux + 7023,
+ instrux + 7024,
+ instrux + 7025,
+ instrux + 7026,
+ instrux + 7027,
+ instrux + 7028,
+};
+
+static const struct itemplate * const itable_evex05059[] = {
+ instrux + 7341,
+ instrux + 7342,
+ instrux + 7343,
+ instrux + 7344,
+ instrux + 7345,
+ instrux + 7346,
+};
+
+static const struct itemplate * const itable_evex0505A[] = {
+ instrux + 7049,
+ instrux + 7050,
+ instrux + 7051,
+};
+
+static const struct itemplate * const itable_evex0505B[] = {
+ instrux + 7040,
+ instrux + 7041,
+ instrux + 7042,
+ instrux + 7086,
+ instrux + 7087,
+ instrux + 7088,
+};
+
+static const struct itemplate * const itable_evex0505C[] = {
+ instrux + 7385,
+ instrux + 7386,
+ instrux + 7387,
+ instrux + 7388,
+ instrux + 7389,
+ instrux + 7390,
+};
+
+static const struct itemplate * const itable_evex0505D[] = {
+ instrux + 7329,
+ instrux + 7330,
+ instrux + 7331,
+};
+
+static const struct itemplate * const itable_evex0505E[] = {
+ instrux + 7141,
+ instrux + 7142,
+ instrux + 7143,
+ instrux + 7144,
+ instrux + 7145,
+ instrux + 7146,
+};
+
+static const struct itemplate * const itable_evex0505F[] = {
+ instrux + 7325,
+ instrux + 7326,
+ instrux + 7327,
+};
+
+static const struct itemplate * const itable_evex05078[] = {
+ instrux + 7111,
+ instrux + 7112,
+ instrux + 7113,
+};
+
+static const struct itemplate * const itable_evex05079[] = {
+ instrux + 7063,
+ instrux + 7064,
+ instrux + 7065,
+};
+
+static const struct itemplate * const itable_evex0507C[] = {
+ instrux + 7117,
+ instrux + 7118,
+ instrux + 7119,
+};
+
+static const struct itemplate * const itable_evex0507D[] = {
+ instrux + 7069,
+ instrux + 7070,
+ instrux + 7071,
+};
+
+static const struct itemplate * const itable_evex0511D[] = {
+ instrux + 7083,
+ instrux + 7084,
+ instrux + 7085,
+};
+
+static const struct itemplate * const itable_evex0515A[] = {
+ instrux + 7043,
+ instrux + 7044,
+ instrux + 7045,
+};
+
+static const struct itemplate * const itable_evex0515B[] = {
+ instrux + 7046,
+ instrux + 7047,
+ instrux + 7048,
+};
+
+static const struct itemplate * const itable_evex0516E[] = {
+ instrux + 7339,
+};
+
+static const struct itemplate * const itable_evex05178[] = {
+ instrux + 7114,
+ instrux + 7115,
+ instrux + 7116,
+};
+
+static const struct itemplate * const itable_evex05179[] = {
+ instrux + 7066,
+ instrux + 7067,
+ instrux + 7068,
+};
+
+static const struct itemplate * const itable_evex0517A[] = {
+ instrux + 7108,
+ instrux + 7109,
+ instrux + 7110,
+};
+
+static const struct itemplate * const itable_evex0517B[] = {
+ instrux + 7060,
+ instrux + 7061,
+ instrux + 7062,
+};
+
+static const struct itemplate * const itable_evex0517C[] = {
+ instrux + 7120,
+ instrux + 7121,
+ instrux + 7122,
+};
+
+static const struct itemplate * const itable_evex0517D[] = {
+ instrux + 7072,
+ instrux + 7073,
+ instrux + 7074,
+};
+
+static const struct itemplate * const itable_evex0517E[] = {
+ instrux + 7340,
+};
+
+static const struct itemplate * const itable_evex05210[] = {
+ instrux + 7333,
+ instrux + 7335,
+ instrux + 7336,
+};
+
+static const struct itemplate * const itable_evex05211[] = {
+ instrux + 7334,
+ instrux + 7337,
+ instrux + 7338,
+};
+
+static const struct itemplate * const itable_evex0522A[] = {
+ instrux + 7099,
+ instrux + 7100,
+ instrux + 7101,
+ instrux + 7102,
+};
+
+static const struct itemplate * const itable_evex0522C[] = {
+ instrux + 7123,
+ instrux + 7124,
+};
+
+static const struct itemplate * const itable_evex0522D[] = {
+ instrux + 7093,
+ instrux + 7094,
+};
+
+static const struct itemplate * const itable_evex05251[] = {
+ instrux + 7383,
+ instrux + 7384,
+};
+
+static const struct itemplate * const itable_evex05258[] = {
+ instrux + 7029,
+ instrux + 7030,
+};
+
+static const struct itemplate * const itable_evex05259[] = {
+ instrux + 7347,
+ instrux + 7348,
+};
+
+static const struct itemplate * const itable_evex0525A[] = {
+ instrux + 7091,
+ instrux + 7092,
+};
+
+static const struct itemplate * const itable_evex0525B[] = {
+ instrux + 7105,
+ instrux + 7106,
+ instrux + 7107,
+};
+
+static const struct itemplate * const itable_evex0525C[] = {
+ instrux + 7391,
+ instrux + 7392,
+};
+
+static const struct itemplate * const itable_evex0525D[] = {
+ instrux + 7332,
+};
+
+static const struct itemplate * const itable_evex0525E[] = {
+ instrux + 7147,
+ instrux + 7148,
+};
+
+static const struct itemplate * const itable_evex0525F[] = {
+ instrux + 7328,
+};
+
+static const struct itemplate * const itable_evex05278[] = {
+ instrux + 7125,
+ instrux + 7126,
+};
+
+static const struct itemplate * const itable_evex05279[] = {
+ instrux + 7097,
+ instrux + 7098,
+};
+
+static const struct itemplate * const itable_evex0527B[] = {
+ instrux + 7133,
+ instrux + 7134,
+};
+
+static const struct itemplate * const itable_evex0527D[] = {
+ instrux + 7138,
+ instrux + 7139,
+ instrux + 7140,
+};
+
+static const struct itemplate * const itable_evex0535A[] = {
+ instrux + 7089,
+ instrux + 7090,
+};
+
+static const struct itemplate * const itable_evex0537A[] = {
+ instrux + 7127,
+ instrux + 7128,
+ instrux + 7129,
+ instrux + 7130,
+ instrux + 7131,
+ instrux + 7132,
+};
+
+static const struct itemplate * const itable_evex0537D[] = {
+ instrux + 7135,
+ instrux + 7136,
+ instrux + 7137,
+};
+
+static const struct itemplate * const itable_evex06013[] = {
+ instrux + 7095,
+ instrux + 7096,
+};
+
+static const struct itemplate * const itable_evex06113[] = {
+ instrux + 7057,
+ instrux + 7058,
+ instrux + 7059,
+};
+
+static const struct itemplate * const itable_evex0612C[] = {
+ instrux + 7372,
+ instrux + 7373,
+ instrux + 7374,
+ instrux + 7375,
+ instrux + 7376,
+ instrux + 7377,
+};
+
+static const struct itemplate * const itable_evex0612D[] = {
+ instrux + 7378,
+ instrux + 7379,
+};
+
+static const struct itemplate * const itable_evex06142[] = {
+ instrux + 7317,
+ instrux + 7318,
+ instrux + 7319,
+};
+
+static const struct itemplate * const itable_evex06143[] = {
+ instrux + 7320,
+};
+
+static const struct itemplate * const itable_evex0614C[] = {
+ instrux + 7349,
+ instrux + 7350,
+ instrux + 7351,
+ instrux + 7352,
+ instrux + 7353,
+ instrux + 7354,
+};
+
+static const struct itemplate * const itable_evex0614D[] = {
+ instrux + 7355,
+ instrux + 7356,
+};
+
+static const struct itemplate * const itable_evex0614E[] = {
+ instrux + 7367,
+ instrux + 7368,
+ instrux + 7369,
+};
+
+static const struct itemplate * const itable_evex0614F[] = {
+ instrux + 7370,
+ instrux + 7371,
+};
+
+static const struct itemplate * const itable_evex06196[] = {
+ instrux + 7181,
+ instrux + 7182,
+ instrux + 7183,
+ instrux + 7184,
+ instrux + 7185,
+ instrux + 7186,
+};
+
+static const struct itemplate * const itable_evex06197[] = {
+ instrux + 7199,
+ instrux + 7200,
+ instrux + 7201,
+ instrux + 7202,
+ instrux + 7203,
+ instrux + 7204,
+};
+
+static const struct itemplate * const itable_evex06198[] = {
+ instrux + 7217,
+ instrux + 7218,
+ instrux + 7219,
+ instrux + 7220,
+ instrux + 7221,
+ instrux + 7222,
+};
+
+static const struct itemplate * const itable_evex06199[] = {
+ instrux + 7253,
+ instrux + 7254,
+};
+
+static const struct itemplate * const itable_evex0619A[] = {
+ instrux + 7265,
+ instrux + 7266,
+ instrux + 7267,
+ instrux + 7268,
+ instrux + 7269,
+ instrux + 7270,
+};
+
+static const struct itemplate * const itable_evex0619B[] = {
+ instrux + 7301,
+ instrux + 7302,
+};
+
+static const struct itemplate * const itable_evex0619C[] = {
+ instrux + 7235,
+ instrux + 7236,
+ instrux + 7237,
+ instrux + 7238,
+ instrux + 7239,
+ instrux + 7240,
+};
+
+static const struct itemplate * const itable_evex0619D[] = {
+ instrux + 7259,
+ instrux + 7260,
+};
+
+static const struct itemplate * const itable_evex0619E[] = {
+ instrux + 7283,
+ instrux + 7284,
+ instrux + 7285,
+ instrux + 7286,
+ instrux + 7287,
+ instrux + 7288,
+};
+
+static const struct itemplate * const itable_evex0619F[] = {
+ instrux + 7307,
+ instrux + 7308,
+};
+
+static const struct itemplate * const itable_evex061A6[] = {
+ instrux + 7187,
+ instrux + 7188,
+ instrux + 7189,
+ instrux + 7190,
+ instrux + 7191,
+ instrux + 7192,
+};
+
+static const struct itemplate * const itable_evex061A7[] = {
+ instrux + 7205,
+ instrux + 7206,
+ instrux + 7207,
+ instrux + 7208,
+ instrux + 7209,
+ instrux + 7210,
+};
+
+static const struct itemplate * const itable_evex061A8[] = {
+ instrux + 7223,
+ instrux + 7224,
+ instrux + 7225,
+ instrux + 7226,
+ instrux + 7227,
+ instrux + 7228,
+};
+
+static const struct itemplate * const itable_evex061A9[] = {
+ instrux + 7255,
+ instrux + 7256,
+};
+
+static const struct itemplate * const itable_evex061AA[] = {
+ instrux + 7271,
+ instrux + 7272,
+ instrux + 7273,
+ instrux + 7274,
+ instrux + 7275,
+ instrux + 7276,
+};
+
+static const struct itemplate * const itable_evex061AB[] = {
+ instrux + 7303,
+ instrux + 7304,
+};
+
+static const struct itemplate * const itable_evex061AC[] = {
+ instrux + 7241,
+ instrux + 7242,
+ instrux + 7243,
+ instrux + 7244,
+ instrux + 7245,
+ instrux + 7246,
+};
+
+static const struct itemplate * const itable_evex061AD[] = {
+ instrux + 7261,
+ instrux + 7262,
+};
+
+static const struct itemplate * const itable_evex061AE[] = {
+ instrux + 7289,
+ instrux + 7290,
+ instrux + 7291,
+ instrux + 7292,
+ instrux + 7293,
+ instrux + 7294,
+};
+
+static const struct itemplate * const itable_evex061AF[] = {
+ instrux + 7309,
+ instrux + 7310,
+};
+
+static const struct itemplate * const itable_evex061B6[] = {
+ instrux + 7193,
+ instrux + 7194,
+ instrux + 7195,
+ instrux + 7196,
+ instrux + 7197,
+ instrux + 7198,
+};
+
+static const struct itemplate * const itable_evex061B7[] = {
+ instrux + 7211,
+ instrux + 7212,
+ instrux + 7213,
+ instrux + 7214,
+ instrux + 7215,
+ instrux + 7216,
+};
+
+static const struct itemplate * const itable_evex061B8[] = {
+ instrux + 7229,
+ instrux + 7230,
+ instrux + 7231,
+ instrux + 7232,
+ instrux + 7233,
+ instrux + 7234,
+};
+
+static const struct itemplate * const itable_evex061B9[] = {
+ instrux + 7257,
+ instrux + 7258,
+};
+
+static const struct itemplate * const itable_evex061BA[] = {
+ instrux + 7277,
+ instrux + 7278,
+ instrux + 7279,
+ instrux + 7280,
+ instrux + 7281,
+ instrux + 7282,
+};
+
+static const struct itemplate * const itable_evex061BB[] = {
+ instrux + 7305,
+ instrux + 7306,
+};
+
+static const struct itemplate * const itable_evex061BC[] = {
+ instrux + 7247,
+ instrux + 7248,
+ instrux + 7249,
+ instrux + 7250,
+ instrux + 7251,
+ instrux + 7252,
+};
+
+static const struct itemplate * const itable_evex061BD[] = {
+ instrux + 7263,
+ instrux + 7264,
+};
+
+static const struct itemplate * const itable_evex061BE[] = {
+ instrux + 7295,
+ instrux + 7296,
+ instrux + 7297,
+ instrux + 7298,
+ instrux + 7299,
+ instrux + 7300,
+};
+
+static const struct itemplate * const itable_evex061BF[] = {
+ instrux + 7311,
+ instrux + 7312,
+};
+
+static const struct itemplate * const itable_evex06256[] = {
+ instrux + 7155,
+ instrux + 7156,
+ instrux + 7157,
+ instrux + 7158,
+ instrux + 7159,
+ instrux + 7160,
+};
+
+static const struct itemplate * const itable_evex06257[] = {
+ instrux + 7163,
+ instrux + 7164,
+};
+
+static const struct itemplate * const itable_evex062D6[] = {
+ instrux + 7171,
+ instrux + 7172,
+ instrux + 7173,
+ instrux + 7174,
+ instrux + 7175,
+ instrux + 7176,
+};
+
+static const struct itemplate * const itable_evex062D7[] = {
+ instrux + 7179,
+ instrux + 7180,
+};
+
+static const struct itemplate * const itable_evex06356[] = {
+ instrux + 7149,
+ instrux + 7150,
+ instrux + 7151,
+ instrux + 7152,
+ instrux + 7153,
+ instrux + 7154,
+};
+
+static const struct itemplate * const itable_evex06357[] = {
+ instrux + 7161,
+ instrux + 7162,
+};
+
+static const struct itemplate * const itable_evex063D6[] = {
+ instrux + 7165,
+ instrux + 7166,
+ instrux + 7167,
+ instrux + 7168,
+ instrux + 7169,
+ instrux + 7170,
+};
+
+static const struct itemplate * const itable_evex063D7[] = {
+ instrux + 7177,
+ instrux + 7178,
+};
+
+static const struct itemplate * const itable_vex01010[] = {
+ instrux + 2746,
+ instrux + 2748,
+};
+
+static const struct itemplate * const itable_vex01011[] = {
+ instrux + 2747,
+ instrux + 2749,
+};
+
+static const struct itemplate * const itable_vex01012[] = {
+ instrux + 2694,
+ instrux + 2695,
+ instrux + 2707,
+ instrux + 2708,
+};
+
+static const struct itemplate * const itable_vex01013[] = {
+ instrux + 2709,
+};
+
+static const struct itemplate * const itable_vex01014[] = {
+ instrux + 3097,
+ instrux + 3098,
+ instrux + 3099,
+ instrux + 3100,
+};
+
+static const struct itemplate * const itable_vex01015[] = {
+ instrux + 3089,
+ instrux + 3090,
+ instrux + 3091,
+ instrux + 3092,
+};
+
+static const struct itemplate * const itable_vex01016[] = {
+ instrux + 2699,
+ instrux + 2700,
+ instrux + 2702,
+ instrux + 2703,
+};
+
+static const struct itemplate * const itable_vex01017[] = {
+ instrux + 2701,
+};
+
+static const struct itemplate * const itable_vex01028[] = {
+ instrux + 2670,
+ instrux + 2672,
+};
+
+static const struct itemplate * const itable_vex01029[] = {
+ instrux + 2671,
+ instrux + 2673,
+};
+
+static const struct itemplate * const itable_vex0102B[] = {
+ instrux + 2724,
+ instrux + 2725,
+};
+
+static const struct itemplate * const itable_vex0102E[] = {
+ instrux + 3084,
+};
+
+static const struct itemplate * const itable_vex0102F[] = {
+ instrux + 2546,
+};
+
+static const struct itemplate * const itable_vex01041[] = {
+ instrux + 4111,
+ instrux + 4112,
+};
+
+static const struct itemplate * const itable_vex01042[] = {
+ instrux + 4109,
+ instrux + 4110,
+};
+
+static const struct itemplate * const itable_vex01044[] = {
+ instrux + 4131,
+ instrux + 4132,
+};
+
+static const struct itemplate * const itable_vex01045[] = {
+ instrux + 4135,
+ instrux + 4136,
+};
+
+static const struct itemplate * const itable_vex01046[] = {
+ instrux + 4158,
+ instrux + 4159,
+};
+
+static const struct itemplate * const itable_vex01047[] = {
+ instrux + 4162,
+ instrux + 4163,
+};
+
+static const struct itemplate * const itable_vex0104A[] = {
+ instrux + 4103,
+ instrux + 4104,
+};
+
+static const struct itemplate * const itable_vex0104B[] = {
+ instrux + 4154,
+ instrux + 4155,
+};
+
+static const struct itemplate * const itable_vex01050[] = {
+ instrux + 2714,
+ instrux + 2715,
+ instrux + 2716,
+ instrux + 2717,
+};
+
+static const struct itemplate * const itable_vex01051[] = {
+ instrux + 3060,
+ instrux + 3061,
+};
+
+static const struct itemplate * const itable_vex01052[] = {
+ instrux + 3038,
+ instrux + 3039,
+};
+
+static const struct itemplate * const itable_vex01053[] = {
+ instrux + 3034,
+ instrux + 3035,
+};
+
+static const struct itemplate * const itable_vex01054[] = {
+ instrux + 1949,
+ instrux + 1950,
+ instrux + 1951,
+ instrux + 1952,
+};
+
+static const struct itemplate * const itable_vex01055[] = {
+ instrux + 1957,
+ instrux + 1958,
+ instrux + 1959,
+ instrux + 1960,
+};
+
+static const struct itemplate * const itable_vex01056[] = {
+ instrux + 2768,
+ instrux + 2769,
+ instrux + 2770,
+ instrux + 2771,
+};
+
+static const struct itemplate * const itable_vex01057[] = {
+ instrux + 3105,
+ instrux + 3106,
+ instrux + 3107,
+ instrux + 3108,
+};
+
+static const struct itemplate * const itable_vex01058[] = {
+ instrux + 1929,
+ instrux + 1930,
+ instrux + 1931,
+ instrux + 1932,
+};
+
+static const struct itemplate * const itable_vex01059[] = {
+ instrux + 2756,
+ instrux + 2757,
+ instrux + 2758,
+ instrux + 2759,
+};
+
+static const struct itemplate * const itable_vex0105A[] = {
+ instrux + 2561,
+ instrux + 2562,
+};
+
+static const struct itemplate * const itable_vex0105B[] = {
+ instrux + 2549,
+ instrux + 2550,
+};
+
+static const struct itemplate * const itable_vex0105C[] = {
+ instrux + 3071,
+ instrux + 3072,
+ instrux + 3073,
+ instrux + 3074,
+};
+
+static const struct itemplate * const itable_vex0105D[] = {
+ instrux + 2658,
+ instrux + 2659,
+ instrux + 2660,
+ instrux + 2661,
+};
+
+static const struct itemplate * const itable_vex0105E[] = {
+ instrux + 2593,
+ instrux + 2594,
+ instrux + 2595,
+ instrux + 2596,
+};
+
+static const struct itemplate * const itable_vex0105F[] = {
+ instrux + 2646,
+ instrux + 2647,
+ instrux + 2648,
+ instrux + 2649,
+};
+
+static const struct itemplate * const itable_vex01077[] = {
+ instrux + 3109,
+ instrux + 3110,
+};
+
+static const struct itemplate * const itable_vex01090[] = {
+ instrux + 4121,
+ instrux + 4125,
+};
+
+static const struct itemplate * const itable_vex01091[] = {
+ instrux + 4122,
+ instrux + 4126,
+};
+
+static const struct itemplate * const itable_vex01092[] = {
+ instrux + 4127,
+};
+
+static const struct itemplate * const itable_vex01093[] = {
+ instrux + 4128,
+};
+
+static const struct itemplate * const itable_vex01098[] = {
+ instrux + 4139,
+ instrux + 4140,
+};
+
+static const struct itemplate * const itable_vex01099[] = {
+ instrux + 4151,
+ instrux + 4152,
+};
+
+static const struct itemplate * const itable_vex010AE[] = {
+ instrux + 2632,
+ instrux + 3066,
+};
+
+static const struct itemplate * const itable_vex010C2[] = {
+ instrux + 2169,
+ instrux + 2170,
+ instrux + 2171,
+ instrux + 2172,
+ instrux + 2173,
+ instrux + 2174,
+ instrux + 2175,
+ instrux + 2176,
+ instrux + 2177,
+ instrux + 2178,
+ instrux + 2179,
+ instrux + 2180,
+ instrux + 2181,
+ instrux + 2182,
+ instrux + 2183,
+ instrux + 2184,
+ instrux + 2185,
+ instrux + 2186,
+ instrux + 2187,
+ instrux + 2188,
+ instrux + 2189,
+ instrux + 2190,
+ instrux + 2191,
+ instrux + 2192,
+ instrux + 2193,
+ instrux + 2194,
+ instrux + 2195,
+ instrux + 2196,
+ instrux + 2197,
+ instrux + 2198,
+ instrux + 2199,
+ instrux + 2200,
+ instrux + 2201,
+ instrux + 2202,
+ instrux + 2203,
+ instrux + 2204,
+ instrux + 2205,
+ instrux + 2206,
+ instrux + 2207,
+ instrux + 2208,
+ instrux + 2209,
+ instrux + 2210,
+ instrux + 2211,
+ instrux + 2212,
+ instrux + 2213,
+ instrux + 2214,
+ instrux + 2215,
+ instrux + 2216,
+ instrux + 2217,
+ instrux + 2218,
+ instrux + 2219,
+ instrux + 2220,
+ instrux + 2221,
+ instrux + 2222,
+ instrux + 2223,
+ instrux + 2224,
+ instrux + 2225,
+ instrux + 2226,
+ instrux + 2227,
+ instrux + 2228,
+ instrux + 2229,
+ instrux + 2230,
+ instrux + 2231,
+ instrux + 2232,
+ instrux + 2233,
+ instrux + 2234,
+ instrux + 2235,
+ instrux + 2236,
+ instrux + 2237,
+ instrux + 2238,
+ instrux + 2239,
+ instrux + 2240,
+ instrux + 2241,
+ instrux + 2242,
+ instrux + 2243,
+ instrux + 2244,
+ instrux + 2245,
+ instrux + 2246,
+ instrux + 2247,
+ instrux + 2248,
+ instrux + 2249,
+ instrux + 2250,
+ instrux + 2251,
+ instrux + 2252,
+ instrux + 2253,
+ instrux + 2254,
+ instrux + 2255,
+ instrux + 2256,
+ instrux + 2257,
+ instrux + 2258,
+ instrux + 2259,
+ instrux + 2260,
+ instrux + 2261,
+ instrux + 2262,
+ instrux + 2263,
+ instrux + 2264,
+ instrux + 2265,
+ instrux + 2266,
+ instrux + 2267,
+ instrux + 2268,
+ instrux + 2269,
+ instrux + 2270,
+ instrux + 2271,
+ instrux + 2272,
+ instrux + 2273,
+ instrux + 2274,
+ instrux + 2275,
+ instrux + 2276,
+ instrux + 2277,
+ instrux + 2278,
+ instrux + 2279,
+ instrux + 2280,
+ instrux + 2281,
+ instrux + 2282,
+ instrux + 2283,
+ instrux + 2284,
+ instrux + 2285,
+ instrux + 2286,
+ instrux + 2287,
+ instrux + 2288,
+ instrux + 2289,
+ instrux + 2290,
+ instrux + 2291,
+ instrux + 2292,
+ instrux + 2293,
+ instrux + 2294,
+ instrux + 2295,
+ instrux + 2296,
+ instrux + 2297,
+ instrux + 2298,
+ instrux + 2299,
+ instrux + 2300,
+ instrux + 2301,
+ instrux + 2302,
+ instrux + 2303,
+ instrux + 2304,
+ instrux + 2305,
+ instrux + 2306,
+ instrux + 2307,
+ instrux + 2308,
+ instrux + 2309,
+ instrux + 2310,
+ instrux + 2311,
+ instrux + 2312,
+ instrux + 2313,
+ instrux + 2314,
+ instrux + 2315,
+ instrux + 2316,
+ instrux + 2317,
+ instrux + 2318,
+ instrux + 2319,
+ instrux + 2320,
+ instrux + 2321,
+ instrux + 2322,
+ instrux + 2323,
+ instrux + 2324,
+ instrux + 2325,
+ instrux + 2326,
+ instrux + 2327,
+ instrux + 2328,
+ instrux + 2329,
+ instrux + 2330,
+ instrux + 2331,
+ instrux + 2332,
+ instrux + 2333,
+ instrux + 2334,
+ instrux + 2335,
+ instrux + 2336,
+ instrux + 2337,
+ instrux + 2338,
+ instrux + 2339,
+ instrux + 2340,
+ instrux + 2341,
+ instrux + 2342,
+ instrux + 2343,
+ instrux + 2344,
+ instrux + 2345,
+ instrux + 2346,
+ instrux + 2347,
+ instrux + 2348,
+ instrux + 2349,
+ instrux + 2350,
+ instrux + 2351,
+ instrux + 2352,
+ instrux + 2353,
+ instrux + 2354,
+ instrux + 2355,
+ instrux + 2356,
+};
+
+static const struct itemplate * const itable_vex010C6[] = {
+ instrux + 3054,
+ instrux + 3055,
+ instrux + 3056,
+ instrux + 3057,
+};
+
+static const struct itemplate * const itable_vex01110[] = {
+ instrux + 2742,
+ instrux + 2744,
+};
+
+static const struct itemplate * const itable_vex01111[] = {
+ instrux + 2743,
+ instrux + 2745,
+};
+
+static const struct itemplate * const itable_vex01112[] = {
+ instrux + 2704,
+ instrux + 2705,
+};
+
+static const struct itemplate * const itable_vex01113[] = {
+ instrux + 2706,
+};
+
+static const struct itemplate * const itable_vex01114[] = {
+ instrux + 3093,
+ instrux + 3094,
+ instrux + 3095,
+ instrux + 3096,
+};
+
+static const struct itemplate * const itable_vex01115[] = {
+ instrux + 3085,
+ instrux + 3086,
+ instrux + 3087,
+ instrux + 3088,
+};
+
+static const struct itemplate * const itable_vex01116[] = {
+ instrux + 2696,
+ instrux + 2697,
+};
+
+static const struct itemplate * const itable_vex01117[] = {
+ instrux + 2698,
+};
+
+static const struct itemplate * const itable_vex01128[] = {
+ instrux + 2666,
+ instrux + 2668,
+};
+
+static const struct itemplate * const itable_vex01129[] = {
+ instrux + 2667,
+ instrux + 2669,
+};
+
+static const struct itemplate * const itable_vex0112B[] = {
+ instrux + 2722,
+ instrux + 2723,
+};
+
+static const struct itemplate * const itable_vex0112E[] = {
+ instrux + 3083,
+};
+
+static const struct itemplate * const itable_vex0112F[] = {
+ instrux + 2545,
+};
+
+static const struct itemplate * const itable_vex01141[] = {
+ instrux + 4105,
+ instrux + 4106,
+};
+
+static const struct itemplate * const itable_vex01142[] = {
+ instrux + 4107,
+ instrux + 4108,
+};
+
+static const struct itemplate * const itable_vex01144[] = {
+ instrux + 4129,
+ instrux + 4130,
+};
+
+static const struct itemplate * const itable_vex01145[] = {
+ instrux + 4133,
+ instrux + 4134,
+};
+
+static const struct itemplate * const itable_vex01146[] = {
+ instrux + 4156,
+ instrux + 4157,
+};
+
+static const struct itemplate * const itable_vex01147[] = {
+ instrux + 4160,
+ instrux + 4161,
+};
+
+static const struct itemplate * const itable_vex0114A[] = {
+ instrux + 4101,
+ instrux + 4102,
+};
+
+static const struct itemplate * const itable_vex0114B[] = {
+ instrux + 4153,
+};
+
+static const struct itemplate * const itable_vex01150[] = {
+ instrux + 2710,
+ instrux + 2711,
+ instrux + 2712,
+ instrux + 2713,
+};
+
+static const struct itemplate * const itable_vex01151[] = {
+ instrux + 3058,
+ instrux + 3059,
+};
+
+static const struct itemplate * const itable_vex01154[] = {
+ instrux + 1945,
+ instrux + 1946,
+ instrux + 1947,
+ instrux + 1948,
+};
+
+static const struct itemplate * const itable_vex01155[] = {
+ instrux + 1953,
+ instrux + 1954,
+ instrux + 1955,
+ instrux + 1956,
+};
+
+static const struct itemplate * const itable_vex01156[] = {
+ instrux + 2764,
+ instrux + 2765,
+ instrux + 2766,
+ instrux + 2767,
+};
+
+static const struct itemplate * const itable_vex01157[] = {
+ instrux + 3101,
+ instrux + 3102,
+ instrux + 3103,
+ instrux + 3104,
+};
+
+static const struct itemplate * const itable_vex01158[] = {
+ instrux + 1925,
+ instrux + 1926,
+ instrux + 1927,
+ instrux + 1928,
+};
+
+static const struct itemplate * const itable_vex01159[] = {
+ instrux + 2752,
+ instrux + 2753,
+ instrux + 2754,
+ instrux + 2755,
+};
+
+static const struct itemplate * const itable_vex0115A[] = {
+ instrux + 2555,
+ instrux + 2556,
+ instrux + 2557,
+ instrux + 2558,
+};
+
+static const struct itemplate * const itable_vex0115B[] = {
+ instrux + 2559,
+ instrux + 2560,
+};
+
+static const struct itemplate * const itable_vex0115C[] = {
+ instrux + 3067,
+ instrux + 3068,
+ instrux + 3069,
+ instrux + 3070,
+};
+
+static const struct itemplate * const itable_vex0115D[] = {
+ instrux + 2654,
+ instrux + 2655,
+ instrux + 2656,
+ instrux + 2657,
+};
+
+static const struct itemplate * const itable_vex0115E[] = {
+ instrux + 2589,
+ instrux + 2590,
+ instrux + 2591,
+ instrux + 2592,
+};
+
+static const struct itemplate * const itable_vex0115F[] = {
+ instrux + 2642,
+ instrux + 2643,
+ instrux + 2644,
+ instrux + 2645,
+};
+
+static const struct itemplate * const itable_vex01160[] = {
+ instrux + 3024,
+ instrux + 3025,
+ instrux + 3885,
+ instrux + 3886,
+};
+
+static const struct itemplate * const itable_vex01161[] = {
+ instrux + 3026,
+ instrux + 3027,
+ instrux + 3887,
+ instrux + 3888,
+};
+
+static const struct itemplate * const itable_vex01162[] = {
+ instrux + 3028,
+ instrux + 3029,
+ instrux + 3889,
+ instrux + 3890,
+};
+
+static const struct itemplate * const itable_vex01163[] = {
+ instrux + 2775,
+ instrux + 2776,
+ instrux + 3682,
+ instrux + 3683,
+};
+
+static const struct itemplate * const itable_vex01164[] = {
+ instrux + 2825,
+ instrux + 2826,
+ instrux + 3728,
+ instrux + 3729,
+};
+
+static const struct itemplate * const itable_vex01165[] = {
+ instrux + 2827,
+ instrux + 2828,
+ instrux + 3730,
+ instrux + 3731,
+};
+
+static const struct itemplate * const itable_vex01166[] = {
+ instrux + 2829,
+ instrux + 2830,
+ instrux + 3732,
+ instrux + 3733,
+};
+
+static const struct itemplate * const itable_vex01167[] = {
+ instrux + 2779,
+ instrux + 2780,
+ instrux + 3688,
+ instrux + 3689,
+};
+
+static const struct itemplate * const itable_vex01168[] = {
+ instrux + 3016,
+ instrux + 3017,
+ instrux + 3877,
+ instrux + 3878,
+};
+
+static const struct itemplate * const itable_vex01169[] = {
+ instrux + 3018,
+ instrux + 3019,
+ instrux + 3879,
+ instrux + 3880,
+};
+
+static const struct itemplate * const itable_vex0116A[] = {
+ instrux + 3020,
+ instrux + 3021,
+ instrux + 3881,
+ instrux + 3882,
+};
+
+static const struct itemplate * const itable_vex0116B[] = {
+ instrux + 2777,
+ instrux + 2778,
+ instrux + 3684,
+ instrux + 3685,
+};
+
+static const struct itemplate * const itable_vex0116C[] = {
+ instrux + 3030,
+ instrux + 3031,
+ instrux + 3891,
+ instrux + 3892,
+};
+
+static const struct itemplate * const itable_vex0116D[] = {
+ instrux + 3022,
+ instrux + 3023,
+ instrux + 3883,
+ instrux + 3884,
+};
+
+static const struct itemplate * const itable_vex0116E[] = {
+ instrux + 2674,
+ instrux + 2678,
+};
+
+static const struct itemplate * const itable_vex0116F[] = {
+ instrux + 2682,
+ instrux + 2684,
+ instrux + 2686,
+};
+
+static const struct itemplate * const itable_vex01170[] = {
+ instrux + 2953,
+ instrux + 3816,
+};
+
+static const struct itemplate * const itable_vex01171[] = {
+ instrux + 2968,
+ instrux + 2969,
+ instrux + 2980,
+ instrux + 2981,
+ instrux + 2988,
+ instrux + 2989,
+ instrux + 3829,
+ instrux + 3830,
+ instrux + 3841,
+ instrux + 3842,
+ instrux + 3851,
+ instrux + 3852,
+};
+
+static const struct itemplate * const itable_vex01172[] = {
+ instrux + 2972,
+ instrux + 2973,
+ instrux + 2984,
+ instrux + 2985,
+ instrux + 2992,
+ instrux + 2993,
+ instrux + 3833,
+ instrux + 3834,
+ instrux + 3845,
+ instrux + 3846,
+ instrux + 3855,
+ instrux + 3856,
+};
+
+static const struct itemplate * const itable_vex01173[] = {
+ instrux + 2962,
+ instrux + 2963,
+ instrux + 2964,
+ instrux + 2965,
+ instrux + 2976,
+ instrux + 2977,
+ instrux + 2996,
+ instrux + 2997,
+ instrux + 3825,
+ instrux + 3826,
+ instrux + 3837,
+ instrux + 3838,
+ instrux + 3847,
+ instrux + 3848,
+ instrux + 3859,
+ instrux + 3860,
+};
+
+static const struct itemplate * const itable_vex01174[] = {
+ instrux + 2817,
+ instrux + 2818,
+ instrux + 3720,
+ instrux + 3721,
+};
+
+static const struct itemplate * const itable_vex01175[] = {
+ instrux + 2819,
+ instrux + 2820,
+ instrux + 3722,
+ instrux + 3723,
+};
+
+static const struct itemplate * const itable_vex01176[] = {
+ instrux + 2821,
+ instrux + 2822,
+ instrux + 3724,
+ instrux + 3725,
+};
+
+static const struct itemplate * const itable_vex0117C[] = {
+ instrux + 2609,
+ instrux + 2610,
+ instrux + 2611,
+ instrux + 2612,
+};
+
+static const struct itemplate * const itable_vex0117D[] = {
+ instrux + 2617,
+ instrux + 2618,
+ instrux + 2619,
+ instrux + 2620,
+};
+
+static const struct itemplate * const itable_vex0117E[] = {
+ instrux + 2675,
+ instrux + 2679,
+};
+
+static const struct itemplate * const itable_vex0117F[] = {
+ instrux + 2683,
+ instrux + 2685,
+ instrux + 2687,
+};
+
+static const struct itemplate * const itable_vex01190[] = {
+ instrux + 4113,
+ instrux + 4117,
+};
+
+static const struct itemplate * const itable_vex01191[] = {
+ instrux + 4114,
+ instrux + 4118,
+};
+
+static const struct itemplate * const itable_vex01192[] = {
+ instrux + 4115,
+};
+
+static const struct itemplate * const itable_vex01193[] = {
+ instrux + 4116,
+};
+
+static const struct itemplate * const itable_vex01198[] = {
+ instrux + 4137,
+ instrux + 4138,
+};
+
+static const struct itemplate * const itable_vex01199[] = {
+ instrux + 4149,
+ instrux + 4150,
+};
+
+static const struct itemplate * const itable_vex011C2[] = {
+ instrux + 1981,
+ instrux + 1982,
+ instrux + 1983,
+ instrux + 1984,
+ instrux + 1985,
+ instrux + 1986,
+ instrux + 1987,
+ instrux + 1988,
+ instrux + 1989,
+ instrux + 1990,
+ instrux + 1991,
+ instrux + 1992,
+ instrux + 1993,
+ instrux + 1994,
+ instrux + 1995,
+ instrux + 1996,
+ instrux + 1997,
+ instrux + 1998,
+ instrux + 1999,
+ instrux + 2000,
+ instrux + 2001,
+ instrux + 2002,
+ instrux + 2003,
+ instrux + 2004,
+ instrux + 2005,
+ instrux + 2006,
+ instrux + 2007,
+ instrux + 2008,
+ instrux + 2009,
+ instrux + 2010,
+ instrux + 2011,
+ instrux + 2012,
+ instrux + 2013,
+ instrux + 2014,
+ instrux + 2015,
+ instrux + 2016,
+ instrux + 2017,
+ instrux + 2018,
+ instrux + 2019,
+ instrux + 2020,
+ instrux + 2021,
+ instrux + 2022,
+ instrux + 2023,
+ instrux + 2024,
+ instrux + 2025,
+ instrux + 2026,
+ instrux + 2027,
+ instrux + 2028,
+ instrux + 2029,
+ instrux + 2030,
+ instrux + 2031,
+ instrux + 2032,
+ instrux + 2033,
+ instrux + 2034,
+ instrux + 2035,
+ instrux + 2036,
+ instrux + 2037,
+ instrux + 2038,
+ instrux + 2039,
+ instrux + 2040,
+ instrux + 2041,
+ instrux + 2042,
+ instrux + 2043,
+ instrux + 2044,
+ instrux + 2045,
+ instrux + 2046,
+ instrux + 2047,
+ instrux + 2048,
+ instrux + 2049,
+ instrux + 2050,
+ instrux + 2051,
+ instrux + 2052,
+ instrux + 2053,
+ instrux + 2054,
+ instrux + 2055,
+ instrux + 2056,
+ instrux + 2057,
+ instrux + 2058,
+ instrux + 2059,
+ instrux + 2060,
+ instrux + 2061,
+ instrux + 2062,
+ instrux + 2063,
+ instrux + 2064,
+ instrux + 2065,
+ instrux + 2066,
+ instrux + 2067,
+ instrux + 2068,
+ instrux + 2069,
+ instrux + 2070,
+ instrux + 2071,
+ instrux + 2072,
+ instrux + 2073,
+ instrux + 2074,
+ instrux + 2075,
+ instrux + 2076,
+ instrux + 2077,
+ instrux + 2078,
+ instrux + 2079,
+ instrux + 2080,
+ instrux + 2081,
+ instrux + 2082,
+ instrux + 2083,
+ instrux + 2084,
+ instrux + 2085,
+ instrux + 2086,
+ instrux + 2087,
+ instrux + 2088,
+ instrux + 2089,
+ instrux + 2090,
+ instrux + 2091,
+ instrux + 2092,
+ instrux + 2093,
+ instrux + 2094,
+ instrux + 2095,
+ instrux + 2096,
+ instrux + 2097,
+ instrux + 2098,
+ instrux + 2099,
+ instrux + 2100,
+ instrux + 2101,
+ instrux + 2102,
+ instrux + 2103,
+ instrux + 2104,
+ instrux + 2105,
+ instrux + 2106,
+ instrux + 2107,
+ instrux + 2108,
+ instrux + 2109,
+ instrux + 2110,
+ instrux + 2111,
+ instrux + 2112,
+ instrux + 2113,
+ instrux + 2114,
+ instrux + 2115,
+ instrux + 2116,
+ instrux + 2117,
+ instrux + 2118,
+ instrux + 2119,
+ instrux + 2120,
+ instrux + 2121,
+ instrux + 2122,
+ instrux + 2123,
+ instrux + 2124,
+ instrux + 2125,
+ instrux + 2126,
+ instrux + 2127,
+ instrux + 2128,
+ instrux + 2129,
+ instrux + 2130,
+ instrux + 2131,
+ instrux + 2132,
+ instrux + 2133,
+ instrux + 2134,
+ instrux + 2135,
+ instrux + 2136,
+ instrux + 2137,
+ instrux + 2138,
+ instrux + 2139,
+ instrux + 2140,
+ instrux + 2141,
+ instrux + 2142,
+ instrux + 2143,
+ instrux + 2144,
+ instrux + 2145,
+ instrux + 2146,
+ instrux + 2147,
+ instrux + 2148,
+ instrux + 2149,
+ instrux + 2150,
+ instrux + 2151,
+ instrux + 2152,
+ instrux + 2153,
+ instrux + 2154,
+ instrux + 2155,
+ instrux + 2156,
+ instrux + 2157,
+ instrux + 2158,
+ instrux + 2159,
+ instrux + 2160,
+ instrux + 2161,
+ instrux + 2162,
+ instrux + 2163,
+ instrux + 2164,
+ instrux + 2165,
+ instrux + 2166,
+ instrux + 2167,
+ instrux + 2168,
+};
+
+static const struct itemplate * const itable_vex011C4[] = {
+ instrux + 2877,
+ instrux + 2878,
+ instrux + 2879,
+ instrux + 2880,
+ instrux + 2881,
+ instrux + 2882,
+};
+
+static const struct itemplate * const itable_vex011C5[] = {
+ instrux + 2850,
+ instrux + 2851,
+};
+
+static const struct itemplate * const itable_vex011C6[] = {
+ instrux + 3050,
+ instrux + 3051,
+ instrux + 3052,
+ instrux + 3053,
+};
+
+static const struct itemplate * const itable_vex011D0[] = {
+ instrux + 1937,
+ instrux + 1938,
+ instrux + 1939,
+ instrux + 1940,
+};
+
+static const struct itemplate * const itable_vex011D1[] = {
+ instrux + 2986,
+ instrux + 2987,
+ instrux + 3849,
+ instrux + 3850,
+};
+
+static const struct itemplate * const itable_vex011D2[] = {
+ instrux + 2990,
+ instrux + 2991,
+ instrux + 3853,
+ instrux + 3854,
+};
+
+static const struct itemplate * const itable_vex011D3[] = {
+ instrux + 2994,
+ instrux + 2995,
+ instrux + 3857,
+ instrux + 3858,
+};
+
+static const struct itemplate * const itable_vex011D4[] = {
+ instrux + 2789,
+ instrux + 2790,
+ instrux + 3696,
+ instrux + 3697,
+};
+
+static const struct itemplate * const itable_vex011D5[] = {
+ instrux + 2939,
+ instrux + 2940,
+ instrux + 3804,
+ instrux + 3805,
+};
+
+static const struct itemplate * const itable_vex011D6[] = {
+ instrux + 2677,
+};
+
+static const struct itemplate * const itable_vex011D7[] = {
+ instrux + 2919,
+ instrux + 2920,
+ instrux + 3776,
+ instrux + 3777,
+};
+
+static const struct itemplate * const itable_vex011D8[] = {
+ instrux + 3012,
+ instrux + 3013,
+ instrux + 3873,
+ instrux + 3874,
+};
+
+static const struct itemplate * const itable_vex011D9[] = {
+ instrux + 3014,
+ instrux + 3015,
+ instrux + 3875,
+ instrux + 3876,
+};
+
+static const struct itemplate * const itable_vex011DA[] = {
+ instrux + 2913,
+ instrux + 2914,
+ instrux + 3770,
+ instrux + 3771,
+};
+
+static const struct itemplate * const itable_vex011DB[] = {
+ instrux + 2801,
+ instrux + 2802,
+ instrux + 3708,
+ instrux + 3709,
+};
+
+static const struct itemplate * const itable_vex011DC[] = {
+ instrux + 2795,
+ instrux + 2796,
+ instrux + 3702,
+ instrux + 3703,
+};
+
+static const struct itemplate * const itable_vex011DD[] = {
+ instrux + 2797,
+ instrux + 2798,
+ instrux + 3704,
+ instrux + 3705,
+};
+
+static const struct itemplate * const itable_vex011DE[] = {
+ instrux + 2901,
+ instrux + 2902,
+ instrux + 3758,
+ instrux + 3759,
+};
+
+static const struct itemplate * const itable_vex011DF[] = {
+ instrux + 2803,
+ instrux + 2804,
+ instrux + 3710,
+ instrux + 3711,
+};
+
+static const struct itemplate * const itable_vex011E0[] = {
+ instrux + 2805,
+ instrux + 2806,
+ instrux + 3712,
+ instrux + 3713,
+};
+
+static const struct itemplate * const itable_vex011E1[] = {
+ instrux + 2978,
+ instrux + 2979,
+ instrux + 3839,
+ instrux + 3840,
+};
+
+static const struct itemplate * const itable_vex011E2[] = {
+ instrux + 2982,
+ instrux + 2983,
+ instrux + 3843,
+ instrux + 3844,
+};
+
+static const struct itemplate * const itable_vex011E3[] = {
+ instrux + 2807,
+ instrux + 2808,
+ instrux + 3714,
+ instrux + 3715,
+};
+
+static const struct itemplate * const itable_vex011E4[] = {
+ instrux + 2933,
+ instrux + 2934,
+ instrux + 3800,
+ instrux + 3801,
+};
+
+static const struct itemplate * const itable_vex011E5[] = {
+ instrux + 2937,
+ instrux + 2938,
+ instrux + 3802,
+ instrux + 3803,
+};
+
+static const struct itemplate * const itable_vex011E6[] = {
+ instrux + 2579,
+ instrux + 2580,
+ instrux + 2581,
+ instrux + 2582,
+};
+
+static const struct itemplate * const itable_vex011E7[] = {
+ instrux + 2718,
+ instrux + 2719,
+ instrux + 2720,
+};
+
+static const struct itemplate * const itable_vex011E8[] = {
+ instrux + 3008,
+ instrux + 3009,
+ instrux + 3869,
+ instrux + 3870,
+};
+
+static const struct itemplate * const itable_vex011E9[] = {
+ instrux + 3010,
+ instrux + 3011,
+ instrux + 3871,
+ instrux + 3872,
+};
+
+static const struct itemplate * const itable_vex011EA[] = {
+ instrux + 2909,
+ instrux + 2910,
+ instrux + 3766,
+ instrux + 3767,
+};
+
+static const struct itemplate * const itable_vex011EB[] = {
+ instrux + 2947,
+ instrux + 2948,
+ instrux + 3810,
+ instrux + 3811,
+};
+
+static const struct itemplate * const itable_vex011EC[] = {
+ instrux + 2791,
+ instrux + 2792,
+ instrux + 3698,
+ instrux + 3699,
+};
+
+static const struct itemplate * const itable_vex011ED[] = {
+ instrux + 2793,
+ instrux + 2794,
+ instrux + 3700,
+ instrux + 3701,
+};
+
+static const struct itemplate * const itable_vex011EE[] = {
+ instrux + 2897,
+ instrux + 2898,
+ instrux + 3754,
+ instrux + 3755,
+};
+
+static const struct itemplate * const itable_vex011EF[] = {
+ instrux + 3032,
+ instrux + 3033,
+ instrux + 3893,
+ instrux + 3894,
+};
+
+static const struct itemplate * const itable_vex011F1[] = {
+ instrux + 2966,
+ instrux + 2967,
+ instrux + 3827,
+ instrux + 3828,
+};
+
+static const struct itemplate * const itable_vex011F2[] = {
+ instrux + 2970,
+ instrux + 2971,
+ instrux + 3831,
+ instrux + 3832,
+};
+
+static const struct itemplate * const itable_vex011F3[] = {
+ instrux + 2974,
+ instrux + 2975,
+ instrux + 3835,
+ instrux + 3836,
+};
+
+static const struct itemplate * const itable_vex011F4[] = {
+ instrux + 2943,
+ instrux + 2944,
+ instrux + 3808,
+ instrux + 3809,
+};
+
+static const struct itemplate * const itable_vex011F5[] = {
+ instrux + 2891,
+ instrux + 2892,
+ instrux + 3750,
+ instrux + 3751,
+};
+
+static const struct itemplate * const itable_vex011F6[] = {
+ instrux + 2949,
+ instrux + 2950,
+ instrux + 3812,
+ instrux + 3813,
+};
+
+static const struct itemplate * const itable_vex011F7[] = {
+ instrux + 2633,
+};
+
+static const struct itemplate * const itable_vex011F8[] = {
+ instrux + 3000,
+ instrux + 3001,
+ instrux + 3861,
+ instrux + 3862,
+};
+
+static const struct itemplate * const itable_vex011F9[] = {
+ instrux + 3002,
+ instrux + 3003,
+ instrux + 3863,
+ instrux + 3864,
+};
+
+static const struct itemplate * const itable_vex011FA[] = {
+ instrux + 3004,
+ instrux + 3005,
+ instrux + 3865,
+ instrux + 3866,
+};
+
+static const struct itemplate * const itable_vex011FB[] = {
+ instrux + 3006,
+ instrux + 3007,
+ instrux + 3867,
+ instrux + 3868,
+};
+
+static const struct itemplate * const itable_vex011FC[] = {
+ instrux + 2783,
+ instrux + 2784,
+ instrux + 3690,
+ instrux + 3691,
+};
+
+static const struct itemplate * const itable_vex011FD[] = {
+ instrux + 2785,
+ instrux + 2786,
+ instrux + 3692,
+ instrux + 3693,
+};
+
+static const struct itemplate * const itable_vex011FE[] = {
+ instrux + 2787,
+ instrux + 2788,
+ instrux + 3694,
+ instrux + 3695,
+};
+
+static const struct itemplate * const itable_vex01210[] = {
+ instrux + 2736,
+ instrux + 2737,
+ instrux + 2738,
+};
+
+static const struct itemplate * const itable_vex01211[] = {
+ instrux + 2739,
+ instrux + 2740,
+ instrux + 2741,
+};
+
+static const struct itemplate * const itable_vex01212[] = {
+ instrux + 2734,
+ instrux + 2735,
+};
+
+static const struct itemplate * const itable_vex01216[] = {
+ instrux + 2732,
+ instrux + 2733,
+};
+
+static const struct itemplate * const itable_vex0122A[] = {
+ instrux + 2571,
+ instrux + 2572,
+ instrux + 2573,
+ instrux + 2574,
+};
+
+static const struct itemplate * const itable_vex0122C[] = {
+ instrux + 2587,
+ instrux + 2588,
+};
+
+static const struct itemplate * const itable_vex0122D[] = {
+ instrux + 2577,
+ instrux + 2578,
+};
+
+static const struct itemplate * const itable_vex01251[] = {
+ instrux + 3064,
+ instrux + 3065,
+};
+
+static const struct itemplate * const itable_vex01252[] = {
+ instrux + 3040,
+ instrux + 3041,
+};
+
+static const struct itemplate * const itable_vex01253[] = {
+ instrux + 3036,
+ instrux + 3037,
+};
+
+static const struct itemplate * const itable_vex01258[] = {
+ instrux + 1935,
+ instrux + 1936,
+};
+
+static const struct itemplate * const itable_vex01259[] = {
+ instrux + 2762,
+ instrux + 2763,
+};
+
+static const struct itemplate * const itable_vex0125A[] = {
+ instrux + 2575,
+ instrux + 2576,
+};
+
+static const struct itemplate * const itable_vex0125B[] = {
+ instrux + 2583,
+ instrux + 2584,
+};
+
+static const struct itemplate * const itable_vex0125C[] = {
+ instrux + 3077,
+ instrux + 3078,
+};
+
+static const struct itemplate * const itable_vex0125D[] = {
+ instrux + 2664,
+ instrux + 2665,
+};
+
+static const struct itemplate * const itable_vex0125E[] = {
+ instrux + 2599,
+ instrux + 2600,
+};
+
+static const struct itemplate * const itable_vex0125F[] = {
+ instrux + 2652,
+ instrux + 2653,
+};
+
+static const struct itemplate * const itable_vex0126F[] = {
+ instrux + 2688,
+ instrux + 2690,
+ instrux + 2692,
+};
+
+static const struct itemplate * const itable_vex01270[] = {
+ instrux + 2954,
+ instrux + 3817,
+};
+
+static const struct itemplate * const itable_vex0127E[] = {
+ instrux + 2676,
+};
+
+static const struct itemplate * const itable_vex0127F[] = {
+ instrux + 2689,
+ instrux + 2691,
+ instrux + 2693,
+};
+
+static const struct itemplate * const itable_vex012C2[] = {
+ instrux + 2451,
+ instrux + 2452,
+ instrux + 2453,
+ instrux + 2454,
+ instrux + 2455,
+ instrux + 2456,
+ instrux + 2457,
+ instrux + 2458,
+ instrux + 2459,
+ instrux + 2460,
+ instrux + 2461,
+ instrux + 2462,
+ instrux + 2463,
+ instrux + 2464,
+ instrux + 2465,
+ instrux + 2466,
+ instrux + 2467,
+ instrux + 2468,
+ instrux + 2469,
+ instrux + 2470,
+ instrux + 2471,
+ instrux + 2472,
+ instrux + 2473,
+ instrux + 2474,
+ instrux + 2475,
+ instrux + 2476,
+ instrux + 2477,
+ instrux + 2478,
+ instrux + 2479,
+ instrux + 2480,
+ instrux + 2481,
+ instrux + 2482,
+ instrux + 2483,
+ instrux + 2484,
+ instrux + 2485,
+ instrux + 2486,
+ instrux + 2487,
+ instrux + 2488,
+ instrux + 2489,
+ instrux + 2490,
+ instrux + 2491,
+ instrux + 2492,
+ instrux + 2493,
+ instrux + 2494,
+ instrux + 2495,
+ instrux + 2496,
+ instrux + 2497,
+ instrux + 2498,
+ instrux + 2499,
+ instrux + 2500,
+ instrux + 2501,
+ instrux + 2502,
+ instrux + 2503,
+ instrux + 2504,
+ instrux + 2505,
+ instrux + 2506,
+ instrux + 2507,
+ instrux + 2508,
+ instrux + 2509,
+ instrux + 2510,
+ instrux + 2511,
+ instrux + 2512,
+ instrux + 2513,
+ instrux + 2514,
+ instrux + 2515,
+ instrux + 2516,
+ instrux + 2517,
+ instrux + 2518,
+ instrux + 2519,
+ instrux + 2520,
+ instrux + 2521,
+ instrux + 2522,
+ instrux + 2523,
+ instrux + 2524,
+ instrux + 2525,
+ instrux + 2526,
+ instrux + 2527,
+ instrux + 2528,
+ instrux + 2529,
+ instrux + 2530,
+ instrux + 2531,
+ instrux + 2532,
+ instrux + 2533,
+ instrux + 2534,
+ instrux + 2535,
+ instrux + 2536,
+ instrux + 2537,
+ instrux + 2538,
+ instrux + 2539,
+ instrux + 2540,
+ instrux + 2541,
+ instrux + 2542,
+ instrux + 2543,
+ instrux + 2544,
+};
+
+static const struct itemplate * const itable_vex012E6[] = {
+ instrux + 2547,
+ instrux + 2548,
+};
+
+static const struct itemplate * const itable_vex01310[] = {
+ instrux + 2726,
+ instrux + 2727,
+ instrux + 2728,
+};
+
+static const struct itemplate * const itable_vex01311[] = {
+ instrux + 2729,
+ instrux + 2730,
+ instrux + 2731,
+};
+
+static const struct itemplate * const itable_vex01312[] = {
+ instrux + 2680,
+ instrux + 2681,
+};
+
+static const struct itemplate * const itable_vex0132A[] = {
+ instrux + 2567,
+ instrux + 2568,
+ instrux + 2569,
+ instrux + 2570,
+};
+
+static const struct itemplate * const itable_vex0132C[] = {
+ instrux + 2585,
+ instrux + 2586,
+};
+
+static const struct itemplate * const itable_vex0132D[] = {
+ instrux + 2563,
+ instrux + 2564,
+};
+
+static const struct itemplate * const itable_vex01351[] = {
+ instrux + 3062,
+ instrux + 3063,
+};
+
+static const struct itemplate * const itable_vex01358[] = {
+ instrux + 1933,
+ instrux + 1934,
+};
+
+static const struct itemplate * const itable_vex01359[] = {
+ instrux + 2760,
+ instrux + 2761,
+};
+
+static const struct itemplate * const itable_vex0135A[] = {
+ instrux + 2565,
+ instrux + 2566,
+};
+
+static const struct itemplate * const itable_vex0135C[] = {
+ instrux + 3075,
+ instrux + 3076,
+};
+
+static const struct itemplate * const itable_vex0135D[] = {
+ instrux + 2662,
+ instrux + 2663,
+};
+
+static const struct itemplate * const itable_vex0135E[] = {
+ instrux + 2597,
+ instrux + 2598,
+};
+
+static const struct itemplate * const itable_vex0135F[] = {
+ instrux + 2650,
+ instrux + 2651,
+};
+
+static const struct itemplate * const itable_vex01370[] = {
+ instrux + 2955,
+ instrux + 3818,
+};
+
+static const struct itemplate * const itable_vex0137C[] = {
+ instrux + 2613,
+ instrux + 2614,
+ instrux + 2615,
+ instrux + 2616,
+};
+
+static const struct itemplate * const itable_vex0137D[] = {
+ instrux + 2621,
+ instrux + 2622,
+ instrux + 2623,
+ instrux + 2624,
+};
+
+static const struct itemplate * const itable_vex01392[] = {
+ instrux + 4119,
+ instrux + 4123,
+};
+
+static const struct itemplate * const itable_vex01393[] = {
+ instrux + 4120,
+ instrux + 4124,
+};
+
+static const struct itemplate * const itable_vex013C2[] = {
+ instrux + 2357,
+ instrux + 2358,
+ instrux + 2359,
+ instrux + 2360,
+ instrux + 2361,
+ instrux + 2362,
+ instrux + 2363,
+ instrux + 2364,
+ instrux + 2365,
+ instrux + 2366,
+ instrux + 2367,
+ instrux + 2368,
+ instrux + 2369,
+ instrux + 2370,
+ instrux + 2371,
+ instrux + 2372,
+ instrux + 2373,
+ instrux + 2374,
+ instrux + 2375,
+ instrux + 2376,
+ instrux + 2377,
+ instrux + 2378,
+ instrux + 2379,
+ instrux + 2380,
+ instrux + 2381,
+ instrux + 2382,
+ instrux + 2383,
+ instrux + 2384,
+ instrux + 2385,
+ instrux + 2386,
+ instrux + 2387,
+ instrux + 2388,
+ instrux + 2389,
+ instrux + 2390,
+ instrux + 2391,
+ instrux + 2392,
+ instrux + 2393,
+ instrux + 2394,
+ instrux + 2395,
+ instrux + 2396,
+ instrux + 2397,
+ instrux + 2398,
+ instrux + 2399,
+ instrux + 2400,
+ instrux + 2401,
+ instrux + 2402,
+ instrux + 2403,
+ instrux + 2404,
+ instrux + 2405,
+ instrux + 2406,
+ instrux + 2407,
+ instrux + 2408,
+ instrux + 2409,
+ instrux + 2410,
+ instrux + 2411,
+ instrux + 2412,
+ instrux + 2413,
+ instrux + 2414,
+ instrux + 2415,
+ instrux + 2416,
+ instrux + 2417,
+ instrux + 2418,
+ instrux + 2419,
+ instrux + 2420,
+ instrux + 2421,
+ instrux + 2422,
+ instrux + 2423,
+ instrux + 2424,
+ instrux + 2425,
+ instrux + 2426,
+ instrux + 2427,
+ instrux + 2428,
+ instrux + 2429,
+ instrux + 2430,
+ instrux + 2431,
+ instrux + 2432,
+ instrux + 2433,
+ instrux + 2434,
+ instrux + 2435,
+ instrux + 2436,
+ instrux + 2437,
+ instrux + 2438,
+ instrux + 2439,
+ instrux + 2440,
+ instrux + 2441,
+ instrux + 2442,
+ instrux + 2443,
+ instrux + 2444,
+ instrux + 2445,
+ instrux + 2446,
+ instrux + 2447,
+ instrux + 2448,
+ instrux + 2449,
+ instrux + 2450,
+};
+
+static const struct itemplate * const itable_vex013D0[] = {
+ instrux + 1941,
+ instrux + 1942,
+ instrux + 1943,
+ instrux + 1944,
+};
+
+static const struct itemplate * const itable_vex013E6[] = {
+ instrux + 2551,
+ instrux + 2552,
+ instrux + 2553,
+ instrux + 2554,
+};
+
+static const struct itemplate * const itable_vex013F0[] = {
+ instrux + 2629,
+ instrux + 2630,
+ instrux + 2631,
+};
+
+static const struct itemplate * const itable_vex02049[] = {
+ instrux + 7011,
+ instrux + 7020,
+};
+
+static const struct itemplate * const itable_vex02050[] = {
+ instrux + 4093,
+ instrux + 4094,
+};
+
+static const struct itemplate * const itable_vex02051[] = {
+ instrux + 4095,
+ instrux + 4096,
+};
+
+static const struct itemplate * const itable_vex0205E[] = {
+ instrux + 7017,
+};
+
+static const struct itemplate * const itable_vex020B0[] = {
+ instrux + 4081,
+ instrux + 4082,
+};
+
+static const struct itemplate * const itable_vex020F2[] = {
+ instrux + 3991,
+ instrux + 3992,
+};
+
+static const struct itemplate * const itable_vex020F3[] = {
+ instrux + 4001,
+ instrux + 4002,
+ instrux + 4011,
+ instrux + 4012,
+ instrux + 4013,
+ instrux + 4014,
+};
+
+static const struct itemplate * const itable_vex020F5[] = {
+ instrux + 4017,
+ instrux + 4018,
+};
+
+static const struct itemplate * const itable_vex020F7[] = {
+ instrux + 3993,
+ instrux + 3994,
+};
+
+static const struct itemplate * const itable_vex02100[] = {
+ instrux + 2951,
+ instrux + 2952,
+ instrux + 3814,
+ instrux + 3815,
+};
+
+static const struct itemplate * const itable_vex02101[] = {
+ instrux + 2858,
+ instrux + 2859,
+ instrux + 3736,
+ instrux + 3737,
+};
+
+static const struct itemplate * const itable_vex02102[] = {
+ instrux + 2860,
+ instrux + 2861,
+ instrux + 3738,
+ instrux + 3739,
+};
+
+static const struct itemplate * const itable_vex02103[] = {
+ instrux + 2862,
+ instrux + 2863,
+ instrux + 3740,
+ instrux + 3741,
+};
+
+static const struct itemplate * const itable_vex02104[] = {
+ instrux + 2893,
+ instrux + 2894,
+ instrux + 3748,
+ instrux + 3749,
+};
+
+static const struct itemplate * const itable_vex02105[] = {
+ instrux + 2865,
+ instrux + 2866,
+ instrux + 3742,
+ instrux + 3743,
+};
+
+static const struct itemplate * const itable_vex02106[] = {
+ instrux + 2867,
+ instrux + 2868,
+ instrux + 3744,
+ instrux + 3745,
+};
+
+static const struct itemplate * const itable_vex02107[] = {
+ instrux + 2869,
+ instrux + 2870,
+ instrux + 3746,
+ instrux + 3747,
+};
+
+static const struct itemplate * const itable_vex02108[] = {
+ instrux + 2956,
+ instrux + 2957,
+ instrux + 3819,
+ instrux + 3820,
+};
+
+static const struct itemplate * const itable_vex02109[] = {
+ instrux + 2958,
+ instrux + 2959,
+ instrux + 3821,
+ instrux + 3822,
+};
+
+static const struct itemplate * const itable_vex0210A[] = {
+ instrux + 2960,
+ instrux + 2961,
+ instrux + 3823,
+ instrux + 3824,
+};
+
+static const struct itemplate * const itable_vex0210B[] = {
+ instrux + 2935,
+ instrux + 2936,
+ instrux + 3798,
+ instrux + 3799,
+};
+
+static const struct itemplate * const itable_vex0210C[] = {
+ instrux + 2839,
+ instrux + 2840,
+ instrux + 2841,
+ instrux + 2842,
+};
+
+static const struct itemplate * const itable_vex0210D[] = {
+ instrux + 2833,
+ instrux + 2834,
+ instrux + 2835,
+ instrux + 2836,
+};
+
+static const struct itemplate * const itable_vex0210E[] = {
+ instrux + 3079,
+ instrux + 3080,
+};
+
+static const struct itemplate * const itable_vex0210F[] = {
+ instrux + 3081,
+ instrux + 3082,
+};
+
+static const struct itemplate * const itable_vex02113[] = {
+ instrux + 3369,
+ instrux + 3370,
+ instrux + 7052,
+ instrux + 7053,
+};
+
+static const struct itemplate * const itable_vex02116[] = {
+ instrux + 3923,
+ instrux + 3924,
+};
+
+static const struct itemplate * const itable_vex02117[] = {
+ instrux + 2998,
+ instrux + 2999,
+};
+
+static const struct itemplate * const itable_vex02118[] = {
+ instrux + 1977,
+ instrux + 1978,
+ instrux + 3896,
+ instrux + 3897,
+};
+
+static const struct itemplate * const itable_vex02119[] = {
+ instrux + 1979,
+ instrux + 3898,
+};
+
+static const struct itemplate * const itable_vex0211A[] = {
+ instrux + 1980,
+};
+
+static const struct itemplate * const itable_vex0211C[] = {
+ instrux + 2772,
+ instrux + 3679,
+};
+
+static const struct itemplate * const itable_vex0211D[] = {
+ instrux + 2773,
+ instrux + 3680,
+};
+
+static const struct itemplate * const itable_vex0211E[] = {
+ instrux + 2774,
+ instrux + 3681,
+};
+
+static const struct itemplate * const itable_vex02120[] = {
+ instrux + 2921,
+ instrux + 3778,
+};
+
+static const struct itemplate * const itable_vex02121[] = {
+ instrux + 2922,
+ instrux + 3779,
+ instrux + 3780,
+};
+
+static const struct itemplate * const itable_vex02122[] = {
+ instrux + 2923,
+ instrux + 3781,
+ instrux + 3782,
+};
+
+static const struct itemplate * const itable_vex02123[] = {
+ instrux + 2924,
+ instrux + 3783,
+};
+
+static const struct itemplate * const itable_vex02124[] = {
+ instrux + 2925,
+ instrux + 3784,
+ instrux + 3785,
+};
+
+static const struct itemplate * const itable_vex02125[] = {
+ instrux + 2926,
+ instrux + 3786,
+};
+
+static const struct itemplate * const itable_vex02128[] = {
+ instrux + 2945,
+ instrux + 2946,
+ instrux + 3796,
+ instrux + 3797,
+};
+
+static const struct itemplate * const itable_vex02129[] = {
+ instrux + 2823,
+ instrux + 2824,
+ instrux + 3726,
+ instrux + 3727,
+};
+
+static const struct itemplate * const itable_vex0212A[] = {
+ instrux + 2721,
+ instrux + 3895,
+};
+
+static const struct itemplate * const itable_vex0212B[] = {
+ instrux + 2781,
+ instrux + 2782,
+ instrux + 3686,
+ instrux + 3687,
+};
+
+static const struct itemplate * const itable_vex0212C[] = {
+ instrux + 2634,
+ instrux + 2635,
+};
+
+static const struct itemplate * const itable_vex0212D[] = {
+ instrux + 2638,
+ instrux + 2639,
+};
+
+static const struct itemplate * const itable_vex0212E[] = {
+ instrux + 2636,
+ instrux + 2637,
+};
+
+static const struct itemplate * const itable_vex0212F[] = {
+ instrux + 2640,
+ instrux + 2641,
+};
+
+static const struct itemplate * const itable_vex02130[] = {
+ instrux + 2927,
+ instrux + 3787,
+};
+
+static const struct itemplate * const itable_vex02131[] = {
+ instrux + 2928,
+ instrux + 3788,
+ instrux + 3789,
+};
+
+static const struct itemplate * const itable_vex02132[] = {
+ instrux + 2929,
+ instrux + 3790,
+ instrux + 3791,
+};
+
+static const struct itemplate * const itable_vex02133[] = {
+ instrux + 2930,
+ instrux + 3792,
+};
+
+static const struct itemplate * const itable_vex02134[] = {
+ instrux + 2931,
+ instrux + 3793,
+ instrux + 3794,
+};
+
+static const struct itemplate * const itable_vex02135[] = {
+ instrux + 2932,
+ instrux + 3795,
+};
+
+static const struct itemplate * const itable_vex02136[] = {
+ instrux + 3920,
+ instrux + 3921,
+};
+
+static const struct itemplate * const itable_vex02137[] = {
+ instrux + 2831,
+ instrux + 2832,
+ instrux + 3734,
+ instrux + 3735,
+};
+
+static const struct itemplate * const itable_vex02138[] = {
+ instrux + 2907,
+ instrux + 2908,
+ instrux + 3764,
+ instrux + 3765,
+};
+
+static const struct itemplate * const itable_vex02139[] = {
+ instrux + 2911,
+ instrux + 2912,
+ instrux + 3768,
+ instrux + 3769,
+};
+
+static const struct itemplate * const itable_vex0213A[] = {
+ instrux + 2915,
+ instrux + 2916,
+ instrux + 3772,
+ instrux + 3773,
+};
+
+static const struct itemplate * const itable_vex0213B[] = {
+ instrux + 2917,
+ instrux + 2918,
+ instrux + 3774,
+ instrux + 3775,
+};
+
+static const struct itemplate * const itable_vex0213C[] = {
+ instrux + 2895,
+ instrux + 2896,
+ instrux + 3752,
+ instrux + 3753,
+};
+
+static const struct itemplate * const itable_vex0213D[] = {
+ instrux + 2899,
+ instrux + 2900,
+ instrux + 3756,
+ instrux + 3757,
+};
+
+static const struct itemplate * const itable_vex0213E[] = {
+ instrux + 2903,
+ instrux + 2904,
+ instrux + 3760,
+ instrux + 3761,
+};
+
+static const struct itemplate * const itable_vex0213F[] = {
+ instrux + 2905,
+ instrux + 2906,
+ instrux + 3762,
+ instrux + 3763,
+};
+
+static const struct itemplate * const itable_vex02140[] = {
+ instrux + 2941,
+ instrux + 2942,
+ instrux + 3806,
+ instrux + 3807,
+};
+
+static const struct itemplate * const itable_vex02141[] = {
+ instrux + 2864,
+};
+
+static const struct itemplate * const itable_vex02145[] = {
+ instrux + 3959,
+ instrux + 3960,
+ instrux + 3961,
+ instrux + 3962,
+ instrux + 3963,
+ instrux + 3964,
+ instrux + 3965,
+ instrux + 3966,
+};
+
+static const struct itemplate * const itable_vex02146[] = {
+ instrux + 3955,
+ instrux + 3956,
+ instrux + 3957,
+ instrux + 3958,
+};
+
+static const struct itemplate * const itable_vex02147[] = {
+ instrux + 3947,
+ instrux + 3948,
+ instrux + 3949,
+ instrux + 3950,
+ instrux + 3951,
+ instrux + 3952,
+ instrux + 3953,
+ instrux + 3954,
+};
+
+static const struct itemplate * const itable_vex02149[] = {
+ instrux + 7012,
+};
+
+static const struct itemplate * const itable_vex0214B[] = {
+ instrux + 7019,
+};
+
+static const struct itemplate * const itable_vex02158[] = {
+ instrux + 3912,
+ instrux + 3913,
+ instrux + 3914,
+ instrux + 3915,
+};
+
+static const struct itemplate * const itable_vex02159[] = {
+ instrux + 3916,
+ instrux + 3917,
+ instrux + 3918,
+ instrux + 3919,
+};
+
+static const struct itemplate * const itable_vex0215A[] = {
+ instrux + 3899,
+};
+
+static const struct itemplate * const itable_vex0215E[] = {
+ instrux + 7016,
+};
+
+static const struct itemplate * const itable_vex02178[] = {
+ instrux + 3904,
+ instrux + 3905,
+ instrux + 3906,
+ instrux + 3907,
+};
+
+static const struct itemplate * const itable_vex02179[] = {
+ instrux + 3908,
+ instrux + 3909,
+ instrux + 3910,
+ instrux + 3911,
+};
+
+static const struct itemplate * const itable_vex0218C[] = {
+ instrux + 3931,
+ instrux + 3932,
+ instrux + 3933,
+ instrux + 3934,
+ instrux + 3935,
+ instrux + 3936,
+ instrux + 3937,
+ instrux + 3938,
+};
+
+static const struct itemplate * const itable_vex0218E[] = {
+ instrux + 3939,
+ instrux + 3940,
+ instrux + 3941,
+ instrux + 3942,
+ instrux + 3943,
+ instrux + 3944,
+ instrux + 3945,
+ instrux + 3946,
+};
+
+static const struct itemplate * const itable_vex02190[] = {
+ instrux + 3975,
+ instrux + 3977,
+ instrux + 3979,
+ instrux + 3981,
+};
+
+static const struct itemplate * const itable_vex02191[] = {
+ instrux + 3976,
+ instrux + 3978,
+ instrux + 3980,
+ instrux + 3982,
+};
+
+static const struct itemplate * const itable_vex02192[] = {
+ instrux + 3967,
+ instrux + 3969,
+ instrux + 3971,
+ instrux + 3973,
+};
+
+static const struct itemplate * const itable_vex02193[] = {
+ instrux + 3968,
+ instrux + 3970,
+ instrux + 3972,
+ instrux + 3974,
+};
+
+static const struct itemplate * const itable_vex02196[] = {
+ instrux + 3190,
+ instrux + 3191,
+ instrux + 3192,
+ instrux + 3193,
+ instrux + 3194,
+ instrux + 3195,
+ instrux + 3196,
+ instrux + 3197,
+};
+
+static const struct itemplate * const itable_vex02197[] = {
+ instrux + 3238,
+ instrux + 3239,
+ instrux + 3240,
+ instrux + 3241,
+ instrux + 3242,
+ instrux + 3243,
+ instrux + 3244,
+ instrux + 3245,
+};
+
+static const struct itemplate * const itable_vex02198[] = {
+ instrux + 3166,
+ instrux + 3167,
+ instrux + 3168,
+ instrux + 3169,
+ instrux + 3170,
+ instrux + 3171,
+ instrux + 3172,
+ instrux + 3173,
+};
+
+static const struct itemplate * const itable_vex02199[] = {
+ instrux + 3310,
+ instrux + 3311,
+ instrux + 3312,
+ instrux + 3313,
+};
+
+static const struct itemplate * const itable_vex0219A[] = {
+ instrux + 3214,
+ instrux + 3215,
+ instrux + 3216,
+ instrux + 3217,
+ instrux + 3218,
+ instrux + 3219,
+ instrux + 3220,
+ instrux + 3221,
+};
+
+static const struct itemplate * const itable_vex0219B[] = {
+ instrux + 3322,
+ instrux + 3323,
+ instrux + 3324,
+ instrux + 3325,
+};
+
+static const struct itemplate * const itable_vex0219C[] = {
+ instrux + 3262,
+ instrux + 3263,
+ instrux + 3264,
+ instrux + 3265,
+ instrux + 3266,
+ instrux + 3267,
+ instrux + 3268,
+ instrux + 3269,
+};
+
+static const struct itemplate * const itable_vex0219D[] = {
+ instrux + 3334,
+ instrux + 3335,
+ instrux + 3336,
+ instrux + 3337,
+};
+
+static const struct itemplate * const itable_vex0219E[] = {
+ instrux + 3286,
+ instrux + 3287,
+ instrux + 3288,
+ instrux + 3289,
+ instrux + 3290,
+ instrux + 3291,
+ instrux + 3292,
+ instrux + 3293,
+};
+
+static const struct itemplate * const itable_vex0219F[] = {
+ instrux + 3346,
+ instrux + 3347,
+ instrux + 3348,
+ instrux + 3349,
+};
+
+static const struct itemplate * const itable_vex021A6[] = {
+ instrux + 3198,
+ instrux + 3199,
+ instrux + 3200,
+ instrux + 3201,
+ instrux + 3202,
+ instrux + 3203,
+ instrux + 3204,
+ instrux + 3205,
+};
+
+static const struct itemplate * const itable_vex021A7[] = {
+ instrux + 3246,
+ instrux + 3247,
+ instrux + 3248,
+ instrux + 3249,
+ instrux + 3250,
+ instrux + 3251,
+ instrux + 3252,
+ instrux + 3253,
+};
+
+static const struct itemplate * const itable_vex021A8[] = {
+ instrux + 3174,
+ instrux + 3175,
+ instrux + 3176,
+ instrux + 3177,
+ instrux + 3178,
+ instrux + 3179,
+ instrux + 3180,
+ instrux + 3181,
+};
+
+static const struct itemplate * const itable_vex021A9[] = {
+ instrux + 3314,
+ instrux + 3315,
+ instrux + 3316,
+ instrux + 3317,
+};
+
+static const struct itemplate * const itable_vex021AA[] = {
+ instrux + 3222,
+ instrux + 3223,
+ instrux + 3224,
+ instrux + 3225,
+ instrux + 3226,
+ instrux + 3227,
+ instrux + 3228,
+ instrux + 3229,
+};
+
+static const struct itemplate * const itable_vex021AB[] = {
+ instrux + 3326,
+ instrux + 3327,
+ instrux + 3328,
+ instrux + 3329,
+};
+
+static const struct itemplate * const itable_vex021AC[] = {
+ instrux + 3270,
+ instrux + 3271,
+ instrux + 3272,
+ instrux + 3273,
+ instrux + 3274,
+ instrux + 3275,
+ instrux + 3276,
+ instrux + 3277,
+};
+
+static const struct itemplate * const itable_vex021AD[] = {
+ instrux + 3338,
+ instrux + 3339,
+ instrux + 3340,
+ instrux + 3341,
+};
+
+static const struct itemplate * const itable_vex021AE[] = {
+ instrux + 3294,
+ instrux + 3295,
+ instrux + 3296,
+ instrux + 3297,
+ instrux + 3298,
+ instrux + 3299,
+ instrux + 3300,
+ instrux + 3301,
+};
+
+static const struct itemplate * const itable_vex021AF[] = {
+ instrux + 3350,
+ instrux + 3351,
+ instrux + 3352,
+ instrux + 3353,
+};
+
+static const struct itemplate * const itable_vex021B0[] = {
+ instrux + 4077,
+ instrux + 4078,
+};
+
+static const struct itemplate * const itable_vex021B1[] = {
+ instrux + 4073,
+ instrux + 4074,
+};
+
+static const struct itemplate * const itable_vex021B4[] = {
+ instrux + 4099,
+ instrux + 4100,
+};
+
+static const struct itemplate * const itable_vex021B5[] = {
+ instrux + 4097,
+ instrux + 4098,
+};
+
+static const struct itemplate * const itable_vex021B6[] = {
+ instrux + 3206,
+ instrux + 3207,
+ instrux + 3208,
+ instrux + 3209,
+ instrux + 3210,
+ instrux + 3211,
+ instrux + 3212,
+ instrux + 3213,
+};
+
+static const struct itemplate * const itable_vex021B7[] = {
+ instrux + 3254,
+ instrux + 3255,
+ instrux + 3256,
+ instrux + 3257,
+ instrux + 3258,
+ instrux + 3259,
+ instrux + 3260,
+ instrux + 3261,
+};
+
+static const struct itemplate * const itable_vex021B8[] = {
+ instrux + 3182,
+ instrux + 3183,
+ instrux + 3184,
+ instrux + 3185,
+ instrux + 3186,
+ instrux + 3187,
+ instrux + 3188,
+ instrux + 3189,
+};
+
+static const struct itemplate * const itable_vex021B9[] = {
+ instrux + 3318,
+ instrux + 3319,
+ instrux + 3320,
+ instrux + 3321,
+};
+
+static const struct itemplate * const itable_vex021BA[] = {
+ instrux + 3230,
+ instrux + 3231,
+ instrux + 3232,
+ instrux + 3233,
+ instrux + 3234,
+ instrux + 3235,
+ instrux + 3236,
+ instrux + 3237,
+};
+
+static const struct itemplate * const itable_vex021BB[] = {
+ instrux + 3330,
+ instrux + 3331,
+ instrux + 3332,
+ instrux + 3333,
+};
+
+static const struct itemplate * const itable_vex021BC[] = {
+ instrux + 3278,
+ instrux + 3279,
+ instrux + 3280,
+ instrux + 3281,
+ instrux + 3282,
+ instrux + 3283,
+ instrux + 3284,
+ instrux + 3285,
+};
+
+static const struct itemplate * const itable_vex021BD[] = {
+ instrux + 3342,
+ instrux + 3343,
+ instrux + 3344,
+ instrux + 3345,
+};
+
+static const struct itemplate * const itable_vex021BE[] = {
+ instrux + 3302,
+ instrux + 3303,
+ instrux + 3304,
+ instrux + 3305,
+ instrux + 3306,
+ instrux + 3307,
+ instrux + 3308,
+ instrux + 3309,
+};
+
+static const struct itemplate * const itable_vex021BF[] = {
+ instrux + 3354,
+ instrux + 3355,
+ instrux + 3356,
+ instrux + 3357,
+};
+
+static const struct itemplate * const itable_vex021CF[] = {
+ instrux + 6817,
+ instrux + 6818,
+ instrux + 6819,
+ instrux + 6820,
+};
+
+static const struct itemplate * const itable_vex021DB[] = {
+ instrux + 1891,
+};
+
+static const struct itemplate * const itable_vex021DC[] = {
+ instrux + 1883,
+ instrux + 1884,
+ instrux + 1893,
+ instrux + 1894,
+};
+
+static const struct itemplate * const itable_vex021DD[] = {
+ instrux + 1885,
+ instrux + 1886,
+ instrux + 1895,
+ instrux + 1896,
+};
+
+static const struct itemplate * const itable_vex021DE[] = {
+ instrux + 1887,
+ instrux + 1888,
+ instrux + 1897,
+ instrux + 1898,
+};
+
+static const struct itemplate * const itable_vex021DF[] = {
+ instrux + 1889,
+ instrux + 1890,
+ instrux + 1899,
+ instrux + 1900,
+};
+
+static const struct itemplate * const itable_vex021E0[] = {
+ instrux + 7416,
+ instrux + 7432,
+};
+
+static const struct itemplate * const itable_vex021E1[] = {
+ instrux + 7413,
+ instrux + 7429,
+};
+
+static const struct itemplate * const itable_vex021E2[] = {
+ instrux + 7406,
+ instrux + 7422,
+};
+
+static const struct itemplate * const itable_vex021E3[] = {
+ instrux + 7410,
+ instrux + 7426,
+};
+
+static const struct itemplate * const itable_vex021E4[] = {
+ instrux + 7420,
+ instrux + 7436,
+};
+
+static const struct itemplate * const itable_vex021E5[] = {
+ instrux + 7415,
+ instrux + 7431,
+};
+
+static const struct itemplate * const itable_vex021E6[] = {
+ instrux + 7409,
+ instrux + 7425,
+};
+
+static const struct itemplate * const itable_vex021E7[] = {
+ instrux + 7405,
+ instrux + 7421,
+};
+
+static const struct itemplate * const itable_vex021E8[] = {
+ instrux + 7419,
+ instrux + 7435,
+};
+
+static const struct itemplate * const itable_vex021E9[] = {
+ instrux + 7414,
+ instrux + 7430,
+};
+
+static const struct itemplate * const itable_vex021EA[] = {
+ instrux + 7417,
+ instrux + 7433,
+};
+
+static const struct itemplate * const itable_vex021EB[] = {
+ instrux + 7418,
+ instrux + 7434,
+};
+
+static const struct itemplate * const itable_vex021EC[] = {
+ instrux + 7408,
+ instrux + 7424,
+};
+
+static const struct itemplate * const itable_vex021ED[] = {
+ instrux + 7412,
+ instrux + 7428,
+};
+
+static const struct itemplate * const itable_vex021EE[] = {
+ instrux + 7411,
+ instrux + 7427,
+};
+
+static const struct itemplate * const itable_vex021EF[] = {
+ instrux + 7407,
+ instrux + 7423,
+};
+
+static const struct itemplate * const itable_vex021F7[] = {
+ instrux + 4029,
+ instrux + 4030,
+};
+
+static const struct itemplate * const itable_vex0224B[] = {
+ instrux + 7021,
+};
+
+static const struct itemplate * const itable_vex02250[] = {
+ instrux + 4089,
+ instrux + 4090,
+};
+
+static const struct itemplate * const itable_vex02251[] = {
+ instrux + 4091,
+ instrux + 4092,
+};
+
+static const struct itemplate * const itable_vex0225C[] = {
+ instrux + 7013,
+};
+
+static const struct itemplate * const itable_vex0225E[] = {
+ instrux + 7015,
+};
+
+static const struct itemplate * const itable_vex02272[] = {
+ instrux + 4083,
+ instrux + 4084,
+};
+
+static const struct itemplate * const itable_vex022B0[] = {
+ instrux + 4075,
+ instrux + 4076,
+};
+
+static const struct itemplate * const itable_vex022B1[] = {
+ instrux + 4071,
+ instrux + 4072,
+};
+
+static const struct itemplate * const itable_vex022F5[] = {
+ instrux + 4023,
+ instrux + 4024,
+};
+
+static const struct itemplate * const itable_vex022F7[] = {
+ instrux + 4027,
+ instrux + 4028,
+};
+
+static const struct itemplate * const itable_vex02349[] = {
+ instrux + 7022,
+};
+
+static const struct itemplate * const itable_vex0234B[] = {
+ instrux + 7018,
+};
+
+static const struct itemplate * const itable_vex02350[] = {
+ instrux + 4085,
+ instrux + 4086,
+};
+
+static const struct itemplate * const itable_vex02351[] = {
+ instrux + 4087,
+ instrux + 4088,
+};
+
+static const struct itemplate * const itable_vex0235E[] = {
+ instrux + 7014,
+};
+
+static const struct itemplate * const itable_vex023B0[] = {
+ instrux + 4079,
+ instrux + 4080,
+};
+
+static const struct itemplate * const itable_vex023F5[] = {
+ instrux + 4021,
+ instrux + 4022,
+};
+
+static const struct itemplate * const itable_vex023F6[] = {
+ instrux + 4019,
+ instrux + 4020,
+};
+
+static const struct itemplate * const itable_vex023F7[] = {
+ instrux + 4031,
+ instrux + 4032,
+};
+
+static const struct itemplate * const itable_vex03100[] = {
+ instrux + 3925,
+};
+
+static const struct itemplate * const itable_vex03101[] = {
+ instrux + 3922,
+};
+
+static const struct itemplate * const itable_vex03102[] = {
+ instrux + 3900,
+ instrux + 3901,
+ instrux + 3902,
+ instrux + 3903,
+};
+
+static const struct itemplate * const itable_vex03104[] = {
+ instrux + 2843,
+ instrux + 2844,
+};
+
+static const struct itemplate * const itable_vex03105[] = {
+ instrux + 2837,
+ instrux + 2838,
+};
+
+static const struct itemplate * const itable_vex03106[] = {
+ instrux + 2845,
+ instrux + 2846,
+};
+
+static const struct itemplate * const itable_vex03108[] = {
+ instrux + 3044,
+ instrux + 3045,
+};
+
+static const struct itemplate * const itable_vex03109[] = {
+ instrux + 3042,
+ instrux + 3043,
+};
+
+static const struct itemplate * const itable_vex0310A[] = {
+ instrux + 3048,
+ instrux + 3049,
+};
+
+static const struct itemplate * const itable_vex0310B[] = {
+ instrux + 3046,
+ instrux + 3047,
+};
+
+static const struct itemplate * const itable_vex0310C[] = {
+ instrux + 1965,
+ instrux + 1966,
+ instrux + 1967,
+ instrux + 1968,
+};
+
+static const struct itemplate * const itable_vex0310D[] = {
+ instrux + 1961,
+ instrux + 1962,
+ instrux + 1963,
+ instrux + 1964,
+};
+
+static const struct itemplate * const itable_vex0310E[] = {
+ instrux + 2811,
+ instrux + 2812,
+ instrux + 3718,
+ instrux + 3719,
+};
+
+static const struct itemplate * const itable_vex0310F[] = {
+ instrux + 2799,
+ instrux + 2800,
+ instrux + 3706,
+ instrux + 3707,
+};
+
+static const struct itemplate * const itable_vex03114[] = {
+ instrux + 2847,
+ instrux + 2848,
+ instrux + 2849,
+};
+
+static const struct itemplate * const itable_vex03115[] = {
+ instrux + 2852,
+ instrux + 2853,
+ instrux + 2854,
+};
+
+static const struct itemplate * const itable_vex03116[] = {
+ instrux + 2855,
+ instrux + 2856,
+ instrux + 2857,
+};
+
+static const struct itemplate * const itable_vex03117[] = {
+ instrux + 2608,
+};
+
+static const struct itemplate * const itable_vex03118[] = {
+ instrux + 2625,
+ instrux + 2626,
+};
+
+static const struct itemplate * const itable_vex03119[] = {
+ instrux + 2607,
+};
+
+static const struct itemplate * const itable_vex0311D[] = {
+ instrux + 3371,
+ instrux + 3372,
+ instrux + 7075,
+ instrux + 7076,
+};
+
+static const struct itemplate * const itable_vex03120[] = {
+ instrux + 2871,
+ instrux + 2872,
+ instrux + 2873,
+ instrux + 2874,
+ instrux + 2875,
+ instrux + 2876,
+};
+
+static const struct itemplate * const itable_vex03121[] = {
+ instrux + 2627,
+ instrux + 2628,
+};
+
+static const struct itemplate * const itable_vex03122[] = {
+ instrux + 2883,
+ instrux + 2884,
+ instrux + 2885,
+ instrux + 2886,
+ instrux + 2887,
+ instrux + 2888,
+ instrux + 2889,
+ instrux + 2890,
+};
+
+static const struct itemplate * const itable_vex03130[] = {
+ instrux + 4145,
+ instrux + 4148,
+};
+
+static const struct itemplate * const itable_vex03131[] = {
+ instrux + 4146,
+ instrux + 4147,
+};
+
+static const struct itemplate * const itable_vex03132[] = {
+ instrux + 4141,
+ instrux + 4144,
+};
+
+static const struct itemplate * const itable_vex03133[] = {
+ instrux + 4142,
+ instrux + 4143,
+};
+
+static const struct itemplate * const itable_vex03138[] = {
+ instrux + 3929,
+ instrux + 3930,
+};
+
+static const struct itemplate * const itable_vex03139[] = {
+ instrux + 3928,
+};
+
+static const struct itemplate * const itable_vex03140[] = {
+ instrux + 2603,
+ instrux + 2604,
+ instrux + 2605,
+ instrux + 2606,
+};
+
+static const struct itemplate * const itable_vex03141[] = {
+ instrux + 2601,
+ instrux + 2602,
+};
+
+static const struct itemplate * const itable_vex03142[] = {
+ instrux + 2750,
+ instrux + 2751,
+ instrux + 3677,
+ instrux + 3678,
+};
+
+static const struct itemplate * const itable_vex03144[] = {
+ instrux + 3116,
+ instrux + 3117,
+ instrux + 3118,
+ instrux + 3119,
+ instrux + 3120,
+ instrux + 3121,
+ instrux + 3122,
+ instrux + 3123,
+ instrux + 3124,
+ instrux + 3125,
+ instrux + 3126,
+ instrux + 3127,
+ instrux + 3128,
+ instrux + 3129,
+ instrux + 3130,
+ instrux + 3131,
+ instrux + 3132,
+ instrux + 3133,
+ instrux + 3134,
+ instrux + 3135,
+};
+
+static const struct itemplate * const itable_vex03146[] = {
+ instrux + 3926,
+ instrux + 3927,
+};
+
+static const struct itemplate * const itable_vex0314A[] = {
+ instrux + 1973,
+ instrux + 1974,
+ instrux + 1975,
+ instrux + 1976,
+};
+
+static const struct itemplate * const itable_vex0314B[] = {
+ instrux + 1969,
+ instrux + 1970,
+ instrux + 1971,
+ instrux + 1972,
+};
+
+static const struct itemplate * const itable_vex0314C[] = {
+ instrux + 2809,
+ instrux + 2810,
+ instrux + 3716,
+ instrux + 3717,
+};
+
+static const struct itemplate * const itable_vex0315C[] = {
+ instrux + 3431,
+ instrux + 3432,
+ instrux + 3433,
+ instrux + 3434,
+ instrux + 3435,
+ instrux + 3436,
+ instrux + 3437,
+ instrux + 3438,
+};
+
+static const struct itemplate * const itable_vex0315D[] = {
+ instrux + 3423,
+ instrux + 3424,
+ instrux + 3425,
+ instrux + 3426,
+ instrux + 3427,
+ instrux + 3428,
+ instrux + 3429,
+ instrux + 3430,
+};
+
+static const struct itemplate * const itable_vex0315E[] = {
+ instrux + 3447,
+ instrux + 3448,
+ instrux + 3449,
+ instrux + 3450,
+ instrux + 3451,
+ instrux + 3452,
+ instrux + 3453,
+ instrux + 3454,
+};
+
+static const struct itemplate * const itable_vex0315F[] = {
+ instrux + 3439,
+ instrux + 3440,
+ instrux + 3441,
+ instrux + 3442,
+ instrux + 3443,
+ instrux + 3444,
+ instrux + 3445,
+ instrux + 3446,
+};
+
+static const struct itemplate * const itable_vex03160[] = {
+ instrux + 2814,
+};
+
+static const struct itemplate * const itable_vex03161[] = {
+ instrux + 2813,
+};
+
+static const struct itemplate * const itable_vex03162[] = {
+ instrux + 2816,
+};
+
+static const struct itemplate * const itable_vex03163[] = {
+ instrux + 2815,
+};
+
+static const struct itemplate * const itable_vex03168[] = {
+ instrux + 3407,
+ instrux + 3408,
+ instrux + 3409,
+ instrux + 3410,
+ instrux + 3411,
+ instrux + 3412,
+ instrux + 3413,
+ instrux + 3414,
+};
+
+static const struct itemplate * const itable_vex03169[] = {
+ instrux + 3399,
+ instrux + 3400,
+ instrux + 3401,
+ instrux + 3402,
+ instrux + 3403,
+ instrux + 3404,
+ instrux + 3405,
+ instrux + 3406,
+};
+
+static const struct itemplate * const itable_vex0316A[] = {
+ instrux + 3419,
+ instrux + 3420,
+ instrux + 3421,
+ instrux + 3422,
+};
+
+static const struct itemplate * const itable_vex0316B[] = {
+ instrux + 3415,
+ instrux + 3416,
+ instrux + 3417,
+ instrux + 3418,
+};
+
+static const struct itemplate * const itable_vex0316C[] = {
+ instrux + 3463,
+ instrux + 3464,
+ instrux + 3465,
+ instrux + 3466,
+ instrux + 3467,
+ instrux + 3468,
+ instrux + 3469,
+ instrux + 3470,
+};
+
+static const struct itemplate * const itable_vex0316D[] = {
+ instrux + 3455,
+ instrux + 3456,
+ instrux + 3457,
+ instrux + 3458,
+ instrux + 3459,
+ instrux + 3460,
+ instrux + 3461,
+ instrux + 3462,
+};
+
+static const struct itemplate * const itable_vex0316E[] = {
+ instrux + 3475,
+ instrux + 3476,
+ instrux + 3477,
+ instrux + 3478,
+};
+
+static const struct itemplate * const itable_vex0316F[] = {
+ instrux + 3471,
+ instrux + 3472,
+ instrux + 3473,
+ instrux + 3474,
+};
+
+static const struct itemplate * const itable_vex03178[] = {
+ instrux + 3487,
+ instrux + 3488,
+ instrux + 3489,
+ instrux + 3490,
+ instrux + 3491,
+ instrux + 3492,
+ instrux + 3493,
+ instrux + 3494,
+};
+
+static const struct itemplate * const itable_vex03179[] = {
+ instrux + 3479,
+ instrux + 3480,
+ instrux + 3481,
+ instrux + 3482,
+ instrux + 3483,
+ instrux + 3484,
+ instrux + 3485,
+ instrux + 3486,
+};
+
+static const struct itemplate * const itable_vex0317A[] = {
+ instrux + 3499,
+ instrux + 3500,
+ instrux + 3501,
+ instrux + 3502,
+};
+
+static const struct itemplate * const itable_vex0317B[] = {
+ instrux + 3495,
+ instrux + 3496,
+ instrux + 3497,
+ instrux + 3498,
+};
+
+static const struct itemplate * const itable_vex0317C[] = {
+ instrux + 3511,
+ instrux + 3512,
+ instrux + 3513,
+ instrux + 3514,
+ instrux + 3515,
+ instrux + 3516,
+ instrux + 3517,
+ instrux + 3518,
+};
+
+static const struct itemplate * const itable_vex0317D[] = {
+ instrux + 3503,
+ instrux + 3504,
+ instrux + 3505,
+ instrux + 3506,
+ instrux + 3507,
+ instrux + 3508,
+ instrux + 3509,
+ instrux + 3510,
+};
+
+static const struct itemplate * const itable_vex0317E[] = {
+ instrux + 3523,
+ instrux + 3524,
+ instrux + 3525,
+ instrux + 3526,
+};
+
+static const struct itemplate * const itable_vex0317F[] = {
+ instrux + 3519,
+ instrux + 3520,
+ instrux + 3521,
+ instrux + 3522,
+};
+
+static const struct itemplate * const itable_vex031CE[] = {
+ instrux + 6806,
+ instrux + 6807,
+ instrux + 6808,
+ instrux + 6809,
+};
+
+static const struct itemplate * const itable_vex031CF[] = {
+ instrux + 6795,
+ instrux + 6796,
+ instrux + 6797,
+ instrux + 6798,
+};
+
+static const struct itemplate * const itable_vex031DF[] = {
+ instrux + 1892,
+};
+
+static const struct itemplate * const itable_vex033F0[] = {
+ instrux + 4025,
+ instrux + 4026,
+};
+
+static const struct itemplate * const itable_xop08085[] = {
+ instrux + 3607,
+ instrux + 3608,
+};
+
+static const struct itemplate * const itable_xop08086[] = {
+ instrux + 3605,
+ instrux + 3606,
+};
+
+static const struct itemplate * const itable_xop08087[] = {
+ instrux + 3603,
+ instrux + 3604,
+};
+
+static const struct itemplate * const itable_xop0808E[] = {
+ instrux + 3599,
+ instrux + 3600,
+};
+
+static const struct itemplate * const itable_xop0808F[] = {
+ instrux + 3601,
+ instrux + 3602,
+};
+
+static const struct itemplate * const itable_xop08095[] = {
+ instrux + 3611,
+ instrux + 3612,
+};
+
+static const struct itemplate * const itable_xop08096[] = {
+ instrux + 3609,
+ instrux + 3610,
+};
+
+static const struct itemplate * const itable_xop08097[] = {
+ instrux + 3597,
+ instrux + 3598,
+};
+
+static const struct itemplate * const itable_xop0809E[] = {
+ instrux + 3593,
+ instrux + 3594,
+};
+
+static const struct itemplate * const itable_xop0809F[] = {
+ instrux + 3595,
+ instrux + 3596,
+};
+
+static const struct itemplate * const itable_xop080A2[] = {
+ instrux + 3539,
+ instrux + 3540,
+ instrux + 3541,
+ instrux + 3542,
+ instrux + 3543,
+ instrux + 3544,
+ instrux + 3545,
+ instrux + 3546,
+};
+
+static const struct itemplate * const itable_xop080A3[] = {
+ instrux + 3617,
+ instrux + 3618,
+ instrux + 3619,
+ instrux + 3620,
+};
+
+static const struct itemplate * const itable_xop080A6[] = {
+ instrux + 3613,
+ instrux + 3614,
+};
+
+static const struct itemplate * const itable_xop080B6[] = {
+ instrux + 3615,
+ instrux + 3616,
+};
+
+static const struct itemplate * const itable_xop080C0[] = {
+ instrux + 3625,
+ instrux + 3626,
+};
+
+static const struct itemplate * const itable_xop080C1[] = {
+ instrux + 3643,
+ instrux + 3644,
+};
+
+static const struct itemplate * const itable_xop080C2[] = {
+ instrux + 3631,
+ instrux + 3632,
+};
+
+static const struct itemplate * const itable_xop080C3[] = {
+ instrux + 3637,
+ instrux + 3638,
+};
+
+static const struct itemplate * const itable_xop080CC[] = {
+ instrux + 3547,
+ instrux + 3548,
+};
+
+static const struct itemplate * const itable_xop080CD[] = {
+ instrux + 3561,
+ instrux + 3562,
+};
+
+static const struct itemplate * const itable_xop080CE[] = {
+ instrux + 3549,
+ instrux + 3550,
+};
+
+static const struct itemplate * const itable_xop080CF[] = {
+ instrux + 3551,
+ instrux + 3552,
+};
+
+static const struct itemplate * const itable_xop080EC[] = {
+ instrux + 3553,
+ instrux + 3554,
+};
+
+static const struct itemplate * const itable_xop080ED[] = {
+ instrux + 3559,
+ instrux + 3560,
+};
+
+static const struct itemplate * const itable_xop080EE[] = {
+ instrux + 3555,
+ instrux + 3556,
+};
+
+static const struct itemplate * const itable_xop080EF[] = {
+ instrux + 3557,
+ instrux + 3558,
+};
+
+static const struct itemplate * const itable_xop09001[] = {
+ instrux + 3999,
+ instrux + 4000,
+ instrux + 4003,
+ instrux + 4004,
+ instrux + 4005,
+ instrux + 4006,
+ instrux + 4007,
+ instrux + 4008,
+ instrux + 4015,
+ instrux + 4016,
+ instrux + 4036,
+ instrux + 4037,
+ instrux + 4038,
+ instrux + 4039,
+};
+
+static const struct itemplate * const itable_xop09002[] = {
+ instrux + 3997,
+ instrux + 3998,
+ instrux + 4009,
+ instrux + 4010,
+};
+
+static const struct itemplate * const itable_xop09012[] = {
+ instrux + 3391,
+ instrux + 3392,
+ instrux + 3393,
+ instrux + 3394,
+};
+
+static const struct itemplate * const itable_xop09080[] = {
+ instrux + 3531,
+ instrux + 3532,
+ instrux + 3533,
+ instrux + 3534,
+};
+
+static const struct itemplate * const itable_xop09081[] = {
+ instrux + 3527,
+ instrux + 3528,
+ instrux + 3529,
+ instrux + 3530,
+};
+
+static const struct itemplate * const itable_xop09082[] = {
+ instrux + 3537,
+ instrux + 3538,
+};
+
+static const struct itemplate * const itable_xop09083[] = {
+ instrux + 3535,
+ instrux + 3536,
+};
+
+static const struct itemplate * const itable_xop09090[] = {
+ instrux + 3621,
+ instrux + 3622,
+ instrux + 3623,
+ instrux + 3624,
+};
+
+static const struct itemplate * const itable_xop09091[] = {
+ instrux + 3639,
+ instrux + 3640,
+ instrux + 3641,
+ instrux + 3642,
+};
+
+static const struct itemplate * const itable_xop09092[] = {
+ instrux + 3627,
+ instrux + 3628,
+ instrux + 3629,
+ instrux + 3630,
+};
+
+static const struct itemplate * const itable_xop09093[] = {
+ instrux + 3633,
+ instrux + 3634,
+ instrux + 3635,
+ instrux + 3636,
+};
+
+static const struct itemplate * const itable_xop09094[] = {
+ instrux + 3661,
+ instrux + 3662,
+ instrux + 3663,
+ instrux + 3664,
+};
+
+static const struct itemplate * const itable_xop09095[] = {
+ instrux + 3673,
+ instrux + 3674,
+ instrux + 3675,
+ instrux + 3676,
+};
+
+static const struct itemplate * const itable_xop09096[] = {
+ instrux + 3665,
+ instrux + 3666,
+ instrux + 3667,
+ instrux + 3668,
+};
+
+static const struct itemplate * const itable_xop09097[] = {
+ instrux + 3669,
+ instrux + 3670,
+ instrux + 3671,
+ instrux + 3672,
+};
+
+static const struct itemplate * const itable_xop09098[] = {
+ instrux + 3645,
+ instrux + 3646,
+ instrux + 3647,
+ instrux + 3648,
+};
+
+static const struct itemplate * const itable_xop09099[] = {
+ instrux + 3657,
+ instrux + 3658,
+ instrux + 3659,
+ instrux + 3660,
+};
+
+static const struct itemplate * const itable_xop0909A[] = {
+ instrux + 3649,
+ instrux + 3650,
+ instrux + 3651,
+ instrux + 3652,
+};
+
+static const struct itemplate * const itable_xop0909B[] = {
+ instrux + 3653,
+ instrux + 3654,
+ instrux + 3655,
+ instrux + 3656,
+};
+
+static const struct itemplate * const itable_xop090C1[] = {
+ instrux + 3567,
+ instrux + 3568,
+};
+
+static const struct itemplate * const itable_xop090C2[] = {
+ instrux + 3563,
+ instrux + 3564,
+};
+
+static const struct itemplate * const itable_xop090C3[] = {
+ instrux + 3565,
+ instrux + 3566,
+};
+
+static const struct itemplate * const itable_xop090C6[] = {
+ instrux + 3583,
+ instrux + 3584,
+};
+
+static const struct itemplate * const itable_xop090C7[] = {
+ instrux + 3585,
+ instrux + 3586,
+};
+
+static const struct itemplate * const itable_xop090CB[] = {
+ instrux + 3569,
+ instrux + 3570,
+};
+
+static const struct itemplate * const itable_xop090D1[] = {
+ instrux + 3575,
+ instrux + 3576,
+};
+
+static const struct itemplate * const itable_xop090D2[] = {
+ instrux + 3571,
+ instrux + 3572,
+};
+
+static const struct itemplate * const itable_xop090D3[] = {
+ instrux + 3573,
+ instrux + 3574,
+};
+
+static const struct itemplate * const itable_xop090D6[] = {
+ instrux + 3579,
+ instrux + 3580,
+};
+
+static const struct itemplate * const itable_xop090D7[] = {
+ instrux + 3581,
+ instrux + 3582,
+};
+
+static const struct itemplate * const itable_xop090DB[] = {
+ instrux + 3577,
+ instrux + 3578,
+};
+
+static const struct itemplate * const itable_xop090E1[] = {
+ instrux + 3587,
+ instrux + 3588,
+};
+
+static const struct itemplate * const itable_xop090E2[] = {
+ instrux + 3591,
+ instrux + 3592,
+};
+
+static const struct itemplate * const itable_xop090E3[] = {
+ instrux + 3589,
+ instrux + 3590,
+};
+
+static const struct itemplate * const itable_xop0A010[] = {
+ instrux + 3995,
+ instrux + 3996,
+};
+
+static const struct itemplate * const itable_xop0A012[] = {
+ instrux + 3395,
+ instrux + 3396,
+ instrux + 3397,
+ instrux + 3398,
+};
+
+static const struct disasm_index itable_vex010[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_vex01010, 2 },
+ /* 0x11 */ { itable_vex01011, 2 },
+ /* 0x12 */ { itable_vex01012, 4 },
+ /* 0x13 */ { itable_vex01013, 1 },
+ /* 0x14 */ { itable_vex01014, 4 },
+ /* 0x15 */ { itable_vex01015, 4 },
+ /* 0x16 */ { itable_vex01016, 4 },
+ /* 0x17 */ { itable_vex01017, 1 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { itable_vex01028, 2 },
+ /* 0x29 */ { itable_vex01029, 2 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { itable_vex0102B, 2 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { itable_vex0102E, 1 },
+ /* 0x2f */ { itable_vex0102F, 1 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { itable_vex01041, 2 },
+ /* 0x42 */ { itable_vex01042, 2 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { itable_vex01044, 2 },
+ /* 0x45 */ { itable_vex01045, 2 },
+ /* 0x46 */ { itable_vex01046, 2 },
+ /* 0x47 */ { itable_vex01047, 2 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { itable_vex0104A, 2 },
+ /* 0x4b */ { itable_vex0104B, 2 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { itable_vex01050, 4 },
+ /* 0x51 */ { itable_vex01051, 2 },
+ /* 0x52 */ { itable_vex01052, 2 },
+ /* 0x53 */ { itable_vex01053, 2 },
+ /* 0x54 */ { itable_vex01054, 4 },
+ /* 0x55 */ { itable_vex01055, 4 },
+ /* 0x56 */ { itable_vex01056, 4 },
+ /* 0x57 */ { itable_vex01057, 4 },
+ /* 0x58 */ { itable_vex01058, 4 },
+ /* 0x59 */ { itable_vex01059, 4 },
+ /* 0x5a */ { itable_vex0105A, 2 },
+ /* 0x5b */ { itable_vex0105B, 2 },
+ /* 0x5c */ { itable_vex0105C, 4 },
+ /* 0x5d */ { itable_vex0105D, 4 },
+ /* 0x5e */ { itable_vex0105E, 4 },
+ /* 0x5f */ { itable_vex0105F, 4 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { itable_vex01077, 2 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { itable_vex01090, 2 },
+ /* 0x91 */ { itable_vex01091, 2 },
+ /* 0x92 */ { itable_vex01092, 1 },
+ /* 0x93 */ { itable_vex01093, 1 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { itable_vex01098, 2 },
+ /* 0x99 */ { itable_vex01099, 2 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { itable_vex010AE, 2 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_vex010C2, 188 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { itable_vex010C6, 4 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex011[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_vex01110, 2 },
+ /* 0x11 */ { itable_vex01111, 2 },
+ /* 0x12 */ { itable_vex01112, 2 },
+ /* 0x13 */ { itable_vex01113, 1 },
+ /* 0x14 */ { itable_vex01114, 4 },
+ /* 0x15 */ { itable_vex01115, 4 },
+ /* 0x16 */ { itable_vex01116, 2 },
+ /* 0x17 */ { itable_vex01117, 1 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { itable_vex01128, 2 },
+ /* 0x29 */ { itable_vex01129, 2 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { itable_vex0112B, 2 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { itable_vex0112E, 1 },
+ /* 0x2f */ { itable_vex0112F, 1 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { itable_vex01141, 2 },
+ /* 0x42 */ { itable_vex01142, 2 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { itable_vex01144, 2 },
+ /* 0x45 */ { itable_vex01145, 2 },
+ /* 0x46 */ { itable_vex01146, 2 },
+ /* 0x47 */ { itable_vex01147, 2 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { itable_vex0114A, 2 },
+ /* 0x4b */ { itable_vex0114B, 1 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { itable_vex01150, 4 },
+ /* 0x51 */ { itable_vex01151, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { itable_vex01154, 4 },
+ /* 0x55 */ { itable_vex01155, 4 },
+ /* 0x56 */ { itable_vex01156, 4 },
+ /* 0x57 */ { itable_vex01157, 4 },
+ /* 0x58 */ { itable_vex01158, 4 },
+ /* 0x59 */ { itable_vex01159, 4 },
+ /* 0x5a */ { itable_vex0115A, 4 },
+ /* 0x5b */ { itable_vex0115B, 2 },
+ /* 0x5c */ { itable_vex0115C, 4 },
+ /* 0x5d */ { itable_vex0115D, 4 },
+ /* 0x5e */ { itable_vex0115E, 4 },
+ /* 0x5f */ { itable_vex0115F, 4 },
+ /* 0x60 */ { itable_vex01160, 4 },
+ /* 0x61 */ { itable_vex01161, 4 },
+ /* 0x62 */ { itable_vex01162, 4 },
+ /* 0x63 */ { itable_vex01163, 4 },
+ /* 0x64 */ { itable_vex01164, 4 },
+ /* 0x65 */ { itable_vex01165, 4 },
+ /* 0x66 */ { itable_vex01166, 4 },
+ /* 0x67 */ { itable_vex01167, 4 },
+ /* 0x68 */ { itable_vex01168, 4 },
+ /* 0x69 */ { itable_vex01169, 4 },
+ /* 0x6a */ { itable_vex0116A, 4 },
+ /* 0x6b */ { itable_vex0116B, 4 },
+ /* 0x6c */ { itable_vex0116C, 4 },
+ /* 0x6d */ { itable_vex0116D, 4 },
+ /* 0x6e */ { itable_vex0116E, 2 },
+ /* 0x6f */ { itable_vex0116F, 3 },
+ /* 0x70 */ { itable_vex01170, 2 },
+ /* 0x71 */ { itable_vex01171, 12 },
+ /* 0x72 */ { itable_vex01172, 12 },
+ /* 0x73 */ { itable_vex01173, 16 },
+ /* 0x74 */ { itable_vex01174, 4 },
+ /* 0x75 */ { itable_vex01175, 4 },
+ /* 0x76 */ { itable_vex01176, 4 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { itable_vex0117C, 4 },
+ /* 0x7d */ { itable_vex0117D, 4 },
+ /* 0x7e */ { itable_vex0117E, 2 },
+ /* 0x7f */ { itable_vex0117F, 3 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { itable_vex01190, 2 },
+ /* 0x91 */ { itable_vex01191, 2 },
+ /* 0x92 */ { itable_vex01192, 1 },
+ /* 0x93 */ { itable_vex01193, 1 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { itable_vex01198, 2 },
+ /* 0x99 */ { itable_vex01199, 2 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_vex011C2, 188 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { itable_vex011C4, 6 },
+ /* 0xc5 */ { itable_vex011C5, 2 },
+ /* 0xc6 */ { itable_vex011C6, 4 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { itable_vex011D0, 4 },
+ /* 0xd1 */ { itable_vex011D1, 4 },
+ /* 0xd2 */ { itable_vex011D2, 4 },
+ /* 0xd3 */ { itable_vex011D3, 4 },
+ /* 0xd4 */ { itable_vex011D4, 4 },
+ /* 0xd5 */ { itable_vex011D5, 4 },
+ /* 0xd6 */ { itable_vex011D6, 1 },
+ /* 0xd7 */ { itable_vex011D7, 4 },
+ /* 0xd8 */ { itable_vex011D8, 4 },
+ /* 0xd9 */ { itable_vex011D9, 4 },
+ /* 0xda */ { itable_vex011DA, 4 },
+ /* 0xdb */ { itable_vex011DB, 4 },
+ /* 0xdc */ { itable_vex011DC, 4 },
+ /* 0xdd */ { itable_vex011DD, 4 },
+ /* 0xde */ { itable_vex011DE, 4 },
+ /* 0xdf */ { itable_vex011DF, 4 },
+ /* 0xe0 */ { itable_vex011E0, 4 },
+ /* 0xe1 */ { itable_vex011E1, 4 },
+ /* 0xe2 */ { itable_vex011E2, 4 },
+ /* 0xe3 */ { itable_vex011E3, 4 },
+ /* 0xe4 */ { itable_vex011E4, 4 },
+ /* 0xe5 */ { itable_vex011E5, 4 },
+ /* 0xe6 */ { itable_vex011E6, 4 },
+ /* 0xe7 */ { itable_vex011E7, 3 },
+ /* 0xe8 */ { itable_vex011E8, 4 },
+ /* 0xe9 */ { itable_vex011E9, 4 },
+ /* 0xea */ { itable_vex011EA, 4 },
+ /* 0xeb */ { itable_vex011EB, 4 },
+ /* 0xec */ { itable_vex011EC, 4 },
+ /* 0xed */ { itable_vex011ED, 4 },
+ /* 0xee */ { itable_vex011EE, 4 },
+ /* 0xef */ { itable_vex011EF, 4 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { itable_vex011F1, 4 },
+ /* 0xf2 */ { itable_vex011F2, 4 },
+ /* 0xf3 */ { itable_vex011F3, 4 },
+ /* 0xf4 */ { itable_vex011F4, 4 },
+ /* 0xf5 */ { itable_vex011F5, 4 },
+ /* 0xf6 */ { itable_vex011F6, 4 },
+ /* 0xf7 */ { itable_vex011F7, 1 },
+ /* 0xf8 */ { itable_vex011F8, 4 },
+ /* 0xf9 */ { itable_vex011F9, 4 },
+ /* 0xfa */ { itable_vex011FA, 4 },
+ /* 0xfb */ { itable_vex011FB, 4 },
+ /* 0xfc */ { itable_vex011FC, 4 },
+ /* 0xfd */ { itable_vex011FD, 4 },
+ /* 0xfe */ { itable_vex011FE, 4 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex012[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_vex01210, 3 },
+ /* 0x11 */ { itable_vex01211, 3 },
+ /* 0x12 */ { itable_vex01212, 2 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { itable_vex01216, 2 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { itable_vex0122A, 4 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { itable_vex0122C, 2 },
+ /* 0x2d */ { itable_vex0122D, 2 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_vex01251, 2 },
+ /* 0x52 */ { itable_vex01252, 2 },
+ /* 0x53 */ { itable_vex01253, 2 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_vex01258, 2 },
+ /* 0x59 */ { itable_vex01259, 2 },
+ /* 0x5a */ { itable_vex0125A, 2 },
+ /* 0x5b */ { itable_vex0125B, 2 },
+ /* 0x5c */ { itable_vex0125C, 2 },
+ /* 0x5d */ { itable_vex0125D, 2 },
+ /* 0x5e */ { itable_vex0125E, 2 },
+ /* 0x5f */ { itable_vex0125F, 2 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { itable_vex0126F, 3 },
+ /* 0x70 */ { itable_vex01270, 2 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { itable_vex0127E, 1 },
+ /* 0x7f */ { itable_vex0127F, 3 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_vex012C2, 94 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { itable_vex012E6, 2 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex013[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_vex01310, 3 },
+ /* 0x11 */ { itable_vex01311, 3 },
+ /* 0x12 */ { itable_vex01312, 2 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { itable_vex0132A, 4 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { itable_vex0132C, 2 },
+ /* 0x2d */ { itable_vex0132D, 2 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_vex01351, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_vex01358, 2 },
+ /* 0x59 */ { itable_vex01359, 2 },
+ /* 0x5a */ { itable_vex0135A, 2 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { itable_vex0135C, 2 },
+ /* 0x5d */ { itable_vex0135D, 2 },
+ /* 0x5e */ { itable_vex0135E, 2 },
+ /* 0x5f */ { itable_vex0135F, 2 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { itable_vex01370, 2 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { itable_vex0137C, 4 },
+ /* 0x7d */ { itable_vex0137D, 4 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { itable_vex01392, 2 },
+ /* 0x93 */ { itable_vex01393, 2 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_vex013C2, 94 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { itable_vex013D0, 4 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { itable_vex013E6, 4 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { itable_vex013F0, 3 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex020[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { itable_vex02049, 2 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { itable_vex02050, 2 },
+ /* 0x51 */ { itable_vex02051, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { itable_vex0205E, 1 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { itable_vex020B0, 2 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { itable_vex020F2, 2 },
+ /* 0xf3 */ { itable_vex020F3, 6 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { itable_vex020F5, 2 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { itable_vex020F7, 2 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex021[256] = {
+ /* 0x00 */ { itable_vex02100, 4 },
+ /* 0x01 */ { itable_vex02101, 4 },
+ /* 0x02 */ { itable_vex02102, 4 },
+ /* 0x03 */ { itable_vex02103, 4 },
+ /* 0x04 */ { itable_vex02104, 4 },
+ /* 0x05 */ { itable_vex02105, 4 },
+ /* 0x06 */ { itable_vex02106, 4 },
+ /* 0x07 */ { itable_vex02107, 4 },
+ /* 0x08 */ { itable_vex02108, 4 },
+ /* 0x09 */ { itable_vex02109, 4 },
+ /* 0x0a */ { itable_vex0210A, 4 },
+ /* 0x0b */ { itable_vex0210B, 4 },
+ /* 0x0c */ { itable_vex0210C, 4 },
+ /* 0x0d */ { itable_vex0210D, 4 },
+ /* 0x0e */ { itable_vex0210E, 2 },
+ /* 0x0f */ { itable_vex0210F, 2 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { itable_vex02113, 4 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { itable_vex02116, 2 },
+ /* 0x17 */ { itable_vex02117, 2 },
+ /* 0x18 */ { itable_vex02118, 4 },
+ /* 0x19 */ { itable_vex02119, 2 },
+ /* 0x1a */ { itable_vex0211A, 1 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { itable_vex0211C, 2 },
+ /* 0x1d */ { itable_vex0211D, 2 },
+ /* 0x1e */ { itable_vex0211E, 2 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { itable_vex02120, 2 },
+ /* 0x21 */ { itable_vex02121, 3 },
+ /* 0x22 */ { itable_vex02122, 3 },
+ /* 0x23 */ { itable_vex02123, 2 },
+ /* 0x24 */ { itable_vex02124, 3 },
+ /* 0x25 */ { itable_vex02125, 2 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { itable_vex02128, 4 },
+ /* 0x29 */ { itable_vex02129, 4 },
+ /* 0x2a */ { itable_vex0212A, 2 },
+ /* 0x2b */ { itable_vex0212B, 4 },
+ /* 0x2c */ { itable_vex0212C, 2 },
+ /* 0x2d */ { itable_vex0212D, 2 },
+ /* 0x2e */ { itable_vex0212E, 2 },
+ /* 0x2f */ { itable_vex0212F, 2 },
+ /* 0x30 */ { itable_vex02130, 2 },
+ /* 0x31 */ { itable_vex02131, 3 },
+ /* 0x32 */ { itable_vex02132, 3 },
+ /* 0x33 */ { itable_vex02133, 2 },
+ /* 0x34 */ { itable_vex02134, 3 },
+ /* 0x35 */ { itable_vex02135, 2 },
+ /* 0x36 */ { itable_vex02136, 2 },
+ /* 0x37 */ { itable_vex02137, 4 },
+ /* 0x38 */ { itable_vex02138, 4 },
+ /* 0x39 */ { itable_vex02139, 4 },
+ /* 0x3a */ { itable_vex0213A, 4 },
+ /* 0x3b */ { itable_vex0213B, 4 },
+ /* 0x3c */ { itable_vex0213C, 4 },
+ /* 0x3d */ { itable_vex0213D, 4 },
+ /* 0x3e */ { itable_vex0213E, 4 },
+ /* 0x3f */ { itable_vex0213F, 4 },
+ /* 0x40 */ { itable_vex02140, 4 },
+ /* 0x41 */ { itable_vex02141, 1 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { itable_vex02145, 8 },
+ /* 0x46 */ { itable_vex02146, 4 },
+ /* 0x47 */ { itable_vex02147, 8 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { itable_vex02149, 1 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { itable_vex0214B, 1 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_vex02158, 4 },
+ /* 0x59 */ { itable_vex02159, 4 },
+ /* 0x5a */ { itable_vex0215A, 1 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { itable_vex0215E, 1 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_vex02178, 4 },
+ /* 0x79 */ { itable_vex02179, 4 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { itable_vex0218C, 8 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { itable_vex0218E, 8 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { itable_vex02190, 4 },
+ /* 0x91 */ { itable_vex02191, 4 },
+ /* 0x92 */ { itable_vex02192, 4 },
+ /* 0x93 */ { itable_vex02193, 4 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { itable_vex02196, 8 },
+ /* 0x97 */ { itable_vex02197, 8 },
+ /* 0x98 */ { itable_vex02198, 8 },
+ /* 0x99 */ { itable_vex02199, 4 },
+ /* 0x9a */ { itable_vex0219A, 8 },
+ /* 0x9b */ { itable_vex0219B, 4 },
+ /* 0x9c */ { itable_vex0219C, 8 },
+ /* 0x9d */ { itable_vex0219D, 4 },
+ /* 0x9e */ { itable_vex0219E, 8 },
+ /* 0x9f */ { itable_vex0219F, 4 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { itable_vex021A6, 8 },
+ /* 0xa7 */ { itable_vex021A7, 8 },
+ /* 0xa8 */ { itable_vex021A8, 8 },
+ /* 0xa9 */ { itable_vex021A9, 4 },
+ /* 0xaa */ { itable_vex021AA, 8 },
+ /* 0xab */ { itable_vex021AB, 4 },
+ /* 0xac */ { itable_vex021AC, 8 },
+ /* 0xad */ { itable_vex021AD, 4 },
+ /* 0xae */ { itable_vex021AE, 8 },
+ /* 0xaf */ { itable_vex021AF, 4 },
+ /* 0xb0 */ { itable_vex021B0, 2 },
+ /* 0xb1 */ { itable_vex021B1, 2 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { itable_vex021B4, 2 },
+ /* 0xb5 */ { itable_vex021B5, 2 },
+ /* 0xb6 */ { itable_vex021B6, 8 },
+ /* 0xb7 */ { itable_vex021B7, 8 },
+ /* 0xb8 */ { itable_vex021B8, 8 },
+ /* 0xb9 */ { itable_vex021B9, 4 },
+ /* 0xba */ { itable_vex021BA, 8 },
+ /* 0xbb */ { itable_vex021BB, 4 },
+ /* 0xbc */ { itable_vex021BC, 8 },
+ /* 0xbd */ { itable_vex021BD, 4 },
+ /* 0xbe */ { itable_vex021BE, 8 },
+ /* 0xbf */ { itable_vex021BF, 4 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { itable_vex021CF, 4 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { itable_vex021DB, 1 },
+ /* 0xdc */ { itable_vex021DC, 4 },
+ /* 0xdd */ { itable_vex021DD, 4 },
+ /* 0xde */ { itable_vex021DE, 4 },
+ /* 0xdf */ { itable_vex021DF, 4 },
+ /* 0xe0 */ { itable_vex021E0, 2 },
+ /* 0xe1 */ { itable_vex021E1, 2 },
+ /* 0xe2 */ { itable_vex021E2, 2 },
+ /* 0xe3 */ { itable_vex021E3, 2 },
+ /* 0xe4 */ { itable_vex021E4, 2 },
+ /* 0xe5 */ { itable_vex021E5, 2 },
+ /* 0xe6 */ { itable_vex021E6, 2 },
+ /* 0xe7 */ { itable_vex021E7, 2 },
+ /* 0xe8 */ { itable_vex021E8, 2 },
+ /* 0xe9 */ { itable_vex021E9, 2 },
+ /* 0xea */ { itable_vex021EA, 2 },
+ /* 0xeb */ { itable_vex021EB, 2 },
+ /* 0xec */ { itable_vex021EC, 2 },
+ /* 0xed */ { itable_vex021ED, 2 },
+ /* 0xee */ { itable_vex021EE, 2 },
+ /* 0xef */ { itable_vex021EF, 2 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { itable_vex021F7, 2 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex022[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { itable_vex0224B, 1 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { itable_vex02250, 2 },
+ /* 0x51 */ { itable_vex02251, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { itable_vex0225C, 1 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { itable_vex0225E, 1 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { itable_vex02272, 2 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { itable_vex022B0, 2 },
+ /* 0xb1 */ { itable_vex022B1, 2 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { itable_vex022F5, 2 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { itable_vex022F7, 2 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex023[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { itable_vex02349, 1 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { itable_vex0234B, 1 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { itable_vex02350, 2 },
+ /* 0x51 */ { itable_vex02351, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { itable_vex0235E, 1 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { itable_vex023B0, 2 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { itable_vex023F5, 2 },
+ /* 0xf6 */ { itable_vex023F6, 2 },
+ /* 0xf7 */ { itable_vex023F7, 2 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex031[256] = {
+ /* 0x00 */ { itable_vex03100, 1 },
+ /* 0x01 */ { itable_vex03101, 1 },
+ /* 0x02 */ { itable_vex03102, 4 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { itable_vex03104, 2 },
+ /* 0x05 */ { itable_vex03105, 2 },
+ /* 0x06 */ { itable_vex03106, 2 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { itable_vex03108, 2 },
+ /* 0x09 */ { itable_vex03109, 2 },
+ /* 0x0a */ { itable_vex0310A, 2 },
+ /* 0x0b */ { itable_vex0310B, 2 },
+ /* 0x0c */ { itable_vex0310C, 4 },
+ /* 0x0d */ { itable_vex0310D, 4 },
+ /* 0x0e */ { itable_vex0310E, 4 },
+ /* 0x0f */ { itable_vex0310F, 4 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { itable_vex03114, 3 },
+ /* 0x15 */ { itable_vex03115, 3 },
+ /* 0x16 */ { itable_vex03116, 3 },
+ /* 0x17 */ { itable_vex03117, 1 },
+ /* 0x18 */ { itable_vex03118, 2 },
+ /* 0x19 */ { itable_vex03119, 1 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { itable_vex0311D, 4 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { itable_vex03120, 6 },
+ /* 0x21 */ { itable_vex03121, 2 },
+ /* 0x22 */ { itable_vex03122, 8 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { itable_vex03130, 2 },
+ /* 0x31 */ { itable_vex03131, 2 },
+ /* 0x32 */ { itable_vex03132, 2 },
+ /* 0x33 */ { itable_vex03133, 2 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { itable_vex03138, 2 },
+ /* 0x39 */ { itable_vex03139, 1 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { itable_vex03140, 4 },
+ /* 0x41 */ { itable_vex03141, 2 },
+ /* 0x42 */ { itable_vex03142, 4 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { itable_vex03144, 20 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { itable_vex03146, 2 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { itable_vex0314A, 4 },
+ /* 0x4b */ { itable_vex0314B, 4 },
+ /* 0x4c */ { itable_vex0314C, 4 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { itable_vex0315C, 8 },
+ /* 0x5d */ { itable_vex0315D, 8 },
+ /* 0x5e */ { itable_vex0315E, 8 },
+ /* 0x5f */ { itable_vex0315F, 8 },
+ /* 0x60 */ { itable_vex03160, 1 },
+ /* 0x61 */ { itable_vex03161, 1 },
+ /* 0x62 */ { itable_vex03162, 1 },
+ /* 0x63 */ { itable_vex03163, 1 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { itable_vex03168, 8 },
+ /* 0x69 */ { itable_vex03169, 8 },
+ /* 0x6a */ { itable_vex0316A, 4 },
+ /* 0x6b */ { itable_vex0316B, 4 },
+ /* 0x6c */ { itable_vex0316C, 8 },
+ /* 0x6d */ { itable_vex0316D, 8 },
+ /* 0x6e */ { itable_vex0316E, 4 },
+ /* 0x6f */ { itable_vex0316F, 4 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_vex03178, 8 },
+ /* 0x79 */ { itable_vex03179, 8 },
+ /* 0x7a */ { itable_vex0317A, 4 },
+ /* 0x7b */ { itable_vex0317B, 4 },
+ /* 0x7c */ { itable_vex0317C, 8 },
+ /* 0x7d */ { itable_vex0317D, 8 },
+ /* 0x7e */ { itable_vex0317E, 4 },
+ /* 0x7f */ { itable_vex0317F, 4 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { itable_vex031CE, 4 },
+ /* 0xcf */ { itable_vex031CF, 4 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { itable_vex031DF, 1 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_vex033[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { itable_vex033F0, 2 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_xop080[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { itable_xop08085, 2 },
+ /* 0x86 */ { itable_xop08086, 2 },
+ /* 0x87 */ { itable_xop08087, 2 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { itable_xop0808E, 2 },
+ /* 0x8f */ { itable_xop0808F, 2 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { itable_xop08095, 2 },
+ /* 0x96 */ { itable_xop08096, 2 },
+ /* 0x97 */ { itable_xop08097, 2 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { itable_xop0809E, 2 },
+ /* 0x9f */ { itable_xop0809F, 2 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { itable_xop080A2, 8 },
+ /* 0xa3 */ { itable_xop080A3, 4 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { itable_xop080A6, 2 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { itable_xop080B6, 2 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { itable_xop080C0, 2 },
+ /* 0xc1 */ { itable_xop080C1, 2 },
+ /* 0xc2 */ { itable_xop080C2, 2 },
+ /* 0xc3 */ { itable_xop080C3, 2 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { itable_xop080CC, 2 },
+ /* 0xcd */ { itable_xop080CD, 2 },
+ /* 0xce */ { itable_xop080CE, 2 },
+ /* 0xcf */ { itable_xop080CF, 2 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { itable_xop080EC, 2 },
+ /* 0xed */ { itable_xop080ED, 2 },
+ /* 0xee */ { itable_xop080EE, 2 },
+ /* 0xef */ { itable_xop080EF, 2 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_xop090[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { itable_xop09001, 14 },
+ /* 0x02 */ { itable_xop09002, 4 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { itable_xop09012, 4 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { itable_xop09080, 4 },
+ /* 0x81 */ { itable_xop09081, 4 },
+ /* 0x82 */ { itable_xop09082, 2 },
+ /* 0x83 */ { itable_xop09083, 2 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { itable_xop09090, 4 },
+ /* 0x91 */ { itable_xop09091, 4 },
+ /* 0x92 */ { itable_xop09092, 4 },
+ /* 0x93 */ { itable_xop09093, 4 },
+ /* 0x94 */ { itable_xop09094, 4 },
+ /* 0x95 */ { itable_xop09095, 4 },
+ /* 0x96 */ { itable_xop09096, 4 },
+ /* 0x97 */ { itable_xop09097, 4 },
+ /* 0x98 */ { itable_xop09098, 4 },
+ /* 0x99 */ { itable_xop09099, 4 },
+ /* 0x9a */ { itable_xop0909A, 4 },
+ /* 0x9b */ { itable_xop0909B, 4 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { itable_xop090C1, 2 },
+ /* 0xc2 */ { itable_xop090C2, 2 },
+ /* 0xc3 */ { itable_xop090C3, 2 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { itable_xop090C6, 2 },
+ /* 0xc7 */ { itable_xop090C7, 2 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { itable_xop090CB, 2 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { itable_xop090D1, 2 },
+ /* 0xd2 */ { itable_xop090D2, 2 },
+ /* 0xd3 */ { itable_xop090D3, 2 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { itable_xop090D6, 2 },
+ /* 0xd7 */ { itable_xop090D7, 2 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { itable_xop090DB, 2 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { itable_xop090E1, 2 },
+ /* 0xe2 */ { itable_xop090E2, 2 },
+ /* 0xe3 */ { itable_xop090E3, 2 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_xop0A0[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_xop0A010, 2 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { itable_xop0A012, 4 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex010[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_evex01010, 3 },
+ /* 0x11 */ { itable_evex01011, 6 },
+ /* 0x12 */ { itable_evex01012, 4 },
+ /* 0x13 */ { itable_evex01013, 1 },
+ /* 0x14 */ { itable_evex01014, 6 },
+ /* 0x15 */ { itable_evex01015, 6 },
+ /* 0x16 */ { itable_evex01016, 4 },
+ /* 0x17 */ { itable_evex01017, 1 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { itable_evex01028, 3 },
+ /* 0x29 */ { itable_evex01029, 6 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { itable_evex0102B, 3 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { itable_evex0102E, 1 },
+ /* 0x2f */ { itable_evex0102F, 1 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_evex01051, 3 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { itable_evex01054, 6 },
+ /* 0x55 */ { itable_evex01055, 6 },
+ /* 0x56 */ { itable_evex01056, 6 },
+ /* 0x57 */ { itable_evex01057, 6 },
+ /* 0x58 */ { itable_evex01058, 6 },
+ /* 0x59 */ { itable_evex01059, 6 },
+ /* 0x5a */ { itable_evex0105A, 3 },
+ /* 0x5b */ { itable_evex0105B, 6 },
+ /* 0x5c */ { itable_evex0105C, 6 },
+ /* 0x5d */ { itable_evex0105D, 6 },
+ /* 0x5e */ { itable_evex0105E, 6 },
+ /* 0x5f */ { itable_evex0105F, 6 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_evex01078, 6 },
+ /* 0x79 */ { itable_evex01079, 6 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_evex010C2, 141 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { itable_evex010C6, 6 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex011[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_evex01110, 3 },
+ /* 0x11 */ { itable_evex01111, 6 },
+ /* 0x12 */ { itable_evex01112, 2 },
+ /* 0x13 */ { itable_evex01113, 1 },
+ /* 0x14 */ { itable_evex01114, 6 },
+ /* 0x15 */ { itable_evex01115, 6 },
+ /* 0x16 */ { itable_evex01116, 2 },
+ /* 0x17 */ { itable_evex01117, 1 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { itable_evex01128, 3 },
+ /* 0x29 */ { itable_evex01129, 6 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { itable_evex0112B, 3 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { itable_evex0112E, 1 },
+ /* 0x2f */ { itable_evex0112F, 1 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_evex01151, 3 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { itable_evex01154, 6 },
+ /* 0x55 */ { itable_evex01155, 6 },
+ /* 0x56 */ { itable_evex01156, 6 },
+ /* 0x57 */ { itable_evex01157, 6 },
+ /* 0x58 */ { itable_evex01158, 6 },
+ /* 0x59 */ { itable_evex01159, 6 },
+ /* 0x5a */ { itable_evex0115A, 3 },
+ /* 0x5b */ { itable_evex0115B, 3 },
+ /* 0x5c */ { itable_evex0115C, 6 },
+ /* 0x5d */ { itable_evex0115D, 6 },
+ /* 0x5e */ { itable_evex0115E, 6 },
+ /* 0x5f */ { itable_evex0115F, 6 },
+ /* 0x60 */ { itable_evex01160, 6 },
+ /* 0x61 */ { itable_evex01161, 6 },
+ /* 0x62 */ { itable_evex01162, 6 },
+ /* 0x63 */ { itable_evex01163, 6 },
+ /* 0x64 */ { itable_evex01164, 3 },
+ /* 0x65 */ { itable_evex01165, 3 },
+ /* 0x66 */ { itable_evex01166, 3 },
+ /* 0x67 */ { itable_evex01167, 6 },
+ /* 0x68 */ { itable_evex01168, 6 },
+ /* 0x69 */ { itable_evex01169, 6 },
+ /* 0x6a */ { itable_evex0116A, 6 },
+ /* 0x6b */ { itable_evex0116B, 6 },
+ /* 0x6c */ { itable_evex0116C, 6 },
+ /* 0x6d */ { itable_evex0116D, 6 },
+ /* 0x6e */ { itable_evex0116E, 2 },
+ /* 0x6f */ { itable_evex0116F, 6 },
+ /* 0x70 */ { itable_evex01170, 3 },
+ /* 0x71 */ { itable_evex01171, 18 },
+ /* 0x72 */ { itable_evex01172, 48 },
+ /* 0x73 */ { itable_evex01173, 24 },
+ /* 0x74 */ { itable_evex01174, 3 },
+ /* 0x75 */ { itable_evex01175, 3 },
+ /* 0x76 */ { itable_evex01176, 3 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_evex01178, 6 },
+ /* 0x79 */ { itable_evex01179, 6 },
+ /* 0x7a */ { itable_evex0117A, 6 },
+ /* 0x7b */ { itable_evex0117B, 6 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { itable_evex0117E, 2 },
+ /* 0x7f */ { itable_evex0117F, 6 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_evex011C2, 141 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { itable_evex011C4, 4 },
+ /* 0xc5 */ { itable_evex011C5, 3 },
+ /* 0xc6 */ { itable_evex011C6, 6 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { itable_evex011D1, 6 },
+ /* 0xd2 */ { itable_evex011D2, 6 },
+ /* 0xd3 */ { itable_evex011D3, 6 },
+ /* 0xd4 */ { itable_evex011D4, 6 },
+ /* 0xd5 */ { itable_evex011D5, 6 },
+ /* 0xd6 */ { itable_evex011D6, 1 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { itable_evex011D8, 6 },
+ /* 0xd9 */ { itable_evex011D9, 6 },
+ /* 0xda */ { itable_evex011DA, 6 },
+ /* 0xdb */ { itable_evex011DB, 12 },
+ /* 0xdc */ { itable_evex011DC, 6 },
+ /* 0xdd */ { itable_evex011DD, 6 },
+ /* 0xde */ { itable_evex011DE, 6 },
+ /* 0xdf */ { itable_evex011DF, 12 },
+ /* 0xe0 */ { itable_evex011E0, 6 },
+ /* 0xe1 */ { itable_evex011E1, 6 },
+ /* 0xe2 */ { itable_evex011E2, 12 },
+ /* 0xe3 */ { itable_evex011E3, 6 },
+ /* 0xe4 */ { itable_evex011E4, 6 },
+ /* 0xe5 */ { itable_evex011E5, 6 },
+ /* 0xe6 */ { itable_evex011E6, 3 },
+ /* 0xe7 */ { itable_evex011E7, 3 },
+ /* 0xe8 */ { itable_evex011E8, 6 },
+ /* 0xe9 */ { itable_evex011E9, 6 },
+ /* 0xea */ { itable_evex011EA, 6 },
+ /* 0xeb */ { itable_evex011EB, 12 },
+ /* 0xec */ { itable_evex011EC, 6 },
+ /* 0xed */ { itable_evex011ED, 6 },
+ /* 0xee */ { itable_evex011EE, 6 },
+ /* 0xef */ { itable_evex011EF, 12 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { itable_evex011F1, 6 },
+ /* 0xf2 */ { itable_evex011F2, 6 },
+ /* 0xf3 */ { itable_evex011F3, 6 },
+ /* 0xf4 */ { itable_evex011F4, 6 },
+ /* 0xf5 */ { itable_evex011F5, 6 },
+ /* 0xf6 */ { itable_evex011F6, 6 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { itable_evex011F8, 6 },
+ /* 0xf9 */ { itable_evex011F9, 6 },
+ /* 0xfa */ { itable_evex011FA, 6 },
+ /* 0xfb */ { itable_evex011FB, 6 },
+ /* 0xfc */ { itable_evex011FC, 6 },
+ /* 0xfd */ { itable_evex011FD, 6 },
+ /* 0xfe */ { itable_evex011FE, 6 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex012[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_evex01210, 3 },
+ /* 0x11 */ { itable_evex01211, 3 },
+ /* 0x12 */ { itable_evex01212, 3 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { itable_evex01216, 3 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { itable_evex0122A, 2 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { itable_evex0122C, 2 },
+ /* 0x2d */ { itable_evex0122D, 2 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_evex01251, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_evex01258, 2 },
+ /* 0x59 */ { itable_evex01259, 2 },
+ /* 0x5a */ { itable_evex0125A, 1 },
+ /* 0x5b */ { itable_evex0125B, 3 },
+ /* 0x5c */ { itable_evex0125C, 2 },
+ /* 0x5d */ { itable_evex0125D, 2 },
+ /* 0x5e */ { itable_evex0125E, 2 },
+ /* 0x5f */ { itable_evex0125F, 2 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { itable_evex0126F, 6 },
+ /* 0x70 */ { itable_evex01270, 3 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_evex01278, 2 },
+ /* 0x79 */ { itable_evex01279, 2 },
+ /* 0x7a */ { itable_evex0127A, 6 },
+ /* 0x7b */ { itable_evex0127B, 2 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { itable_evex0127E, 1 },
+ /* 0x7f */ { itable_evex0127F, 6 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_evex012C2, 47 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { itable_evex012E6, 6 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex013[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_evex01310, 3 },
+ /* 0x11 */ { itable_evex01311, 3 },
+ /* 0x12 */ { itable_evex01312, 3 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { itable_evex0132A, 2 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { itable_evex0132C, 2 },
+ /* 0x2d */ { itable_evex0132D, 2 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_evex01351, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_evex01358, 2 },
+ /* 0x59 */ { itable_evex01359, 2 },
+ /* 0x5a */ { itable_evex0135A, 1 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { itable_evex0135C, 2 },
+ /* 0x5d */ { itable_evex0135D, 2 },
+ /* 0x5e */ { itable_evex0135E, 2 },
+ /* 0x5f */ { itable_evex0135F, 2 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { itable_evex0136F, 6 },
+ /* 0x70 */ { itable_evex01370, 3 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_evex01378, 2 },
+ /* 0x79 */ { itable_evex01379, 2 },
+ /* 0x7a */ { itable_evex0137A, 6 },
+ /* 0x7b */ { itable_evex0137B, 2 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { itable_evex0137F, 6 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_evex013C2, 47 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { itable_evex013E6, 3 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex021[256] = {
+ /* 0x00 */ { itable_evex02100, 6 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { itable_evex02104, 6 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { itable_evex0210B, 6 },
+ /* 0x0c */ { itable_evex0210C, 6 },
+ /* 0x0d */ { itable_evex0210D, 6 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_evex02110, 6 },
+ /* 0x11 */ { itable_evex02111, 6 },
+ /* 0x12 */ { itable_evex02112, 6 },
+ /* 0x13 */ { itable_evex02113, 6 },
+ /* 0x14 */ { itable_evex02114, 12 },
+ /* 0x15 */ { itable_evex02115, 12 },
+ /* 0x16 */ { itable_evex02116, 8 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { itable_evex02118, 6 },
+ /* 0x19 */ { itable_evex02119, 6 },
+ /* 0x1a */ { itable_evex0211A, 4 },
+ /* 0x1b */ { itable_evex0211B, 2 },
+ /* 0x1c */ { itable_evex0211C, 3 },
+ /* 0x1d */ { itable_evex0211D, 3 },
+ /* 0x1e */ { itable_evex0211E, 3 },
+ /* 0x1f */ { itable_evex0211F, 3 },
+ /* 0x20 */ { itable_evex02120, 3 },
+ /* 0x21 */ { itable_evex02121, 3 },
+ /* 0x22 */ { itable_evex02122, 3 },
+ /* 0x23 */ { itable_evex02123, 3 },
+ /* 0x24 */ { itable_evex02124, 3 },
+ /* 0x25 */ { itable_evex02125, 3 },
+ /* 0x26 */ { itable_evex02126, 6 },
+ /* 0x27 */ { itable_evex02127, 6 },
+ /* 0x28 */ { itable_evex02128, 6 },
+ /* 0x29 */ { itable_evex02129, 3 },
+ /* 0x2a */ { itable_evex0212A, 3 },
+ /* 0x2b */ { itable_evex0212B, 6 },
+ /* 0x2c */ { itable_evex0212C, 12 },
+ /* 0x2d */ { itable_evex0212D, 4 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { itable_evex02130, 3 },
+ /* 0x31 */ { itable_evex02131, 3 },
+ /* 0x32 */ { itable_evex02132, 3 },
+ /* 0x33 */ { itable_evex02133, 3 },
+ /* 0x34 */ { itable_evex02134, 3 },
+ /* 0x35 */ { itable_evex02135, 3 },
+ /* 0x36 */ { itable_evex02136, 8 },
+ /* 0x37 */ { itable_evex02137, 3 },
+ /* 0x38 */ { itable_evex02138, 6 },
+ /* 0x39 */ { itable_evex02139, 12 },
+ /* 0x3a */ { itable_evex0213A, 6 },
+ /* 0x3b */ { itable_evex0213B, 12 },
+ /* 0x3c */ { itable_evex0213C, 6 },
+ /* 0x3d */ { itable_evex0213D, 12 },
+ /* 0x3e */ { itable_evex0213E, 6 },
+ /* 0x3f */ { itable_evex0213F, 12 },
+ /* 0x40 */ { itable_evex02140, 12 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { itable_evex02142, 6 },
+ /* 0x43 */ { itable_evex02143, 2 },
+ /* 0x44 */ { itable_evex02144, 6 },
+ /* 0x45 */ { itable_evex02145, 12 },
+ /* 0x46 */ { itable_evex02146, 12 },
+ /* 0x47 */ { itable_evex02147, 12 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { itable_evex0214C, 6 },
+ /* 0x4d */ { itable_evex0214D, 4 },
+ /* 0x4e */ { itable_evex0214E, 6 },
+ /* 0x4f */ { itable_evex0214F, 4 },
+ /* 0x50 */ { itable_evex02150, 6 },
+ /* 0x51 */ { itable_evex02151, 6 },
+ /* 0x52 */ { itable_evex02152, 6 },
+ /* 0x53 */ { itable_evex02153, 6 },
+ /* 0x54 */ { itable_evex02154, 6 },
+ /* 0x55 */ { itable_evex02155, 6 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_evex02158, 6 },
+ /* 0x59 */ { itable_evex02159, 9 },
+ /* 0x5a */ { itable_evex0215A, 4 },
+ /* 0x5b */ { itable_evex0215B, 2 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { itable_evex02162, 6 },
+ /* 0x63 */ { itable_evex02163, 12 },
+ /* 0x64 */ { itable_evex02164, 6 },
+ /* 0x65 */ { itable_evex02165, 6 },
+ /* 0x66 */ { itable_evex02166, 6 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { itable_evex02170, 6 },
+ /* 0x71 */ { itable_evex02171, 12 },
+ /* 0x72 */ { itable_evex02172, 6 },
+ /* 0x73 */ { itable_evex02173, 12 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { itable_evex02175, 6 },
+ /* 0x76 */ { itable_evex02176, 6 },
+ /* 0x77 */ { itable_evex02177, 6 },
+ /* 0x78 */ { itable_evex02178, 3 },
+ /* 0x79 */ { itable_evex02179, 3 },
+ /* 0x7a */ { itable_evex0217A, 12 },
+ /* 0x7b */ { itable_evex0217B, 9 },
+ /* 0x7c */ { itable_evex0217C, 6 },
+ /* 0x7d */ { itable_evex0217D, 6 },
+ /* 0x7e */ { itable_evex0217E, 6 },
+ /* 0x7f */ { itable_evex0217F, 6 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { itable_evex02183, 6 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { itable_evex02188, 12 },
+ /* 0x89 */ { itable_evex02189, 12 },
+ /* 0x8a */ { itable_evex0218A, 12 },
+ /* 0x8b */ { itable_evex0218B, 12 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { itable_evex0218D, 12 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { itable_evex0218F, 3 },
+ /* 0x90 */ { itable_evex02190, 6 },
+ /* 0x91 */ { itable_evex02191, 6 },
+ /* 0x92 */ { itable_evex02192, 6 },
+ /* 0x93 */ { itable_evex02193, 6 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { itable_evex02196, 6 },
+ /* 0x97 */ { itable_evex02197, 6 },
+ /* 0x98 */ { itable_evex02198, 6 },
+ /* 0x99 */ { itable_evex02199, 2 },
+ /* 0x9a */ { itable_evex0219A, 6 },
+ /* 0x9b */ { itable_evex0219B, 2 },
+ /* 0x9c */ { itable_evex0219C, 6 },
+ /* 0x9d */ { itable_evex0219D, 2 },
+ /* 0x9e */ { itable_evex0219E, 6 },
+ /* 0x9f */ { itable_evex0219F, 2 },
+ /* 0xa0 */ { itable_evex021A0, 6 },
+ /* 0xa1 */ { itable_evex021A1, 6 },
+ /* 0xa2 */ { itable_evex021A2, 6 },
+ /* 0xa3 */ { itable_evex021A3, 6 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { itable_evex021A6, 6 },
+ /* 0xa7 */ { itable_evex021A7, 6 },
+ /* 0xa8 */ { itable_evex021A8, 6 },
+ /* 0xa9 */ { itable_evex021A9, 2 },
+ /* 0xaa */ { itable_evex021AA, 6 },
+ /* 0xab */ { itable_evex021AB, 2 },
+ /* 0xac */ { itable_evex021AC, 6 },
+ /* 0xad */ { itable_evex021AD, 2 },
+ /* 0xae */ { itable_evex021AE, 6 },
+ /* 0xaf */ { itable_evex021AF, 2 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { itable_evex021B4, 3 },
+ /* 0xb5 */ { itable_evex021B5, 3 },
+ /* 0xb6 */ { itable_evex021B6, 6 },
+ /* 0xb7 */ { itable_evex021B7, 6 },
+ /* 0xb8 */ { itable_evex021B8, 6 },
+ /* 0xb9 */ { itable_evex021B9, 2 },
+ /* 0xba */ { itable_evex021BA, 6 },
+ /* 0xbb */ { itable_evex021BB, 2 },
+ /* 0xbc */ { itable_evex021BC, 6 },
+ /* 0xbd */ { itable_evex021BD, 2 },
+ /* 0xbe */ { itable_evex021BE, 6 },
+ /* 0xbf */ { itable_evex021BF, 2 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { itable_evex021C4, 6 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { itable_evex021C6, 8 },
+ /* 0xc7 */ { itable_evex021C7, 8 },
+ /* 0xc8 */ { itable_evex021C8, 2 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { itable_evex021CA, 2 },
+ /* 0xcb */ { itable_evex021CB, 4 },
+ /* 0xcc */ { itable_evex021CC, 2 },
+ /* 0xcd */ { itable_evex021CD, 4 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { itable_evex021CF, 6 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { itable_evex021DC, 6 },
+ /* 0xdd */ { itable_evex021DD, 6 },
+ /* 0xde */ { itable_evex021DE, 6 },
+ /* 0xdf */ { itable_evex021DF, 6 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex022[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_evex02210, 6 },
+ /* 0x11 */ { itable_evex02211, 6 },
+ /* 0x12 */ { itable_evex02212, 6 },
+ /* 0x13 */ { itable_evex02213, 6 },
+ /* 0x14 */ { itable_evex02214, 6 },
+ /* 0x15 */ { itable_evex02215, 6 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { itable_evex02220, 6 },
+ /* 0x21 */ { itable_evex02221, 6 },
+ /* 0x22 */ { itable_evex02222, 6 },
+ /* 0x23 */ { itable_evex02223, 6 },
+ /* 0x24 */ { itable_evex02224, 6 },
+ /* 0x25 */ { itable_evex02225, 6 },
+ /* 0x26 */ { itable_evex02226, 6 },
+ /* 0x27 */ { itable_evex02227, 6 },
+ /* 0x28 */ { itable_evex02228, 6 },
+ /* 0x29 */ { itable_evex02229, 6 },
+ /* 0x2a */ { itable_evex0222A, 3 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { itable_evex02230, 6 },
+ /* 0x31 */ { itable_evex02231, 6 },
+ /* 0x32 */ { itable_evex02232, 6 },
+ /* 0x33 */ { itable_evex02233, 6 },
+ /* 0x34 */ { itable_evex02234, 6 },
+ /* 0x35 */ { itable_evex02235, 6 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { itable_evex02238, 6 },
+ /* 0x39 */ { itable_evex02239, 6 },
+ /* 0x3a */ { itable_evex0223A, 3 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { itable_evex02252, 6 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { itable_evex02272, 6 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex023[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { itable_evex02352, 1 },
+ /* 0x53 */ { itable_evex02353, 1 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { itable_evex02368, 3 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { itable_evex02372, 6 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { itable_evex0239A, 1 },
+ /* 0x9b */ { itable_evex0239B, 1 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { itable_evex023AA, 1 },
+ /* 0xab */ { itable_evex023AB, 1 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex030[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { itable_evex03008, 3 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { itable_evex0300A, 2 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { itable_evex03025, 3 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { itable_evex03027, 1 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { itable_evex03056, 3 },
+ /* 0x57 */ { itable_evex03057, 2 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { itable_evex03066, 3 },
+ /* 0x67 */ { itable_evex03067, 1 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_evex030C2, 6 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex031[256] = {
+ /* 0x00 */ { itable_evex03100, 2 },
+ /* 0x01 */ { itable_evex03101, 2 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { itable_evex03103, 12 },
+ /* 0x04 */ { itable_evex03104, 3 },
+ /* 0x05 */ { itable_evex03105, 3 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { itable_evex03108, 3 },
+ /* 0x09 */ { itable_evex03109, 3 },
+ /* 0x0a */ { itable_evex0310A, 2 },
+ /* 0x0b */ { itable_evex0310B, 2 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { itable_evex0310F, 6 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { itable_evex03114, 5 },
+ /* 0x15 */ { itable_evex03115, 4 },
+ /* 0x16 */ { itable_evex03116, 2 },
+ /* 0x17 */ { itable_evex03117, 3 },
+ /* 0x18 */ { itable_evex03118, 8 },
+ /* 0x19 */ { itable_evex03119, 8 },
+ /* 0x1a */ { itable_evex0311A, 4 },
+ /* 0x1b */ { itable_evex0311B, 4 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { itable_evex0311D, 12 },
+ /* 0x1e */ { itable_evex0311E, 60 },
+ /* 0x1f */ { itable_evex0311F, 60 },
+ /* 0x20 */ { itable_evex03120, 4 },
+ /* 0x21 */ { itable_evex03121, 2 },
+ /* 0x22 */ { itable_evex03122, 4 },
+ /* 0x23 */ { itable_evex03123, 8 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { itable_evex03125, 6 },
+ /* 0x26 */ { itable_evex03126, 6 },
+ /* 0x27 */ { itable_evex03127, 2 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { itable_evex03138, 8 },
+ /* 0x39 */ { itable_evex03139, 8 },
+ /* 0x3a */ { itable_evex0313A, 4 },
+ /* 0x3b */ { itable_evex0313B, 4 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { itable_evex0313E, 60 },
+ /* 0x3f */ { itable_evex0313F, 60 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { itable_evex03142, 6 },
+ /* 0x43 */ { itable_evex03143, 8 },
+ /* 0x44 */ { itable_evex03144, 30 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { itable_evex03150, 12 },
+ /* 0x51 */ { itable_evex03151, 4 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { itable_evex03154, 12 },
+ /* 0x55 */ { itable_evex03155, 4 },
+ /* 0x56 */ { itable_evex03156, 6 },
+ /* 0x57 */ { itable_evex03157, 4 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { itable_evex03166, 6 },
+ /* 0x67 */ { itable_evex03167, 2 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { itable_evex03170, 6 },
+ /* 0x71 */ { itable_evex03171, 12 },
+ /* 0x72 */ { itable_evex03172, 6 },
+ /* 0x73 */ { itable_evex03173, 12 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { itable_evex031CE, 6 },
+ /* 0xcf */ { itable_evex031CF, 6 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex032[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { itable_evex032C2, 2 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex050[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { itable_evex0501D, 2 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { itable_evex0502E, 1 },
+ /* 0x2f */ { itable_evex0502F, 1 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_evex05051, 3 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_evex05058, 6 },
+ /* 0x59 */ { itable_evex05059, 6 },
+ /* 0x5a */ { itable_evex0505A, 3 },
+ /* 0x5b */ { itable_evex0505B, 6 },
+ /* 0x5c */ { itable_evex0505C, 6 },
+ /* 0x5d */ { itable_evex0505D, 3 },
+ /* 0x5e */ { itable_evex0505E, 6 },
+ /* 0x5f */ { itable_evex0505F, 3 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_evex05078, 3 },
+ /* 0x79 */ { itable_evex05079, 3 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { itable_evex0507C, 3 },
+ /* 0x7d */ { itable_evex0507D, 3 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex051[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { itable_evex0511D, 3 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { itable_evex0515A, 3 },
+ /* 0x5b */ { itable_evex0515B, 3 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { itable_evex0516E, 1 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_evex05178, 3 },
+ /* 0x79 */ { itable_evex05179, 3 },
+ /* 0x7a */ { itable_evex0517A, 3 },
+ /* 0x7b */ { itable_evex0517B, 3 },
+ /* 0x7c */ { itable_evex0517C, 3 },
+ /* 0x7d */ { itable_evex0517D, 3 },
+ /* 0x7e */ { itable_evex0517E, 1 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex052[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_evex05210, 3 },
+ /* 0x11 */ { itable_evex05211, 3 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { itable_evex0522A, 4 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { itable_evex0522C, 2 },
+ /* 0x2d */ { itable_evex0522D, 2 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { itable_evex05251, 2 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { itable_evex05258, 2 },
+ /* 0x59 */ { itable_evex05259, 2 },
+ /* 0x5a */ { itable_evex0525A, 2 },
+ /* 0x5b */ { itable_evex0525B, 3 },
+ /* 0x5c */ { itable_evex0525C, 2 },
+ /* 0x5d */ { itable_evex0525D, 1 },
+ /* 0x5e */ { itable_evex0525E, 2 },
+ /* 0x5f */ { itable_evex0525F, 1 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { itable_evex05278, 2 },
+ /* 0x79 */ { itable_evex05279, 2 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { itable_evex0527B, 2 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { itable_evex0527D, 3 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex053[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { itable_evex0535A, 2 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { itable_evex0537A, 6 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { itable_evex0537D, 3 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex060[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { itable_evex06013, 2 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex061[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { itable_evex06113, 3 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { itable_evex0612C, 6 },
+ /* 0x2d */ { itable_evex0612D, 2 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { itable_evex06142, 3 },
+ /* 0x43 */ { itable_evex06143, 1 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { itable_evex0614C, 6 },
+ /* 0x4d */ { itable_evex0614D, 2 },
+ /* 0x4e */ { itable_evex0614E, 3 },
+ /* 0x4f */ { itable_evex0614F, 2 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { itable_evex06196, 6 },
+ /* 0x97 */ { itable_evex06197, 6 },
+ /* 0x98 */ { itable_evex06198, 6 },
+ /* 0x99 */ { itable_evex06199, 2 },
+ /* 0x9a */ { itable_evex0619A, 6 },
+ /* 0x9b */ { itable_evex0619B, 2 },
+ /* 0x9c */ { itable_evex0619C, 6 },
+ /* 0x9d */ { itable_evex0619D, 2 },
+ /* 0x9e */ { itable_evex0619E, 6 },
+ /* 0x9f */ { itable_evex0619F, 2 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { itable_evex061A6, 6 },
+ /* 0xa7 */ { itable_evex061A7, 6 },
+ /* 0xa8 */ { itable_evex061A8, 6 },
+ /* 0xa9 */ { itable_evex061A9, 2 },
+ /* 0xaa */ { itable_evex061AA, 6 },
+ /* 0xab */ { itable_evex061AB, 2 },
+ /* 0xac */ { itable_evex061AC, 6 },
+ /* 0xad */ { itable_evex061AD, 2 },
+ /* 0xae */ { itable_evex061AE, 6 },
+ /* 0xaf */ { itable_evex061AF, 2 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { itable_evex061B6, 6 },
+ /* 0xb7 */ { itable_evex061B7, 6 },
+ /* 0xb8 */ { itable_evex061B8, 6 },
+ /* 0xb9 */ { itable_evex061B9, 2 },
+ /* 0xba */ { itable_evex061BA, 6 },
+ /* 0xbb */ { itable_evex061BB, 2 },
+ /* 0xbc */ { itable_evex061BC, 6 },
+ /* 0xbd */ { itable_evex061BD, 2 },
+ /* 0xbe */ { itable_evex061BE, 6 },
+ /* 0xbf */ { itable_evex061BF, 2 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex062[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { itable_evex06256, 6 },
+ /* 0x57 */ { itable_evex06257, 2 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { itable_evex062D6, 6 },
+ /* 0xd7 */ { itable_evex062D7, 2 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_evex063[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { itable_evex06356, 6 },
+ /* 0x57 */ { itable_evex06357, 2 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { itable_evex063D6, 6 },
+ /* 0xd7 */ { itable_evex063D7, 2 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_0F38[256] = {
+ /* 0x00 */ { itable_0F3800, 2 },
+ /* 0x01 */ { itable_0F3801, 2 },
+ /* 0x02 */ { itable_0F3802, 2 },
+ /* 0x03 */ { itable_0F3803, 2 },
+ /* 0x04 */ { itable_0F3804, 2 },
+ /* 0x05 */ { itable_0F3805, 2 },
+ /* 0x06 */ { itable_0F3806, 2 },
+ /* 0x07 */ { itable_0F3807, 2 },
+ /* 0x08 */ { itable_0F3808, 2 },
+ /* 0x09 */ { itable_0F3809, 2 },
+ /* 0x0a */ { itable_0F380A, 2 },
+ /* 0x0b */ { itable_0F380B, 2 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { itable_0F3810, 2 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { itable_0F3814, 2 },
+ /* 0x15 */ { itable_0F3815, 2 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { itable_0F3817, 1 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { itable_0F381C, 2 },
+ /* 0x1d */ { itable_0F381D, 2 },
+ /* 0x1e */ { itable_0F381E, 2 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { itable_0F3820, 1 },
+ /* 0x21 */ { itable_0F3821, 1 },
+ /* 0x22 */ { itable_0F3822, 1 },
+ /* 0x23 */ { itable_0F3823, 1 },
+ /* 0x24 */ { itable_0F3824, 1 },
+ /* 0x25 */ { itable_0F3825, 1 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { itable_0F3828, 1 },
+ /* 0x29 */ { itable_0F3829, 1 },
+ /* 0x2a */ { itable_0F382A, 1 },
+ /* 0x2b */ { itable_0F382B, 1 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { itable_0F3830, 1 },
+ /* 0x31 */ { itable_0F3831, 1 },
+ /* 0x32 */ { itable_0F3832, 1 },
+ /* 0x33 */ { itable_0F3833, 1 },
+ /* 0x34 */ { itable_0F3834, 1 },
+ /* 0x35 */ { itable_0F3835, 1 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { itable_0F3837, 1 },
+ /* 0x38 */ { itable_0F3838, 1 },
+ /* 0x39 */ { itable_0F3839, 1 },
+ /* 0x3a */ { itable_0F383A, 1 },
+ /* 0x3b */ { itable_0F383B, 1 },
+ /* 0x3c */ { itable_0F383C, 1 },
+ /* 0x3d */ { itable_0F383D, 1 },
+ /* 0x3e */ { itable_0F383E, 1 },
+ /* 0x3f */ { itable_0F383F, 1 },
+ /* 0x40 */ { itable_0F3840, 1 },
+ /* 0x41 */ { itable_0F3841, 1 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { itable_0F3880, 2 },
+ /* 0x81 */ { itable_0F3881, 2 },
+ /* 0x82 */ { itable_0F3882, 2 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { itable_0F38C8, 1 },
+ /* 0xc9 */ { itable_0F38C9, 1 },
+ /* 0xca */ { itable_0F38CA, 1 },
+ /* 0xcb */ { itable_0F38CB, 2 },
+ /* 0xcc */ { itable_0F38CC, 1 },
+ /* 0xcd */ { itable_0F38CD, 1 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { itable_0F38CF, 1 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { itable_0F38DB, 1 },
+ /* 0xdc */ { itable_0F38DC, 1 },
+ /* 0xdd */ { itable_0F38DD, 1 },
+ /* 0xde */ { itable_0F38DE, 1 },
+ /* 0xdf */ { itable_0F38DF, 1 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { itable_0F38F0, 5 },
+ /* 0xf1 */ { itable_0F38F1, 6 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { itable_0F38F5, 2 },
+ /* 0xf6 */ { itable_0F38F6, 6 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { itable_0F38F8, 9 },
+ /* 0xf9 */ { itable_0F38F9, 2 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { itable_0F38FC, 6 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_0F3A[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { itable_0F3A08, 1 },
+ /* 0x09 */ { itable_0F3A09, 1 },
+ /* 0x0a */ { itable_0F3A0A, 1 },
+ /* 0x0b */ { itable_0F3A0B, 1 },
+ /* 0x0c */ { itable_0F3A0C, 1 },
+ /* 0x0d */ { itable_0F3A0D, 1 },
+ /* 0x0e */ { itable_0F3A0E, 1 },
+ /* 0x0f */ { itable_0F3A0F, 2 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { itable_0F3A14, 3 },
+ /* 0x15 */ { itable_0F3A15, 3 },
+ /* 0x16 */ { itable_0F3A16, 2 },
+ /* 0x17 */ { itable_0F3A17, 2 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { itable_0F3A20, 3 },
+ /* 0x21 */ { itable_0F3A21, 1 },
+ /* 0x22 */ { itable_0F3A22, 2 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { itable_0F3A40, 1 },
+ /* 0x41 */ { itable_0F3A41, 1 },
+ /* 0x42 */ { itable_0F3A42, 1 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { itable_0F3A44, 5 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { itable_0F3A60, 1 },
+ /* 0x61 */ { itable_0F3A61, 1 },
+ /* 0x62 */ { itable_0F3A62, 1 },
+ /* 0x63 */ { itable_0F3A63, 1 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { NULL, 0 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { NULL, 0 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { itable_0F3ACC, 1 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { itable_0F3ACE, 1 },
+ /* 0xcf */ { itable_0F3ACF, 1 },
+ /* 0xd0 */ { NULL, 0 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { itable_0F3ADF, 1 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { itable_0F3AF0, 1 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_0FA6[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { itable_0FA6C0, 1 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { itable_0FA6C8, 1 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { itable_0FA6D0, 1 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { NULL, 0 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { NULL, 0 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { NULL, 0 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_0FA7[256] = {
+ /* 0x00 */ { NULL, 0 },
+ /* 0x01 */ { NULL, 0 },
+ /* 0x02 */ { NULL, 0 },
+ /* 0x03 */ { NULL, 0 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { NULL, 0 },
+ /* 0x06 */ { NULL, 0 },
+ /* 0x07 */ { NULL, 0 },
+ /* 0x08 */ { NULL, 0 },
+ /* 0x09 */ { NULL, 0 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { NULL, 0 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { NULL, 0 },
+ /* 0x0e */ { NULL, 0 },
+ /* 0x0f */ { NULL, 0 },
+ /* 0x10 */ { NULL, 0 },
+ /* 0x11 */ { NULL, 0 },
+ /* 0x12 */ { NULL, 0 },
+ /* 0x13 */ { NULL, 0 },
+ /* 0x14 */ { NULL, 0 },
+ /* 0x15 */ { NULL, 0 },
+ /* 0x16 */ { NULL, 0 },
+ /* 0x17 */ { NULL, 0 },
+ /* 0x18 */ { NULL, 0 },
+ /* 0x19 */ { NULL, 0 },
+ /* 0x1a */ { NULL, 0 },
+ /* 0x1b */ { NULL, 0 },
+ /* 0x1c */ { NULL, 0 },
+ /* 0x1d */ { NULL, 0 },
+ /* 0x1e */ { NULL, 0 },
+ /* 0x1f */ { NULL, 0 },
+ /* 0x20 */ { NULL, 0 },
+ /* 0x21 */ { NULL, 0 },
+ /* 0x22 */ { NULL, 0 },
+ /* 0x23 */ { NULL, 0 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { NULL, 0 },
+ /* 0x29 */ { NULL, 0 },
+ /* 0x2a */ { NULL, 0 },
+ /* 0x2b */ { NULL, 0 },
+ /* 0x2c */ { NULL, 0 },
+ /* 0x2d */ { NULL, 0 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { NULL, 0 },
+ /* 0x30 */ { NULL, 0 },
+ /* 0x31 */ { NULL, 0 },
+ /* 0x32 */ { NULL, 0 },
+ /* 0x33 */ { NULL, 0 },
+ /* 0x34 */ { NULL, 0 },
+ /* 0x35 */ { NULL, 0 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { NULL, 0 },
+ /* 0x38 */ { NULL, 0 },
+ /* 0x39 */ { NULL, 0 },
+ /* 0x3a */ { NULL, 0 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { NULL, 0 },
+ /* 0x3d */ { NULL, 0 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { NULL, 0 },
+ /* 0x41 */ { NULL, 0 },
+ /* 0x42 */ { NULL, 0 },
+ /* 0x43 */ { NULL, 0 },
+ /* 0x44 */ { NULL, 0 },
+ /* 0x45 */ { NULL, 0 },
+ /* 0x46 */ { NULL, 0 },
+ /* 0x47 */ { NULL, 0 },
+ /* 0x48 */ { NULL, 0 },
+ /* 0x49 */ { NULL, 0 },
+ /* 0x4a */ { NULL, 0 },
+ /* 0x4b */ { NULL, 0 },
+ /* 0x4c */ { NULL, 0 },
+ /* 0x4d */ { NULL, 0 },
+ /* 0x4e */ { NULL, 0 },
+ /* 0x4f */ { NULL, 0 },
+ /* 0x50 */ { NULL, 0 },
+ /* 0x51 */ { NULL, 0 },
+ /* 0x52 */ { NULL, 0 },
+ /* 0x53 */ { NULL, 0 },
+ /* 0x54 */ { NULL, 0 },
+ /* 0x55 */ { NULL, 0 },
+ /* 0x56 */ { NULL, 0 },
+ /* 0x57 */ { NULL, 0 },
+ /* 0x58 */ { NULL, 0 },
+ /* 0x59 */ { NULL, 0 },
+ /* 0x5a */ { NULL, 0 },
+ /* 0x5b */ { NULL, 0 },
+ /* 0x5c */ { NULL, 0 },
+ /* 0x5d */ { NULL, 0 },
+ /* 0x5e */ { NULL, 0 },
+ /* 0x5f */ { NULL, 0 },
+ /* 0x60 */ { NULL, 0 },
+ /* 0x61 */ { NULL, 0 },
+ /* 0x62 */ { NULL, 0 },
+ /* 0x63 */ { NULL, 0 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { NULL, 0 },
+ /* 0x69 */ { NULL, 0 },
+ /* 0x6a */ { NULL, 0 },
+ /* 0x6b */ { NULL, 0 },
+ /* 0x6c */ { NULL, 0 },
+ /* 0x6d */ { NULL, 0 },
+ /* 0x6e */ { NULL, 0 },
+ /* 0x6f */ { NULL, 0 },
+ /* 0x70 */ { NULL, 0 },
+ /* 0x71 */ { NULL, 0 },
+ /* 0x72 */ { NULL, 0 },
+ /* 0x73 */ { NULL, 0 },
+ /* 0x74 */ { NULL, 0 },
+ /* 0x75 */ { NULL, 0 },
+ /* 0x76 */ { NULL, 0 },
+ /* 0x77 */ { NULL, 0 },
+ /* 0x78 */ { NULL, 0 },
+ /* 0x79 */ { NULL, 0 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { NULL, 0 },
+ /* 0x7c */ { NULL, 0 },
+ /* 0x7d */ { NULL, 0 },
+ /* 0x7e */ { NULL, 0 },
+ /* 0x7f */ { NULL, 0 },
+ /* 0x80 */ { NULL, 0 },
+ /* 0x81 */ { NULL, 0 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { NULL, 0 },
+ /* 0x84 */ { NULL, 0 },
+ /* 0x85 */ { NULL, 0 },
+ /* 0x86 */ { NULL, 0 },
+ /* 0x87 */ { NULL, 0 },
+ /* 0x88 */ { NULL, 0 },
+ /* 0x89 */ { NULL, 0 },
+ /* 0x8a */ { NULL, 0 },
+ /* 0x8b */ { NULL, 0 },
+ /* 0x8c */ { NULL, 0 },
+ /* 0x8d */ { NULL, 0 },
+ /* 0x8e */ { NULL, 0 },
+ /* 0x8f */ { NULL, 0 },
+ /* 0x90 */ { NULL, 0 },
+ /* 0x91 */ { NULL, 0 },
+ /* 0x92 */ { NULL, 0 },
+ /* 0x93 */ { NULL, 0 },
+ /* 0x94 */ { NULL, 0 },
+ /* 0x95 */ { NULL, 0 },
+ /* 0x96 */ { NULL, 0 },
+ /* 0x97 */ { NULL, 0 },
+ /* 0x98 */ { NULL, 0 },
+ /* 0x99 */ { NULL, 0 },
+ /* 0x9a */ { NULL, 0 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { NULL, 0 },
+ /* 0x9d */ { NULL, 0 },
+ /* 0x9e */ { NULL, 0 },
+ /* 0x9f */ { NULL, 0 },
+ /* 0xa0 */ { NULL, 0 },
+ /* 0xa1 */ { NULL, 0 },
+ /* 0xa2 */ { NULL, 0 },
+ /* 0xa3 */ { NULL, 0 },
+ /* 0xa4 */ { NULL, 0 },
+ /* 0xa5 */ { NULL, 0 },
+ /* 0xa6 */ { NULL, 0 },
+ /* 0xa7 */ { NULL, 0 },
+ /* 0xa8 */ { NULL, 0 },
+ /* 0xa9 */ { NULL, 0 },
+ /* 0xaa */ { NULL, 0 },
+ /* 0xab */ { NULL, 0 },
+ /* 0xac */ { NULL, 0 },
+ /* 0xad */ { NULL, 0 },
+ /* 0xae */ { NULL, 0 },
+ /* 0xaf */ { NULL, 0 },
+ /* 0xb0 */ { NULL, 0 },
+ /* 0xb1 */ { NULL, 0 },
+ /* 0xb2 */ { NULL, 0 },
+ /* 0xb3 */ { NULL, 0 },
+ /* 0xb4 */ { NULL, 0 },
+ /* 0xb5 */ { NULL, 0 },
+ /* 0xb6 */ { NULL, 0 },
+ /* 0xb7 */ { NULL, 0 },
+ /* 0xb8 */ { NULL, 0 },
+ /* 0xb9 */ { NULL, 0 },
+ /* 0xba */ { NULL, 0 },
+ /* 0xbb */ { NULL, 0 },
+ /* 0xbc */ { NULL, 0 },
+ /* 0xbd */ { NULL, 0 },
+ /* 0xbe */ { NULL, 0 },
+ /* 0xbf */ { NULL, 0 },
+ /* 0xc0 */ { itable_0FA7C0, 1 },
+ /* 0xc1 */ { NULL, 0 },
+ /* 0xc2 */ { NULL, 0 },
+ /* 0xc3 */ { NULL, 0 },
+ /* 0xc4 */ { NULL, 0 },
+ /* 0xc5 */ { NULL, 0 },
+ /* 0xc6 */ { NULL, 0 },
+ /* 0xc7 */ { NULL, 0 },
+ /* 0xc8 */ { itable_0FA7C8, 1 },
+ /* 0xc9 */ { NULL, 0 },
+ /* 0xca */ { NULL, 0 },
+ /* 0xcb */ { NULL, 0 },
+ /* 0xcc */ { NULL, 0 },
+ /* 0xcd */ { NULL, 0 },
+ /* 0xce */ { NULL, 0 },
+ /* 0xcf */ { NULL, 0 },
+ /* 0xd0 */ { itable_0FA7D0, 1 },
+ /* 0xd1 */ { NULL, 0 },
+ /* 0xd2 */ { NULL, 0 },
+ /* 0xd3 */ { NULL, 0 },
+ /* 0xd4 */ { NULL, 0 },
+ /* 0xd5 */ { NULL, 0 },
+ /* 0xd6 */ { NULL, 0 },
+ /* 0xd7 */ { NULL, 0 },
+ /* 0xd8 */ { itable_0FA7D8, 1 },
+ /* 0xd9 */ { NULL, 0 },
+ /* 0xda */ { NULL, 0 },
+ /* 0xdb */ { NULL, 0 },
+ /* 0xdc */ { NULL, 0 },
+ /* 0xdd */ { NULL, 0 },
+ /* 0xde */ { NULL, 0 },
+ /* 0xdf */ { NULL, 0 },
+ /* 0xe0 */ { itable_0FA7E0, 1 },
+ /* 0xe1 */ { NULL, 0 },
+ /* 0xe2 */ { NULL, 0 },
+ /* 0xe3 */ { NULL, 0 },
+ /* 0xe4 */ { NULL, 0 },
+ /* 0xe5 */ { NULL, 0 },
+ /* 0xe6 */ { NULL, 0 },
+ /* 0xe7 */ { NULL, 0 },
+ /* 0xe8 */ { itable_0FA7E8, 1 },
+ /* 0xe9 */ { NULL, 0 },
+ /* 0xea */ { NULL, 0 },
+ /* 0xeb */ { NULL, 0 },
+ /* 0xec */ { NULL, 0 },
+ /* 0xed */ { NULL, 0 },
+ /* 0xee */ { NULL, 0 },
+ /* 0xef */ { NULL, 0 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { NULL, 0 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { NULL, 0 },
+ /* 0xf5 */ { NULL, 0 },
+ /* 0xf6 */ { NULL, 0 },
+ /* 0xf7 */ { NULL, 0 },
+ /* 0xf8 */ { NULL, 0 },
+ /* 0xf9 */ { NULL, 0 },
+ /* 0xfa */ { NULL, 0 },
+ /* 0xfb */ { NULL, 0 },
+ /* 0xfc */ { NULL, 0 },
+ /* 0xfd */ { NULL, 0 },
+ /* 0xfe */ { NULL, 0 },
+ /* 0xff */ { NULL, 0 },
+};
+
+static const struct disasm_index itable_0F[256] = {
+ /* 0x00 */ { itable_0F00, 24 },
+ /* 0x01 */ { itable_0F01, 66 },
+ /* 0x02 */ { itable_0F02, 10 },
+ /* 0x03 */ { itable_0F03, 10 },
+ /* 0x04 */ { NULL, 0 },
+ /* 0x05 */ { itable_0F05, 1 },
+ /* 0x06 */ { itable_0F06, 1 },
+ /* 0x07 */ { itable_0F07, 1 },
+ /* 0x08 */ { itable_0F08, 1 },
+ /* 0x09 */ { itable_0F09, 3 },
+ /* 0x0a */ { NULL, 0 },
+ /* 0x0b */ { itable_0F0B, 1 },
+ /* 0x0c */ { NULL, 0 },
+ /* 0x0d */ { itable_0F0D, 3 },
+ /* 0x0e */ { itable_0F0E, 1 },
+ /* 0x0f */ { itable_0F0F, 26 },
+ /* 0x10 */ { itable_0F10, 4 },
+ /* 0x11 */ { itable_0F11, 4 },
+ /* 0x12 */ { itable_0F12, 5 },
+ /* 0x13 */ { itable_0F13, 2 },
+ /* 0x14 */ { itable_0F14, 2 },
+ /* 0x15 */ { itable_0F15, 2 },
+ /* 0x16 */ { itable_0F16, 4 },
+ /* 0x17 */ { itable_0F17, 2 },
+ /* 0x18 */ { itable_0F18, 30 },
+ /* 0x19 */ { itable_0F19, 24 },
+ /* 0x1a */ { itable_0F1A, 35 },
+ /* 0x1b */ { itable_0F1B, 35 },
+ /* 0x1c */ { itable_0F1C, 25 },
+ /* 0x1d */ { itable_0F1D, 24 },
+ /* 0x1e */ { itable_0F1E, 28 },
+ /* 0x1f */ { itable_0F1F, 27 },
+ /* 0x20 */ { itable_0F20, 2 },
+ /* 0x21 */ { itable_0F21, 2 },
+ /* 0x22 */ { itable_0F22, 2 },
+ /* 0x23 */ { itable_0F23, 2 },
+ /* 0x24 */ { NULL, 0 },
+ /* 0x25 */ { NULL, 0 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { NULL, 0 },
+ /* 0x28 */ { itable_0F28, 2 },
+ /* 0x29 */ { itable_0F29, 2 },
+ /* 0x2a */ { itable_0F2A, 6 },
+ /* 0x2b */ { itable_0F2B, 4 },
+ /* 0x2c */ { itable_0F2C, 8 },
+ /* 0x2d */ { itable_0F2D, 10 },
+ /* 0x2e */ { itable_0F2E, 2 },
+ /* 0x2f */ { itable_0F2F, 2 },
+ /* 0x30 */ { itable_0F30, 1 },
+ /* 0x31 */ { itable_0F31, 1 },
+ /* 0x32 */ { itable_0F32, 1 },
+ /* 0x33 */ { itable_0F33, 1 },
+ /* 0x34 */ { itable_0F34, 1 },
+ /* 0x35 */ { itable_0F35, 1 },
+ /* 0x36 */ { itable_0F36, 1 },
+ /* 0x37 */ { itable_0F37, 2 },
+ /* 0x38 */ { itable_0F38, -1 },
+ /* 0x39 */ { itable_0F39, 1 },
+ /* 0x3a */ { itable_0F3A, -1 },
+ /* 0x3b */ { NULL, 0 },
+ /* 0x3c */ { itable_0F3C, 1 },
+ /* 0x3d */ { itable_0F3D, 1 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { NULL, 0 },
+ /* 0x40 */ { itable_0F40, 6 },
+ /* 0x41 */ { itable_0F41, 6 },
+ /* 0x42 */ { itable_0F42, 6 },
+ /* 0x43 */ { itable_0F43, 6 },
+ /* 0x44 */ { itable_0F44, 6 },
+ /* 0x45 */ { itable_0F45, 6 },
+ /* 0x46 */ { itable_0F46, 6 },
+ /* 0x47 */ { itable_0F47, 6 },
+ /* 0x48 */ { itable_0F48, 6 },
+ /* 0x49 */ { itable_0F49, 6 },
+ /* 0x4a */ { itable_0F4A, 6 },
+ /* 0x4b */ { itable_0F4B, 6 },
+ /* 0x4c */ { itable_0F4C, 6 },
+ /* 0x4d */ { itable_0F4D, 6 },
+ /* 0x4e */ { itable_0F4E, 6 },
+ /* 0x4f */ { itable_0F4F, 6 },
+ /* 0x50 */ { itable_0F50, 5 },
+ /* 0x51 */ { itable_0F51, 5 },
+ /* 0x52 */ { itable_0F52, 3 },
+ /* 0x53 */ { itable_0F53, 2 },
+ /* 0x54 */ { itable_0F54, 3 },
+ /* 0x55 */ { itable_0F55, 3 },
+ /* 0x56 */ { itable_0F56, 2 },
+ /* 0x57 */ { itable_0F57, 2 },
+ /* 0x58 */ { itable_0F58, 5 },
+ /* 0x59 */ { itable_0F59, 5 },
+ /* 0x5a */ { itable_0F5A, 5 },
+ /* 0x5b */ { itable_0F5B, 4 },
+ /* 0x5c */ { itable_0F5C, 5 },
+ /* 0x5d */ { itable_0F5D, 5 },
+ /* 0x5e */ { itable_0F5E, 5 },
+ /* 0x5f */ { itable_0F5F, 4 },
+ /* 0x60 */ { itable_0F60, 2 },
+ /* 0x61 */ { itable_0F61, 2 },
+ /* 0x62 */ { itable_0F62, 2 },
+ /* 0x63 */ { itable_0F63, 2 },
+ /* 0x64 */ { itable_0F64, 2 },
+ /* 0x65 */ { itable_0F65, 2 },
+ /* 0x66 */ { itable_0F66, 2 },
+ /* 0x67 */ { itable_0F67, 2 },
+ /* 0x68 */ { itable_0F68, 2 },
+ /* 0x69 */ { itable_0F69, 2 },
+ /* 0x6a */ { itable_0F6A, 2 },
+ /* 0x6b */ { itable_0F6B, 2 },
+ /* 0x6c */ { itable_0F6C, 1 },
+ /* 0x6d */ { itable_0F6D, 1 },
+ /* 0x6e */ { itable_0F6E, 5 },
+ /* 0x6f */ { itable_0F6F, 3 },
+ /* 0x70 */ { itable_0F70, 7 },
+ /* 0x71 */ { itable_0F71, 6 },
+ /* 0x72 */ { itable_0F72, 6 },
+ /* 0x73 */ { itable_0F73, 6 },
+ /* 0x74 */ { itable_0F74, 2 },
+ /* 0x75 */ { itable_0F75, 2 },
+ /* 0x76 */ { itable_0F76, 2 },
+ /* 0x77 */ { itable_0F77, 1 },
+ /* 0x78 */ { itable_0F78, 5 },
+ /* 0x79 */ { itable_0F79, 5 },
+ /* 0x7a */ { NULL, 0 },
+ /* 0x7b */ { itable_0F7B, 1 },
+ /* 0x7c */ { itable_0F7C, 3 },
+ /* 0x7d */ { itable_0F7D, 3 },
+ /* 0x7e */ { itable_0F7E, 7 },
+ /* 0x7f */ { itable_0F7F, 3 },
+ /* 0x80 */ { itable_0F80, 4 },
+ /* 0x81 */ { itable_0F81, 4 },
+ /* 0x82 */ { itable_0F82, 4 },
+ /* 0x83 */ { itable_0F83, 4 },
+ /* 0x84 */ { itable_0F84, 4 },
+ /* 0x85 */ { itable_0F85, 4 },
+ /* 0x86 */ { itable_0F86, 4 },
+ /* 0x87 */ { itable_0F87, 4 },
+ /* 0x88 */ { itable_0F88, 4 },
+ /* 0x89 */ { itable_0F89, 4 },
+ /* 0x8a */ { itable_0F8A, 4 },
+ /* 0x8b */ { itable_0F8B, 4 },
+ /* 0x8c */ { itable_0F8C, 4 },
+ /* 0x8d */ { itable_0F8D, 4 },
+ /* 0x8e */ { itable_0F8E, 4 },
+ /* 0x8f */ { itable_0F8F, 4 },
+ /* 0x90 */ { itable_0F90, 2 },
+ /* 0x91 */ { itable_0F91, 2 },
+ /* 0x92 */ { itable_0F92, 2 },
+ /* 0x93 */ { itable_0F93, 2 },
+ /* 0x94 */ { itable_0F94, 2 },
+ /* 0x95 */ { itable_0F95, 2 },
+ /* 0x96 */ { itable_0F96, 2 },
+ /* 0x97 */ { itable_0F97, 2 },
+ /* 0x98 */ { itable_0F98, 2 },
+ /* 0x99 */ { itable_0F99, 2 },
+ /* 0x9a */ { itable_0F9A, 2 },
+ /* 0x9b */ { itable_0F9B, 2 },
+ /* 0x9c */ { itable_0F9C, 2 },
+ /* 0x9d */ { itable_0F9D, 2 },
+ /* 0x9e */ { itable_0F9E, 2 },
+ /* 0x9f */ { itable_0F9F, 2 },
+ /* 0xa0 */ { itable_0FA0, 1 },
+ /* 0xa1 */ { itable_0FA1, 1 },
+ /* 0xa2 */ { itable_0FA2, 1 },
+ /* 0xa3 */ { itable_0FA3, 6 },
+ /* 0xa4 */ { itable_0FA4, 6 },
+ /* 0xa5 */ { itable_0FA5, 6 },
+ /* 0xa6 */ { itable_0FA6, -1 },
+ /* 0xa7 */ { itable_0FA7, -1 },
+ /* 0xa8 */ { itable_0FA8, 1 },
+ /* 0xa9 */ { itable_0FA9, 1 },
+ /* 0xaa */ { itable_0FAA, 1 },
+ /* 0xab */ { itable_0FAB, 6 },
+ /* 0xac */ { itable_0FAC, 6 },
+ /* 0xad */ { itable_0FAD, 6 },
+ /* 0xae */ { itable_0FAE, 40 },
+ /* 0xaf */ { itable_0FAF, 6 },
+ /* 0xb0 */ { itable_0FB0, 2 },
+ /* 0xb1 */ { itable_0FB1, 6 },
+ /* 0xb2 */ { itable_0FB2, 3 },
+ /* 0xb3 */ { itable_0FB3, 6 },
+ /* 0xb4 */ { itable_0FB4, 3 },
+ /* 0xb5 */ { itable_0FB5, 3 },
+ /* 0xb6 */ { itable_0FB6, 4 },
+ /* 0xb7 */ { itable_0FB7, 2 },
+ /* 0xb8 */ { itable_0FB8, 6 },
+ /* 0xb9 */ { itable_0FB9, 3 },
+ /* 0xba */ { itable_0FBA, 12 },
+ /* 0xbb */ { itable_0FBB, 6 },
+ /* 0xbc */ { itable_0FBC, 9 },
+ /* 0xbd */ { itable_0FBD, 9 },
+ /* 0xbe */ { itable_0FBE, 4 },
+ /* 0xbf */ { itable_0FBF, 2 },
+ /* 0xc0 */ { itable_0FC0, 2 },
+ /* 0xc1 */ { itable_0FC1, 6 },
+ /* 0xc2 */ { itable_0FC2, 36 },
+ /* 0xc3 */ { itable_0FC3, 2 },
+ /* 0xc4 */ { itable_0FC4, 6 },
+ /* 0xc5 */ { itable_0FC5, 2 },
+ /* 0xc6 */ { itable_0FC6, 2 },
+ /* 0xc7 */ { itable_0FC7, 22 },
+ /* 0xc8 */ { itable_0FC8, 2 },
+ /* 0xc9 */ { itable_0FC9, 2 },
+ /* 0xca */ { itable_0FCA, 2 },
+ /* 0xcb */ { itable_0FCB, 2 },
+ /* 0xcc */ { itable_0FCC, 2 },
+ /* 0xcd */ { itable_0FCD, 2 },
+ /* 0xce */ { itable_0FCE, 2 },
+ /* 0xcf */ { itable_0FCF, 2 },
+ /* 0xd0 */ { itable_0FD0, 2 },
+ /* 0xd1 */ { itable_0FD1, 2 },
+ /* 0xd2 */ { itable_0FD2, 2 },
+ /* 0xd3 */ { itable_0FD3, 2 },
+ /* 0xd4 */ { itable_0FD4, 2 },
+ /* 0xd5 */ { itable_0FD5, 2 },
+ /* 0xd6 */ { itable_0FD6, 4 },
+ /* 0xd7 */ { itable_0FD7, 2 },
+ /* 0xd8 */ { itable_0FD8, 2 },
+ /* 0xd9 */ { itable_0FD9, 2 },
+ /* 0xda */ { itable_0FDA, 2 },
+ /* 0xdb */ { itable_0FDB, 2 },
+ /* 0xdc */ { itable_0FDC, 2 },
+ /* 0xdd */ { itable_0FDD, 2 },
+ /* 0xde */ { itable_0FDE, 2 },
+ /* 0xdf */ { itable_0FDF, 2 },
+ /* 0xe0 */ { itable_0FE0, 2 },
+ /* 0xe1 */ { itable_0FE1, 2 },
+ /* 0xe2 */ { itable_0FE2, 2 },
+ /* 0xe3 */ { itable_0FE3, 2 },
+ /* 0xe4 */ { itable_0FE4, 2 },
+ /* 0xe5 */ { itable_0FE5, 2 },
+ /* 0xe6 */ { itable_0FE6, 3 },
+ /* 0xe7 */ { itable_0FE7, 2 },
+ /* 0xe8 */ { itable_0FE8, 2 },
+ /* 0xe9 */ { itable_0FE9, 2 },
+ /* 0xea */ { itable_0FEA, 2 },
+ /* 0xeb */ { itable_0FEB, 2 },
+ /* 0xec */ { itable_0FEC, 2 },
+ /* 0xed */ { itable_0FED, 2 },
+ /* 0xee */ { itable_0FEE, 2 },
+ /* 0xef */ { itable_0FEF, 2 },
+ /* 0xf0 */ { itable_0FF0, 1 },
+ /* 0xf1 */ { itable_0FF1, 2 },
+ /* 0xf2 */ { itable_0FF2, 2 },
+ /* 0xf3 */ { itable_0FF3, 2 },
+ /* 0xf4 */ { itable_0FF4, 2 },
+ /* 0xf5 */ { itable_0FF5, 2 },
+ /* 0xf6 */ { itable_0FF6, 2 },
+ /* 0xf7 */ { itable_0FF7, 2 },
+ /* 0xf8 */ { itable_0FF8, 2 },
+ /* 0xf9 */ { itable_0FF9, 2 },
+ /* 0xfa */ { itable_0FFA, 2 },
+ /* 0xfb */ { itable_0FFB, 2 },
+ /* 0xfc */ { itable_0FFC, 2 },
+ /* 0xfd */ { itable_0FFD, 2 },
+ /* 0xfe */ { itable_0FFE, 2 },
+ /* 0xff */ { itable_0FFF, 4 },
+};
+
+const struct disasm_index itable[256] = {
+ /* 0x00 */ { itable_00, 2 },
+ /* 0x01 */ { itable_01, 6 },
+ /* 0x02 */ { itable_02, 2 },
+ /* 0x03 */ { itable_03, 6 },
+ /* 0x04 */ { itable_04, 1 },
+ /* 0x05 */ { itable_05, 3 },
+ /* 0x06 */ { itable_06, 1 },
+ /* 0x07 */ { itable_07, 1 },
+ /* 0x08 */ { itable_08, 2 },
+ /* 0x09 */ { itable_09, 6 },
+ /* 0x0a */ { itable_0A, 2 },
+ /* 0x0b */ { itable_0B, 6 },
+ /* 0x0c */ { itable_0C, 1 },
+ /* 0x0d */ { itable_0D, 3 },
+ /* 0x0e */ { itable_0E, 1 },
+ /* 0x0f */ { itable_0F, -1 },
+ /* 0x10 */ { itable_10, 2 },
+ /* 0x11 */ { itable_11, 6 },
+ /* 0x12 */ { itable_12, 2 },
+ /* 0x13 */ { itable_13, 6 },
+ /* 0x14 */ { itable_14, 1 },
+ /* 0x15 */ { itable_15, 3 },
+ /* 0x16 */ { itable_16, 1 },
+ /* 0x17 */ { itable_17, 1 },
+ /* 0x18 */ { itable_18, 2 },
+ /* 0x19 */ { itable_19, 6 },
+ /* 0x1a */ { itable_1A, 2 },
+ /* 0x1b */ { itable_1B, 6 },
+ /* 0x1c */ { itable_1C, 1 },
+ /* 0x1d */ { itable_1D, 3 },
+ /* 0x1e */ { itable_1E, 1 },
+ /* 0x1f */ { itable_1F, 1 },
+ /* 0x20 */ { itable_20, 2 },
+ /* 0x21 */ { itable_21, 6 },
+ /* 0x22 */ { itable_22, 2 },
+ /* 0x23 */ { itable_23, 6 },
+ /* 0x24 */ { itable_24, 1 },
+ /* 0x25 */ { itable_25, 3 },
+ /* 0x26 */ { NULL, 0 },
+ /* 0x27 */ { itable_27, 1 },
+ /* 0x28 */ { itable_28, 2 },
+ /* 0x29 */ { itable_29, 6 },
+ /* 0x2a */ { itable_2A, 2 },
+ /* 0x2b */ { itable_2B, 6 },
+ /* 0x2c */ { itable_2C, 1 },
+ /* 0x2d */ { itable_2D, 3 },
+ /* 0x2e */ { NULL, 0 },
+ /* 0x2f */ { itable_2F, 1 },
+ /* 0x30 */ { itable_30, 2 },
+ /* 0x31 */ { itable_31, 6 },
+ /* 0x32 */ { itable_32, 2 },
+ /* 0x33 */ { itable_33, 6 },
+ /* 0x34 */ { itable_34, 1 },
+ /* 0x35 */ { itable_35, 3 },
+ /* 0x36 */ { NULL, 0 },
+ /* 0x37 */ { itable_37, 1 },
+ /* 0x38 */ { itable_38, 2 },
+ /* 0x39 */ { itable_39, 6 },
+ /* 0x3a */ { itable_3A, 2 },
+ /* 0x3b */ { itable_3B, 6 },
+ /* 0x3c */ { itable_3C, 1 },
+ /* 0x3d */ { itable_3D, 3 },
+ /* 0x3e */ { NULL, 0 },
+ /* 0x3f */ { itable_3F, 1 },
+ /* 0x40 */ { itable_40, 2 },
+ /* 0x41 */ { itable_41, 2 },
+ /* 0x42 */ { itable_42, 2 },
+ /* 0x43 */ { itable_43, 2 },
+ /* 0x44 */ { itable_44, 2 },
+ /* 0x45 */ { itable_45, 2 },
+ /* 0x46 */ { itable_46, 2 },
+ /* 0x47 */ { itable_47, 2 },
+ /* 0x48 */ { itable_48, 2 },
+ /* 0x49 */ { itable_49, 2 },
+ /* 0x4a */ { itable_4A, 2 },
+ /* 0x4b */ { itable_4B, 2 },
+ /* 0x4c */ { itable_4C, 2 },
+ /* 0x4d */ { itable_4D, 2 },
+ /* 0x4e */ { itable_4E, 2 },
+ /* 0x4f */ { itable_4F, 2 },
+ /* 0x50 */ { itable_50, 3 },
+ /* 0x51 */ { itable_51, 3 },
+ /* 0x52 */ { itable_52, 3 },
+ /* 0x53 */ { itable_53, 3 },
+ /* 0x54 */ { itable_54, 3 },
+ /* 0x55 */ { itable_55, 3 },
+ /* 0x56 */ { itable_56, 3 },
+ /* 0x57 */ { itable_57, 3 },
+ /* 0x58 */ { itable_58, 3 },
+ /* 0x59 */ { itable_59, 3 },
+ /* 0x5a */ { itable_5A, 3 },
+ /* 0x5b */ { itable_5B, 3 },
+ /* 0x5c */ { itable_5C, 3 },
+ /* 0x5d */ { itable_5D, 3 },
+ /* 0x5e */ { itable_5E, 3 },
+ /* 0x5f */ { itable_5F, 3 },
+ /* 0x60 */ { itable_60, 3 },
+ /* 0x61 */ { itable_61, 3 },
+ /* 0x62 */ { itable_62, 2 },
+ /* 0x63 */ { itable_63, 3 },
+ /* 0x64 */ { NULL, 0 },
+ /* 0x65 */ { NULL, 0 },
+ /* 0x66 */ { NULL, 0 },
+ /* 0x67 */ { NULL, 0 },
+ /* 0x68 */ { itable_68, 5 },
+ /* 0x69 */ { itable_69, 9 },
+ /* 0x6a */ { itable_6A, 1 },
+ /* 0x6b */ { itable_6B, 9 },
+ /* 0x6c */ { itable_6C, 1 },
+ /* 0x6d */ { itable_6D, 2 },
+ /* 0x6e */ { itable_6E, 1 },
+ /* 0x6f */ { itable_6F, 2 },
+ /* 0x70 */ { itable_70, 1 },
+ /* 0x71 */ { itable_71, 1 },
+ /* 0x72 */ { itable_72, 1 },
+ /* 0x73 */ { itable_73, 1 },
+ /* 0x74 */ { itable_74, 1 },
+ /* 0x75 */ { itable_75, 1 },
+ /* 0x76 */ { itable_76, 1 },
+ /* 0x77 */ { itable_77, 1 },
+ /* 0x78 */ { itable_78, 1 },
+ /* 0x79 */ { itable_79, 1 },
+ /* 0x7a */ { itable_7A, 1 },
+ /* 0x7b */ { itable_7B, 1 },
+ /* 0x7c */ { itable_7C, 1 },
+ /* 0x7d */ { itable_7D, 1 },
+ /* 0x7e */ { itable_7E, 1 },
+ /* 0x7f */ { itable_7F, 1 },
+ /* 0x80 */ { itable_80, 15 },
+ /* 0x81 */ { itable_81, 40 },
+ /* 0x82 */ { NULL, 0 },
+ /* 0x83 */ { itable_83, 24 },
+ /* 0x84 */ { itable_84, 3 },
+ /* 0x85 */ { itable_85, 9 },
+ /* 0x86 */ { itable_86, 4 },
+ /* 0x87 */ { itable_87, 12 },
+ /* 0x88 */ { itable_88, 2 },
+ /* 0x89 */ { itable_89, 6 },
+ /* 0x8a */ { itable_8A, 2 },
+ /* 0x8b */ { itable_8B, 6 },
+ /* 0x8c */ { itable_8C, 4 },
+ /* 0x8d */ { itable_8D, 3 },
+ /* 0x8e */ { itable_8E, 4 },
+ /* 0x8f */ { itable_8F, 3 },
+ /* 0x90 */ { itable_90, 9 },
+ /* 0x91 */ { itable_91, 6 },
+ /* 0x92 */ { itable_92, 6 },
+ /* 0x93 */ { itable_93, 6 },
+ /* 0x94 */ { itable_94, 6 },
+ /* 0x95 */ { itable_95, 6 },
+ /* 0x96 */ { itable_96, 6 },
+ /* 0x97 */ { itable_97, 6 },
+ /* 0x98 */ { itable_98, 3 },
+ /* 0x99 */ { itable_99, 3 },
+ /* 0x9a */ { itable_9A, 5 },
+ /* 0x9b */ { NULL, 0 },
+ /* 0x9c */ { itable_9C, 4 },
+ /* 0x9d */ { itable_9D, 4 },
+ /* 0x9e */ { itable_9E, 1 },
+ /* 0x9f */ { itable_9F, 1 },
+ /* 0xa0 */ { itable_A0, 1 },
+ /* 0xa1 */ { itable_A1, 3 },
+ /* 0xa2 */ { itable_A2, 1 },
+ /* 0xa3 */ { itable_A3, 3 },
+ /* 0xa4 */ { itable_A4, 1 },
+ /* 0xa5 */ { itable_A5, 3 },
+ /* 0xa6 */ { itable_A6, 1 },
+ /* 0xa7 */ { itable_A7, 3 },
+ /* 0xa8 */ { itable_A8, 1 },
+ /* 0xa9 */ { itable_A9, 3 },
+ /* 0xaa */ { itable_AA, 1 },
+ /* 0xab */ { itable_AB, 3 },
+ /* 0xac */ { itable_AC, 1 },
+ /* 0xad */ { itable_AD, 3 },
+ /* 0xae */ { itable_AE, 1 },
+ /* 0xaf */ { itable_AF, 3 },
+ /* 0xb0 */ { itable_B0, 1 },
+ /* 0xb1 */ { itable_B1, 1 },
+ /* 0xb2 */ { itable_B2, 1 },
+ /* 0xb3 */ { itable_B3, 1 },
+ /* 0xb4 */ { itable_B4, 1 },
+ /* 0xb5 */ { itable_B5, 1 },
+ /* 0xb6 */ { itable_B6, 1 },
+ /* 0xb7 */ { itable_B7, 1 },
+ /* 0xb8 */ { itable_B8, 3 },
+ /* 0xb9 */ { itable_B9, 3 },
+ /* 0xba */ { itable_BA, 3 },
+ /* 0xbb */ { itable_BB, 3 },
+ /* 0xbc */ { itable_BC, 3 },
+ /* 0xbd */ { itable_BD, 3 },
+ /* 0xbe */ { itable_BE, 3 },
+ /* 0xbf */ { itable_BF, 3 },
+ /* 0xc0 */ { itable_C0, 7 },
+ /* 0xc1 */ { itable_C1, 21 },
+ /* 0xc2 */ { itable_C2, 8 },
+ /* 0xc3 */ { itable_C3, 8 },
+ /* 0xc4 */ { itable_C4, 2 },
+ /* 0xc5 */ { itable_C5, 2 },
+ /* 0xc6 */ { itable_C6, 4 },
+ /* 0xc7 */ { itable_C7, 10 },
+ /* 0xc8 */ { itable_C8, 1 },
+ /* 0xc9 */ { itable_C9, 1 },
+ /* 0xca */ { itable_CA, 4 },
+ /* 0xcb */ { itable_CB, 4 },
+ /* 0xcc */ { itable_CC, 1 },
+ /* 0xcd */ { itable_CD, 1 },
+ /* 0xce */ { itable_CE, 1 },
+ /* 0xcf */ { itable_CF, 4 },
+ /* 0xd0 */ { itable_D0, 7 },
+ /* 0xd1 */ { itable_D1, 21 },
+ /* 0xd2 */ { itable_D2, 7 },
+ /* 0xd3 */ { itable_D3, 21 },
+ /* 0xd4 */ { itable_D4, 2 },
+ /* 0xd5 */ { itable_D5, 2 },
+ /* 0xd6 */ { itable_D6, 1 },
+ /* 0xd7 */ { itable_D7, 2 },
+ /* 0xd8 */ { itable_D8, 24 },
+ /* 0xd9 */ { itable_D9, 41 },
+ /* 0xda */ { itable_DA, 17 },
+ /* 0xdb */ { itable_DB, 27 },
+ /* 0xdc */ { itable_DC, 20 },
+ /* 0xdd */ { itable_DD, 17 },
+ /* 0xde */ { itable_DE, 21 },
+ /* 0xdf */ { itable_DF, 18 },
+ /* 0xe0 */ { itable_E0, 8 },
+ /* 0xe1 */ { itable_E1, 8 },
+ /* 0xe2 */ { itable_E2, 4 },
+ /* 0xe3 */ { itable_E3, 3 },
+ /* 0xe4 */ { itable_E4, 1 },
+ /* 0xe5 */ { itable_E5, 2 },
+ /* 0xe6 */ { itable_E6, 1 },
+ /* 0xe7 */ { itable_E7, 2 },
+ /* 0xe8 */ { itable_E8, 4 },
+ /* 0xe9 */ { itable_E9, 4 },
+ /* 0xea */ { itable_EA, 5 },
+ /* 0xeb */ { itable_EB, 1 },
+ /* 0xec */ { itable_EC, 1 },
+ /* 0xed */ { itable_ED, 2 },
+ /* 0xee */ { itable_EE, 1 },
+ /* 0xef */ { itable_EF, 2 },
+ /* 0xf0 */ { NULL, 0 },
+ /* 0xf1 */ { itable_F1, 2 },
+ /* 0xf2 */ { NULL, 0 },
+ /* 0xf3 */ { NULL, 0 },
+ /* 0xf4 */ { itable_F4, 1 },
+ /* 0xf5 */ { itable_F5, 1 },
+ /* 0xf6 */ { itable_F6, 8 },
+ /* 0xf7 */ { itable_F7, 23 },
+ /* 0xf8 */ { itable_F8, 1 },
+ /* 0xf9 */ { itable_F9, 1 },
+ /* 0xfa */ { itable_FA, 1 },
+ /* 0xfb */ { itable_FB, 1 },
+ /* 0xfc */ { itable_FC, 1 },
+ /* 0xfd */ { itable_FD, 1 },
+ /* 0xfe */ { itable_FE, 2 },
+ /* 0xff */ { itable_FF, 27 },
+};
+
+const struct disasm_index * const itable_vex[NASM_VEX_CLASSES][32][4] =
+{
+ {
+ { NULL, NULL, NULL, NULL, },
+ { itable_vex010, itable_vex011, itable_vex012, itable_vex013, },
+ { itable_vex020, itable_vex021, itable_vex022, itable_vex023, },
+ { NULL, itable_vex031, NULL, itable_vex033, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ },
+ {
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { itable_xop080, NULL, NULL, NULL, },
+ { itable_xop090, NULL, NULL, NULL, },
+ { itable_xop0A0, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ },
+ {
+ { NULL, NULL, NULL, NULL, },
+ { itable_evex010,itable_evex011,itable_evex012,itable_evex013,},
+ { NULL, itable_evex021,itable_evex022,itable_evex023,},
+ { itable_evex030,itable_evex031,itable_evex032,NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { itable_evex050,itable_evex051,itable_evex052,itable_evex053,},
+ { itable_evex060,itable_evex061,itable_evex062,itable_evex063,},
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ { NULL, NULL, NULL, NULL, },
+ },
+};
diff --git a/vere/ext/nasm/x86/insnsi.h b/vere/ext/nasm/x86/insnsi.h
new file mode 100644
index 0000000..65188c0
--- /dev/null
+++ b/vere/ext/nasm/x86/insnsi.h
@@ -0,0 +1,2265 @@
+/* This file is auto-generated from insns.dat by insns.pl - don't edit it */
+
+/* This file in included by nasm.h */
+
+/* Instruction names */
+
+#ifndef NASM_INSNSI_H
+#define NASM_INSNSI_H 1
+
+enum opcode {
+ I_DB,
+ I_DW,
+ I_DD,
+ I_DQ,
+ I_DT,
+ I_DO,
+ I_DY,
+ I_DZ,
+ I_RESB,
+ I_RESW,
+ I_RESD,
+ I_RESQ,
+ I_REST,
+ I_RESO,
+ I_RESY,
+ I_RESZ,
+ I_INCBIN,
+ I_AAA,
+ I_AAD,
+ I_AAM,
+ I_AAS,
+ I_ADC,
+ I_ADD,
+ I_AND,
+ I_ARPL,
+ I_BB0_RESET,
+ I_BB1_RESET,
+ I_BOUND,
+ I_BSF,
+ I_BSR,
+ I_BSWAP,
+ I_BT,
+ I_BTC,
+ I_BTR,
+ I_BTS,
+ I_CALL,
+ I_CBW,
+ I_CDQ,
+ I_CDQE,
+ I_CLC,
+ I_CLD,
+ I_CLI,
+ I_CLTS,
+ I_CMC,
+ I_CMP,
+ I_CMPSB,
+ I_CMPSD,
+ I_CMPSQ,
+ I_CMPSW,
+ I_CMPXCHG,
+ I_CMPXCHG486,
+ I_CMPXCHG8B,
+ I_CMPXCHG16B,
+ I_CPUID,
+ I_CPU_READ,
+ I_CPU_WRITE,
+ I_CQO,
+ I_CWD,
+ I_CWDE,
+ I_DAA,
+ I_DAS,
+ I_DEC,
+ I_DIV,
+ I_DMINT,
+ I_EMMS,
+ I_ENTER,
+ I_EQU,
+ I_F2XM1,
+ I_FABS,
+ I_FADD,
+ I_FADDP,
+ I_FBLD,
+ I_FBSTP,
+ I_FCHS,
+ I_FCLEX,
+ I_FCMOVB,
+ I_FCMOVBE,
+ I_FCMOVE,
+ I_FCMOVNB,
+ I_FCMOVNBE,
+ I_FCMOVNE,
+ I_FCMOVNU,
+ I_FCMOVU,
+ I_FCOM,
+ I_FCOMI,
+ I_FCOMIP,
+ I_FCOMP,
+ I_FCOMPP,
+ I_FCOS,
+ I_FDECSTP,
+ I_FDISI,
+ I_FDIV,
+ I_FDIVP,
+ I_FDIVR,
+ I_FDIVRP,
+ I_FEMMS,
+ I_FENI,
+ I_FFREE,
+ I_FFREEP,
+ I_FIADD,
+ I_FICOM,
+ I_FICOMP,
+ I_FIDIV,
+ I_FIDIVR,
+ I_FILD,
+ I_FIMUL,
+ I_FINCSTP,
+ I_FINIT,
+ I_FIST,
+ I_FISTP,
+ I_FISTTP,
+ I_FISUB,
+ I_FISUBR,
+ I_FLD,
+ I_FLD1,
+ I_FLDCW,
+ I_FLDENV,
+ I_FLDL2E,
+ I_FLDL2T,
+ I_FLDLG2,
+ I_FLDLN2,
+ I_FLDPI,
+ I_FLDZ,
+ I_FMUL,
+ I_FMULP,
+ I_FNCLEX,
+ I_FNDISI,
+ I_FNENI,
+ I_FNINIT,
+ I_FNOP,
+ I_FNSAVE,
+ I_FNSTCW,
+ I_FNSTENV,
+ I_FNSTSW,
+ I_FPATAN,
+ I_FPREM,
+ I_FPREM1,
+ I_FPTAN,
+ I_FRNDINT,
+ I_FRSTOR,
+ I_FSAVE,
+ I_FSCALE,
+ I_FSETPM,
+ I_FSIN,
+ I_FSINCOS,
+ I_FSQRT,
+ I_FST,
+ I_FSTCW,
+ I_FSTENV,
+ I_FSTP,
+ I_FSTSW,
+ I_FSUB,
+ I_FSUBP,
+ I_FSUBR,
+ I_FSUBRP,
+ I_FTST,
+ I_FUCOM,
+ I_FUCOMI,
+ I_FUCOMIP,
+ I_FUCOMP,
+ I_FUCOMPP,
+ I_FXAM,
+ I_FXCH,
+ I_FXTRACT,
+ I_FYL2X,
+ I_FYL2XP1,
+ I_HLT,
+ I_IBTS,
+ I_ICEBP,
+ I_IDIV,
+ I_IMUL,
+ I_IN,
+ I_INC,
+ I_INSB,
+ I_INSD,
+ I_INSW,
+ I_INT,
+ I_INT01,
+ I_INT1,
+ I_INT03,
+ I_INT3,
+ I_INTO,
+ I_INVD,
+ I_INVPCID,
+ I_INVLPG,
+ I_INVLPGA,
+ I_IRET,
+ I_IRETD,
+ I_IRETQ,
+ I_IRETW,
+ I_JCXZ,
+ I_JECXZ,
+ I_JRCXZ,
+ I_JMP,
+ I_JMPE,
+ I_LAHF,
+ I_LAR,
+ I_LDS,
+ I_LEA,
+ I_LEAVE,
+ I_LES,
+ I_LFENCE,
+ I_LFS,
+ I_LGDT,
+ I_LGS,
+ I_LIDT,
+ I_LLDT,
+ I_LMSW,
+ I_LOADALL,
+ I_LOADALL286,
+ I_LODSB,
+ I_LODSD,
+ I_LODSQ,
+ I_LODSW,
+ I_LOOP,
+ I_LOOPE,
+ I_LOOPNE,
+ I_LOOPNZ,
+ I_LOOPZ,
+ I_LSL,
+ I_LSS,
+ I_LTR,
+ I_MFENCE,
+ I_MONITOR,
+ I_MONITORX,
+ I_MOV,
+ I_MOVD,
+ I_MOVQ,
+ I_MOVSB,
+ I_MOVSD,
+ I_MOVSQ,
+ I_MOVSW,
+ I_MOVSX,
+ I_MOVSXD,
+ I_MOVZX,
+ I_MUL,
+ I_MWAIT,
+ I_MWAITX,
+ I_NEG,
+ I_NOP,
+ I_NOT,
+ I_OR,
+ I_OUT,
+ I_OUTSB,
+ I_OUTSD,
+ I_OUTSW,
+ I_PACKSSDW,
+ I_PACKSSWB,
+ I_PACKUSWB,
+ I_PADDB,
+ I_PADDD,
+ I_PADDSB,
+ I_PADDSIW,
+ I_PADDSW,
+ I_PADDUSB,
+ I_PADDUSW,
+ I_PADDW,
+ I_PAND,
+ I_PANDN,
+ I_PAUSE,
+ I_PAVEB,
+ I_PAVGUSB,
+ I_PCMPEQB,
+ I_PCMPEQD,
+ I_PCMPEQW,
+ I_PCMPGTB,
+ I_PCMPGTD,
+ I_PCMPGTW,
+ I_PDISTIB,
+ I_PF2ID,
+ I_PFACC,
+ I_PFADD,
+ I_PFCMPEQ,
+ I_PFCMPGE,
+ I_PFCMPGT,
+ I_PFMAX,
+ I_PFMIN,
+ I_PFMUL,
+ I_PFRCP,
+ I_PFRCPIT1,
+ I_PFRCPIT2,
+ I_PFRSQIT1,
+ I_PFRSQRT,
+ I_PFSUB,
+ I_PFSUBR,
+ I_PI2FD,
+ I_PMACHRIW,
+ I_PMADDWD,
+ I_PMAGW,
+ I_PMULHRIW,
+ I_PMULHRWA,
+ I_PMULHRWC,
+ I_PMULHW,
+ I_PMULLW,
+ I_PMVGEZB,
+ I_PMVLZB,
+ I_PMVNZB,
+ I_PMVZB,
+ I_POP,
+ I_POPA,
+ I_POPAD,
+ I_POPAW,
+ I_POPF,
+ I_POPFD,
+ I_POPFQ,
+ I_POPFW,
+ I_POR,
+ I_PREFETCH,
+ I_PREFETCHW,
+ I_PSLLD,
+ I_PSLLQ,
+ I_PSLLW,
+ I_PSRAD,
+ I_PSRAW,
+ I_PSRLD,
+ I_PSRLQ,
+ I_PSRLW,
+ I_PSUBB,
+ I_PSUBD,
+ I_PSUBSB,
+ I_PSUBSIW,
+ I_PSUBSW,
+ I_PSUBUSB,
+ I_PSUBUSW,
+ I_PSUBW,
+ I_PUNPCKHBW,
+ I_PUNPCKHDQ,
+ I_PUNPCKHWD,
+ I_PUNPCKLBW,
+ I_PUNPCKLDQ,
+ I_PUNPCKLWD,
+ I_PUSH,
+ I_PUSHA,
+ I_PUSHAD,
+ I_PUSHAW,
+ I_PUSHF,
+ I_PUSHFD,
+ I_PUSHFQ,
+ I_PUSHFW,
+ I_PXOR,
+ I_RCL,
+ I_RCR,
+ I_RDSHR,
+ I_RDMSR,
+ I_RDPMC,
+ I_RDTSC,
+ I_RDTSCP,
+ I_RET,
+ I_RETF,
+ I_RETN,
+ I_RETW,
+ I_RETFW,
+ I_RETNW,
+ I_RETD,
+ I_RETFD,
+ I_RETND,
+ I_RETQ,
+ I_RETFQ,
+ I_RETNQ,
+ I_ROL,
+ I_ROR,
+ I_RDM,
+ I_RSDC,
+ I_RSLDT,
+ I_RSM,
+ I_RSTS,
+ I_SAHF,
+ I_SAL,
+ I_SALC,
+ I_SAR,
+ I_SBB,
+ I_SCASB,
+ I_SCASD,
+ I_SCASQ,
+ I_SCASW,
+ I_SFENCE,
+ I_SGDT,
+ I_SHL,
+ I_SHLD,
+ I_SHR,
+ I_SHRD,
+ I_SIDT,
+ I_SLDT,
+ I_SKINIT,
+ I_SMI,
+ I_SMINT,
+ I_SMINTOLD,
+ I_SMSW,
+ I_STC,
+ I_STD,
+ I_STI,
+ I_STOSB,
+ I_STOSD,
+ I_STOSQ,
+ I_STOSW,
+ I_STR,
+ I_SUB,
+ I_SVDC,
+ I_SVLDT,
+ I_SVTS,
+ I_SWAPGS,
+ I_SYSCALL,
+ I_SYSENTER,
+ I_SYSEXIT,
+ I_SYSRET,
+ I_TEST,
+ I_UD0,
+ I_UD1,
+ I_UD2B,
+ I_UD2,
+ I_UD2A,
+ I_UMOV,
+ I_VERR,
+ I_VERW,
+ I_FWAIT,
+ I_WBINVD,
+ I_WRSHR,
+ I_WRMSR,
+ I_XADD,
+ I_XBTS,
+ I_XCHG,
+ I_XLATB,
+ I_XLAT,
+ I_XOR,
+ I_CMOVA,
+ I_CMOVAE,
+ I_CMOVB,
+ I_CMOVBE,
+ I_CMOVC,
+ I_CMOVE,
+ I_CMOVG,
+ I_CMOVGE,
+ I_CMOVL,
+ I_CMOVLE,
+ I_CMOVNA,
+ I_CMOVNAE,
+ I_CMOVNB,
+ I_CMOVNBE,
+ I_CMOVNC,
+ I_CMOVNE,
+ I_CMOVNG,
+ I_CMOVNGE,
+ I_CMOVNL,
+ I_CMOVNLE,
+ I_CMOVNO,
+ I_CMOVNP,
+ I_CMOVNS,
+ I_CMOVNZ,
+ I_CMOVO,
+ I_CMOVP,
+ I_CMOVPE,
+ I_CMOVPO,
+ I_CMOVS,
+ I_CMOVZ,
+ I_JA,
+ I_JAE,
+ I_JB,
+ I_JBE,
+ I_JC,
+ I_JE,
+ I_JG,
+ I_JGE,
+ I_JL,
+ I_JLE,
+ I_JNA,
+ I_JNAE,
+ I_JNB,
+ I_JNBE,
+ I_JNC,
+ I_JNE,
+ I_JNG,
+ I_JNGE,
+ I_JNL,
+ I_JNLE,
+ I_JNO,
+ I_JNP,
+ I_JNS,
+ I_JNZ,
+ I_JO,
+ I_JP,
+ I_JPE,
+ I_JPO,
+ I_JS,
+ I_JZ,
+ I_SETA,
+ I_SETAE,
+ I_SETB,
+ I_SETBE,
+ I_SETC,
+ I_SETE,
+ I_SETG,
+ I_SETGE,
+ I_SETL,
+ I_SETLE,
+ I_SETNA,
+ I_SETNAE,
+ I_SETNB,
+ I_SETNBE,
+ I_SETNC,
+ I_SETNE,
+ I_SETNG,
+ I_SETNGE,
+ I_SETNL,
+ I_SETNLE,
+ I_SETNO,
+ I_SETNP,
+ I_SETNS,
+ I_SETNZ,
+ I_SETO,
+ I_SETP,
+ I_SETPE,
+ I_SETPO,
+ I_SETS,
+ I_SETZ,
+ I_ADDPS,
+ I_ADDSS,
+ I_ANDNPS,
+ I_ANDPS,
+ I_CMPEQPS,
+ I_CMPEQSS,
+ I_CMPLEPS,
+ I_CMPLESS,
+ I_CMPLTPS,
+ I_CMPLTSS,
+ I_CMPNEQPS,
+ I_CMPNEQSS,
+ I_CMPNLEPS,
+ I_CMPNLESS,
+ I_CMPNLTPS,
+ I_CMPNLTSS,
+ I_CMPORDPS,
+ I_CMPORDSS,
+ I_CMPUNORDPS,
+ I_CMPUNORDSS,
+ I_CMPPS,
+ I_CMPSS,
+ I_COMISS,
+ I_CVTPI2PS,
+ I_CVTPS2PI,
+ I_CVTSI2SS,
+ I_CVTSS2SI,
+ I_CVTTPS2PI,
+ I_CVTTSS2SI,
+ I_DIVPS,
+ I_DIVSS,
+ I_LDMXCSR,
+ I_MAXPS,
+ I_MAXSS,
+ I_MINPS,
+ I_MINSS,
+ I_MOVAPS,
+ I_MOVHPS,
+ I_MOVLHPS,
+ I_MOVLPS,
+ I_MOVHLPS,
+ I_MOVMSKPS,
+ I_MOVNTPS,
+ I_MOVSS,
+ I_MOVUPS,
+ I_MULPS,
+ I_MULSS,
+ I_ORPS,
+ I_RCPPS,
+ I_RCPSS,
+ I_RSQRTPS,
+ I_RSQRTSS,
+ I_SHUFPS,
+ I_SQRTPS,
+ I_SQRTSS,
+ I_STMXCSR,
+ I_SUBPS,
+ I_SUBSS,
+ I_UCOMISS,
+ I_UNPCKHPS,
+ I_UNPCKLPS,
+ I_XORPS,
+ I_FXRSTOR,
+ I_FXRSTOR64,
+ I_FXSAVE,
+ I_FXSAVE64,
+ I_XGETBV,
+ I_XSETBV,
+ I_XSAVE,
+ I_XSAVE64,
+ I_XSAVEC,
+ I_XSAVEC64,
+ I_XSAVEOPT,
+ I_XSAVEOPT64,
+ I_XSAVES,
+ I_XSAVES64,
+ I_XRSTOR,
+ I_XRSTOR64,
+ I_XRSTORS,
+ I_XRSTORS64,
+ I_PREFETCHNTA,
+ I_PREFETCHT0,
+ I_PREFETCHT1,
+ I_PREFETCHT2,
+ I_PREFETCHIT0,
+ I_PREFETCHIT1,
+ I_MASKMOVQ,
+ I_MOVNTQ,
+ I_PAVGB,
+ I_PAVGW,
+ I_PEXTRW,
+ I_PINSRW,
+ I_PMAXSW,
+ I_PMAXUB,
+ I_PMINSW,
+ I_PMINUB,
+ I_PMOVMSKB,
+ I_PMULHUW,
+ I_PSADBW,
+ I_PSHUFW,
+ I_PF2IW,
+ I_PFNACC,
+ I_PFPNACC,
+ I_PI2FW,
+ I_PSWAPD,
+ I_MASKMOVDQU,
+ I_CLFLUSH,
+ I_MOVNTDQ,
+ I_MOVNTI,
+ I_MOVNTPD,
+ I_MOVDQA,
+ I_MOVDQU,
+ I_MOVDQ2Q,
+ I_MOVQ2DQ,
+ I_PADDQ,
+ I_PMULUDQ,
+ I_PSHUFD,
+ I_PSHUFHW,
+ I_PSHUFLW,
+ I_PSLLDQ,
+ I_PSRLDQ,
+ I_PSUBQ,
+ I_PUNPCKHQDQ,
+ I_PUNPCKLQDQ,
+ I_ADDPD,
+ I_ADDSD,
+ I_ANDNPD,
+ I_ANDPD,
+ I_CMPEQPD,
+ I_CMPEQSD,
+ I_CMPLEPD,
+ I_CMPLESD,
+ I_CMPLTPD,
+ I_CMPLTSD,
+ I_CMPNEQPD,
+ I_CMPNEQSD,
+ I_CMPNLEPD,
+ I_CMPNLESD,
+ I_CMPNLTPD,
+ I_CMPNLTSD,
+ I_CMPORDPD,
+ I_CMPORDSD,
+ I_CMPUNORDPD,
+ I_CMPUNORDSD,
+ I_CMPPD,
+ I_COMISD,
+ I_CVTDQ2PD,
+ I_CVTDQ2PS,
+ I_CVTPD2DQ,
+ I_CVTPD2PI,
+ I_CVTPD2PS,
+ I_CVTPI2PD,
+ I_CVTPS2DQ,
+ I_CVTPS2PD,
+ I_CVTSD2SI,
+ I_CVTSD2SS,
+ I_CVTSI2SD,
+ I_CVTSS2SD,
+ I_CVTTPD2PI,
+ I_CVTTPD2DQ,
+ I_CVTTPS2DQ,
+ I_CVTTSD2SI,
+ I_DIVPD,
+ I_DIVSD,
+ I_MAXPD,
+ I_MAXSD,
+ I_MINPD,
+ I_MINSD,
+ I_MOVAPD,
+ I_MOVHPD,
+ I_MOVLPD,
+ I_MOVMSKPD,
+ I_MOVUPD,
+ I_MULPD,
+ I_MULSD,
+ I_ORPD,
+ I_SHUFPD,
+ I_SQRTPD,
+ I_SQRTSD,
+ I_SUBPD,
+ I_SUBSD,
+ I_UCOMISD,
+ I_UNPCKHPD,
+ I_UNPCKLPD,
+ I_XORPD,
+ I_ADDSUBPD,
+ I_ADDSUBPS,
+ I_HADDPD,
+ I_HADDPS,
+ I_HSUBPD,
+ I_HSUBPS,
+ I_LDDQU,
+ I_MOVDDUP,
+ I_MOVSHDUP,
+ I_MOVSLDUP,
+ I_CLGI,
+ I_STGI,
+ I_VMCALL,
+ I_VMCLEAR,
+ I_VMFUNC,
+ I_VMLAUNCH,
+ I_VMLOAD,
+ I_VMMCALL,
+ I_VMPTRLD,
+ I_VMPTRST,
+ I_VMREAD,
+ I_VMRESUME,
+ I_VMRUN,
+ I_VMSAVE,
+ I_VMWRITE,
+ I_VMXOFF,
+ I_VMXON,
+ I_INVEPT,
+ I_INVVPID,
+ I_PVALIDATE,
+ I_RMPADJUST,
+ I_VMGEXIT,
+ I_PABSB,
+ I_PABSW,
+ I_PABSD,
+ I_PALIGNR,
+ I_PHADDW,
+ I_PHADDD,
+ I_PHADDSW,
+ I_PHSUBW,
+ I_PHSUBD,
+ I_PHSUBSW,
+ I_PMADDUBSW,
+ I_PMULHRSW,
+ I_PSHUFB,
+ I_PSIGNB,
+ I_PSIGNW,
+ I_PSIGND,
+ I_EXTRQ,
+ I_INSERTQ,
+ I_MOVNTSD,
+ I_MOVNTSS,
+ I_LZCNT,
+ I_BLENDPD,
+ I_BLENDPS,
+ I_BLENDVPD,
+ I_BLENDVPS,
+ I_DPPD,
+ I_DPPS,
+ I_EXTRACTPS,
+ I_INSERTPS,
+ I_MOVNTDQA,
+ I_MPSADBW,
+ I_PACKUSDW,
+ I_PBLENDVB,
+ I_PBLENDW,
+ I_PCMPEQQ,
+ I_PEXTRB,
+ I_PEXTRD,
+ I_PEXTRQ,
+ I_PHMINPOSUW,
+ I_PINSRB,
+ I_PINSRD,
+ I_PINSRQ,
+ I_PMAXSB,
+ I_PMAXSD,
+ I_PMAXUD,
+ I_PMAXUW,
+ I_PMINSB,
+ I_PMINSD,
+ I_PMINUD,
+ I_PMINUW,
+ I_PMOVSXBW,
+ I_PMOVSXBD,
+ I_PMOVSXBQ,
+ I_PMOVSXWD,
+ I_PMOVSXWQ,
+ I_PMOVSXDQ,
+ I_PMOVZXBW,
+ I_PMOVZXBD,
+ I_PMOVZXBQ,
+ I_PMOVZXWD,
+ I_PMOVZXWQ,
+ I_PMOVZXDQ,
+ I_PMULDQ,
+ I_PMULLD,
+ I_PTEST,
+ I_ROUNDPD,
+ I_ROUNDPS,
+ I_ROUNDSD,
+ I_ROUNDSS,
+ I_CRC32,
+ I_PCMPESTRI,
+ I_PCMPESTRM,
+ I_PCMPISTRI,
+ I_PCMPISTRM,
+ I_PCMPGTQ,
+ I_POPCNT,
+ I_GETSEC,
+ I_PFRCPV,
+ I_PFRSQRTV,
+ I_MOVBE,
+ I_AESENC,
+ I_AESENCLAST,
+ I_AESDEC,
+ I_AESDECLAST,
+ I_AESIMC,
+ I_AESKEYGENASSIST,
+ I_VAESENC,
+ I_VAESENCLAST,
+ I_VAESDEC,
+ I_VAESDECLAST,
+ I_VAESIMC,
+ I_VAESKEYGENASSIST,
+ I_VADDPD,
+ I_VADDPS,
+ I_VADDSD,
+ I_VADDSS,
+ I_VADDSUBPD,
+ I_VADDSUBPS,
+ I_VANDPD,
+ I_VANDPS,
+ I_VANDNPD,
+ I_VANDNPS,
+ I_VBLENDPD,
+ I_VBLENDPS,
+ I_VBLENDVPD,
+ I_VBLENDVPS,
+ I_VBROADCASTSS,
+ I_VBROADCASTSD,
+ I_VBROADCASTF128,
+ I_VCMPEQ_OSPD,
+ I_VCMPEQPD,
+ I_VCMPLT_OSPD,
+ I_VCMPLTPD,
+ I_VCMPLE_OSPD,
+ I_VCMPLEPD,
+ I_VCMPUNORD_QPD,
+ I_VCMPUNORDPD,
+ I_VCMPNEQ_UQPD,
+ I_VCMPNEQPD,
+ I_VCMPNLT_USPD,
+ I_VCMPNLTPD,
+ I_VCMPNLE_USPD,
+ I_VCMPNLEPD,
+ I_VCMPORD_QPD,
+ I_VCMPORDPD,
+ I_VCMPEQ_UQPD,
+ I_VCMPNGE_USPD,
+ I_VCMPNGEPD,
+ I_VCMPNGT_USPD,
+ I_VCMPNGTPD,
+ I_VCMPFALSE_OQPD,
+ I_VCMPFALSEPD,
+ I_VCMPNEQ_OQPD,
+ I_VCMPGE_OSPD,
+ I_VCMPGEPD,
+ I_VCMPGT_OSPD,
+ I_VCMPGTPD,
+ I_VCMPTRUE_UQPD,
+ I_VCMPTRUEPD,
+ I_VCMPLT_OQPD,
+ I_VCMPLE_OQPD,
+ I_VCMPUNORD_SPD,
+ I_VCMPNEQ_USPD,
+ I_VCMPNLT_UQPD,
+ I_VCMPNLE_UQPD,
+ I_VCMPORD_SPD,
+ I_VCMPEQ_USPD,
+ I_VCMPNGE_UQPD,
+ I_VCMPNGT_UQPD,
+ I_VCMPFALSE_OSPD,
+ I_VCMPNEQ_OSPD,
+ I_VCMPGE_OQPD,
+ I_VCMPGT_OQPD,
+ I_VCMPTRUE_USPD,
+ I_VCMPPD,
+ I_VCMPEQ_OSPS,
+ I_VCMPEQPS,
+ I_VCMPLT_OSPS,
+ I_VCMPLTPS,
+ I_VCMPLE_OSPS,
+ I_VCMPLEPS,
+ I_VCMPUNORD_QPS,
+ I_VCMPUNORDPS,
+ I_VCMPNEQ_UQPS,
+ I_VCMPNEQPS,
+ I_VCMPNLT_USPS,
+ I_VCMPNLTPS,
+ I_VCMPNLE_USPS,
+ I_VCMPNLEPS,
+ I_VCMPORD_QPS,
+ I_VCMPORDPS,
+ I_VCMPEQ_UQPS,
+ I_VCMPNGE_USPS,
+ I_VCMPNGEPS,
+ I_VCMPNGT_USPS,
+ I_VCMPNGTPS,
+ I_VCMPFALSE_OQPS,
+ I_VCMPFALSEPS,
+ I_VCMPNEQ_OQPS,
+ I_VCMPGE_OSPS,
+ I_VCMPGEPS,
+ I_VCMPGT_OSPS,
+ I_VCMPGTPS,
+ I_VCMPTRUE_UQPS,
+ I_VCMPTRUEPS,
+ I_VCMPLT_OQPS,
+ I_VCMPLE_OQPS,
+ I_VCMPUNORD_SPS,
+ I_VCMPNEQ_USPS,
+ I_VCMPNLT_UQPS,
+ I_VCMPNLE_UQPS,
+ I_VCMPORD_SPS,
+ I_VCMPEQ_USPS,
+ I_VCMPNGE_UQPS,
+ I_VCMPNGT_UQPS,
+ I_VCMPFALSE_OSPS,
+ I_VCMPNEQ_OSPS,
+ I_VCMPGE_OQPS,
+ I_VCMPGT_OQPS,
+ I_VCMPTRUE_USPS,
+ I_VCMPPS,
+ I_VCMPEQ_OSSD,
+ I_VCMPEQSD,
+ I_VCMPLT_OSSD,
+ I_VCMPLTSD,
+ I_VCMPLE_OSSD,
+ I_VCMPLESD,
+ I_VCMPUNORD_QSD,
+ I_VCMPUNORDSD,
+ I_VCMPNEQ_UQSD,
+ I_VCMPNEQSD,
+ I_VCMPNLT_USSD,
+ I_VCMPNLTSD,
+ I_VCMPNLE_USSD,
+ I_VCMPNLESD,
+ I_VCMPORD_QSD,
+ I_VCMPORDSD,
+ I_VCMPEQ_UQSD,
+ I_VCMPNGE_USSD,
+ I_VCMPNGESD,
+ I_VCMPNGT_USSD,
+ I_VCMPNGTSD,
+ I_VCMPFALSE_OQSD,
+ I_VCMPFALSESD,
+ I_VCMPNEQ_OQSD,
+ I_VCMPGE_OSSD,
+ I_VCMPGESD,
+ I_VCMPGT_OSSD,
+ I_VCMPGTSD,
+ I_VCMPTRUE_UQSD,
+ I_VCMPTRUESD,
+ I_VCMPLT_OQSD,
+ I_VCMPLE_OQSD,
+ I_VCMPUNORD_SSD,
+ I_VCMPNEQ_USSD,
+ I_VCMPNLT_UQSD,
+ I_VCMPNLE_UQSD,
+ I_VCMPORD_SSD,
+ I_VCMPEQ_USSD,
+ I_VCMPNGE_UQSD,
+ I_VCMPNGT_UQSD,
+ I_VCMPFALSE_OSSD,
+ I_VCMPNEQ_OSSD,
+ I_VCMPGE_OQSD,
+ I_VCMPGT_OQSD,
+ I_VCMPTRUE_USSD,
+ I_VCMPSD,
+ I_VCMPEQ_OSSS,
+ I_VCMPEQSS,
+ I_VCMPLT_OSSS,
+ I_VCMPLTSS,
+ I_VCMPLE_OSSS,
+ I_VCMPLESS,
+ I_VCMPUNORD_QSS,
+ I_VCMPUNORDSS,
+ I_VCMPNEQ_UQSS,
+ I_VCMPNEQSS,
+ I_VCMPNLT_USSS,
+ I_VCMPNLTSS,
+ I_VCMPNLE_USSS,
+ I_VCMPNLESS,
+ I_VCMPORD_QSS,
+ I_VCMPORDSS,
+ I_VCMPEQ_UQSS,
+ I_VCMPNGE_USSS,
+ I_VCMPNGESS,
+ I_VCMPNGT_USSS,
+ I_VCMPNGTSS,
+ I_VCMPFALSE_OQSS,
+ I_VCMPFALSESS,
+ I_VCMPNEQ_OQSS,
+ I_VCMPGE_OSSS,
+ I_VCMPGESS,
+ I_VCMPGT_OSSS,
+ I_VCMPGTSS,
+ I_VCMPTRUE_UQSS,
+ I_VCMPTRUESS,
+ I_VCMPLT_OQSS,
+ I_VCMPLE_OQSS,
+ I_VCMPUNORD_SSS,
+ I_VCMPNEQ_USSS,
+ I_VCMPNLT_UQSS,
+ I_VCMPNLE_UQSS,
+ I_VCMPORD_SSS,
+ I_VCMPEQ_USSS,
+ I_VCMPNGE_UQSS,
+ I_VCMPNGT_UQSS,
+ I_VCMPFALSE_OSSS,
+ I_VCMPNEQ_OSSS,
+ I_VCMPGE_OQSS,
+ I_VCMPGT_OQSS,
+ I_VCMPTRUE_USSS,
+ I_VCMPSS,
+ I_VCOMISD,
+ I_VCOMISS,
+ I_VCVTDQ2PD,
+ I_VCVTDQ2PS,
+ I_VCVTPD2DQ,
+ I_VCVTPD2PS,
+ I_VCVTPS2DQ,
+ I_VCVTPS2PD,
+ I_VCVTSD2SI,
+ I_VCVTSD2SS,
+ I_VCVTSI2SD,
+ I_VCVTSI2SS,
+ I_VCVTSS2SD,
+ I_VCVTSS2SI,
+ I_VCVTTPD2DQ,
+ I_VCVTTPS2DQ,
+ I_VCVTTSD2SI,
+ I_VCVTTSS2SI,
+ I_VDIVPD,
+ I_VDIVPS,
+ I_VDIVSD,
+ I_VDIVSS,
+ I_VDPPD,
+ I_VDPPS,
+ I_VEXTRACTF128,
+ I_VEXTRACTPS,
+ I_VHADDPD,
+ I_VHADDPS,
+ I_VHSUBPD,
+ I_VHSUBPS,
+ I_VINSERTF128,
+ I_VINSERTPS,
+ I_VLDDQU,
+ I_VLDQQU,
+ I_VLDMXCSR,
+ I_VMASKMOVDQU,
+ I_VMASKMOVPS,
+ I_VMASKMOVPD,
+ I_VMAXPD,
+ I_VMAXPS,
+ I_VMAXSD,
+ I_VMAXSS,
+ I_VMINPD,
+ I_VMINPS,
+ I_VMINSD,
+ I_VMINSS,
+ I_VMOVAPD,
+ I_VMOVAPS,
+ I_VMOVD,
+ I_VMOVQ,
+ I_VMOVDDUP,
+ I_VMOVDQA,
+ I_VMOVQQA,
+ I_VMOVDQU,
+ I_VMOVQQU,
+ I_VMOVHLPS,
+ I_VMOVHPD,
+ I_VMOVHPS,
+ I_VMOVLHPS,
+ I_VMOVLPD,
+ I_VMOVLPS,
+ I_VMOVMSKPD,
+ I_VMOVMSKPS,
+ I_VMOVNTDQ,
+ I_VMOVNTQQ,
+ I_VMOVNTDQA,
+ I_VMOVNTPD,
+ I_VMOVNTPS,
+ I_VMOVSD,
+ I_VMOVSHDUP,
+ I_VMOVSLDUP,
+ I_VMOVSS,
+ I_VMOVUPD,
+ I_VMOVUPS,
+ I_VMPSADBW,
+ I_VMULPD,
+ I_VMULPS,
+ I_VMULSD,
+ I_VMULSS,
+ I_VORPD,
+ I_VORPS,
+ I_VPABSB,
+ I_VPABSW,
+ I_VPABSD,
+ I_VPACKSSWB,
+ I_VPACKSSDW,
+ I_VPACKUSWB,
+ I_VPACKUSDW,
+ I_VPADDB,
+ I_VPADDW,
+ I_VPADDD,
+ I_VPADDQ,
+ I_VPADDSB,
+ I_VPADDSW,
+ I_VPADDUSB,
+ I_VPADDUSW,
+ I_VPALIGNR,
+ I_VPAND,
+ I_VPANDN,
+ I_VPAVGB,
+ I_VPAVGW,
+ I_VPBLENDVB,
+ I_VPBLENDW,
+ I_VPCMPESTRI,
+ I_VPCMPESTRM,
+ I_VPCMPISTRI,
+ I_VPCMPISTRM,
+ I_VPCMPEQB,
+ I_VPCMPEQW,
+ I_VPCMPEQD,
+ I_VPCMPEQQ,
+ I_VPCMPGTB,
+ I_VPCMPGTW,
+ I_VPCMPGTD,
+ I_VPCMPGTQ,
+ I_VPERMILPD,
+ I_VPERMILPS,
+ I_VPERM2F128,
+ I_VPEXTRB,
+ I_VPEXTRW,
+ I_VPEXTRD,
+ I_VPEXTRQ,
+ I_VPHADDW,
+ I_VPHADDD,
+ I_VPHADDSW,
+ I_VPHMINPOSUW,
+ I_VPHSUBW,
+ I_VPHSUBD,
+ I_VPHSUBSW,
+ I_VPINSRB,
+ I_VPINSRW,
+ I_VPINSRD,
+ I_VPINSRQ,
+ I_VPMADDWD,
+ I_VPMADDUBSW,
+ I_VPMAXSB,
+ I_VPMAXSW,
+ I_VPMAXSD,
+ I_VPMAXUB,
+ I_VPMAXUW,
+ I_VPMAXUD,
+ I_VPMINSB,
+ I_VPMINSW,
+ I_VPMINSD,
+ I_VPMINUB,
+ I_VPMINUW,
+ I_VPMINUD,
+ I_VPMOVMSKB,
+ I_VPMOVSXBW,
+ I_VPMOVSXBD,
+ I_VPMOVSXBQ,
+ I_VPMOVSXWD,
+ I_VPMOVSXWQ,
+ I_VPMOVSXDQ,
+ I_VPMOVZXBW,
+ I_VPMOVZXBD,
+ I_VPMOVZXBQ,
+ I_VPMOVZXWD,
+ I_VPMOVZXWQ,
+ I_VPMOVZXDQ,
+ I_VPMULHUW,
+ I_VPMULHRSW,
+ I_VPMULHW,
+ I_VPMULLW,
+ I_VPMULLD,
+ I_VPMULUDQ,
+ I_VPMULDQ,
+ I_VPOR,
+ I_VPSADBW,
+ I_VPSHUFB,
+ I_VPSHUFD,
+ I_VPSHUFHW,
+ I_VPSHUFLW,
+ I_VPSIGNB,
+ I_VPSIGNW,
+ I_VPSIGND,
+ I_VPSLLDQ,
+ I_VPSRLDQ,
+ I_VPSLLW,
+ I_VPSLLD,
+ I_VPSLLQ,
+ I_VPSRAW,
+ I_VPSRAD,
+ I_VPSRLW,
+ I_VPSRLD,
+ I_VPSRLQ,
+ I_VPTEST,
+ I_VPSUBB,
+ I_VPSUBW,
+ I_VPSUBD,
+ I_VPSUBQ,
+ I_VPSUBSB,
+ I_VPSUBSW,
+ I_VPSUBUSB,
+ I_VPSUBUSW,
+ I_VPUNPCKHBW,
+ I_VPUNPCKHWD,
+ I_VPUNPCKHDQ,
+ I_VPUNPCKHQDQ,
+ I_VPUNPCKLBW,
+ I_VPUNPCKLWD,
+ I_VPUNPCKLDQ,
+ I_VPUNPCKLQDQ,
+ I_VPXOR,
+ I_VRCPPS,
+ I_VRCPSS,
+ I_VRSQRTPS,
+ I_VRSQRTSS,
+ I_VROUNDPD,
+ I_VROUNDPS,
+ I_VROUNDSD,
+ I_VROUNDSS,
+ I_VSHUFPD,
+ I_VSHUFPS,
+ I_VSQRTPD,
+ I_VSQRTPS,
+ I_VSQRTSD,
+ I_VSQRTSS,
+ I_VSTMXCSR,
+ I_VSUBPD,
+ I_VSUBPS,
+ I_VSUBSD,
+ I_VSUBSS,
+ I_VTESTPS,
+ I_VTESTPD,
+ I_VUCOMISD,
+ I_VUCOMISS,
+ I_VUNPCKHPD,
+ I_VUNPCKHPS,
+ I_VUNPCKLPD,
+ I_VUNPCKLPS,
+ I_VXORPD,
+ I_VXORPS,
+ I_VZEROALL,
+ I_VZEROUPPER,
+ I_PCLMULLQLQDQ,
+ I_PCLMULHQLQDQ,
+ I_PCLMULLQHQDQ,
+ I_PCLMULHQHQDQ,
+ I_PCLMULQDQ,
+ I_VPCLMULLQLQDQ,
+ I_VPCLMULHQLQDQ,
+ I_VPCLMULLQHQDQ,
+ I_VPCLMULHQHQDQ,
+ I_VPCLMULQDQ,
+ I_VFMADD132PS,
+ I_VFMADD132PD,
+ I_VFMADD312PS,
+ I_VFMADD312PD,
+ I_VFMADD213PS,
+ I_VFMADD213PD,
+ I_VFMADD123PS,
+ I_VFMADD123PD,
+ I_VFMADD231PS,
+ I_VFMADD231PD,
+ I_VFMADD321PS,
+ I_VFMADD321PD,
+ I_VFMADDSUB132PS,
+ I_VFMADDSUB132PD,
+ I_VFMADDSUB312PS,
+ I_VFMADDSUB312PD,
+ I_VFMADDSUB213PS,
+ I_VFMADDSUB213PD,
+ I_VFMADDSUB123PS,
+ I_VFMADDSUB123PD,
+ I_VFMADDSUB231PS,
+ I_VFMADDSUB231PD,
+ I_VFMADDSUB321PS,
+ I_VFMADDSUB321PD,
+ I_VFMSUB132PS,
+ I_VFMSUB132PD,
+ I_VFMSUB312PS,
+ I_VFMSUB312PD,
+ I_VFMSUB213PS,
+ I_VFMSUB213PD,
+ I_VFMSUB123PS,
+ I_VFMSUB123PD,
+ I_VFMSUB231PS,
+ I_VFMSUB231PD,
+ I_VFMSUB321PS,
+ I_VFMSUB321PD,
+ I_VFMSUBADD132PS,
+ I_VFMSUBADD132PD,
+ I_VFMSUBADD312PS,
+ I_VFMSUBADD312PD,
+ I_VFMSUBADD213PS,
+ I_VFMSUBADD213PD,
+ I_VFMSUBADD123PS,
+ I_VFMSUBADD123PD,
+ I_VFMSUBADD231PS,
+ I_VFMSUBADD231PD,
+ I_VFMSUBADD321PS,
+ I_VFMSUBADD321PD,
+ I_VFNMADD132PS,
+ I_VFNMADD132PD,
+ I_VFNMADD312PS,
+ I_VFNMADD312PD,
+ I_VFNMADD213PS,
+ I_VFNMADD213PD,
+ I_VFNMADD123PS,
+ I_VFNMADD123PD,
+ I_VFNMADD231PS,
+ I_VFNMADD231PD,
+ I_VFNMADD321PS,
+ I_VFNMADD321PD,
+ I_VFNMSUB132PS,
+ I_VFNMSUB132PD,
+ I_VFNMSUB312PS,
+ I_VFNMSUB312PD,
+ I_VFNMSUB213PS,
+ I_VFNMSUB213PD,
+ I_VFNMSUB123PS,
+ I_VFNMSUB123PD,
+ I_VFNMSUB231PS,
+ I_VFNMSUB231PD,
+ I_VFNMSUB321PS,
+ I_VFNMSUB321PD,
+ I_VFMADD132SS,
+ I_VFMADD132SD,
+ I_VFMADD312SS,
+ I_VFMADD312SD,
+ I_VFMADD213SS,
+ I_VFMADD213SD,
+ I_VFMADD123SS,
+ I_VFMADD123SD,
+ I_VFMADD231SS,
+ I_VFMADD231SD,
+ I_VFMADD321SS,
+ I_VFMADD321SD,
+ I_VFMSUB132SS,
+ I_VFMSUB132SD,
+ I_VFMSUB312SS,
+ I_VFMSUB312SD,
+ I_VFMSUB213SS,
+ I_VFMSUB213SD,
+ I_VFMSUB123SS,
+ I_VFMSUB123SD,
+ I_VFMSUB231SS,
+ I_VFMSUB231SD,
+ I_VFMSUB321SS,
+ I_VFMSUB321SD,
+ I_VFNMADD132SS,
+ I_VFNMADD132SD,
+ I_VFNMADD312SS,
+ I_VFNMADD312SD,
+ I_VFNMADD213SS,
+ I_VFNMADD213SD,
+ I_VFNMADD123SS,
+ I_VFNMADD123SD,
+ I_VFNMADD231SS,
+ I_VFNMADD231SD,
+ I_VFNMADD321SS,
+ I_VFNMADD321SD,
+ I_VFNMSUB132SS,
+ I_VFNMSUB132SD,
+ I_VFNMSUB312SS,
+ I_VFNMSUB312SD,
+ I_VFNMSUB213SS,
+ I_VFNMSUB213SD,
+ I_VFNMSUB123SS,
+ I_VFNMSUB123SD,
+ I_VFNMSUB231SS,
+ I_VFNMSUB231SD,
+ I_VFNMSUB321SS,
+ I_VFNMSUB321SD,
+ I_RDFSBASE,
+ I_RDGSBASE,
+ I_RDRAND,
+ I_WRFSBASE,
+ I_WRGSBASE,
+ I_VCVTPH2PS,
+ I_VCVTPS2PH,
+ I_ADCX,
+ I_ADOX,
+ I_RDSEED,
+ I_CLAC,
+ I_STAC,
+ I_XSTORE,
+ I_XCRYPTECB,
+ I_XCRYPTCBC,
+ I_XCRYPTCTR,
+ I_XCRYPTCFB,
+ I_XCRYPTOFB,
+ I_MONTMUL,
+ I_XSHA1,
+ I_XSHA256,
+ I_LLWPCB,
+ I_SLWPCB,
+ I_LWPVAL,
+ I_LWPINS,
+ I_VFMADDPD,
+ I_VFMADDPS,
+ I_VFMADDSD,
+ I_VFMADDSS,
+ I_VFMADDSUBPD,
+ I_VFMADDSUBPS,
+ I_VFMSUBADDPD,
+ I_VFMSUBADDPS,
+ I_VFMSUBPD,
+ I_VFMSUBPS,
+ I_VFMSUBSD,
+ I_VFMSUBSS,
+ I_VFNMADDPD,
+ I_VFNMADDPS,
+ I_VFNMADDSD,
+ I_VFNMADDSS,
+ I_VFNMSUBPD,
+ I_VFNMSUBPS,
+ I_VFNMSUBSD,
+ I_VFNMSUBSS,
+ I_VFRCZPD,
+ I_VFRCZPS,
+ I_VFRCZSD,
+ I_VFRCZSS,
+ I_VPCMOV,
+ I_VPCOMB,
+ I_VPCOMD,
+ I_VPCOMQ,
+ I_VPCOMUB,
+ I_VPCOMUD,
+ I_VPCOMUQ,
+ I_VPCOMUW,
+ I_VPCOMW,
+ I_VPHADDBD,
+ I_VPHADDBQ,
+ I_VPHADDBW,
+ I_VPHADDDQ,
+ I_VPHADDUBD,
+ I_VPHADDUBQ,
+ I_VPHADDUBW,
+ I_VPHADDUDQ,
+ I_VPHADDUWD,
+ I_VPHADDUWQ,
+ I_VPHADDWD,
+ I_VPHADDWQ,
+ I_VPHSUBBW,
+ I_VPHSUBDQ,
+ I_VPHSUBWD,
+ I_VPMACSDD,
+ I_VPMACSDQH,
+ I_VPMACSDQL,
+ I_VPMACSSDD,
+ I_VPMACSSDQH,
+ I_VPMACSSDQL,
+ I_VPMACSSWD,
+ I_VPMACSSWW,
+ I_VPMACSWD,
+ I_VPMACSWW,
+ I_VPMADCSSWD,
+ I_VPMADCSWD,
+ I_VPPERM,
+ I_VPROTB,
+ I_VPROTD,
+ I_VPROTQ,
+ I_VPROTW,
+ I_VPSHAB,
+ I_VPSHAD,
+ I_VPSHAQ,
+ I_VPSHAW,
+ I_VPSHLB,
+ I_VPSHLD,
+ I_VPSHLQ,
+ I_VPSHLW,
+ I_VBROADCASTI128,
+ I_VPBLENDD,
+ I_VPBROADCASTB,
+ I_VPBROADCASTW,
+ I_VPBROADCASTD,
+ I_VPBROADCASTQ,
+ I_VPERMD,
+ I_VPERMPD,
+ I_VPERMPS,
+ I_VPERMQ,
+ I_VPERM2I128,
+ I_VEXTRACTI128,
+ I_VINSERTI128,
+ I_VPMASKMOVD,
+ I_VPMASKMOVQ,
+ I_VPSLLVD,
+ I_VPSLLVQ,
+ I_VPSRAVD,
+ I_VPSRLVD,
+ I_VPSRLVQ,
+ I_VGATHERDPD,
+ I_VGATHERQPD,
+ I_VGATHERDPS,
+ I_VGATHERQPS,
+ I_VPGATHERDD,
+ I_VPGATHERQD,
+ I_VPGATHERDQ,
+ I_VPGATHERQQ,
+ I_XABORT,
+ I_XBEGIN,
+ I_XEND,
+ I_XTEST,
+ I_ANDN,
+ I_BEXTR,
+ I_BLCI,
+ I_BLCIC,
+ I_BLSI,
+ I_BLSIC,
+ I_BLCFILL,
+ I_BLSFILL,
+ I_BLCMSK,
+ I_BLSMSK,
+ I_BLSR,
+ I_BLCS,
+ I_BZHI,
+ I_MULX,
+ I_PDEP,
+ I_PEXT,
+ I_RORX,
+ I_SARX,
+ I_SHLX,
+ I_SHRX,
+ I_TZCNT,
+ I_TZMSK,
+ I_T1MSKC,
+ I_PREFETCHWT1,
+ I_BNDMK,
+ I_BNDCL,
+ I_BNDCU,
+ I_BNDCN,
+ I_BNDMOV,
+ I_BNDLDX,
+ I_BNDSTX,
+ I_SHA1MSG1,
+ I_SHA1MSG2,
+ I_SHA1NEXTE,
+ I_SHA1RNDS4,
+ I_SHA256MSG1,
+ I_SHA256MSG2,
+ I_SHA256RNDS2,
+ I_VBCSTNEBF16PS,
+ I_VBCSTNESH2PS,
+ I_VCVTNEEBF162PS,
+ I_VCVTNEEPH2PS,
+ I_VCVTNEOBF162PS,
+ I_VCVTNEOPH2PS,
+ I_VCVTNEPS2BF16,
+ I_VPDPBSSD,
+ I_VPDPBSSDS,
+ I_VPDPBSUD,
+ I_VPDPBSUDS,
+ I_VPDPBUUD,
+ I_VPDPBUUDS,
+ I_VPMADD52HUQ,
+ I_VPMADD52LUQ,
+ I_KADDB,
+ I_KADDD,
+ I_KADDQ,
+ I_KADDW,
+ I_KANDB,
+ I_KANDD,
+ I_KANDNB,
+ I_KANDND,
+ I_KANDNQ,
+ I_KANDNW,
+ I_KANDQ,
+ I_KANDW,
+ I_KMOVB,
+ I_KMOVD,
+ I_KMOVQ,
+ I_KMOVW,
+ I_KNOTB,
+ I_KNOTD,
+ I_KNOTQ,
+ I_KNOTW,
+ I_KORB,
+ I_KORD,
+ I_KORQ,
+ I_KORW,
+ I_KORTESTB,
+ I_KORTESTD,
+ I_KORTESTQ,
+ I_KORTESTW,
+ I_KSHIFTLB,
+ I_KSHIFTLD,
+ I_KSHIFTLQ,
+ I_KSHIFTLW,
+ I_KSHIFTRB,
+ I_KSHIFTRD,
+ I_KSHIFTRQ,
+ I_KSHIFTRW,
+ I_KTESTB,
+ I_KTESTD,
+ I_KTESTQ,
+ I_KTESTW,
+ I_KUNPCKBW,
+ I_KUNPCKDQ,
+ I_KUNPCKWD,
+ I_KXNORB,
+ I_KXNORD,
+ I_KXNORQ,
+ I_KXNORW,
+ I_KXORB,
+ I_KXORD,
+ I_KXORQ,
+ I_KXORW,
+ I_KADD,
+ I_KAND,
+ I_KANDN,
+ I_KMOV,
+ I_KNOT,
+ I_KOR,
+ I_KORTEST,
+ I_KSHIFTL,
+ I_KSHIFTR,
+ I_KTEST,
+ I_KUNPCK,
+ I_KXNOR,
+ I_KXOR,
+ I_VALIGND,
+ I_VALIGNQ,
+ I_VBLENDMPD,
+ I_VBLENDMPS,
+ I_VBROADCASTF32X2,
+ I_VBROADCASTF32X4,
+ I_VBROADCASTF32X8,
+ I_VBROADCASTF64X2,
+ I_VBROADCASTF64X4,
+ I_VBROADCASTI32X2,
+ I_VBROADCASTI32X4,
+ I_VBROADCASTI32X8,
+ I_VBROADCASTI64X2,
+ I_VBROADCASTI64X4,
+ I_VCMPEQ_OQPD,
+ I_VCMPEQ_OQPS,
+ I_VCMPEQ_OQSD,
+ I_VCMPEQ_OQSS,
+ I_VCOMPRESSPD,
+ I_VCOMPRESSPS,
+ I_VCVTPD2QQ,
+ I_VCVTPD2UDQ,
+ I_VCVTPD2UQQ,
+ I_VCVTPS2QQ,
+ I_VCVTPS2UDQ,
+ I_VCVTPS2UQQ,
+ I_VCVTQQ2PD,
+ I_VCVTQQ2PS,
+ I_VCVTSD2USI,
+ I_VCVTSS2USI,
+ I_VCVTTPD2QQ,
+ I_VCVTTPD2UDQ,
+ I_VCVTTPD2UQQ,
+ I_VCVTTPS2QQ,
+ I_VCVTTPS2UDQ,
+ I_VCVTTPS2UQQ,
+ I_VCVTTSD2USI,
+ I_VCVTTSS2USI,
+ I_VCVTUDQ2PD,
+ I_VCVTUDQ2PS,
+ I_VCVTUQQ2PD,
+ I_VCVTUQQ2PS,
+ I_VCVTUSI2SD,
+ I_VCVTUSI2SS,
+ I_VDBPSADBW,
+ I_VEXP2PD,
+ I_VEXP2PS,
+ I_VEXPANDPD,
+ I_VEXPANDPS,
+ I_VEXTRACTF32X4,
+ I_VEXTRACTF32X8,
+ I_VEXTRACTF64X2,
+ I_VEXTRACTF64X4,
+ I_VEXTRACTI32X4,
+ I_VEXTRACTI32X8,
+ I_VEXTRACTI64X2,
+ I_VEXTRACTI64X4,
+ I_VFIXUPIMMPD,
+ I_VFIXUPIMMPS,
+ I_VFIXUPIMMSD,
+ I_VFIXUPIMMSS,
+ I_VFPCLASSPD,
+ I_VFPCLASSPS,
+ I_VFPCLASSSD,
+ I_VFPCLASSSS,
+ I_VGATHERPF0DPD,
+ I_VGATHERPF0DPS,
+ I_VGATHERPF0QPD,
+ I_VGATHERPF0QPS,
+ I_VGATHERPF1DPD,
+ I_VGATHERPF1DPS,
+ I_VGATHERPF1QPD,
+ I_VGATHERPF1QPS,
+ I_VGETEXPPD,
+ I_VGETEXPPS,
+ I_VGETEXPSD,
+ I_VGETEXPSS,
+ I_VGETMANTPD,
+ I_VGETMANTPS,
+ I_VGETMANTSD,
+ I_VGETMANTSS,
+ I_VINSERTF32X4,
+ I_VINSERTF32X8,
+ I_VINSERTF64X2,
+ I_VINSERTF64X4,
+ I_VINSERTI32X4,
+ I_VINSERTI32X8,
+ I_VINSERTI64X2,
+ I_VINSERTI64X4,
+ I_VMOVDQA32,
+ I_VMOVDQA64,
+ I_VMOVDQU16,
+ I_VMOVDQU32,
+ I_VMOVDQU64,
+ I_VMOVDQU8,
+ I_VPABSQ,
+ I_VPANDD,
+ I_VPANDND,
+ I_VPANDNQ,
+ I_VPANDQ,
+ I_VPBLENDMB,
+ I_VPBLENDMD,
+ I_VPBLENDMQ,
+ I_VPBLENDMW,
+ I_VPBROADCASTMB2Q,
+ I_VPBROADCASTMW2D,
+ I_VPCMPEQUB,
+ I_VPCMPEQUD,
+ I_VPCMPEQUQ,
+ I_VPCMPEQUW,
+ I_VPCMPGEB,
+ I_VPCMPGED,
+ I_VPCMPGEQ,
+ I_VPCMPGEUB,
+ I_VPCMPGEUD,
+ I_VPCMPGEUQ,
+ I_VPCMPGEUW,
+ I_VPCMPGEW,
+ I_VPCMPGTUB,
+ I_VPCMPGTUD,
+ I_VPCMPGTUQ,
+ I_VPCMPGTUW,
+ I_VPCMPLEB,
+ I_VPCMPLED,
+ I_VPCMPLEQ,
+ I_VPCMPLEUB,
+ I_VPCMPLEUD,
+ I_VPCMPLEUQ,
+ I_VPCMPLEUW,
+ I_VPCMPLEW,
+ I_VPCMPLTB,
+ I_VPCMPLTD,
+ I_VPCMPLTQ,
+ I_VPCMPLTUB,
+ I_VPCMPLTUD,
+ I_VPCMPLTUQ,
+ I_VPCMPLTUW,
+ I_VPCMPLTW,
+ I_VPCMPNEQB,
+ I_VPCMPNEQD,
+ I_VPCMPNEQQ,
+ I_VPCMPNEQUB,
+ I_VPCMPNEQUD,
+ I_VPCMPNEQUQ,
+ I_VPCMPNEQUW,
+ I_VPCMPNEQW,
+ I_VPCMPNGTB,
+ I_VPCMPNGTD,
+ I_VPCMPNGTQ,
+ I_VPCMPNGTUB,
+ I_VPCMPNGTUD,
+ I_VPCMPNGTUQ,
+ I_VPCMPNGTUW,
+ I_VPCMPNGTW,
+ I_VPCMPNLEB,
+ I_VPCMPNLED,
+ I_VPCMPNLEQ,
+ I_VPCMPNLEUB,
+ I_VPCMPNLEUD,
+ I_VPCMPNLEUQ,
+ I_VPCMPNLEUW,
+ I_VPCMPNLEW,
+ I_VPCMPNLTB,
+ I_VPCMPNLTD,
+ I_VPCMPNLTQ,
+ I_VPCMPNLTUB,
+ I_VPCMPNLTUD,
+ I_VPCMPNLTUQ,
+ I_VPCMPNLTUW,
+ I_VPCMPNLTW,
+ I_VPCMPB,
+ I_VPCMPD,
+ I_VPCMPQ,
+ I_VPCMPUB,
+ I_VPCMPUD,
+ I_VPCMPUQ,
+ I_VPCMPUW,
+ I_VPCMPW,
+ I_VPCOMPRESSD,
+ I_VPCOMPRESSQ,
+ I_VPCONFLICTD,
+ I_VPCONFLICTQ,
+ I_VPERMB,
+ I_VPERMI2B,
+ I_VPERMI2D,
+ I_VPERMI2PD,
+ I_VPERMI2PS,
+ I_VPERMI2Q,
+ I_VPERMI2W,
+ I_VPERMT2B,
+ I_VPERMT2D,
+ I_VPERMT2PD,
+ I_VPERMT2PS,
+ I_VPERMT2Q,
+ I_VPERMT2W,
+ I_VPERMW,
+ I_VPEXPANDD,
+ I_VPEXPANDQ,
+ I_VPLZCNTD,
+ I_VPLZCNTQ,
+ I_VPMAXSQ,
+ I_VPMAXUQ,
+ I_VPMINSQ,
+ I_VPMINUQ,
+ I_VPMOVB2M,
+ I_VPMOVD2M,
+ I_VPMOVDB,
+ I_VPMOVDW,
+ I_VPMOVM2B,
+ I_VPMOVM2D,
+ I_VPMOVM2Q,
+ I_VPMOVM2W,
+ I_VPMOVQ2M,
+ I_VPMOVQB,
+ I_VPMOVQD,
+ I_VPMOVQW,
+ I_VPMOVSDB,
+ I_VPMOVSDW,
+ I_VPMOVSQB,
+ I_VPMOVSQD,
+ I_VPMOVSQW,
+ I_VPMOVSWB,
+ I_VPMOVUSDB,
+ I_VPMOVUSDW,
+ I_VPMOVUSQB,
+ I_VPMOVUSQD,
+ I_VPMOVUSQW,
+ I_VPMOVUSWB,
+ I_VPMOVW2M,
+ I_VPMOVWB,
+ I_VPMULLQ,
+ I_VPMULTISHIFTQB,
+ I_VPORD,
+ I_VPORQ,
+ I_VPROLD,
+ I_VPROLQ,
+ I_VPROLVD,
+ I_VPROLVQ,
+ I_VPRORD,
+ I_VPRORQ,
+ I_VPRORVD,
+ I_VPRORVQ,
+ I_VPSCATTERDD,
+ I_VPSCATTERDQ,
+ I_VPSCATTERQD,
+ I_VPSCATTERQQ,
+ I_VPSLLVW,
+ I_VPSRAQ,
+ I_VPSRAVQ,
+ I_VPSRAVW,
+ I_VPSRLVW,
+ I_VPTERNLOGD,
+ I_VPTERNLOGQ,
+ I_VPTESTMB,
+ I_VPTESTMD,
+ I_VPTESTMQ,
+ I_VPTESTMW,
+ I_VPTESTNMB,
+ I_VPTESTNMD,
+ I_VPTESTNMQ,
+ I_VPTESTNMW,
+ I_VPXORD,
+ I_VPXORQ,
+ I_VRANGEPD,
+ I_VRANGEPS,
+ I_VRANGESD,
+ I_VRANGESS,
+ I_VRCP14PD,
+ I_VRCP14PS,
+ I_VRCP14SD,
+ I_VRCP14SS,
+ I_VRCP28PD,
+ I_VRCP28PS,
+ I_VRCP28SD,
+ I_VRCP28SS,
+ I_VREDUCEPD,
+ I_VREDUCEPS,
+ I_VREDUCESD,
+ I_VREDUCESS,
+ I_VRNDSCALEPD,
+ I_VRNDSCALEPS,
+ I_VRNDSCALESD,
+ I_VRNDSCALESS,
+ I_VRSQRT14PD,
+ I_VRSQRT14PS,
+ I_VRSQRT14SD,
+ I_VRSQRT14SS,
+ I_VRSQRT28PD,
+ I_VRSQRT28PS,
+ I_VRSQRT28SD,
+ I_VRSQRT28SS,
+ I_VSCALEFPD,
+ I_VSCALEFPS,
+ I_VSCALEFSD,
+ I_VSCALEFSS,
+ I_VSCATTERDPD,
+ I_VSCATTERDPS,
+ I_VSCATTERPF0DPD,
+ I_VSCATTERPF0DPS,
+ I_VSCATTERPF0QPD,
+ I_VSCATTERPF0QPS,
+ I_VSCATTERPF1DPD,
+ I_VSCATTERPF1DPS,
+ I_VSCATTERPF1QPD,
+ I_VSCATTERPF1QPS,
+ I_VSCATTERQPD,
+ I_VSCATTERQPS,
+ I_VSHUFF32X4,
+ I_VSHUFF64X2,
+ I_VSHUFI32X4,
+ I_VSHUFI64X2,
+ I_RDPKRU,
+ I_WRPKRU,
+ I_RDPID,
+ I_CLFLUSHOPT,
+ I_CLWB,
+ I_PCOMMIT,
+ I_CLZERO,
+ I_PTWRITE,
+ I_CLDEMOTE,
+ I_MOVDIRI,
+ I_MOVDIR64B,
+ I_PCONFIG,
+ I_TPAUSE,
+ I_UMONITOR,
+ I_UMWAIT,
+ I_WBNOINVD,
+ I_GF2P8AFFINEINVQB,
+ I_VGF2P8AFFINEINVQB,
+ I_GF2P8AFFINEQB,
+ I_VGF2P8AFFINEQB,
+ I_GF2P8MULB,
+ I_VGF2P8MULB,
+ I_VPCOMPRESSB,
+ I_VPCOMPRESSW,
+ I_VPEXPANDB,
+ I_VPEXPANDW,
+ I_VPSHLDW,
+ I_VPSHLDD,
+ I_VPSHLDQ,
+ I_VPSHLDVW,
+ I_VPSHLDVD,
+ I_VPSHLDVQ,
+ I_VPSHRDW,
+ I_VPSHRDD,
+ I_VPSHRDQ,
+ I_VPSHRDVW,
+ I_VPSHRDVD,
+ I_VPSHRDVQ,
+ I_VPDPBUSD,
+ I_VPDPBUSDS,
+ I_VPDPWSSD,
+ I_VPDPWSSDS,
+ I_VPOPCNTB,
+ I_VPOPCNTW,
+ I_VPOPCNTD,
+ I_VPOPCNTQ,
+ I_VPSHUFBITQMB,
+ I_V4FMADDPS,
+ I_V4FNMADDPS,
+ I_V4FMADDSS,
+ I_V4FNMADDSS,
+ I_V4DPWSSDS,
+ I_V4DPWSSD,
+ I_ENCLS,
+ I_ENCLU,
+ I_ENCLV,
+ I_CLRSSBSY,
+ I_ENDBR32,
+ I_ENDBR64,
+ I_INCSSPD,
+ I_INCSSPQ,
+ I_RDSSPD,
+ I_RDSSPQ,
+ I_RSTORSSP,
+ I_SAVEPREVSSP,
+ I_SETSSBSY,
+ I_WRUSSD,
+ I_WRUSSQ,
+ I_WRSSD,
+ I_WRSSQ,
+ I_ENQCMD,
+ I_ENQCMDS,
+ I_SERIALIZE,
+ I_XRESLDTRK,
+ I_XSUSLDTRK,
+ I_VCVTNE2PS2BF16,
+ I_VDPBF16PS,
+ I_VP2INTERSECTD,
+ I_LDTILECFG,
+ I_STTILECFG,
+ I_TDPBF16PS,
+ I_TDPBSSD,
+ I_TDPBSUD,
+ I_TDPBUSD,
+ I_TDPBUUD,
+ I_TILELOADD,
+ I_TILELOADDT1,
+ I_TILERELEASE,
+ I_TILESTORED,
+ I_TILEZERO,
+ I_VADDPH,
+ I_VADDSH,
+ I_VCMPPH,
+ I_VCMPSH,
+ I_VCOMISH,
+ I_VCVTDQ2PH,
+ I_VCVTPD2PH,
+ I_VCVTPH2DQ,
+ I_VCVTPH2PD,
+ I_VCVTPH2PSX,
+ I_VCVTPH2QQ,
+ I_VCVTPH2UDQ,
+ I_VCVTPH2UQQ,
+ I_VCVTPH2UW,
+ I_VCVTPH2W,
+ I_VCVTQQ2PH,
+ I_VCVTSD2SH,
+ I_VCVTSH2SD,
+ I_VCVTSH2SI,
+ I_VCVTSH2SS,
+ I_VCVTSH2USI,
+ I_VCVTSI2SH,
+ I_VCVTSS2SH,
+ I_VCVTTPH2DQ,
+ I_VCVTTPH2QQ,
+ I_VCVTTPH2UDQ,
+ I_VCVTTPH2UQQ,
+ I_VCVTTPH2UW,
+ I_VCVTTPH2W,
+ I_VCVTTSH2SI,
+ I_VCVTTSH2USI,
+ I_VCVTUDQ2PH,
+ I_VCVTUQQ2PH,
+ I_VCVTUSI2SH,
+ I_VCVTUW2PH,
+ I_VCVTW2PH,
+ I_VDIVPH,
+ I_VDIVSH,
+ I_VFCMADDCPH,
+ I_VFMADDCPH,
+ I_VFCMADDCSH,
+ I_VFMADDCSH,
+ I_VFCMULCPCH,
+ I_VFMULCPCH,
+ I_VFCMULCSH,
+ I_VFMULCSH,
+ I_VFMADDSUB132PH,
+ I_VFMADDSUB213PH,
+ I_VFMADDSUB231PH,
+ I_VFMSUBADD132PH,
+ I_VFMSUBADD213PH,
+ I_VFMSUBADD231PH,
+ I_VPMADD132PH,
+ I_VPMADD213PH,
+ I_VPMADD231PH,
+ I_VFMADD132PH,
+ I_VFMADD213PH,
+ I_VFMADD231PH,
+ I_VPMADD132SH,
+ I_VPMADD213SH,
+ I_VPMADD231SH,
+ I_VPNMADD132SH,
+ I_VPNMADD213SH,
+ I_VPNMADD231SH,
+ I_VPMSUB132PH,
+ I_VPMSUB213PH,
+ I_VPMSUB231PH,
+ I_VFMSUB132PH,
+ I_VFMSUB213PH,
+ I_VFMSUB231PH,
+ I_VPMSUB132SH,
+ I_VPMSUB213SH,
+ I_VPMSUB231SH,
+ I_VPNMSUB132SH,
+ I_VPNMSUB213SH,
+ I_VPNMSUB231SH,
+ I_VFPCLASSPH,
+ I_VFPCLASSSH,
+ I_VGETEXPPH,
+ I_VGETEXPSH,
+ I_VGETMANTPH,
+ I_VGETMANTSH,
+ I_VGETMAXPH,
+ I_VGETMAXSH,
+ I_VGETMINPH,
+ I_VGETMINSH,
+ I_VMOVSH,
+ I_VMOVW,
+ I_VMULPH,
+ I_VMULSH,
+ I_VRCPPH,
+ I_VRCPSH,
+ I_VREDUCEPH,
+ I_VREDUCESH,
+ I_VENDSCALEPH,
+ I_VENDSCALESH,
+ I_VRSQRTPH,
+ I_VRSQRTSH,
+ I_VSCALEFPH,
+ I_VSCALEFSH,
+ I_VSQRTPH,
+ I_VSQRTSH,
+ I_VSUBPH,
+ I_VSUBSH,
+ I_VUCOMISH,
+ I_AADD,
+ I_AAND,
+ I_AXOR,
+ I_CLUI,
+ I_SENDUIPI,
+ I_STUI,
+ I_TESTUI,
+ I_UIRET,
+ I_CMPAXADD,
+ I_CMPAEXADD,
+ I_CMPBXADD,
+ I_CMPBEXADD,
+ I_CMPCXADD,
+ I_CMPEXADD,
+ I_CMPGXADD,
+ I_CMPGEXADD,
+ I_CMPLXADD,
+ I_CMPLEXADD,
+ I_CMPNAXADD,
+ I_CMPNAEXADD,
+ I_CMPNBXADD,
+ I_CMPNBEXADD,
+ I_CMPNCXADD,
+ I_CMPNEXADD,
+ I_CMPNGXADD,
+ I_CMPNGEXADD,
+ I_CMPNLXADD,
+ I_CMPNLEXADD,
+ I_CMPNOXADD,
+ I_CMPNPXADD,
+ I_CMPNSXADD,
+ I_CMPNZXADD,
+ I_CMPOXADD,
+ I_CMPPXADD,
+ I_CMPPEXADD,
+ I_CMPPOXADD,
+ I_CMPSXADD,
+ I_CMPZXADD,
+ I_WRMSRNS,
+ I_RDMSRLIST,
+ I_WRMSRLIST,
+ I_HRESET,
+ I_HINT_NOP0,
+ I_HINT_NOP1,
+ I_HINT_NOP2,
+ I_HINT_NOP3,
+ I_HINT_NOP4,
+ I_HINT_NOP5,
+ I_HINT_NOP6,
+ I_HINT_NOP7,
+ I_HINT_NOP8,
+ I_HINT_NOP9,
+ I_HINT_NOP10,
+ I_HINT_NOP11,
+ I_HINT_NOP12,
+ I_HINT_NOP13,
+ I_HINT_NOP14,
+ I_HINT_NOP15,
+ I_HINT_NOP16,
+ I_HINT_NOP17,
+ I_HINT_NOP18,
+ I_HINT_NOP19,
+ I_HINT_NOP20,
+ I_HINT_NOP21,
+ I_HINT_NOP22,
+ I_HINT_NOP23,
+ I_HINT_NOP24,
+ I_HINT_NOP25,
+ I_HINT_NOP26,
+ I_HINT_NOP27,
+ I_HINT_NOP28,
+ I_HINT_NOP29,
+ I_HINT_NOP30,
+ I_HINT_NOP31,
+ I_HINT_NOP32,
+ I_HINT_NOP33,
+ I_HINT_NOP34,
+ I_HINT_NOP35,
+ I_HINT_NOP36,
+ I_HINT_NOP37,
+ I_HINT_NOP38,
+ I_HINT_NOP39,
+ I_HINT_NOP40,
+ I_HINT_NOP41,
+ I_HINT_NOP42,
+ I_HINT_NOP43,
+ I_HINT_NOP44,
+ I_HINT_NOP45,
+ I_HINT_NOP46,
+ I_HINT_NOP47,
+ I_HINT_NOP48,
+ I_HINT_NOP49,
+ I_HINT_NOP50,
+ I_HINT_NOP51,
+ I_HINT_NOP52,
+ I_HINT_NOP53,
+ I_HINT_NOP54,
+ I_HINT_NOP55,
+ I_HINT_NOP56,
+ I_HINT_NOP57,
+ I_HINT_NOP58,
+ I_HINT_NOP59,
+ I_HINT_NOP60,
+ I_HINT_NOP61,
+ I_HINT_NOP62,
+ I_HINT_NOP63,
+ I_none = -1
+};
+
+#define MAX_INSLEN 17
+#define NASM_VEX_CLASSES 3
+#define NO_DECORATOR {0,0,0,0,0}
+#endif /* NASM_INSNSI_H */
diff --git a/vere/ext/nasm/x86/insnsn.c b/vere/ext/nasm/x86/insnsn.c
new file mode 100644
index 0000000..88505a5
--- /dev/null
+++ b/vere/ext/nasm/x86/insnsn.c
@@ -0,0 +1,2254 @@
+/* This file is auto-generated from insns.dat by insns.pl - don't edit it */
+
+#include "tables.h"
+
+const char * const nasm_insn_names[] = {
+ "db",
+ "dw",
+ "dd",
+ "dq",
+ "dt",
+ "do",
+ "dy",
+ "dz",
+ "resb",
+ "resw",
+ "resd",
+ "resq",
+ "rest",
+ "reso",
+ "resy",
+ "resz",
+ "incbin",
+ "aaa",
+ "aad",
+ "aam",
+ "aas",
+ "adc",
+ "add",
+ "and",
+ "arpl",
+ "bb0_reset",
+ "bb1_reset",
+ "bound",
+ "bsf",
+ "bsr",
+ "bswap",
+ "bt",
+ "btc",
+ "btr",
+ "bts",
+ "call",
+ "cbw",
+ "cdq",
+ "cdqe",
+ "clc",
+ "cld",
+ "cli",
+ "clts",
+ "cmc",
+ "cmp",
+ "cmpsb",
+ "cmpsd",
+ "cmpsq",
+ "cmpsw",
+ "cmpxchg",
+ "cmpxchg486",
+ "cmpxchg8b",
+ "cmpxchg16b",
+ "cpuid",
+ "cpu_read",
+ "cpu_write",
+ "cqo",
+ "cwd",
+ "cwde",
+ "daa",
+ "das",
+ "dec",
+ "div",
+ "dmint",
+ "emms",
+ "enter",
+ "equ",
+ "f2xm1",
+ "fabs",
+ "fadd",
+ "faddp",
+ "fbld",
+ "fbstp",
+ "fchs",
+ "fclex",
+ "fcmovb",
+ "fcmovbe",
+ "fcmove",
+ "fcmovnb",
+ "fcmovnbe",
+ "fcmovne",
+ "fcmovnu",
+ "fcmovu",
+ "fcom",
+ "fcomi",
+ "fcomip",
+ "fcomp",
+ "fcompp",
+ "fcos",
+ "fdecstp",
+ "fdisi",
+ "fdiv",
+ "fdivp",
+ "fdivr",
+ "fdivrp",
+ "femms",
+ "feni",
+ "ffree",
+ "ffreep",
+ "fiadd",
+ "ficom",
+ "ficomp",
+ "fidiv",
+ "fidivr",
+ "fild",
+ "fimul",
+ "fincstp",
+ "finit",
+ "fist",
+ "fistp",
+ "fisttp",
+ "fisub",
+ "fisubr",
+ "fld",
+ "fld1",
+ "fldcw",
+ "fldenv",
+ "fldl2e",
+ "fldl2t",
+ "fldlg2",
+ "fldln2",
+ "fldpi",
+ "fldz",
+ "fmul",
+ "fmulp",
+ "fnclex",
+ "fndisi",
+ "fneni",
+ "fninit",
+ "fnop",
+ "fnsave",
+ "fnstcw",
+ "fnstenv",
+ "fnstsw",
+ "fpatan",
+ "fprem",
+ "fprem1",
+ "fptan",
+ "frndint",
+ "frstor",
+ "fsave",
+ "fscale",
+ "fsetpm",
+ "fsin",
+ "fsincos",
+ "fsqrt",
+ "fst",
+ "fstcw",
+ "fstenv",
+ "fstp",
+ "fstsw",
+ "fsub",
+ "fsubp",
+ "fsubr",
+ "fsubrp",
+ "ftst",
+ "fucom",
+ "fucomi",
+ "fucomip",
+ "fucomp",
+ "fucompp",
+ "fxam",
+ "fxch",
+ "fxtract",
+ "fyl2x",
+ "fyl2xp1",
+ "hlt",
+ "ibts",
+ "icebp",
+ "idiv",
+ "imul",
+ "in",
+ "inc",
+ "insb",
+ "insd",
+ "insw",
+ "int",
+ "int01",
+ "int1",
+ "int03",
+ "int3",
+ "into",
+ "invd",
+ "invpcid",
+ "invlpg",
+ "invlpga",
+ "iret",
+ "iretd",
+ "iretq",
+ "iretw",
+ "jcxz",
+ "jecxz",
+ "jrcxz",
+ "jmp",
+ "jmpe",
+ "lahf",
+ "lar",
+ "lds",
+ "lea",
+ "leave",
+ "les",
+ "lfence",
+ "lfs",
+ "lgdt",
+ "lgs",
+ "lidt",
+ "lldt",
+ "lmsw",
+ "loadall",
+ "loadall286",
+ "lodsb",
+ "lodsd",
+ "lodsq",
+ "lodsw",
+ "loop",
+ "loope",
+ "loopne",
+ "loopnz",
+ "loopz",
+ "lsl",
+ "lss",
+ "ltr",
+ "mfence",
+ "monitor",
+ "monitorx",
+ "mov",
+ "movd",
+ "movq",
+ "movsb",
+ "movsd",
+ "movsq",
+ "movsw",
+ "movsx",
+ "movsxd",
+ "movzx",
+ "mul",
+ "mwait",
+ "mwaitx",
+ "neg",
+ "nop",
+ "not",
+ "or",
+ "out",
+ "outsb",
+ "outsd",
+ "outsw",
+ "packssdw",
+ "packsswb",
+ "packuswb",
+ "paddb",
+ "paddd",
+ "paddsb",
+ "paddsiw",
+ "paddsw",
+ "paddusb",
+ "paddusw",
+ "paddw",
+ "pand",
+ "pandn",
+ "pause",
+ "paveb",
+ "pavgusb",
+ "pcmpeqb",
+ "pcmpeqd",
+ "pcmpeqw",
+ "pcmpgtb",
+ "pcmpgtd",
+ "pcmpgtw",
+ "pdistib",
+ "pf2id",
+ "pfacc",
+ "pfadd",
+ "pfcmpeq",
+ "pfcmpge",
+ "pfcmpgt",
+ "pfmax",
+ "pfmin",
+ "pfmul",
+ "pfrcp",
+ "pfrcpit1",
+ "pfrcpit2",
+ "pfrsqit1",
+ "pfrsqrt",
+ "pfsub",
+ "pfsubr",
+ "pi2fd",
+ "pmachriw",
+ "pmaddwd",
+ "pmagw",
+ "pmulhriw",
+ "pmulhrwa",
+ "pmulhrwc",
+ "pmulhw",
+ "pmullw",
+ "pmvgezb",
+ "pmvlzb",
+ "pmvnzb",
+ "pmvzb",
+ "pop",
+ "popa",
+ "popad",
+ "popaw",
+ "popf",
+ "popfd",
+ "popfq",
+ "popfw",
+ "por",
+ "prefetch",
+ "prefetchw",
+ "pslld",
+ "psllq",
+ "psllw",
+ "psrad",
+ "psraw",
+ "psrld",
+ "psrlq",
+ "psrlw",
+ "psubb",
+ "psubd",
+ "psubsb",
+ "psubsiw",
+ "psubsw",
+ "psubusb",
+ "psubusw",
+ "psubw",
+ "punpckhbw",
+ "punpckhdq",
+ "punpckhwd",
+ "punpcklbw",
+ "punpckldq",
+ "punpcklwd",
+ "push",
+ "pusha",
+ "pushad",
+ "pushaw",
+ "pushf",
+ "pushfd",
+ "pushfq",
+ "pushfw",
+ "pxor",
+ "rcl",
+ "rcr",
+ "rdshr",
+ "rdmsr",
+ "rdpmc",
+ "rdtsc",
+ "rdtscp",
+ "ret",
+ "retf",
+ "retn",
+ "retw",
+ "retfw",
+ "retnw",
+ "retd",
+ "retfd",
+ "retnd",
+ "retq",
+ "retfq",
+ "retnq",
+ "rol",
+ "ror",
+ "rdm",
+ "rsdc",
+ "rsldt",
+ "rsm",
+ "rsts",
+ "sahf",
+ "sal",
+ "salc",
+ "sar",
+ "sbb",
+ "scasb",
+ "scasd",
+ "scasq",
+ "scasw",
+ "sfence",
+ "sgdt",
+ "shl",
+ "shld",
+ "shr",
+ "shrd",
+ "sidt",
+ "sldt",
+ "skinit",
+ "smi",
+ "smint",
+ "smintold",
+ "smsw",
+ "stc",
+ "std",
+ "sti",
+ "stosb",
+ "stosd",
+ "stosq",
+ "stosw",
+ "str",
+ "sub",
+ "svdc",
+ "svldt",
+ "svts",
+ "swapgs",
+ "syscall",
+ "sysenter",
+ "sysexit",
+ "sysret",
+ "test",
+ "ud0",
+ "ud1",
+ "ud2b",
+ "ud2",
+ "ud2a",
+ "umov",
+ "verr",
+ "verw",
+ "fwait",
+ "wbinvd",
+ "wrshr",
+ "wrmsr",
+ "xadd",
+ "xbts",
+ "xchg",
+ "xlatb",
+ "xlat",
+ "xor",
+ "cmova",
+ "cmovae",
+ "cmovb",
+ "cmovbe",
+ "cmovc",
+ "cmove",
+ "cmovg",
+ "cmovge",
+ "cmovl",
+ "cmovle",
+ "cmovna",
+ "cmovnae",
+ "cmovnb",
+ "cmovnbe",
+ "cmovnc",
+ "cmovne",
+ "cmovng",
+ "cmovnge",
+ "cmovnl",
+ "cmovnle",
+ "cmovno",
+ "cmovnp",
+ "cmovns",
+ "cmovnz",
+ "cmovo",
+ "cmovp",
+ "cmovpe",
+ "cmovpo",
+ "cmovs",
+ "cmovz",
+ "ja",
+ "jae",
+ "jb",
+ "jbe",
+ "jc",
+ "je",
+ "jg",
+ "jge",
+ "jl",
+ "jle",
+ "jna",
+ "jnae",
+ "jnb",
+ "jnbe",
+ "jnc",
+ "jne",
+ "jng",
+ "jnge",
+ "jnl",
+ "jnle",
+ "jno",
+ "jnp",
+ "jns",
+ "jnz",
+ "jo",
+ "jp",
+ "jpe",
+ "jpo",
+ "js",
+ "jz",
+ "seta",
+ "setae",
+ "setb",
+ "setbe",
+ "setc",
+ "sete",
+ "setg",
+ "setge",
+ "setl",
+ "setle",
+ "setna",
+ "setnae",
+ "setnb",
+ "setnbe",
+ "setnc",
+ "setne",
+ "setng",
+ "setnge",
+ "setnl",
+ "setnle",
+ "setno",
+ "setnp",
+ "setns",
+ "setnz",
+ "seto",
+ "setp",
+ "setpe",
+ "setpo",
+ "sets",
+ "setz",
+ "addps",
+ "addss",
+ "andnps",
+ "andps",
+ "cmpeqps",
+ "cmpeqss",
+ "cmpleps",
+ "cmpless",
+ "cmpltps",
+ "cmpltss",
+ "cmpneqps",
+ "cmpneqss",
+ "cmpnleps",
+ "cmpnless",
+ "cmpnltps",
+ "cmpnltss",
+ "cmpordps",
+ "cmpordss",
+ "cmpunordps",
+ "cmpunordss",
+ "cmpps",
+ "cmpss",
+ "comiss",
+ "cvtpi2ps",
+ "cvtps2pi",
+ "cvtsi2ss",
+ "cvtss2si",
+ "cvttps2pi",
+ "cvttss2si",
+ "divps",
+ "divss",
+ "ldmxcsr",
+ "maxps",
+ "maxss",
+ "minps",
+ "minss",
+ "movaps",
+ "movhps",
+ "movlhps",
+ "movlps",
+ "movhlps",
+ "movmskps",
+ "movntps",
+ "movss",
+ "movups",
+ "mulps",
+ "mulss",
+ "orps",
+ "rcpps",
+ "rcpss",
+ "rsqrtps",
+ "rsqrtss",
+ "shufps",
+ "sqrtps",
+ "sqrtss",
+ "stmxcsr",
+ "subps",
+ "subss",
+ "ucomiss",
+ "unpckhps",
+ "unpcklps",
+ "xorps",
+ "fxrstor",
+ "fxrstor64",
+ "fxsave",
+ "fxsave64",
+ "xgetbv",
+ "xsetbv",
+ "xsave",
+ "xsave64",
+ "xsavec",
+ "xsavec64",
+ "xsaveopt",
+ "xsaveopt64",
+ "xsaves",
+ "xsaves64",
+ "xrstor",
+ "xrstor64",
+ "xrstors",
+ "xrstors64",
+ "prefetchnta",
+ "prefetcht0",
+ "prefetcht1",
+ "prefetcht2",
+ "prefetchit0",
+ "prefetchit1",
+ "maskmovq",
+ "movntq",
+ "pavgb",
+ "pavgw",
+ "pextrw",
+ "pinsrw",
+ "pmaxsw",
+ "pmaxub",
+ "pminsw",
+ "pminub",
+ "pmovmskb",
+ "pmulhuw",
+ "psadbw",
+ "pshufw",
+ "pf2iw",
+ "pfnacc",
+ "pfpnacc",
+ "pi2fw",
+ "pswapd",
+ "maskmovdqu",
+ "clflush",
+ "movntdq",
+ "movnti",
+ "movntpd",
+ "movdqa",
+ "movdqu",
+ "movdq2q",
+ "movq2dq",
+ "paddq",
+ "pmuludq",
+ "pshufd",
+ "pshufhw",
+ "pshuflw",
+ "pslldq",
+ "psrldq",
+ "psubq",
+ "punpckhqdq",
+ "punpcklqdq",
+ "addpd",
+ "addsd",
+ "andnpd",
+ "andpd",
+ "cmpeqpd",
+ "cmpeqsd",
+ "cmplepd",
+ "cmplesd",
+ "cmpltpd",
+ "cmpltsd",
+ "cmpneqpd",
+ "cmpneqsd",
+ "cmpnlepd",
+ "cmpnlesd",
+ "cmpnltpd",
+ "cmpnltsd",
+ "cmpordpd",
+ "cmpordsd",
+ "cmpunordpd",
+ "cmpunordsd",
+ "cmppd",
+ "comisd",
+ "cvtdq2pd",
+ "cvtdq2ps",
+ "cvtpd2dq",
+ "cvtpd2pi",
+ "cvtpd2ps",
+ "cvtpi2pd",
+ "cvtps2dq",
+ "cvtps2pd",
+ "cvtsd2si",
+ "cvtsd2ss",
+ "cvtsi2sd",
+ "cvtss2sd",
+ "cvttpd2pi",
+ "cvttpd2dq",
+ "cvttps2dq",
+ "cvttsd2si",
+ "divpd",
+ "divsd",
+ "maxpd",
+ "maxsd",
+ "minpd",
+ "minsd",
+ "movapd",
+ "movhpd",
+ "movlpd",
+ "movmskpd",
+ "movupd",
+ "mulpd",
+ "mulsd",
+ "orpd",
+ "shufpd",
+ "sqrtpd",
+ "sqrtsd",
+ "subpd",
+ "subsd",
+ "ucomisd",
+ "unpckhpd",
+ "unpcklpd",
+ "xorpd",
+ "addsubpd",
+ "addsubps",
+ "haddpd",
+ "haddps",
+ "hsubpd",
+ "hsubps",
+ "lddqu",
+ "movddup",
+ "movshdup",
+ "movsldup",
+ "clgi",
+ "stgi",
+ "vmcall",
+ "vmclear",
+ "vmfunc",
+ "vmlaunch",
+ "vmload",
+ "vmmcall",
+ "vmptrld",
+ "vmptrst",
+ "vmread",
+ "vmresume",
+ "vmrun",
+ "vmsave",
+ "vmwrite",
+ "vmxoff",
+ "vmxon",
+ "invept",
+ "invvpid",
+ "pvalidate",
+ "rmpadjust",
+ "vmgexit",
+ "pabsb",
+ "pabsw",
+ "pabsd",
+ "palignr",
+ "phaddw",
+ "phaddd",
+ "phaddsw",
+ "phsubw",
+ "phsubd",
+ "phsubsw",
+ "pmaddubsw",
+ "pmulhrsw",
+ "pshufb",
+ "psignb",
+ "psignw",
+ "psignd",
+ "extrq",
+ "insertq",
+ "movntsd",
+ "movntss",
+ "lzcnt",
+ "blendpd",
+ "blendps",
+ "blendvpd",
+ "blendvps",
+ "dppd",
+ "dpps",
+ "extractps",
+ "insertps",
+ "movntdqa",
+ "mpsadbw",
+ "packusdw",
+ "pblendvb",
+ "pblendw",
+ "pcmpeqq",
+ "pextrb",
+ "pextrd",
+ "pextrq",
+ "phminposuw",
+ "pinsrb",
+ "pinsrd",
+ "pinsrq",
+ "pmaxsb",
+ "pmaxsd",
+ "pmaxud",
+ "pmaxuw",
+ "pminsb",
+ "pminsd",
+ "pminud",
+ "pminuw",
+ "pmovsxbw",
+ "pmovsxbd",
+ "pmovsxbq",
+ "pmovsxwd",
+ "pmovsxwq",
+ "pmovsxdq",
+ "pmovzxbw",
+ "pmovzxbd",
+ "pmovzxbq",
+ "pmovzxwd",
+ "pmovzxwq",
+ "pmovzxdq",
+ "pmuldq",
+ "pmulld",
+ "ptest",
+ "roundpd",
+ "roundps",
+ "roundsd",
+ "roundss",
+ "crc32",
+ "pcmpestri",
+ "pcmpestrm",
+ "pcmpistri",
+ "pcmpistrm",
+ "pcmpgtq",
+ "popcnt",
+ "getsec",
+ "pfrcpv",
+ "pfrsqrtv",
+ "movbe",
+ "aesenc",
+ "aesenclast",
+ "aesdec",
+ "aesdeclast",
+ "aesimc",
+ "aeskeygenassist",
+ "vaesenc",
+ "vaesenclast",
+ "vaesdec",
+ "vaesdeclast",
+ "vaesimc",
+ "vaeskeygenassist",
+ "vaddpd",
+ "vaddps",
+ "vaddsd",
+ "vaddss",
+ "vaddsubpd",
+ "vaddsubps",
+ "vandpd",
+ "vandps",
+ "vandnpd",
+ "vandnps",
+ "vblendpd",
+ "vblendps",
+ "vblendvpd",
+ "vblendvps",
+ "vbroadcastss",
+ "vbroadcastsd",
+ "vbroadcastf128",
+ "vcmpeq_ospd",
+ "vcmpeqpd",
+ "vcmplt_ospd",
+ "vcmpltpd",
+ "vcmple_ospd",
+ "vcmplepd",
+ "vcmpunord_qpd",
+ "vcmpunordpd",
+ "vcmpneq_uqpd",
+ "vcmpneqpd",
+ "vcmpnlt_uspd",
+ "vcmpnltpd",
+ "vcmpnle_uspd",
+ "vcmpnlepd",
+ "vcmpord_qpd",
+ "vcmpordpd",
+ "vcmpeq_uqpd",
+ "vcmpnge_uspd",
+ "vcmpngepd",
+ "vcmpngt_uspd",
+ "vcmpngtpd",
+ "vcmpfalse_oqpd",
+ "vcmpfalsepd",
+ "vcmpneq_oqpd",
+ "vcmpge_ospd",
+ "vcmpgepd",
+ "vcmpgt_ospd",
+ "vcmpgtpd",
+ "vcmptrue_uqpd",
+ "vcmptruepd",
+ "vcmplt_oqpd",
+ "vcmple_oqpd",
+ "vcmpunord_spd",
+ "vcmpneq_uspd",
+ "vcmpnlt_uqpd",
+ "vcmpnle_uqpd",
+ "vcmpord_spd",
+ "vcmpeq_uspd",
+ "vcmpnge_uqpd",
+ "vcmpngt_uqpd",
+ "vcmpfalse_ospd",
+ "vcmpneq_ospd",
+ "vcmpge_oqpd",
+ "vcmpgt_oqpd",
+ "vcmptrue_uspd",
+ "vcmppd",
+ "vcmpeq_osps",
+ "vcmpeqps",
+ "vcmplt_osps",
+ "vcmpltps",
+ "vcmple_osps",
+ "vcmpleps",
+ "vcmpunord_qps",
+ "vcmpunordps",
+ "vcmpneq_uqps",
+ "vcmpneqps",
+ "vcmpnlt_usps",
+ "vcmpnltps",
+ "vcmpnle_usps",
+ "vcmpnleps",
+ "vcmpord_qps",
+ "vcmpordps",
+ "vcmpeq_uqps",
+ "vcmpnge_usps",
+ "vcmpngeps",
+ "vcmpngt_usps",
+ "vcmpngtps",
+ "vcmpfalse_oqps",
+ "vcmpfalseps",
+ "vcmpneq_oqps",
+ "vcmpge_osps",
+ "vcmpgeps",
+ "vcmpgt_osps",
+ "vcmpgtps",
+ "vcmptrue_uqps",
+ "vcmptrueps",
+ "vcmplt_oqps",
+ "vcmple_oqps",
+ "vcmpunord_sps",
+ "vcmpneq_usps",
+ "vcmpnlt_uqps",
+ "vcmpnle_uqps",
+ "vcmpord_sps",
+ "vcmpeq_usps",
+ "vcmpnge_uqps",
+ "vcmpngt_uqps",
+ "vcmpfalse_osps",
+ "vcmpneq_osps",
+ "vcmpge_oqps",
+ "vcmpgt_oqps",
+ "vcmptrue_usps",
+ "vcmpps",
+ "vcmpeq_ossd",
+ "vcmpeqsd",
+ "vcmplt_ossd",
+ "vcmpltsd",
+ "vcmple_ossd",
+ "vcmplesd",
+ "vcmpunord_qsd",
+ "vcmpunordsd",
+ "vcmpneq_uqsd",
+ "vcmpneqsd",
+ "vcmpnlt_ussd",
+ "vcmpnltsd",
+ "vcmpnle_ussd",
+ "vcmpnlesd",
+ "vcmpord_qsd",
+ "vcmpordsd",
+ "vcmpeq_uqsd",
+ "vcmpnge_ussd",
+ "vcmpngesd",
+ "vcmpngt_ussd",
+ "vcmpngtsd",
+ "vcmpfalse_oqsd",
+ "vcmpfalsesd",
+ "vcmpneq_oqsd",
+ "vcmpge_ossd",
+ "vcmpgesd",
+ "vcmpgt_ossd",
+ "vcmpgtsd",
+ "vcmptrue_uqsd",
+ "vcmptruesd",
+ "vcmplt_oqsd",
+ "vcmple_oqsd",
+ "vcmpunord_ssd",
+ "vcmpneq_ussd",
+ "vcmpnlt_uqsd",
+ "vcmpnle_uqsd",
+ "vcmpord_ssd",
+ "vcmpeq_ussd",
+ "vcmpnge_uqsd",
+ "vcmpngt_uqsd",
+ "vcmpfalse_ossd",
+ "vcmpneq_ossd",
+ "vcmpge_oqsd",
+ "vcmpgt_oqsd",
+ "vcmptrue_ussd",
+ "vcmpsd",
+ "vcmpeq_osss",
+ "vcmpeqss",
+ "vcmplt_osss",
+ "vcmpltss",
+ "vcmple_osss",
+ "vcmpless",
+ "vcmpunord_qss",
+ "vcmpunordss",
+ "vcmpneq_uqss",
+ "vcmpneqss",
+ "vcmpnlt_usss",
+ "vcmpnltss",
+ "vcmpnle_usss",
+ "vcmpnless",
+ "vcmpord_qss",
+ "vcmpordss",
+ "vcmpeq_uqss",
+ "vcmpnge_usss",
+ "vcmpngess",
+ "vcmpngt_usss",
+ "vcmpngtss",
+ "vcmpfalse_oqss",
+ "vcmpfalsess",
+ "vcmpneq_oqss",
+ "vcmpge_osss",
+ "vcmpgess",
+ "vcmpgt_osss",
+ "vcmpgtss",
+ "vcmptrue_uqss",
+ "vcmptruess",
+ "vcmplt_oqss",
+ "vcmple_oqss",
+ "vcmpunord_sss",
+ "vcmpneq_usss",
+ "vcmpnlt_uqss",
+ "vcmpnle_uqss",
+ "vcmpord_sss",
+ "vcmpeq_usss",
+ "vcmpnge_uqss",
+ "vcmpngt_uqss",
+ "vcmpfalse_osss",
+ "vcmpneq_osss",
+ "vcmpge_oqss",
+ "vcmpgt_oqss",
+ "vcmptrue_usss",
+ "vcmpss",
+ "vcomisd",
+ "vcomiss",
+ "vcvtdq2pd",
+ "vcvtdq2ps",
+ "vcvtpd2dq",
+ "vcvtpd2ps",
+ "vcvtps2dq",
+ "vcvtps2pd",
+ "vcvtsd2si",
+ "vcvtsd2ss",
+ "vcvtsi2sd",
+ "vcvtsi2ss",
+ "vcvtss2sd",
+ "vcvtss2si",
+ "vcvttpd2dq",
+ "vcvttps2dq",
+ "vcvttsd2si",
+ "vcvttss2si",
+ "vdivpd",
+ "vdivps",
+ "vdivsd",
+ "vdivss",
+ "vdppd",
+ "vdpps",
+ "vextractf128",
+ "vextractps",
+ "vhaddpd",
+ "vhaddps",
+ "vhsubpd",
+ "vhsubps",
+ "vinsertf128",
+ "vinsertps",
+ "vlddqu",
+ "vldqqu",
+ "vldmxcsr",
+ "vmaskmovdqu",
+ "vmaskmovps",
+ "vmaskmovpd",
+ "vmaxpd",
+ "vmaxps",
+ "vmaxsd",
+ "vmaxss",
+ "vminpd",
+ "vminps",
+ "vminsd",
+ "vminss",
+ "vmovapd",
+ "vmovaps",
+ "vmovd",
+ "vmovq",
+ "vmovddup",
+ "vmovdqa",
+ "vmovqqa",
+ "vmovdqu",
+ "vmovqqu",
+ "vmovhlps",
+ "vmovhpd",
+ "vmovhps",
+ "vmovlhps",
+ "vmovlpd",
+ "vmovlps",
+ "vmovmskpd",
+ "vmovmskps",
+ "vmovntdq",
+ "vmovntqq",
+ "vmovntdqa",
+ "vmovntpd",
+ "vmovntps",
+ "vmovsd",
+ "vmovshdup",
+ "vmovsldup",
+ "vmovss",
+ "vmovupd",
+ "vmovups",
+ "vmpsadbw",
+ "vmulpd",
+ "vmulps",
+ "vmulsd",
+ "vmulss",
+ "vorpd",
+ "vorps",
+ "vpabsb",
+ "vpabsw",
+ "vpabsd",
+ "vpacksswb",
+ "vpackssdw",
+ "vpackuswb",
+ "vpackusdw",
+ "vpaddb",
+ "vpaddw",
+ "vpaddd",
+ "vpaddq",
+ "vpaddsb",
+ "vpaddsw",
+ "vpaddusb",
+ "vpaddusw",
+ "vpalignr",
+ "vpand",
+ "vpandn",
+ "vpavgb",
+ "vpavgw",
+ "vpblendvb",
+ "vpblendw",
+ "vpcmpestri",
+ "vpcmpestrm",
+ "vpcmpistri",
+ "vpcmpistrm",
+ "vpcmpeqb",
+ "vpcmpeqw",
+ "vpcmpeqd",
+ "vpcmpeqq",
+ "vpcmpgtb",
+ "vpcmpgtw",
+ "vpcmpgtd",
+ "vpcmpgtq",
+ "vpermilpd",
+ "vpermilps",
+ "vperm2f128",
+ "vpextrb",
+ "vpextrw",
+ "vpextrd",
+ "vpextrq",
+ "vphaddw",
+ "vphaddd",
+ "vphaddsw",
+ "vphminposuw",
+ "vphsubw",
+ "vphsubd",
+ "vphsubsw",
+ "vpinsrb",
+ "vpinsrw",
+ "vpinsrd",
+ "vpinsrq",
+ "vpmaddwd",
+ "vpmaddubsw",
+ "vpmaxsb",
+ "vpmaxsw",
+ "vpmaxsd",
+ "vpmaxub",
+ "vpmaxuw",
+ "vpmaxud",
+ "vpminsb",
+ "vpminsw",
+ "vpminsd",
+ "vpminub",
+ "vpminuw",
+ "vpminud",
+ "vpmovmskb",
+ "vpmovsxbw",
+ "vpmovsxbd",
+ "vpmovsxbq",
+ "vpmovsxwd",
+ "vpmovsxwq",
+ "vpmovsxdq",
+ "vpmovzxbw",
+ "vpmovzxbd",
+ "vpmovzxbq",
+ "vpmovzxwd",
+ "vpmovzxwq",
+ "vpmovzxdq",
+ "vpmulhuw",
+ "vpmulhrsw",
+ "vpmulhw",
+ "vpmullw",
+ "vpmulld",
+ "vpmuludq",
+ "vpmuldq",
+ "vpor",
+ "vpsadbw",
+ "vpshufb",
+ "vpshufd",
+ "vpshufhw",
+ "vpshuflw",
+ "vpsignb",
+ "vpsignw",
+ "vpsignd",
+ "vpslldq",
+ "vpsrldq",
+ "vpsllw",
+ "vpslld",
+ "vpsllq",
+ "vpsraw",
+ "vpsrad",
+ "vpsrlw",
+ "vpsrld",
+ "vpsrlq",
+ "vptest",
+ "vpsubb",
+ "vpsubw",
+ "vpsubd",
+ "vpsubq",
+ "vpsubsb",
+ "vpsubsw",
+ "vpsubusb",
+ "vpsubusw",
+ "vpunpckhbw",
+ "vpunpckhwd",
+ "vpunpckhdq",
+ "vpunpckhqdq",
+ "vpunpcklbw",
+ "vpunpcklwd",
+ "vpunpckldq",
+ "vpunpcklqdq",
+ "vpxor",
+ "vrcpps",
+ "vrcpss",
+ "vrsqrtps",
+ "vrsqrtss",
+ "vroundpd",
+ "vroundps",
+ "vroundsd",
+ "vroundss",
+ "vshufpd",
+ "vshufps",
+ "vsqrtpd",
+ "vsqrtps",
+ "vsqrtsd",
+ "vsqrtss",
+ "vstmxcsr",
+ "vsubpd",
+ "vsubps",
+ "vsubsd",
+ "vsubss",
+ "vtestps",
+ "vtestpd",
+ "vucomisd",
+ "vucomiss",
+ "vunpckhpd",
+ "vunpckhps",
+ "vunpcklpd",
+ "vunpcklps",
+ "vxorpd",
+ "vxorps",
+ "vzeroall",
+ "vzeroupper",
+ "pclmullqlqdq",
+ "pclmulhqlqdq",
+ "pclmullqhqdq",
+ "pclmulhqhqdq",
+ "pclmulqdq",
+ "vpclmullqlqdq",
+ "vpclmulhqlqdq",
+ "vpclmullqhqdq",
+ "vpclmulhqhqdq",
+ "vpclmulqdq",
+ "vfmadd132ps",
+ "vfmadd132pd",
+ "vfmadd312ps",
+ "vfmadd312pd",
+ "vfmadd213ps",
+ "vfmadd213pd",
+ "vfmadd123ps",
+ "vfmadd123pd",
+ "vfmadd231ps",
+ "vfmadd231pd",
+ "vfmadd321ps",
+ "vfmadd321pd",
+ "vfmaddsub132ps",
+ "vfmaddsub132pd",
+ "vfmaddsub312ps",
+ "vfmaddsub312pd",
+ "vfmaddsub213ps",
+ "vfmaddsub213pd",
+ "vfmaddsub123ps",
+ "vfmaddsub123pd",
+ "vfmaddsub231ps",
+ "vfmaddsub231pd",
+ "vfmaddsub321ps",
+ "vfmaddsub321pd",
+ "vfmsub132ps",
+ "vfmsub132pd",
+ "vfmsub312ps",
+ "vfmsub312pd",
+ "vfmsub213ps",
+ "vfmsub213pd",
+ "vfmsub123ps",
+ "vfmsub123pd",
+ "vfmsub231ps",
+ "vfmsub231pd",
+ "vfmsub321ps",
+ "vfmsub321pd",
+ "vfmsubadd132ps",
+ "vfmsubadd132pd",
+ "vfmsubadd312ps",
+ "vfmsubadd312pd",
+ "vfmsubadd213ps",
+ "vfmsubadd213pd",
+ "vfmsubadd123ps",
+ "vfmsubadd123pd",
+ "vfmsubadd231ps",
+ "vfmsubadd231pd",
+ "vfmsubadd321ps",
+ "vfmsubadd321pd",
+ "vfnmadd132ps",
+ "vfnmadd132pd",
+ "vfnmadd312ps",
+ "vfnmadd312pd",
+ "vfnmadd213ps",
+ "vfnmadd213pd",
+ "vfnmadd123ps",
+ "vfnmadd123pd",
+ "vfnmadd231ps",
+ "vfnmadd231pd",
+ "vfnmadd321ps",
+ "vfnmadd321pd",
+ "vfnmsub132ps",
+ "vfnmsub132pd",
+ "vfnmsub312ps",
+ "vfnmsub312pd",
+ "vfnmsub213ps",
+ "vfnmsub213pd",
+ "vfnmsub123ps",
+ "vfnmsub123pd",
+ "vfnmsub231ps",
+ "vfnmsub231pd",
+ "vfnmsub321ps",
+ "vfnmsub321pd",
+ "vfmadd132ss",
+ "vfmadd132sd",
+ "vfmadd312ss",
+ "vfmadd312sd",
+ "vfmadd213ss",
+ "vfmadd213sd",
+ "vfmadd123ss",
+ "vfmadd123sd",
+ "vfmadd231ss",
+ "vfmadd231sd",
+ "vfmadd321ss",
+ "vfmadd321sd",
+ "vfmsub132ss",
+ "vfmsub132sd",
+ "vfmsub312ss",
+ "vfmsub312sd",
+ "vfmsub213ss",
+ "vfmsub213sd",
+ "vfmsub123ss",
+ "vfmsub123sd",
+ "vfmsub231ss",
+ "vfmsub231sd",
+ "vfmsub321ss",
+ "vfmsub321sd",
+ "vfnmadd132ss",
+ "vfnmadd132sd",
+ "vfnmadd312ss",
+ "vfnmadd312sd",
+ "vfnmadd213ss",
+ "vfnmadd213sd",
+ "vfnmadd123ss",
+ "vfnmadd123sd",
+ "vfnmadd231ss",
+ "vfnmadd231sd",
+ "vfnmadd321ss",
+ "vfnmadd321sd",
+ "vfnmsub132ss",
+ "vfnmsub132sd",
+ "vfnmsub312ss",
+ "vfnmsub312sd",
+ "vfnmsub213ss",
+ "vfnmsub213sd",
+ "vfnmsub123ss",
+ "vfnmsub123sd",
+ "vfnmsub231ss",
+ "vfnmsub231sd",
+ "vfnmsub321ss",
+ "vfnmsub321sd",
+ "rdfsbase",
+ "rdgsbase",
+ "rdrand",
+ "wrfsbase",
+ "wrgsbase",
+ "vcvtph2ps",
+ "vcvtps2ph",
+ "adcx",
+ "adox",
+ "rdseed",
+ "clac",
+ "stac",
+ "xstore",
+ "xcryptecb",
+ "xcryptcbc",
+ "xcryptctr",
+ "xcryptcfb",
+ "xcryptofb",
+ "montmul",
+ "xsha1",
+ "xsha256",
+ "llwpcb",
+ "slwpcb",
+ "lwpval",
+ "lwpins",
+ "vfmaddpd",
+ "vfmaddps",
+ "vfmaddsd",
+ "vfmaddss",
+ "vfmaddsubpd",
+ "vfmaddsubps",
+ "vfmsubaddpd",
+ "vfmsubaddps",
+ "vfmsubpd",
+ "vfmsubps",
+ "vfmsubsd",
+ "vfmsubss",
+ "vfnmaddpd",
+ "vfnmaddps",
+ "vfnmaddsd",
+ "vfnmaddss",
+ "vfnmsubpd",
+ "vfnmsubps",
+ "vfnmsubsd",
+ "vfnmsubss",
+ "vfrczpd",
+ "vfrczps",
+ "vfrczsd",
+ "vfrczss",
+ "vpcmov",
+ "vpcomb",
+ "vpcomd",
+ "vpcomq",
+ "vpcomub",
+ "vpcomud",
+ "vpcomuq",
+ "vpcomuw",
+ "vpcomw",
+ "vphaddbd",
+ "vphaddbq",
+ "vphaddbw",
+ "vphadddq",
+ "vphaddubd",
+ "vphaddubq",
+ "vphaddubw",
+ "vphaddudq",
+ "vphadduwd",
+ "vphadduwq",
+ "vphaddwd",
+ "vphaddwq",
+ "vphsubbw",
+ "vphsubdq",
+ "vphsubwd",
+ "vpmacsdd",
+ "vpmacsdqh",
+ "vpmacsdql",
+ "vpmacssdd",
+ "vpmacssdqh",
+ "vpmacssdql",
+ "vpmacsswd",
+ "vpmacssww",
+ "vpmacswd",
+ "vpmacsww",
+ "vpmadcsswd",
+ "vpmadcswd",
+ "vpperm",
+ "vprotb",
+ "vprotd",
+ "vprotq",
+ "vprotw",
+ "vpshab",
+ "vpshad",
+ "vpshaq",
+ "vpshaw",
+ "vpshlb",
+ "vpshld",
+ "vpshlq",
+ "vpshlw",
+ "vbroadcasti128",
+ "vpblendd",
+ "vpbroadcastb",
+ "vpbroadcastw",
+ "vpbroadcastd",
+ "vpbroadcastq",
+ "vpermd",
+ "vpermpd",
+ "vpermps",
+ "vpermq",
+ "vperm2i128",
+ "vextracti128",
+ "vinserti128",
+ "vpmaskmovd",
+ "vpmaskmovq",
+ "vpsllvd",
+ "vpsllvq",
+ "vpsravd",
+ "vpsrlvd",
+ "vpsrlvq",
+ "vgatherdpd",
+ "vgatherqpd",
+ "vgatherdps",
+ "vgatherqps",
+ "vpgatherdd",
+ "vpgatherqd",
+ "vpgatherdq",
+ "vpgatherqq",
+ "xabort",
+ "xbegin",
+ "xend",
+ "xtest",
+ "andn",
+ "bextr",
+ "blci",
+ "blcic",
+ "blsi",
+ "blsic",
+ "blcfill",
+ "blsfill",
+ "blcmsk",
+ "blsmsk",
+ "blsr",
+ "blcs",
+ "bzhi",
+ "mulx",
+ "pdep",
+ "pext",
+ "rorx",
+ "sarx",
+ "shlx",
+ "shrx",
+ "tzcnt",
+ "tzmsk",
+ "t1mskc",
+ "prefetchwt1",
+ "bndmk",
+ "bndcl",
+ "bndcu",
+ "bndcn",
+ "bndmov",
+ "bndldx",
+ "bndstx",
+ "sha1msg1",
+ "sha1msg2",
+ "sha1nexte",
+ "sha1rnds4",
+ "sha256msg1",
+ "sha256msg2",
+ "sha256rnds2",
+ "vbcstnebf16ps",
+ "vbcstnesh2ps",
+ "vcvtneebf162ps",
+ "vcvtneeph2ps",
+ "vcvtneobf162ps",
+ "vcvtneoph2ps",
+ "vcvtneps2bf16",
+ "vpdpbssd",
+ "vpdpbssds",
+ "vpdpbsud",
+ "vpdpbsuds",
+ "vpdpbuud",
+ "vpdpbuuds",
+ "vpmadd52huq",
+ "vpmadd52luq",
+ "kaddb",
+ "kaddd",
+ "kaddq",
+ "kaddw",
+ "kandb",
+ "kandd",
+ "kandnb",
+ "kandnd",
+ "kandnq",
+ "kandnw",
+ "kandq",
+ "kandw",
+ "kmovb",
+ "kmovd",
+ "kmovq",
+ "kmovw",
+ "knotb",
+ "knotd",
+ "knotq",
+ "knotw",
+ "korb",
+ "kord",
+ "korq",
+ "korw",
+ "kortestb",
+ "kortestd",
+ "kortestq",
+ "kortestw",
+ "kshiftlb",
+ "kshiftld",
+ "kshiftlq",
+ "kshiftlw",
+ "kshiftrb",
+ "kshiftrd",
+ "kshiftrq",
+ "kshiftrw",
+ "ktestb",
+ "ktestd",
+ "ktestq",
+ "ktestw",
+ "kunpckbw",
+ "kunpckdq",
+ "kunpckwd",
+ "kxnorb",
+ "kxnord",
+ "kxnorq",
+ "kxnorw",
+ "kxorb",
+ "kxord",
+ "kxorq",
+ "kxorw",
+ "kadd",
+ "kand",
+ "kandn",
+ "kmov",
+ "knot",
+ "kor",
+ "kortest",
+ "kshiftl",
+ "kshiftr",
+ "ktest",
+ "kunpck",
+ "kxnor",
+ "kxor",
+ "valignd",
+ "valignq",
+ "vblendmpd",
+ "vblendmps",
+ "vbroadcastf32x2",
+ "vbroadcastf32x4",
+ "vbroadcastf32x8",
+ "vbroadcastf64x2",
+ "vbroadcastf64x4",
+ "vbroadcasti32x2",
+ "vbroadcasti32x4",
+ "vbroadcasti32x8",
+ "vbroadcasti64x2",
+ "vbroadcasti64x4",
+ "vcmpeq_oqpd",
+ "vcmpeq_oqps",
+ "vcmpeq_oqsd",
+ "vcmpeq_oqss",
+ "vcompresspd",
+ "vcompressps",
+ "vcvtpd2qq",
+ "vcvtpd2udq",
+ "vcvtpd2uqq",
+ "vcvtps2qq",
+ "vcvtps2udq",
+ "vcvtps2uqq",
+ "vcvtqq2pd",
+ "vcvtqq2ps",
+ "vcvtsd2usi",
+ "vcvtss2usi",
+ "vcvttpd2qq",
+ "vcvttpd2udq",
+ "vcvttpd2uqq",
+ "vcvttps2qq",
+ "vcvttps2udq",
+ "vcvttps2uqq",
+ "vcvttsd2usi",
+ "vcvttss2usi",
+ "vcvtudq2pd",
+ "vcvtudq2ps",
+ "vcvtuqq2pd",
+ "vcvtuqq2ps",
+ "vcvtusi2sd",
+ "vcvtusi2ss",
+ "vdbpsadbw",
+ "vexp2pd",
+ "vexp2ps",
+ "vexpandpd",
+ "vexpandps",
+ "vextractf32x4",
+ "vextractf32x8",
+ "vextractf64x2",
+ "vextractf64x4",
+ "vextracti32x4",
+ "vextracti32x8",
+ "vextracti64x2",
+ "vextracti64x4",
+ "vfixupimmpd",
+ "vfixupimmps",
+ "vfixupimmsd",
+ "vfixupimmss",
+ "vfpclasspd",
+ "vfpclassps",
+ "vfpclasssd",
+ "vfpclassss",
+ "vgatherpf0dpd",
+ "vgatherpf0dps",
+ "vgatherpf0qpd",
+ "vgatherpf0qps",
+ "vgatherpf1dpd",
+ "vgatherpf1dps",
+ "vgatherpf1qpd",
+ "vgatherpf1qps",
+ "vgetexppd",
+ "vgetexpps",
+ "vgetexpsd",
+ "vgetexpss",
+ "vgetmantpd",
+ "vgetmantps",
+ "vgetmantsd",
+ "vgetmantss",
+ "vinsertf32x4",
+ "vinsertf32x8",
+ "vinsertf64x2",
+ "vinsertf64x4",
+ "vinserti32x4",
+ "vinserti32x8",
+ "vinserti64x2",
+ "vinserti64x4",
+ "vmovdqa32",
+ "vmovdqa64",
+ "vmovdqu16",
+ "vmovdqu32",
+ "vmovdqu64",
+ "vmovdqu8",
+ "vpabsq",
+ "vpandd",
+ "vpandnd",
+ "vpandnq",
+ "vpandq",
+ "vpblendmb",
+ "vpblendmd",
+ "vpblendmq",
+ "vpblendmw",
+ "vpbroadcastmb2q",
+ "vpbroadcastmw2d",
+ "vpcmpequb",
+ "vpcmpequd",
+ "vpcmpequq",
+ "vpcmpequw",
+ "vpcmpgeb",
+ "vpcmpged",
+ "vpcmpgeq",
+ "vpcmpgeub",
+ "vpcmpgeud",
+ "vpcmpgeuq",
+ "vpcmpgeuw",
+ "vpcmpgew",
+ "vpcmpgtub",
+ "vpcmpgtud",
+ "vpcmpgtuq",
+ "vpcmpgtuw",
+ "vpcmpleb",
+ "vpcmpled",
+ "vpcmpleq",
+ "vpcmpleub",
+ "vpcmpleud",
+ "vpcmpleuq",
+ "vpcmpleuw",
+ "vpcmplew",
+ "vpcmpltb",
+ "vpcmpltd",
+ "vpcmpltq",
+ "vpcmpltub",
+ "vpcmpltud",
+ "vpcmpltuq",
+ "vpcmpltuw",
+ "vpcmpltw",
+ "vpcmpneqb",
+ "vpcmpneqd",
+ "vpcmpneqq",
+ "vpcmpnequb",
+ "vpcmpnequd",
+ "vpcmpnequq",
+ "vpcmpnequw",
+ "vpcmpneqw",
+ "vpcmpngtb",
+ "vpcmpngtd",
+ "vpcmpngtq",
+ "vpcmpngtub",
+ "vpcmpngtud",
+ "vpcmpngtuq",
+ "vpcmpngtuw",
+ "vpcmpngtw",
+ "vpcmpnleb",
+ "vpcmpnled",
+ "vpcmpnleq",
+ "vpcmpnleub",
+ "vpcmpnleud",
+ "vpcmpnleuq",
+ "vpcmpnleuw",
+ "vpcmpnlew",
+ "vpcmpnltb",
+ "vpcmpnltd",
+ "vpcmpnltq",
+ "vpcmpnltub",
+ "vpcmpnltud",
+ "vpcmpnltuq",
+ "vpcmpnltuw",
+ "vpcmpnltw",
+ "vpcmpb",
+ "vpcmpd",
+ "vpcmpq",
+ "vpcmpub",
+ "vpcmpud",
+ "vpcmpuq",
+ "vpcmpuw",
+ "vpcmpw",
+ "vpcompressd",
+ "vpcompressq",
+ "vpconflictd",
+ "vpconflictq",
+ "vpermb",
+ "vpermi2b",
+ "vpermi2d",
+ "vpermi2pd",
+ "vpermi2ps",
+ "vpermi2q",
+ "vpermi2w",
+ "vpermt2b",
+ "vpermt2d",
+ "vpermt2pd",
+ "vpermt2ps",
+ "vpermt2q",
+ "vpermt2w",
+ "vpermw",
+ "vpexpandd",
+ "vpexpandq",
+ "vplzcntd",
+ "vplzcntq",
+ "vpmaxsq",
+ "vpmaxuq",
+ "vpminsq",
+ "vpminuq",
+ "vpmovb2m",
+ "vpmovd2m",
+ "vpmovdb",
+ "vpmovdw",
+ "vpmovm2b",
+ "vpmovm2d",
+ "vpmovm2q",
+ "vpmovm2w",
+ "vpmovq2m",
+ "vpmovqb",
+ "vpmovqd",
+ "vpmovqw",
+ "vpmovsdb",
+ "vpmovsdw",
+ "vpmovsqb",
+ "vpmovsqd",
+ "vpmovsqw",
+ "vpmovswb",
+ "vpmovusdb",
+ "vpmovusdw",
+ "vpmovusqb",
+ "vpmovusqd",
+ "vpmovusqw",
+ "vpmovuswb",
+ "vpmovw2m",
+ "vpmovwb",
+ "vpmullq",
+ "vpmultishiftqb",
+ "vpord",
+ "vporq",
+ "vprold",
+ "vprolq",
+ "vprolvd",
+ "vprolvq",
+ "vprord",
+ "vprorq",
+ "vprorvd",
+ "vprorvq",
+ "vpscatterdd",
+ "vpscatterdq",
+ "vpscatterqd",
+ "vpscatterqq",
+ "vpsllvw",
+ "vpsraq",
+ "vpsravq",
+ "vpsravw",
+ "vpsrlvw",
+ "vpternlogd",
+ "vpternlogq",
+ "vptestmb",
+ "vptestmd",
+ "vptestmq",
+ "vptestmw",
+ "vptestnmb",
+ "vptestnmd",
+ "vptestnmq",
+ "vptestnmw",
+ "vpxord",
+ "vpxorq",
+ "vrangepd",
+ "vrangeps",
+ "vrangesd",
+ "vrangess",
+ "vrcp14pd",
+ "vrcp14ps",
+ "vrcp14sd",
+ "vrcp14ss",
+ "vrcp28pd",
+ "vrcp28ps",
+ "vrcp28sd",
+ "vrcp28ss",
+ "vreducepd",
+ "vreduceps",
+ "vreducesd",
+ "vreducess",
+ "vrndscalepd",
+ "vrndscaleps",
+ "vrndscalesd",
+ "vrndscaless",
+ "vrsqrt14pd",
+ "vrsqrt14ps",
+ "vrsqrt14sd",
+ "vrsqrt14ss",
+ "vrsqrt28pd",
+ "vrsqrt28ps",
+ "vrsqrt28sd",
+ "vrsqrt28ss",
+ "vscalefpd",
+ "vscalefps",
+ "vscalefsd",
+ "vscalefss",
+ "vscatterdpd",
+ "vscatterdps",
+ "vscatterpf0dpd",
+ "vscatterpf0dps",
+ "vscatterpf0qpd",
+ "vscatterpf0qps",
+ "vscatterpf1dpd",
+ "vscatterpf1dps",
+ "vscatterpf1qpd",
+ "vscatterpf1qps",
+ "vscatterqpd",
+ "vscatterqps",
+ "vshuff32x4",
+ "vshuff64x2",
+ "vshufi32x4",
+ "vshufi64x2",
+ "rdpkru",
+ "wrpkru",
+ "rdpid",
+ "clflushopt",
+ "clwb",
+ "pcommit",
+ "clzero",
+ "ptwrite",
+ "cldemote",
+ "movdiri",
+ "movdir64b",
+ "pconfig",
+ "tpause",
+ "umonitor",
+ "umwait",
+ "wbnoinvd",
+ "gf2p8affineinvqb",
+ "vgf2p8affineinvqb",
+ "gf2p8affineqb",
+ "vgf2p8affineqb",
+ "gf2p8mulb",
+ "vgf2p8mulb",
+ "vpcompressb",
+ "vpcompressw",
+ "vpexpandb",
+ "vpexpandw",
+ "vpshldw",
+ "vpshldd",
+ "vpshldq",
+ "vpshldvw",
+ "vpshldvd",
+ "vpshldvq",
+ "vpshrdw",
+ "vpshrdd",
+ "vpshrdq",
+ "vpshrdvw",
+ "vpshrdvd",
+ "vpshrdvq",
+ "vpdpbusd",
+ "vpdpbusds",
+ "vpdpwssd",
+ "vpdpwssds",
+ "vpopcntb",
+ "vpopcntw",
+ "vpopcntd",
+ "vpopcntq",
+ "vpshufbitqmb",
+ "v4fmaddps",
+ "v4fnmaddps",
+ "v4fmaddss",
+ "v4fnmaddss",
+ "v4dpwssds",
+ "v4dpwssd",
+ "encls",
+ "enclu",
+ "enclv",
+ "clrssbsy",
+ "endbr32",
+ "endbr64",
+ "incsspd",
+ "incsspq",
+ "rdsspd",
+ "rdsspq",
+ "rstorssp",
+ "saveprevssp",
+ "setssbsy",
+ "wrussd",
+ "wrussq",
+ "wrssd",
+ "wrssq",
+ "enqcmd",
+ "enqcmds",
+ "serialize",
+ "xresldtrk",
+ "xsusldtrk",
+ "vcvtne2ps2bf16",
+ "vdpbf16ps",
+ "vp2intersectd",
+ "ldtilecfg",
+ "sttilecfg",
+ "tdpbf16ps",
+ "tdpbssd",
+ "tdpbsud",
+ "tdpbusd",
+ "tdpbuud",
+ "tileloadd",
+ "tileloaddt1",
+ "tilerelease",
+ "tilestored",
+ "tilezero",
+ "vaddph",
+ "vaddsh",
+ "vcmpph",
+ "vcmpsh",
+ "vcomish",
+ "vcvtdq2ph",
+ "vcvtpd2ph",
+ "vcvtph2dq",
+ "vcvtph2pd",
+ "vcvtph2psx",
+ "vcvtph2qq",
+ "vcvtph2udq",
+ "vcvtph2uqq",
+ "vcvtph2uw",
+ "vcvtph2w",
+ "vcvtqq2ph",
+ "vcvtsd2sh",
+ "vcvtsh2sd",
+ "vcvtsh2si",
+ "vcvtsh2ss",
+ "vcvtsh2usi",
+ "vcvtsi2sh",
+ "vcvtss2sh",
+ "vcvttph2dq",
+ "vcvttph2qq",
+ "vcvttph2udq",
+ "vcvttph2uqq",
+ "vcvttph2uw",
+ "vcvttph2w",
+ "vcvttsh2si",
+ "vcvttsh2usi",
+ "vcvtudq2ph",
+ "vcvtuqq2ph",
+ "vcvtusi2sh",
+ "vcvtuw2ph",
+ "vcvtw2ph",
+ "vdivph",
+ "vdivsh",
+ "vfcmaddcph",
+ "vfmaddcph",
+ "vfcmaddcsh",
+ "vfmaddcsh",
+ "vfcmulcpch",
+ "vfmulcpch",
+ "vfcmulcsh",
+ "vfmulcsh",
+ "vfmaddsub132ph",
+ "vfmaddsub213ph",
+ "vfmaddsub231ph",
+ "vfmsubadd132ph",
+ "vfmsubadd213ph",
+ "vfmsubadd231ph",
+ "vpmadd132ph",
+ "vpmadd213ph",
+ "vpmadd231ph",
+ "vfmadd132ph",
+ "vfmadd213ph",
+ "vfmadd231ph",
+ "vpmadd132sh",
+ "vpmadd213sh",
+ "vpmadd231sh",
+ "vpnmadd132sh",
+ "vpnmadd213sh",
+ "vpnmadd231sh",
+ "vpmsub132ph",
+ "vpmsub213ph",
+ "vpmsub231ph",
+ "vfmsub132ph",
+ "vfmsub213ph",
+ "vfmsub231ph",
+ "vpmsub132sh",
+ "vpmsub213sh",
+ "vpmsub231sh",
+ "vpnmsub132sh",
+ "vpnmsub213sh",
+ "vpnmsub231sh",
+ "vfpclassph",
+ "vfpclasssh",
+ "vgetexpph",
+ "vgetexpsh",
+ "vgetmantph",
+ "vgetmantsh",
+ "vgetmaxph",
+ "vgetmaxsh",
+ "vgetminph",
+ "vgetminsh",
+ "vmovsh",
+ "vmovw",
+ "vmulph",
+ "vmulsh",
+ "vrcpph",
+ "vrcpsh",
+ "vreduceph",
+ "vreducesh",
+ "vendscaleph",
+ "vendscalesh",
+ "vrsqrtph",
+ "vrsqrtsh",
+ "vscalefph",
+ "vscalefsh",
+ "vsqrtph",
+ "vsqrtsh",
+ "vsubph",
+ "vsubsh",
+ "vucomish",
+ "aadd",
+ "aand",
+ "axor",
+ "clui",
+ "senduipi",
+ "stui",
+ "testui",
+ "uiret",
+ "cmpaxadd",
+ "cmpaexadd",
+ "cmpbxadd",
+ "cmpbexadd",
+ "cmpcxadd",
+ "cmpexadd",
+ "cmpgxadd",
+ "cmpgexadd",
+ "cmplxadd",
+ "cmplexadd",
+ "cmpnaxadd",
+ "cmpnaexadd",
+ "cmpnbxadd",
+ "cmpnbexadd",
+ "cmpncxadd",
+ "cmpnexadd",
+ "cmpngxadd",
+ "cmpngexadd",
+ "cmpnlxadd",
+ "cmpnlexadd",
+ "cmpnoxadd",
+ "cmpnpxadd",
+ "cmpnsxadd",
+ "cmpnzxadd",
+ "cmpoxadd",
+ "cmppxadd",
+ "cmppexadd",
+ "cmppoxadd",
+ "cmpsxadd",
+ "cmpzxadd",
+ "wrmsrns",
+ "rdmsrlist",
+ "wrmsrlist",
+ "hreset",
+ "hint_nop0",
+ "hint_nop1",
+ "hint_nop2",
+ "hint_nop3",
+ "hint_nop4",
+ "hint_nop5",
+ "hint_nop6",
+ "hint_nop7",
+ "hint_nop8",
+ "hint_nop9",
+ "hint_nop10",
+ "hint_nop11",
+ "hint_nop12",
+ "hint_nop13",
+ "hint_nop14",
+ "hint_nop15",
+ "hint_nop16",
+ "hint_nop17",
+ "hint_nop18",
+ "hint_nop19",
+ "hint_nop20",
+ "hint_nop21",
+ "hint_nop22",
+ "hint_nop23",
+ "hint_nop24",
+ "hint_nop25",
+ "hint_nop26",
+ "hint_nop27",
+ "hint_nop28",
+ "hint_nop29",
+ "hint_nop30",
+ "hint_nop31",
+ "hint_nop32",
+ "hint_nop33",
+ "hint_nop34",
+ "hint_nop35",
+ "hint_nop36",
+ "hint_nop37",
+ "hint_nop38",
+ "hint_nop39",
+ "hint_nop40",
+ "hint_nop41",
+ "hint_nop42",
+ "hint_nop43",
+ "hint_nop44",
+ "hint_nop45",
+ "hint_nop46",
+ "hint_nop47",
+ "hint_nop48",
+ "hint_nop49",
+ "hint_nop50",
+ "hint_nop51",
+ "hint_nop52",
+ "hint_nop53",
+ "hint_nop54",
+ "hint_nop55",
+ "hint_nop56",
+ "hint_nop57",
+ "hint_nop58",
+ "hint_nop59",
+ "hint_nop60",
+ "hint_nop61",
+ "hint_nop62",
+ "hint_nop63",
+};
diff --git a/vere/ext/nasm/x86/regdis.c b/vere/ext/nasm/x86/regdis.c
new file mode 100644
index 0000000..99179d6
--- /dev/null
+++ b/vere/ext/nasm/x86/regdis.c
@@ -0,0 +1,21 @@
+/* automatically generated from ./x86/regs.dat - do not edit */
+
+#include "regdis.h"
+
+const enum reg_enum nasm_rd_bndreg [ 4] = {R_BND0,R_BND1,R_BND2,R_BND3};
+const enum reg_enum nasm_rd_creg [16] = {R_CR0,R_CR1,R_CR2,R_CR3,R_CR4,R_CR5,R_CR6,R_CR7,R_CR8,R_CR9,R_CR10,R_CR11,R_CR12,R_CR13,R_CR14,R_CR15};
+const enum reg_enum nasm_rd_dreg [16] = {R_DR0,R_DR1,R_DR2,R_DR3,R_DR4,R_DR5,R_DR6,R_DR7,R_DR8,R_DR9,R_DR10,R_DR11,R_DR12,R_DR13,R_DR14,R_DR15};
+const enum reg_enum nasm_rd_fpureg [ 8] = {R_ST0,R_ST1,R_ST2,R_ST3,R_ST4,R_ST5,R_ST6,R_ST7};
+const enum reg_enum nasm_rd_mmxreg [ 8] = {R_MM0,R_MM1,R_MM2,R_MM3,R_MM4,R_MM5,R_MM6,R_MM7};
+const enum reg_enum nasm_rd_opmaskreg[ 8] = {R_K0,R_K1,R_K2,R_K3,R_K4,R_K5,R_K6,R_K7};
+const enum reg_enum nasm_rd_reg16 [16] = {R_AX,R_CX,R_DX,R_BX,R_SP,R_BP,R_SI,R_DI,R_R8W,R_R9W,R_R10W,R_R11W,R_R12W,R_R13W,R_R14W,R_R15W};
+const enum reg_enum nasm_rd_reg32 [16] = {R_EAX,R_ECX,R_EDX,R_EBX,R_ESP,R_EBP,R_ESI,R_EDI,R_R8D,R_R9D,R_R10D,R_R11D,R_R12D,R_R13D,R_R14D,R_R15D};
+const enum reg_enum nasm_rd_reg64 [16] = {R_RAX,R_RCX,R_RDX,R_RBX,R_RSP,R_RBP,R_RSI,R_RDI,R_R8,R_R9,R_R10,R_R11,R_R12,R_R13,R_R14,R_R15};
+const enum reg_enum nasm_rd_reg8 [ 8] = {R_AL,R_CL,R_DL,R_BL,R_AH,R_CH,R_DH,R_BH};
+const enum reg_enum nasm_rd_reg8_rex[16] = {R_AL,R_CL,R_DL,R_BL,R_SPL,R_BPL,R_SIL,R_DIL,R_R8B,R_R9B,R_R10B,R_R11B,R_R12B,R_R13B,R_R14B,R_R15B};
+const enum reg_enum nasm_rd_sreg [ 8] = {R_ES,R_CS,R_SS,R_DS,R_FS,R_GS,R_SEGR6,R_SEGR7};
+const enum reg_enum nasm_rd_tmmreg [ 8] = {R_TMM0,R_TMM1,R_TMM2,R_TMM3,R_TMM4,R_TMM5,R_TMM6,R_TMM7};
+const enum reg_enum nasm_rd_treg [ 8] = {R_TR0,R_TR1,R_TR2,R_TR3,R_TR4,R_TR5,R_TR6,R_TR7};
+const enum reg_enum nasm_rd_xmmreg [32] = {R_XMM0,R_XMM1,R_XMM2,R_XMM3,R_XMM4,R_XMM5,R_XMM6,R_XMM7,R_XMM8,R_XMM9,R_XMM10,R_XMM11,R_XMM12,R_XMM13,R_XMM14,R_XMM15,R_XMM16,R_XMM17,R_XMM18,R_XMM19,R_XMM20,R_XMM21,R_XMM22,R_XMM23,R_XMM24,R_XMM25,R_XMM26,R_XMM27,R_XMM28,R_XMM29,R_XMM30,R_XMM31};
+const enum reg_enum nasm_rd_ymmreg [32] = {R_YMM0,R_YMM1,R_YMM2,R_YMM3,R_YMM4,R_YMM5,R_YMM6,R_YMM7,R_YMM8,R_YMM9,R_YMM10,R_YMM11,R_YMM12,R_YMM13,R_YMM14,R_YMM15,R_YMM16,R_YMM17,R_YMM18,R_YMM19,R_YMM20,R_YMM21,R_YMM22,R_YMM23,R_YMM24,R_YMM25,R_YMM26,R_YMM27,R_YMM28,R_YMM29,R_YMM30,R_YMM31};
+const enum reg_enum nasm_rd_zmmreg [32] = {R_ZMM0,R_ZMM1,R_ZMM2,R_ZMM3,R_ZMM4,R_ZMM5,R_ZMM6,R_ZMM7,R_ZMM8,R_ZMM9,R_ZMM10,R_ZMM11,R_ZMM12,R_ZMM13,R_ZMM14,R_ZMM15,R_ZMM16,R_ZMM17,R_ZMM18,R_ZMM19,R_ZMM20,R_ZMM21,R_ZMM22,R_ZMM23,R_ZMM24,R_ZMM25,R_ZMM26,R_ZMM27,R_ZMM28,R_ZMM29,R_ZMM30,R_ZMM31};
diff --git a/vere/ext/nasm/x86/regflags.c b/vere/ext/nasm/x86/regflags.c
new file mode 100644
index 0000000..ef42544
--- /dev/null
+++ b/vere/ext/nasm/x86/regflags.c
@@ -0,0 +1,256 @@
+/* automatically generated from ./x86/regs.dat - do not edit */
+
+#include "tables.h"
+#include "nasm.h"
+
+const opflags_t nasm_reg_flags[] = {
+ 0,
+ REG_HIGH, /* ah */
+ REG_AL, /* al */
+ REG_AX, /* ax */
+ REG_HIGH, /* bh */
+ REG8NA, /* bl */
+ BNDREG, /* bnd0 */
+ BNDREG, /* bnd1 */
+ BNDREG, /* bnd2 */
+ BNDREG, /* bnd3 */
+ REG16NA, /* bp */
+ REG8NA, /* bpl */
+ REG16NA, /* bx */
+ REG_HIGH, /* ch */
+ REG_CL, /* cl */
+ REG_CREG, /* cr0 */
+ REG_CREG, /* cr1 */
+ REG_CREG, /* cr10 */
+ REG_CREG, /* cr11 */
+ REG_CREG, /* cr12 */
+ REG_CREG, /* cr13 */
+ REG_CREG, /* cr14 */
+ REG_CREG, /* cr15 */
+ REG_CREG, /* cr2 */
+ REG_CREG, /* cr3 */
+ REG_CREG, /* cr4 */
+ REG_CREG, /* cr5 */
+ REG_CREG, /* cr6 */
+ REG_CREG, /* cr7 */
+ REG_CREG, /* cr8 */
+ REG_CREG, /* cr9 */
+ REG_CS, /* cs */
+ REG_CX, /* cx */
+ REG_HIGH, /* dh */
+ REG16NA, /* di */
+ REG8NA, /* dil */
+ REG_DL, /* dl */
+ REG_DREG, /* dr0 */
+ REG_DREG, /* dr1 */
+ REG_DREG, /* dr10 */
+ REG_DREG, /* dr11 */
+ REG_DREG, /* dr12 */
+ REG_DREG, /* dr13 */
+ REG_DREG, /* dr14 */
+ REG_DREG, /* dr15 */
+ REG_DREG, /* dr2 */
+ REG_DREG, /* dr3 */
+ REG_DREG, /* dr4 */
+ REG_DREG, /* dr5 */
+ REG_DREG, /* dr6 */
+ REG_DREG, /* dr7 */
+ REG_DREG, /* dr8 */
+ REG_DREG, /* dr9 */
+ REG_DS, /* ds */
+ REG_DX, /* dx */
+ REG_EAX, /* eax */
+ REG32NA, /* ebp */
+ REG32NA, /* ebx */
+ REG_ECX, /* ecx */
+ REG32NA, /* edi */
+ REG_EDX, /* edx */
+ REG_ES, /* es */
+ REG32NA, /* esi */
+ REG32NA, /* esp */
+ REG_FS, /* fs */
+ REG_GS, /* gs */
+ OPMASK0, /* k0 */
+ OPMASKREG, /* k1 */
+ OPMASKREG, /* k2 */
+ OPMASKREG, /* k3 */
+ OPMASKREG, /* k4 */
+ OPMASKREG, /* k5 */
+ OPMASKREG, /* k6 */
+ OPMASKREG, /* k7 */
+ MMXREG, /* mm0 */
+ MMXREG, /* mm1 */
+ MMXREG, /* mm2 */
+ MMXREG, /* mm3 */
+ MMXREG, /* mm4 */
+ MMXREG, /* mm5 */
+ MMXREG, /* mm6 */
+ MMXREG, /* mm7 */
+ REG64NA, /* r10 */
+ REG8NA, /* r10b */
+ REG32NA, /* r10d */
+ REG16NA, /* r10w */
+ REG64NA, /* r11 */
+ REG8NA, /* r11b */
+ REG32NA, /* r11d */
+ REG16NA, /* r11w */
+ REG64NA, /* r12 */
+ REG8NA, /* r12b */
+ REG32NA, /* r12d */
+ REG16NA, /* r12w */
+ REG64NA, /* r13 */
+ REG8NA, /* r13b */
+ REG32NA, /* r13d */
+ REG16NA, /* r13w */
+ REG64NA, /* r14 */
+ REG8NA, /* r14b */
+ REG32NA, /* r14d */
+ REG16NA, /* r14w */
+ REG64NA, /* r15 */
+ REG8NA, /* r15b */
+ REG32NA, /* r15d */
+ REG16NA, /* r15w */
+ REG64NA, /* r8 */
+ REG8NA, /* r8b */
+ REG32NA, /* r8d */
+ REG16NA, /* r8w */
+ REG64NA, /* r9 */
+ REG8NA, /* r9b */
+ REG32NA, /* r9d */
+ REG16NA, /* r9w */
+ REG_RAX, /* rax */
+ REG64NA, /* rbp */
+ REG64NA, /* rbx */
+ REG_RCX, /* rcx */
+ REG64NA, /* rdi */
+ REG_RDX, /* rdx */
+ REG64NA, /* rsi */
+ REG64NA, /* rsp */
+ REG_SEG67, /* segr6 */
+ REG_SEG67, /* segr7 */
+ REG16NA, /* si */
+ REG8NA, /* sil */
+ REG16NA, /* sp */
+ REG8NA, /* spl */
+ REG_SS, /* ss */
+ FPU0, /* st0 */
+ FPUREG, /* st1 */
+ FPUREG, /* st2 */
+ FPUREG, /* st3 */
+ FPUREG, /* st4 */
+ FPUREG, /* st5 */
+ FPUREG, /* st6 */
+ FPUREG, /* st7 */
+ TMMREG, /* tmm0 */
+ TMMREG, /* tmm1 */
+ TMMREG, /* tmm2 */
+ TMMREG, /* tmm3 */
+ TMMREG, /* tmm4 */
+ TMMREG, /* tmm5 */
+ TMMREG, /* tmm6 */
+ TMMREG, /* tmm7 */
+ REG_TREG, /* tr0 */
+ REG_TREG, /* tr1 */
+ REG_TREG, /* tr2 */
+ REG_TREG, /* tr3 */
+ REG_TREG, /* tr4 */
+ REG_TREG, /* tr5 */
+ REG_TREG, /* tr6 */
+ REG_TREG, /* tr7 */
+ XMM0, /* xmm0 */
+ XMM_L16, /* xmm1 */
+ XMM_L16, /* xmm10 */
+ XMM_L16, /* xmm11 */
+ XMM_L16, /* xmm12 */
+ XMM_L16, /* xmm13 */
+ XMM_L16, /* xmm14 */
+ XMM_L16, /* xmm15 */
+ XMMREG, /* xmm16 */
+ XMMREG, /* xmm17 */
+ XMMREG, /* xmm18 */
+ XMMREG, /* xmm19 */
+ XMM_L16, /* xmm2 */
+ XMMREG, /* xmm20 */
+ XMMREG, /* xmm21 */
+ XMMREG, /* xmm22 */
+ XMMREG, /* xmm23 */
+ XMMREG, /* xmm24 */
+ XMMREG, /* xmm25 */
+ XMMREG, /* xmm26 */
+ XMMREG, /* xmm27 */
+ XMMREG, /* xmm28 */
+ XMMREG, /* xmm29 */
+ XMM_L16, /* xmm3 */
+ XMMREG, /* xmm30 */
+ XMMREG, /* xmm31 */
+ XMM_L16, /* xmm4 */
+ XMM_L16, /* xmm5 */
+ XMM_L16, /* xmm6 */
+ XMM_L16, /* xmm7 */
+ XMM_L16, /* xmm8 */
+ XMM_L16, /* xmm9 */
+ YMM0, /* ymm0 */
+ YMM_L16, /* ymm1 */
+ YMM_L16, /* ymm10 */
+ YMM_L16, /* ymm11 */
+ YMM_L16, /* ymm12 */
+ YMM_L16, /* ymm13 */
+ YMM_L16, /* ymm14 */
+ YMM_L16, /* ymm15 */
+ YMMREG, /* ymm16 */
+ YMMREG, /* ymm17 */
+ YMMREG, /* ymm18 */
+ YMMREG, /* ymm19 */
+ YMM_L16, /* ymm2 */
+ YMMREG, /* ymm20 */
+ YMMREG, /* ymm21 */
+ YMMREG, /* ymm22 */
+ YMMREG, /* ymm23 */
+ YMMREG, /* ymm24 */
+ YMMREG, /* ymm25 */
+ YMMREG, /* ymm26 */
+ YMMREG, /* ymm27 */
+ YMMREG, /* ymm28 */
+ YMMREG, /* ymm29 */
+ YMM_L16, /* ymm3 */
+ YMMREG, /* ymm30 */
+ YMMREG, /* ymm31 */
+ YMM_L16, /* ymm4 */
+ YMM_L16, /* ymm5 */
+ YMM_L16, /* ymm6 */
+ YMM_L16, /* ymm7 */
+ YMM_L16, /* ymm8 */
+ YMM_L16, /* ymm9 */
+ ZMM0, /* zmm0 */
+ ZMM_L16, /* zmm1 */
+ ZMM_L16, /* zmm10 */
+ ZMM_L16, /* zmm11 */
+ ZMM_L16, /* zmm12 */
+ ZMM_L16, /* zmm13 */
+ ZMM_L16, /* zmm14 */
+ ZMM_L16, /* zmm15 */
+ ZMMREG, /* zmm16 */
+ ZMMREG, /* zmm17 */
+ ZMMREG, /* zmm18 */
+ ZMMREG, /* zmm19 */
+ ZMM_L16, /* zmm2 */
+ ZMMREG, /* zmm20 */
+ ZMMREG, /* zmm21 */
+ ZMMREG, /* zmm22 */
+ ZMMREG, /* zmm23 */
+ ZMMREG, /* zmm24 */
+ ZMMREG, /* zmm25 */
+ ZMMREG, /* zmm26 */
+ ZMMREG, /* zmm27 */
+ ZMMREG, /* zmm28 */
+ ZMMREG, /* zmm29 */
+ ZMM_L16, /* zmm3 */
+ ZMMREG, /* zmm30 */
+ ZMMREG, /* zmm31 */
+ ZMM_L16, /* zmm4 */
+ ZMM_L16, /* zmm5 */
+ ZMM_L16, /* zmm6 */
+ ZMM_L16, /* zmm7 */
+ ZMM_L16, /* zmm8 */
+ ZMM_L16, /* zmm9 */
+};
diff --git a/vere/ext/nasm/x86/regs.c b/vere/ext/nasm/x86/regs.c
new file mode 100644
index 0000000..1e4fd01
--- /dev/null
+++ b/vere/ext/nasm/x86/regs.c
@@ -0,0 +1,254 @@
+/* automatically generated from ./x86/regs.dat - do not edit */
+
+#include "tables.h"
+
+const char * const nasm_reg_names[] = {
+ "ah",
+ "al",
+ "ax",
+ "bh",
+ "bl",
+ "bnd0",
+ "bnd1",
+ "bnd2",
+ "bnd3",
+ "bp",
+ "bpl",
+ "bx",
+ "ch",
+ "cl",
+ "cr0",
+ "cr1",
+ "cr10",
+ "cr11",
+ "cr12",
+ "cr13",
+ "cr14",
+ "cr15",
+ "cr2",
+ "cr3",
+ "cr4",
+ "cr5",
+ "cr6",
+ "cr7",
+ "cr8",
+ "cr9",
+ "cs",
+ "cx",
+ "dh",
+ "di",
+ "dil",
+ "dl",
+ "dr0",
+ "dr1",
+ "dr10",
+ "dr11",
+ "dr12",
+ "dr13",
+ "dr14",
+ "dr15",
+ "dr2",
+ "dr3",
+ "dr4",
+ "dr5",
+ "dr6",
+ "dr7",
+ "dr8",
+ "dr9",
+ "ds",
+ "dx",
+ "eax",
+ "ebp",
+ "ebx",
+ "ecx",
+ "edi",
+ "edx",
+ "es",
+ "esi",
+ "esp",
+ "fs",
+ "gs",
+ "k0",
+ "k1",
+ "k2",
+ "k3",
+ "k4",
+ "k5",
+ "k6",
+ "k7",
+ "mm0",
+ "mm1",
+ "mm2",
+ "mm3",
+ "mm4",
+ "mm5",
+ "mm6",
+ "mm7",
+ "r10",
+ "r10b",
+ "r10d",
+ "r10w",
+ "r11",
+ "r11b",
+ "r11d",
+ "r11w",
+ "r12",
+ "r12b",
+ "r12d",
+ "r12w",
+ "r13",
+ "r13b",
+ "r13d",
+ "r13w",
+ "r14",
+ "r14b",
+ "r14d",
+ "r14w",
+ "r15",
+ "r15b",
+ "r15d",
+ "r15w",
+ "r8",
+ "r8b",
+ "r8d",
+ "r8w",
+ "r9",
+ "r9b",
+ "r9d",
+ "r9w",
+ "rax",
+ "rbp",
+ "rbx",
+ "rcx",
+ "rdi",
+ "rdx",
+ "rsi",
+ "rsp",
+ "segr6",
+ "segr7",
+ "si",
+ "sil",
+ "sp",
+ "spl",
+ "ss",
+ "st0",
+ "st1",
+ "st2",
+ "st3",
+ "st4",
+ "st5",
+ "st6",
+ "st7",
+ "tmm0",
+ "tmm1",
+ "tmm2",
+ "tmm3",
+ "tmm4",
+ "tmm5",
+ "tmm6",
+ "tmm7",
+ "tr0",
+ "tr1",
+ "tr2",
+ "tr3",
+ "tr4",
+ "tr5",
+ "tr6",
+ "tr7",
+ "xmm0",
+ "xmm1",
+ "xmm10",
+ "xmm11",
+ "xmm12",
+ "xmm13",
+ "xmm14",
+ "xmm15",
+ "xmm16",
+ "xmm17",
+ "xmm18",
+ "xmm19",
+ "xmm2",
+ "xmm20",
+ "xmm21",
+ "xmm22",
+ "xmm23",
+ "xmm24",
+ "xmm25",
+ "xmm26",
+ "xmm27",
+ "xmm28",
+ "xmm29",
+ "xmm3",
+ "xmm30",
+ "xmm31",
+ "xmm4",
+ "xmm5",
+ "xmm6",
+ "xmm7",
+ "xmm8",
+ "xmm9",
+ "ymm0",
+ "ymm1",
+ "ymm10",
+ "ymm11",
+ "ymm12",
+ "ymm13",
+ "ymm14",
+ "ymm15",
+ "ymm16",
+ "ymm17",
+ "ymm18",
+ "ymm19",
+ "ymm2",
+ "ymm20",
+ "ymm21",
+ "ymm22",
+ "ymm23",
+ "ymm24",
+ "ymm25",
+ "ymm26",
+ "ymm27",
+ "ymm28",
+ "ymm29",
+ "ymm3",
+ "ymm30",
+ "ymm31",
+ "ymm4",
+ "ymm5",
+ "ymm6",
+ "ymm7",
+ "ymm8",
+ "ymm9",
+ "zmm0",
+ "zmm1",
+ "zmm10",
+ "zmm11",
+ "zmm12",
+ "zmm13",
+ "zmm14",
+ "zmm15",
+ "zmm16",
+ "zmm17",
+ "zmm18",
+ "zmm19",
+ "zmm2",
+ "zmm20",
+ "zmm21",
+ "zmm22",
+ "zmm23",
+ "zmm24",
+ "zmm25",
+ "zmm26",
+ "zmm27",
+ "zmm28",
+ "zmm29",
+ "zmm3",
+ "zmm30",
+ "zmm31",
+ "zmm4",
+ "zmm5",
+ "zmm6",
+ "zmm7",
+ "zmm8",
+ "zmm9"
+};
diff --git a/vere/ext/nasm/x86/regs.dat b/vere/ext/nasm/x86/regs.dat
new file mode 100644
index 0000000..cec8420
--- /dev/null
+++ b/vere/ext/nasm/x86/regs.dat
@@ -0,0 +1,141 @@
+## --------------------------------------------------------------------------
+##
+## Copyright 1996-2009 The NASM Authors - All Rights Reserved
+## See the file AUTHORS included with the NASM distribution for
+## the specific copyright holders.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following
+## conditions are met:
+##
+## * Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## * Redistributions in binary form must reproduce the above
+## copyright notice, this list of conditions and the following
+## disclaimer in the documentation and/or other materials provided
+## with the distribution.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##
+## --------------------------------------------------------------------------
+
+#
+# List of registers and their classes; classes are defined in nasm.h
+#
+# The columns are:
+#
+# register name, assembler class, disassembler class(es), x86 register number[, token flag]
+#
+# If the register name ends in two numbers separated by a dash, then it is
+# repeated as many times as indicated, and the register number is
+# updated with it.
+#
+# If 'token flag' is present, this value will be assigned to tokflag field in
+# 'struct tokendata tokendata[]' table. Token flag can be used for specifying
+# special usage of corresponding register. E.g. opmask registers can be either
+# enclosed by curly braces or standalone operand depending on the usage.
+#
+
+# General-purpose registers
+al REG_AL reg8,reg8_rex 0
+ah REG_HIGH reg8 4
+ax REG_AX reg16 0
+eax REG_EAX reg32 0
+rax REG_RAX reg64 0
+bl REG8NA reg8,reg8_rex 3
+bh REG_HIGH reg8 7
+bx REG16NA reg16 3
+ebx REG32NA reg32 3
+rbx REG64NA reg64 3
+cl REG_CL reg8,reg8_rex 1
+ch REG_HIGH reg8 5
+cx REG_CX reg16 1
+ecx REG_ECX reg32 1
+rcx REG_RCX reg64 1
+dl REG_DL reg8,reg8_rex 2
+dh REG_HIGH reg8 6
+dx REG_DX reg16 2
+edx REG_EDX reg32 2
+rdx REG_RDX reg64 2
+spl REG8NA reg8_rex 4
+sp REG16NA reg16 4
+esp REG32NA reg32 4
+rsp REG64NA reg64 4
+bpl REG8NA reg8_rex 5
+bp REG16NA reg16 5
+ebp REG32NA reg32 5
+rbp REG64NA reg64 5
+sil REG8NA reg8_rex 6
+si REG16NA reg16 6
+esi REG32NA reg32 6
+rsi REG64NA reg64 6
+dil REG8NA reg8_rex 7
+di REG16NA reg16 7
+edi REG32NA reg32 7
+rdi REG64NA reg64 7
+r8-15b REG8NA reg8_rex 8
+r8-15w REG16NA reg16 8
+r8-15d REG32NA reg32 8
+r8-15 REG64NA reg64 8
+
+# Segment registers
+es REG_ES sreg 0
+cs REG_CS sreg 1
+ss REG_SS sreg 2
+ds REG_DS sreg 3
+fs REG_FS sreg 4
+gs REG_GS sreg 5
+segr6-7 REG_SEG67 sreg 6
+
+# Control registers
+cr0-15 REG_CREG creg 0
+
+# Debug registers
+dr0-15 REG_DREG dreg 0
+
+# Test registers
+tr0-7 REG_TREG treg 0
+
+# Floating-point registers
+st0 FPU0 fpureg 0
+st1-7 FPUREG fpureg 1
+
+# MMX registers
+mm0-7 MMXREG mmxreg 0
+
+# SSE registers
+xmm0 XMM0 xmmreg 0
+xmm1-15 XMM_L16 xmmreg 1
+xmm16-31 XMMREG xmmreg 16
+
+# AVX registers
+ymm0 YMM0 ymmreg 0
+ymm1-15 YMM_L16 ymmreg 1
+ymm16-31 YMMREG ymmreg 16
+
+# AVX512 registers
+zmm0 ZMM0 zmmreg 0
+zmm1-15 ZMM_L16 zmmreg 1
+zmm16-31 ZMMREG zmmreg 16
+
+# AMX tile registers
+tmm0-7 TMMREG tmmreg 0
+
+# Opmask registers
+k0 OPMASK0 opmaskreg 0
+k1-7 OPMASKREG opmaskreg 1 TFLAG_BRC_OPT
+
+# Bounds registers
+bnd0-3 BNDREG bndreg 0
diff --git a/vere/ext/nasm/x86/regs.h b/vere/ext/nasm/x86/regs.h
new file mode 100644
index 0000000..f1bca71
--- /dev/null
+++ b/vere/ext/nasm/x86/regs.h
@@ -0,0 +1,514 @@
+/* automatically generated from ./x86/regs.dat - do not edit */
+
+#ifndef NASM_REGS_H
+#define NASM_REGS_H
+
+#define EXPR_REG_START 1
+
+enum reg_enum {
+ R_zero = 0,
+ R_none = -1,
+ R_AH = EXPR_REG_START,
+ R_AL,
+ R_AX,
+ R_BH,
+ R_BL,
+ R_BND0,
+ R_BND1,
+ R_BND2,
+ R_BND3,
+ R_BP,
+ R_BPL,
+ R_BX,
+ R_CH,
+ R_CL,
+ R_CR0,
+ R_CR1,
+ R_CR10,
+ R_CR11,
+ R_CR12,
+ R_CR13,
+ R_CR14,
+ R_CR15,
+ R_CR2,
+ R_CR3,
+ R_CR4,
+ R_CR5,
+ R_CR6,
+ R_CR7,
+ R_CR8,
+ R_CR9,
+ R_CS,
+ R_CX,
+ R_DH,
+ R_DI,
+ R_DIL,
+ R_DL,
+ R_DR0,
+ R_DR1,
+ R_DR10,
+ R_DR11,
+ R_DR12,
+ R_DR13,
+ R_DR14,
+ R_DR15,
+ R_DR2,
+ R_DR3,
+ R_DR4,
+ R_DR5,
+ R_DR6,
+ R_DR7,
+ R_DR8,
+ R_DR9,
+ R_DS,
+ R_DX,
+ R_EAX,
+ R_EBP,
+ R_EBX,
+ R_ECX,
+ R_EDI,
+ R_EDX,
+ R_ES,
+ R_ESI,
+ R_ESP,
+ R_FS,
+ R_GS,
+ R_K0,
+ R_K1,
+ R_K2,
+ R_K3,
+ R_K4,
+ R_K5,
+ R_K6,
+ R_K7,
+ R_MM0,
+ R_MM1,
+ R_MM2,
+ R_MM3,
+ R_MM4,
+ R_MM5,
+ R_MM6,
+ R_MM7,
+ R_R10,
+ R_R10B,
+ R_R10D,
+ R_R10W,
+ R_R11,
+ R_R11B,
+ R_R11D,
+ R_R11W,
+ R_R12,
+ R_R12B,
+ R_R12D,
+ R_R12W,
+ R_R13,
+ R_R13B,
+ R_R13D,
+ R_R13W,
+ R_R14,
+ R_R14B,
+ R_R14D,
+ R_R14W,
+ R_R15,
+ R_R15B,
+ R_R15D,
+ R_R15W,
+ R_R8,
+ R_R8B,
+ R_R8D,
+ R_R8W,
+ R_R9,
+ R_R9B,
+ R_R9D,
+ R_R9W,
+ R_RAX,
+ R_RBP,
+ R_RBX,
+ R_RCX,
+ R_RDI,
+ R_RDX,
+ R_RSI,
+ R_RSP,
+ R_SEGR6,
+ R_SEGR7,
+ R_SI,
+ R_SIL,
+ R_SP,
+ R_SPL,
+ R_SS,
+ R_ST0,
+ R_ST1,
+ R_ST2,
+ R_ST3,
+ R_ST4,
+ R_ST5,
+ R_ST6,
+ R_ST7,
+ R_TMM0,
+ R_TMM1,
+ R_TMM2,
+ R_TMM3,
+ R_TMM4,
+ R_TMM5,
+ R_TMM6,
+ R_TMM7,
+ R_TR0,
+ R_TR1,
+ R_TR2,
+ R_TR3,
+ R_TR4,
+ R_TR5,
+ R_TR6,
+ R_TR7,
+ R_XMM0,
+ R_XMM1,
+ R_XMM10,
+ R_XMM11,
+ R_XMM12,
+ R_XMM13,
+ R_XMM14,
+ R_XMM15,
+ R_XMM16,
+ R_XMM17,
+ R_XMM18,
+ R_XMM19,
+ R_XMM2,
+ R_XMM20,
+ R_XMM21,
+ R_XMM22,
+ R_XMM23,
+ R_XMM24,
+ R_XMM25,
+ R_XMM26,
+ R_XMM27,
+ R_XMM28,
+ R_XMM29,
+ R_XMM3,
+ R_XMM30,
+ R_XMM31,
+ R_XMM4,
+ R_XMM5,
+ R_XMM6,
+ R_XMM7,
+ R_XMM8,
+ R_XMM9,
+ R_YMM0,
+ R_YMM1,
+ R_YMM10,
+ R_YMM11,
+ R_YMM12,
+ R_YMM13,
+ R_YMM14,
+ R_YMM15,
+ R_YMM16,
+ R_YMM17,
+ R_YMM18,
+ R_YMM19,
+ R_YMM2,
+ R_YMM20,
+ R_YMM21,
+ R_YMM22,
+ R_YMM23,
+ R_YMM24,
+ R_YMM25,
+ R_YMM26,
+ R_YMM27,
+ R_YMM28,
+ R_YMM29,
+ R_YMM3,
+ R_YMM30,
+ R_YMM31,
+ R_YMM4,
+ R_YMM5,
+ R_YMM6,
+ R_YMM7,
+ R_YMM8,
+ R_YMM9,
+ R_ZMM0,
+ R_ZMM1,
+ R_ZMM10,
+ R_ZMM11,
+ R_ZMM12,
+ R_ZMM13,
+ R_ZMM14,
+ R_ZMM15,
+ R_ZMM16,
+ R_ZMM17,
+ R_ZMM18,
+ R_ZMM19,
+ R_ZMM2,
+ R_ZMM20,
+ R_ZMM21,
+ R_ZMM22,
+ R_ZMM23,
+ R_ZMM24,
+ R_ZMM25,
+ R_ZMM26,
+ R_ZMM27,
+ R_ZMM28,
+ R_ZMM29,
+ R_ZMM3,
+ R_ZMM30,
+ R_ZMM31,
+ R_ZMM4,
+ R_ZMM5,
+ R_ZMM6,
+ R_ZMM7,
+ R_ZMM8,
+ R_ZMM9,
+ REG_ENUM_LIMIT
+};
+
+#define EXPR_REG_END 248
+
+#define REG_NUM_AH 4
+#define REG_NUM_AL 0
+#define REG_NUM_AX 0
+#define REG_NUM_BH 7
+#define REG_NUM_BL 3
+#define REG_NUM_BND0 0
+#define REG_NUM_BND1 1
+#define REG_NUM_BND2 2
+#define REG_NUM_BND3 3
+#define REG_NUM_BP 5
+#define REG_NUM_BPL 5
+#define REG_NUM_BX 3
+#define REG_NUM_CH 5
+#define REG_NUM_CL 1
+#define REG_NUM_CR0 0
+#define REG_NUM_CR1 1
+#define REG_NUM_CR10 10
+#define REG_NUM_CR11 11
+#define REG_NUM_CR12 12
+#define REG_NUM_CR13 13
+#define REG_NUM_CR14 14
+#define REG_NUM_CR15 15
+#define REG_NUM_CR2 2
+#define REG_NUM_CR3 3
+#define REG_NUM_CR4 4
+#define REG_NUM_CR5 5
+#define REG_NUM_CR6 6
+#define REG_NUM_CR7 7
+#define REG_NUM_CR8 8
+#define REG_NUM_CR9 9
+#define REG_NUM_CS 1
+#define REG_NUM_CX 1
+#define REG_NUM_DH 6
+#define REG_NUM_DI 7
+#define REG_NUM_DIL 7
+#define REG_NUM_DL 2
+#define REG_NUM_DR0 0
+#define REG_NUM_DR1 1
+#define REG_NUM_DR10 10
+#define REG_NUM_DR11 11
+#define REG_NUM_DR12 12
+#define REG_NUM_DR13 13
+#define REG_NUM_DR14 14
+#define REG_NUM_DR15 15
+#define REG_NUM_DR2 2
+#define REG_NUM_DR3 3
+#define REG_NUM_DR4 4
+#define REG_NUM_DR5 5
+#define REG_NUM_DR6 6
+#define REG_NUM_DR7 7
+#define REG_NUM_DR8 8
+#define REG_NUM_DR9 9
+#define REG_NUM_DS 3
+#define REG_NUM_DX 2
+#define REG_NUM_EAX 0
+#define REG_NUM_EBP 5
+#define REG_NUM_EBX 3
+#define REG_NUM_ECX 1
+#define REG_NUM_EDI 7
+#define REG_NUM_EDX 2
+#define REG_NUM_ES 0
+#define REG_NUM_ESI 6
+#define REG_NUM_ESP 4
+#define REG_NUM_FS 4
+#define REG_NUM_GS 5
+#define REG_NUM_K0 0
+#define REG_NUM_K1 1
+#define REG_NUM_K2 2
+#define REG_NUM_K3 3
+#define REG_NUM_K4 4
+#define REG_NUM_K5 5
+#define REG_NUM_K6 6
+#define REG_NUM_K7 7
+#define REG_NUM_MM0 0
+#define REG_NUM_MM1 1
+#define REG_NUM_MM2 2
+#define REG_NUM_MM3 3
+#define REG_NUM_MM4 4
+#define REG_NUM_MM5 5
+#define REG_NUM_MM6 6
+#define REG_NUM_MM7 7
+#define REG_NUM_R10 10
+#define REG_NUM_R10B 10
+#define REG_NUM_R10D 10
+#define REG_NUM_R10W 10
+#define REG_NUM_R11 11
+#define REG_NUM_R11B 11
+#define REG_NUM_R11D 11
+#define REG_NUM_R11W 11
+#define REG_NUM_R12 12
+#define REG_NUM_R12B 12
+#define REG_NUM_R12D 12
+#define REG_NUM_R12W 12
+#define REG_NUM_R13 13
+#define REG_NUM_R13B 13
+#define REG_NUM_R13D 13
+#define REG_NUM_R13W 13
+#define REG_NUM_R14 14
+#define REG_NUM_R14B 14
+#define REG_NUM_R14D 14
+#define REG_NUM_R14W 14
+#define REG_NUM_R15 15
+#define REG_NUM_R15B 15
+#define REG_NUM_R15D 15
+#define REG_NUM_R15W 15
+#define REG_NUM_R8 8
+#define REG_NUM_R8B 8
+#define REG_NUM_R8D 8
+#define REG_NUM_R8W 8
+#define REG_NUM_R9 9
+#define REG_NUM_R9B 9
+#define REG_NUM_R9D 9
+#define REG_NUM_R9W 9
+#define REG_NUM_RAX 0
+#define REG_NUM_RBP 5
+#define REG_NUM_RBX 3
+#define REG_NUM_RCX 1
+#define REG_NUM_RDI 7
+#define REG_NUM_RDX 2
+#define REG_NUM_RSI 6
+#define REG_NUM_RSP 4
+#define REG_NUM_SEGR6 6
+#define REG_NUM_SEGR7 7
+#define REG_NUM_SI 6
+#define REG_NUM_SIL 6
+#define REG_NUM_SP 4
+#define REG_NUM_SPL 4
+#define REG_NUM_SS 2
+#define REG_NUM_ST0 0
+#define REG_NUM_ST1 1
+#define REG_NUM_ST2 2
+#define REG_NUM_ST3 3
+#define REG_NUM_ST4 4
+#define REG_NUM_ST5 5
+#define REG_NUM_ST6 6
+#define REG_NUM_ST7 7
+#define REG_NUM_TMM0 0
+#define REG_NUM_TMM1 1
+#define REG_NUM_TMM2 2
+#define REG_NUM_TMM3 3
+#define REG_NUM_TMM4 4
+#define REG_NUM_TMM5 5
+#define REG_NUM_TMM6 6
+#define REG_NUM_TMM7 7
+#define REG_NUM_TR0 0
+#define REG_NUM_TR1 1
+#define REG_NUM_TR2 2
+#define REG_NUM_TR3 3
+#define REG_NUM_TR4 4
+#define REG_NUM_TR5 5
+#define REG_NUM_TR6 6
+#define REG_NUM_TR7 7
+#define REG_NUM_XMM0 0
+#define REG_NUM_XMM1 1
+#define REG_NUM_XMM10 10
+#define REG_NUM_XMM11 11
+#define REG_NUM_XMM12 12
+#define REG_NUM_XMM13 13
+#define REG_NUM_XMM14 14
+#define REG_NUM_XMM15 15
+#define REG_NUM_XMM16 16
+#define REG_NUM_XMM17 17
+#define REG_NUM_XMM18 18
+#define REG_NUM_XMM19 19
+#define REG_NUM_XMM2 2
+#define REG_NUM_XMM20 20
+#define REG_NUM_XMM21 21
+#define REG_NUM_XMM22 22
+#define REG_NUM_XMM23 23
+#define REG_NUM_XMM24 24
+#define REG_NUM_XMM25 25
+#define REG_NUM_XMM26 26
+#define REG_NUM_XMM27 27
+#define REG_NUM_XMM28 28
+#define REG_NUM_XMM29 29
+#define REG_NUM_XMM3 3
+#define REG_NUM_XMM30 30
+#define REG_NUM_XMM31 31
+#define REG_NUM_XMM4 4
+#define REG_NUM_XMM5 5
+#define REG_NUM_XMM6 6
+#define REG_NUM_XMM7 7
+#define REG_NUM_XMM8 8
+#define REG_NUM_XMM9 9
+#define REG_NUM_YMM0 0
+#define REG_NUM_YMM1 1
+#define REG_NUM_YMM10 10
+#define REG_NUM_YMM11 11
+#define REG_NUM_YMM12 12
+#define REG_NUM_YMM13 13
+#define REG_NUM_YMM14 14
+#define REG_NUM_YMM15 15
+#define REG_NUM_YMM16 16
+#define REG_NUM_YMM17 17
+#define REG_NUM_YMM18 18
+#define REG_NUM_YMM19 19
+#define REG_NUM_YMM2 2
+#define REG_NUM_YMM20 20
+#define REG_NUM_YMM21 21
+#define REG_NUM_YMM22 22
+#define REG_NUM_YMM23 23
+#define REG_NUM_YMM24 24
+#define REG_NUM_YMM25 25
+#define REG_NUM_YMM26 26
+#define REG_NUM_YMM27 27
+#define REG_NUM_YMM28 28
+#define REG_NUM_YMM29 29
+#define REG_NUM_YMM3 3
+#define REG_NUM_YMM30 30
+#define REG_NUM_YMM31 31
+#define REG_NUM_YMM4 4
+#define REG_NUM_YMM5 5
+#define REG_NUM_YMM6 6
+#define REG_NUM_YMM7 7
+#define REG_NUM_YMM8 8
+#define REG_NUM_YMM9 9
+#define REG_NUM_ZMM0 0
+#define REG_NUM_ZMM1 1
+#define REG_NUM_ZMM10 10
+#define REG_NUM_ZMM11 11
+#define REG_NUM_ZMM12 12
+#define REG_NUM_ZMM13 13
+#define REG_NUM_ZMM14 14
+#define REG_NUM_ZMM15 15
+#define REG_NUM_ZMM16 16
+#define REG_NUM_ZMM17 17
+#define REG_NUM_ZMM18 18
+#define REG_NUM_ZMM19 19
+#define REG_NUM_ZMM2 2
+#define REG_NUM_ZMM20 20
+#define REG_NUM_ZMM21 21
+#define REG_NUM_ZMM22 22
+#define REG_NUM_ZMM23 23
+#define REG_NUM_ZMM24 24
+#define REG_NUM_ZMM25 25
+#define REG_NUM_ZMM26 26
+#define REG_NUM_ZMM27 27
+#define REG_NUM_ZMM28 28
+#define REG_NUM_ZMM29 29
+#define REG_NUM_ZMM3 3
+#define REG_NUM_ZMM30 30
+#define REG_NUM_ZMM31 31
+#define REG_NUM_ZMM4 4
+#define REG_NUM_ZMM5 5
+#define REG_NUM_ZMM6 6
+#define REG_NUM_ZMM7 7
+#define REG_NUM_ZMM8 8
+#define REG_NUM_ZMM9 9
+
+
+#endif /* NASM_REGS_H */
diff --git a/vere/ext/nasm/x86/regs.pl b/vere/ext/nasm/x86/regs.pl
new file mode 100755
index 0000000..31a3fb3
--- /dev/null
+++ b/vere/ext/nasm/x86/regs.pl
@@ -0,0 +1,205 @@
+#!/usr/bin/perl
+## --------------------------------------------------------------------------
+##
+## Copyright 1996-2009 The NASM Authors - All Rights Reserved
+## See the file AUTHORS included with the NASM distribution for
+## the specific copyright holders.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following
+## conditions are met:
+##
+## * Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## * Redistributions in binary form must reproduce the above
+## copyright notice, this list of conditions and the following
+## disclaimer in the documentation and/or other materials provided
+## with the distribution.
+##
+## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+## CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+## INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+## MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+## CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+## SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+## NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+## LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+## CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+## OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+## EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+##
+## --------------------------------------------------------------------------
+
+#
+# Read regs.dat and output regs.h and regs.c (included in names.c)
+#
+
+$nline = 0;
+
+sub toint($) {
+ my($v) = @_;
+
+ return ($v =~ /^0/) ? oct $v : $v+0;
+}
+
+sub process_line($) {
+ my($line) = @_;
+ my @v;
+
+ if ( $line !~ /^\s*(\S+)\s*(\S+)\s*(\S+)\s*([0-9]+)\s*(\S*)/i ) {
+ die "regs.dat:$nline: invalid input\n";
+ }
+ $reg = $1;
+ $aclass = $2;
+ $dclasses = $3;
+ $x86regno = toint($4);
+
+ if ($reg =~ /^(.*[^0-9])([0-9]+)\-([0-9]+)(|[^0-9].*)$/) {
+ $nregs = $3-$2+1;
+ $reg = $1.$2.$4;
+ $reg_nr = $2;
+ $reg_prefix = $1;
+ $reg_suffix = $4;
+ } else {
+ $nregs = 1;
+ undef $reg_prefix;
+ undef $reg_suffix;
+ }
+
+ while ($nregs--) {
+ $regs{$reg} = $aclass;
+ $regvals{$reg} = $x86regno;
+
+ foreach $dclass (split(/,/, $dclasses)) {
+ if ( !defined($disclass{$dclass}) ) {
+ $disclass{$dclass} = [];
+ }
+
+ $disclass{$dclass}->[$x86regno] = $reg;
+ }
+
+ # Compute the next register, if any
+ if (defined($reg_prefix)) {
+ $x86regno++;
+ $reg_nr++;
+ $reg = sprintf("%s%u%s", $reg_prefix, $reg_nr, $reg_suffix);
+ } else {
+ # Not a dashed sequence
+ die if ($nregs);
+ }
+ }
+}
+
+($fmt, $file) = @ARGV;
+
+%regs = ();
+%regvals = ();
+%disclass = ();
+open(REGS, '<', $file) or die "$0: Cannot open $file\n";
+while ( defined($line = <REGS>) ) {
+ $nline++;
+
+ chomp $line;
+ $line =~ s/\s*(\#.*|)$//;
+
+ next if ( $line eq '' );
+
+ process_line($line);
+}
+close(REGS);
+
+if ( $fmt eq 'h' ) {
+ # Output regs.h
+ print "/* automatically generated from $file - do not edit */\n\n";
+ print "#ifndef NASM_REGS_H\n";
+ print "#define NASM_REGS_H\n\n";
+
+ $expr_regs = 1;
+ printf "#define EXPR_REG_START %d\n\n", $expr_regs;
+ print "enum reg_enum {\n";
+ # Unfortunately the code uses both 0 and -1 as "no register" in
+ # different places...
+ print " R_zero = 0,\n";
+ print " R_none = -1,\n";
+ $attach = ' = EXPR_REG_START'; # EXPR_REG_START == 1
+ foreach $reg ( sort(keys(%regs)) ) {
+ print " R_\U${reg}\E${attach},\n";
+ $attach = '';
+ $expr_regs++;
+ }
+ print " REG_ENUM_LIMIT\n";
+ print "};\n\n";
+ printf "#define EXPR_REG_END %d\n\n", $expr_regs-1;
+ foreach $reg ( sort(keys(%regs)) ) {
+ printf "#define %-15s %2d\n", "REG_NUM_\U${reg}", $regvals{$reg};
+ }
+ print "\n\n#endif /* NASM_REGS_H */\n";
+} elsif ( $fmt eq 'c' ) {
+ # Output regs.c
+ print "/* automatically generated from $file - do not edit */\n\n";
+ print "#include \"tables.h\"\n\n";
+ print "const char * const nasm_reg_names[] = "; $ch = '{';
+ # This one has no dummy entry for 0
+ foreach $reg ( sort(keys(%regs)) ) {
+ print "$ch\n \"${reg}\"";
+ $ch = ',';
+ }
+ print "\n};\n";
+} elsif ( $fmt eq 'fc' ) {
+ # Output regflags.c
+ print "/* automatically generated from $file - do not edit */\n\n";
+ print "#include \"tables.h\"\n";
+ print "#include \"nasm.h\"\n\n";
+ print "const opflags_t nasm_reg_flags[] = {\n";
+ printf " 0,\n"; # Dummy entry for 0
+ foreach $reg ( sort(keys(%regs)) ) {
+ # Print the class of the register
+ printf " %-15s /* %-5s */\n",
+ $regs{$reg}.',', $reg;
+ }
+ print "};\n";
+} elsif ( $fmt eq 'vc' ) {
+ # Output regvals.c
+ print "/* automatically generated from $file - do not edit */\n\n";
+ print "#include \"tables.h\"\n\n";
+ print "const int nasm_regvals[] = {\n";
+ print " -1,\n"; # Dummy entry for 0
+ foreach $reg ( sort(keys(%regs)) ) {
+ # Print the x86 value of the register
+ printf " %2d, /* %-5s */\n", $regvals{$reg}, $reg;
+ }
+ print "};\n";
+} elsif ( $fmt eq 'dc' ) {
+ # Output regdis.c
+ print "/* automatically generated from $file - do not edit */\n\n";
+ print "#include \"regdis.h\"\n\n";
+ foreach $class ( sort(keys(%disclass)) ) {
+ printf "const enum reg_enum nasm_rd_%-8s[%2d] = {",
+ $class, scalar @{$disclass{$class}};
+ @foo = @{$disclass{$class}};
+ @bar = ();
+ for ( $i = 0 ; $i < scalar(@foo) ; $i++ ) {
+ if (defined($foo[$i])) {
+ push(@bar, "R_\U$foo[$i]\E");
+ } else {
+ die "$0: No register name for class $class, value $i\n";
+ }
+ }
+ print join(',', @bar), "};\n";
+ }
+} elsif ( $fmt eq 'dh' ) {
+ # Output regdis.h
+ print "/* automatically generated from $file - do not edit */\n\n";
+ print "#ifndef NASM_REGDIS_H\n";
+ print "#define NASM_REGDIS_H\n\n";
+ print "#include \"regs.h\"\n\n";
+ foreach $class ( sort(keys(%disclass)) ) {
+ printf "extern const enum reg_enum nasm_rd_%-8s[%2d];\n",
+ $class, scalar @{$disclass{$class}};
+ }
+ print "\n#endif /* NASM_REGDIS_H */\n";
+} else {
+ die "$0: Unknown output format\n";
+}
diff --git a/vere/ext/nasm/x86/regvals.c b/vere/ext/nasm/x86/regvals.c
new file mode 100644
index 0000000..458abb7
--- /dev/null
+++ b/vere/ext/nasm/x86/regvals.c
@@ -0,0 +1,255 @@
+/* automatically generated from ./x86/regs.dat - do not edit */
+
+#include "tables.h"
+
+const int nasm_regvals[] = {
+ -1,
+ 4, /* ah */
+ 0, /* al */
+ 0, /* ax */
+ 7, /* bh */
+ 3, /* bl */
+ 0, /* bnd0 */
+ 1, /* bnd1 */
+ 2, /* bnd2 */
+ 3, /* bnd3 */
+ 5, /* bp */
+ 5, /* bpl */
+ 3, /* bx */
+ 5, /* ch */
+ 1, /* cl */
+ 0, /* cr0 */
+ 1, /* cr1 */
+ 10, /* cr10 */
+ 11, /* cr11 */
+ 12, /* cr12 */
+ 13, /* cr13 */
+ 14, /* cr14 */
+ 15, /* cr15 */
+ 2, /* cr2 */
+ 3, /* cr3 */
+ 4, /* cr4 */
+ 5, /* cr5 */
+ 6, /* cr6 */
+ 7, /* cr7 */
+ 8, /* cr8 */
+ 9, /* cr9 */
+ 1, /* cs */
+ 1, /* cx */
+ 6, /* dh */
+ 7, /* di */
+ 7, /* dil */
+ 2, /* dl */
+ 0, /* dr0 */
+ 1, /* dr1 */
+ 10, /* dr10 */
+ 11, /* dr11 */
+ 12, /* dr12 */
+ 13, /* dr13 */
+ 14, /* dr14 */
+ 15, /* dr15 */
+ 2, /* dr2 */
+ 3, /* dr3 */
+ 4, /* dr4 */
+ 5, /* dr5 */
+ 6, /* dr6 */
+ 7, /* dr7 */
+ 8, /* dr8 */
+ 9, /* dr9 */
+ 3, /* ds */
+ 2, /* dx */
+ 0, /* eax */
+ 5, /* ebp */
+ 3, /* ebx */
+ 1, /* ecx */
+ 7, /* edi */
+ 2, /* edx */
+ 0, /* es */
+ 6, /* esi */
+ 4, /* esp */
+ 4, /* fs */
+ 5, /* gs */
+ 0, /* k0 */
+ 1, /* k1 */
+ 2, /* k2 */
+ 3, /* k3 */
+ 4, /* k4 */
+ 5, /* k5 */
+ 6, /* k6 */
+ 7, /* k7 */
+ 0, /* mm0 */
+ 1, /* mm1 */
+ 2, /* mm2 */
+ 3, /* mm3 */
+ 4, /* mm4 */
+ 5, /* mm5 */
+ 6, /* mm6 */
+ 7, /* mm7 */
+ 10, /* r10 */
+ 10, /* r10b */
+ 10, /* r10d */
+ 10, /* r10w */
+ 11, /* r11 */
+ 11, /* r11b */
+ 11, /* r11d */
+ 11, /* r11w */
+ 12, /* r12 */
+ 12, /* r12b */
+ 12, /* r12d */
+ 12, /* r12w */
+ 13, /* r13 */
+ 13, /* r13b */
+ 13, /* r13d */
+ 13, /* r13w */
+ 14, /* r14 */
+ 14, /* r14b */
+ 14, /* r14d */
+ 14, /* r14w */
+ 15, /* r15 */
+ 15, /* r15b */
+ 15, /* r15d */
+ 15, /* r15w */
+ 8, /* r8 */
+ 8, /* r8b */
+ 8, /* r8d */
+ 8, /* r8w */
+ 9, /* r9 */
+ 9, /* r9b */
+ 9, /* r9d */
+ 9, /* r9w */
+ 0, /* rax */
+ 5, /* rbp */
+ 3, /* rbx */
+ 1, /* rcx */
+ 7, /* rdi */
+ 2, /* rdx */
+ 6, /* rsi */
+ 4, /* rsp */
+ 6, /* segr6 */
+ 7, /* segr7 */
+ 6, /* si */
+ 6, /* sil */
+ 4, /* sp */
+ 4, /* spl */
+ 2, /* ss */
+ 0, /* st0 */
+ 1, /* st1 */
+ 2, /* st2 */
+ 3, /* st3 */
+ 4, /* st4 */
+ 5, /* st5 */
+ 6, /* st6 */
+ 7, /* st7 */
+ 0, /* tmm0 */
+ 1, /* tmm1 */
+ 2, /* tmm2 */
+ 3, /* tmm3 */
+ 4, /* tmm4 */
+ 5, /* tmm5 */
+ 6, /* tmm6 */
+ 7, /* tmm7 */
+ 0, /* tr0 */
+ 1, /* tr1 */
+ 2, /* tr2 */
+ 3, /* tr3 */
+ 4, /* tr4 */
+ 5, /* tr5 */
+ 6, /* tr6 */
+ 7, /* tr7 */
+ 0, /* xmm0 */
+ 1, /* xmm1 */
+ 10, /* xmm10 */
+ 11, /* xmm11 */
+ 12, /* xmm12 */
+ 13, /* xmm13 */
+ 14, /* xmm14 */
+ 15, /* xmm15 */
+ 16, /* xmm16 */
+ 17, /* xmm17 */
+ 18, /* xmm18 */
+ 19, /* xmm19 */
+ 2, /* xmm2 */
+ 20, /* xmm20 */
+ 21, /* xmm21 */
+ 22, /* xmm22 */
+ 23, /* xmm23 */
+ 24, /* xmm24 */
+ 25, /* xmm25 */
+ 26, /* xmm26 */
+ 27, /* xmm27 */
+ 28, /* xmm28 */
+ 29, /* xmm29 */
+ 3, /* xmm3 */
+ 30, /* xmm30 */
+ 31, /* xmm31 */
+ 4, /* xmm4 */
+ 5, /* xmm5 */
+ 6, /* xmm6 */
+ 7, /* xmm7 */
+ 8, /* xmm8 */
+ 9, /* xmm9 */
+ 0, /* ymm0 */
+ 1, /* ymm1 */
+ 10, /* ymm10 */
+ 11, /* ymm11 */
+ 12, /* ymm12 */
+ 13, /* ymm13 */
+ 14, /* ymm14 */
+ 15, /* ymm15 */
+ 16, /* ymm16 */
+ 17, /* ymm17 */
+ 18, /* ymm18 */
+ 19, /* ymm19 */
+ 2, /* ymm2 */
+ 20, /* ymm20 */
+ 21, /* ymm21 */
+ 22, /* ymm22 */
+ 23, /* ymm23 */
+ 24, /* ymm24 */
+ 25, /* ymm25 */
+ 26, /* ymm26 */
+ 27, /* ymm27 */
+ 28, /* ymm28 */
+ 29, /* ymm29 */
+ 3, /* ymm3 */
+ 30, /* ymm30 */
+ 31, /* ymm31 */
+ 4, /* ymm4 */
+ 5, /* ymm5 */
+ 6, /* ymm6 */
+ 7, /* ymm7 */
+ 8, /* ymm8 */
+ 9, /* ymm9 */
+ 0, /* zmm0 */
+ 1, /* zmm1 */
+ 10, /* zmm10 */
+ 11, /* zmm11 */
+ 12, /* zmm12 */
+ 13, /* zmm13 */
+ 14, /* zmm14 */
+ 15, /* zmm15 */
+ 16, /* zmm16 */
+ 17, /* zmm17 */
+ 18, /* zmm18 */
+ 19, /* zmm19 */
+ 2, /* zmm2 */
+ 20, /* zmm20 */
+ 21, /* zmm21 */
+ 22, /* zmm22 */
+ 23, /* zmm23 */
+ 24, /* zmm24 */
+ 25, /* zmm25 */
+ 26, /* zmm26 */
+ 27, /* zmm27 */
+ 28, /* zmm28 */
+ 29, /* zmm29 */
+ 3, /* zmm3 */
+ 30, /* zmm30 */
+ 31, /* zmm31 */
+ 4, /* zmm4 */
+ 5, /* zmm5 */
+ 6, /* zmm6 */
+ 7, /* zmm7 */
+ 8, /* zmm8 */
+ 9, /* zmm9 */
+};